Tamura Mizuki / STM32F746_FFT

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Dependencies:   BSP_DISCO_F746NG SDFileSystem_Warning_Fixed

mbed_src_STM32F7/hal/spi_api.h@3:6f7e05dd8d15, 2020-03-06 (annotated)

Committer:
aria19970520
Date:
Fri Mar 06 06:52:14 2020 +0000
Revision:
3:6f7e05dd8d15
Parent:
0:3e46577dc273 
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MikamiUitOpen 0:3e46577dc273 1 /* mbed Microcontroller Library
MikamiUitOpen 0:3e46577dc273 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 0:3e46577dc273 3 *
MikamiUitOpen 0:3e46577dc273 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 0:3e46577dc273 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 0:3e46577dc273 6 * You may obtain a copy of the License at
MikamiUitOpen 0:3e46577dc273 7 *
MikamiUitOpen 0:3e46577dc273 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 0:3e46577dc273 9 *
MikamiUitOpen 0:3e46577dc273 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 0:3e46577dc273 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 0:3e46577dc273 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 0:3e46577dc273 13 * See the License for the specific language governing permissions and
MikamiUitOpen 0:3e46577dc273 14 * limitations under the License.
MikamiUitOpen 0:3e46577dc273 15 */
MikamiUitOpen 0:3e46577dc273 16 #ifndef MBED_SPI_API_H
MikamiUitOpen 0:3e46577dc273 17 #define MBED_SPI_API_H
MikamiUitOpen 0:3e46577dc273 18
MikamiUitOpen 0:3e46577dc273 19 #include "device.h"
MikamiUitOpen 0:3e46577dc273 20 #include "dma_api.h"
MikamiUitOpen 0:3e46577dc273 21 #include "buffer.h"
MikamiUitOpen 0:3e46577dc273 22
MikamiUitOpen 0:3e46577dc273 23 #if DEVICE_SPI
MikamiUitOpen 0:3e46577dc273 24
MikamiUitOpen 0:3e46577dc273 25 #define SPI_EVENT_ERROR (1 << 1)
MikamiUitOpen 0:3e46577dc273 26 #define SPI_EVENT_COMPLETE (1 << 2)
MikamiUitOpen 0:3e46577dc273 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
MikamiUitOpen 0:3e46577dc273 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
MikamiUitOpen 0:3e46577dc273 29
MikamiUitOpen 0:3e46577dc273 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
MikamiUitOpen 0:3e46577dc273 31
MikamiUitOpen 0:3e46577dc273 32 #define SPI_FILL_WORD (0xFFFF)
MikamiUitOpen 0:3e46577dc273 33
MikamiUitOpen 0:3e46577dc273 34 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 0:3e46577dc273 35 /** Asynch spi hal structure
MikamiUitOpen 0:3e46577dc273 36 */
MikamiUitOpen 0:3e46577dc273 37 typedef struct {
MikamiUitOpen 0:3e46577dc273 38 struct spi_s spi; /**< Target specific spi structure */
MikamiUitOpen 0:3e46577dc273 39 struct buffer_s tx_buff; /**< Tx buffer */
MikamiUitOpen 0:3e46577dc273 40 struct buffer_s rx_buff; /**< Rx buffer */
MikamiUitOpen 0:3e46577dc273 41 } spi_t;
MikamiUitOpen 0:3e46577dc273 42
MikamiUitOpen 0:3e46577dc273 43 #else
MikamiUitOpen 0:3e46577dc273 44 /** Non-asynch spi hal structure
MikamiUitOpen 0:3e46577dc273 45 */
MikamiUitOpen 0:3e46577dc273 46 typedef struct spi_s spi_t;
MikamiUitOpen 0:3e46577dc273 47
MikamiUitOpen 0:3e46577dc273 48 #endif
MikamiUitOpen 0:3e46577dc273 49
MikamiUitOpen 0:3e46577dc273 50 #ifdef __cplusplus
MikamiUitOpen 0:3e46577dc273 51 extern "C" {
MikamiUitOpen 0:3e46577dc273 52 #endif
MikamiUitOpen 0:3e46577dc273 53
MikamiUitOpen 0:3e46577dc273 54 /**
MikamiUitOpen 0:3e46577dc273 55 * \defgroup GeneralSPI SPI Configuration Functions
MikamiUitOpen 0:3e46577dc273 56 * @{
MikamiUitOpen 0:3e46577dc273 57 */
MikamiUitOpen 0:3e46577dc273 58
MikamiUitOpen 0:3e46577dc273 59 /** Initialize the SPI peripheral
MikamiUitOpen 0:3e46577dc273 60 *
MikamiUitOpen 0:3e46577dc273 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
MikamiUitOpen 0:3e46577dc273 62 * @param[out] obj The SPI object to initialize
MikamiUitOpen 0:3e46577dc273 63 * @param[in] mosi The pin to use for MOSI
MikamiUitOpen 0:3e46577dc273 64 * @param[in] miso The pin to use for MISO
MikamiUitOpen 0:3e46577dc273 65 * @param[in] sclk The pin to use for SCLK
MikamiUitOpen 0:3e46577dc273 66 * @param[in] ssel The pin to use for SSEL
MikamiUitOpen 0:3e46577dc273 67 */
MikamiUitOpen 0:3e46577dc273 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
MikamiUitOpen 0:3e46577dc273 69
MikamiUitOpen 0:3e46577dc273 70 /** Release a SPI object
MikamiUitOpen 0:3e46577dc273 71 *
MikamiUitOpen 0:3e46577dc273 72 * TODO: spi_free is currently unimplemented
MikamiUitOpen 0:3e46577dc273 73 * This will require reference counting at the C++ level to be safe
MikamiUitOpen 0:3e46577dc273 74 *
MikamiUitOpen 0:3e46577dc273 75 * Return the pins owned by the SPI object to their reset state
MikamiUitOpen 0:3e46577dc273 76 * Disable the SPI peripheral
MikamiUitOpen 0:3e46577dc273 77 * Disable the SPI clock
MikamiUitOpen 0:3e46577dc273 78 * @param[in] obj The SPI object to deinitialize
MikamiUitOpen 0:3e46577dc273 79 */
MikamiUitOpen 0:3e46577dc273 80 void spi_free(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 81
MikamiUitOpen 0:3e46577dc273 82 /** Configure the SPI format
MikamiUitOpen 0:3e46577dc273 83 *
MikamiUitOpen 0:3e46577dc273 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
MikamiUitOpen 0:3e46577dc273 85 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 0:3e46577dc273 86 * @param[in] bits The number of bits per frame
MikamiUitOpen 0:3e46577dc273 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
MikamiUitOpen 0:3e46577dc273 88 * @param[in] slave Zero for master mode or non-zero for slave mode
MikamiUitOpen 0:3e46577dc273 89 */
MikamiUitOpen 0:3e46577dc273 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
MikamiUitOpen 0:3e46577dc273 91
MikamiUitOpen 0:3e46577dc273 92 /** Set the SPI baud rate
MikamiUitOpen 0:3e46577dc273 93 *
MikamiUitOpen 0:3e46577dc273 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
MikamiUitOpen 0:3e46577dc273 95 * Configures the SPI peripheral's baud rate
MikamiUitOpen 0:3e46577dc273 96 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 0:3e46577dc273 97 * @param[in] hz The baud rate in Hz
MikamiUitOpen 0:3e46577dc273 98 */
MikamiUitOpen 0:3e46577dc273 99 void spi_frequency(spi_t *obj, int hz);
MikamiUitOpen 0:3e46577dc273 100
MikamiUitOpen 0:3e46577dc273 101 /**@}*/
MikamiUitOpen 0:3e46577dc273 102 /**
MikamiUitOpen 0:3e46577dc273 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
MikamiUitOpen 0:3e46577dc273 104 * @{
MikamiUitOpen 0:3e46577dc273 105 */
MikamiUitOpen 0:3e46577dc273 106
MikamiUitOpen 0:3e46577dc273 107 /** Write a byte out in master mode and receive a value
MikamiUitOpen 0:3e46577dc273 108 *
MikamiUitOpen 0:3e46577dc273 109 * @param[in] obj The SPI peripheral to use for sending
MikamiUitOpen 0:3e46577dc273 110 * @param[in] value The value to send
MikamiUitOpen 0:3e46577dc273 111 * @return Returns the value received during send
MikamiUitOpen 0:3e46577dc273 112 */
MikamiUitOpen 0:3e46577dc273 113 int spi_master_write(spi_t *obj, int value);
MikamiUitOpen 0:3e46577dc273 114
MikamiUitOpen 0:3e46577dc273 115 /** Check if a value is available to read
MikamiUitOpen 0:3e46577dc273 116 *
MikamiUitOpen 0:3e46577dc273 117 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 0:3e46577dc273 118 * @return non-zero if a value is available
MikamiUitOpen 0:3e46577dc273 119 */
MikamiUitOpen 0:3e46577dc273 120 int spi_slave_receive(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 121
MikamiUitOpen 0:3e46577dc273 122 /** Get a received value out of the SPI receive buffer in slave mode
MikamiUitOpen 0:3e46577dc273 123 *
MikamiUitOpen 0:3e46577dc273 124 * Blocks until a value is available
MikamiUitOpen 0:3e46577dc273 125 * @param[in] obj The SPI peripheral to read
MikamiUitOpen 0:3e46577dc273 126 * @return The value received
MikamiUitOpen 0:3e46577dc273 127 */
MikamiUitOpen 0:3e46577dc273 128 int spi_slave_read(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 129
MikamiUitOpen 0:3e46577dc273 130 /** Write a value to the SPI peripheral in slave mode
MikamiUitOpen 0:3e46577dc273 131 *
MikamiUitOpen 0:3e46577dc273 132 * Blocks until the SPI peripheral can be written to
MikamiUitOpen 0:3e46577dc273 133 * @param[in] obj The SPI peripheral to write
MikamiUitOpen 0:3e46577dc273 134 * @param[in] value The value to write
MikamiUitOpen 0:3e46577dc273 135 */
MikamiUitOpen 0:3e46577dc273 136 void spi_slave_write(spi_t *obj, int value);
MikamiUitOpen 0:3e46577dc273 137
MikamiUitOpen 0:3e46577dc273 138 /** Checks if the specified SPI peripheral is in use
MikamiUitOpen 0:3e46577dc273 139 *
MikamiUitOpen 0:3e46577dc273 140 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 0:3e46577dc273 141 * @return non-zero if the peripheral is currently transmitting
MikamiUitOpen 0:3e46577dc273 142 */
MikamiUitOpen 0:3e46577dc273 143 int spi_busy(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 144
MikamiUitOpen 0:3e46577dc273 145 /** Get the module number
MikamiUitOpen 0:3e46577dc273 146 *
MikamiUitOpen 0:3e46577dc273 147 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 0:3e46577dc273 148 * @return The module number
MikamiUitOpen 0:3e46577dc273 149 */
MikamiUitOpen 0:3e46577dc273 150 uint8_t spi_get_module(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 151
MikamiUitOpen 0:3e46577dc273 152 /**@}*/
MikamiUitOpen 0:3e46577dc273 153
MikamiUitOpen 0:3e46577dc273 154 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 0:3e46577dc273 155 /**
MikamiUitOpen 0:3e46577dc273 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
MikamiUitOpen 0:3e46577dc273 157 * @{
MikamiUitOpen 0:3e46577dc273 158 */
MikamiUitOpen 0:3e46577dc273 159
MikamiUitOpen 0:3e46577dc273 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
MikamiUitOpen 0:3e46577dc273 161 *
MikamiUitOpen 0:3e46577dc273 162 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 0:3e46577dc273 163 * @param[in] tx The buffer to send
MikamiUitOpen 0:3e46577dc273 164 * @param[in] tx_length The number of words to transmit
MikamiUitOpen 0:3e46577dc273 165 * @param[in] rx The buffer to receive
MikamiUitOpen 0:3e46577dc273 166 * @param[in] rx_length The number of words to receive
MikamiUitOpen 0:3e46577dc273 167 * @param[in] bit_width The bit width of buffer words
MikamiUitOpen 0:3e46577dc273 168 * @param[in] event The logical OR of events to be registered
MikamiUitOpen 0:3e46577dc273 169 * @param[in] handler SPI interrupt handler
MikamiUitOpen 0:3e46577dc273 170 * @param[in] hint A suggestion for how to use DMA with this transfer
MikamiUitOpen 0:3e46577dc273 171 */
MikamiUitOpen 0:3e46577dc273 172 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
MikamiUitOpen 0:3e46577dc273 173
MikamiUitOpen 0:3e46577dc273 174 /** The asynchronous IRQ handler
MikamiUitOpen 0:3e46577dc273 175 *
MikamiUitOpen 0:3e46577dc273 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
MikamiUitOpen 0:3e46577dc273 177 * conditions, such as buffer overflows or transfer complete.
MikamiUitOpen 0:3e46577dc273 178 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 0:3e46577dc273 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
MikamiUitOpen 0:3e46577dc273 180 */
MikamiUitOpen 0:3e46577dc273 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 182
MikamiUitOpen 0:3e46577dc273 183 /** Attempts to determine if the SPI peripheral is already in use.
MikamiUitOpen 0:3e46577dc273 184 *
MikamiUitOpen 0:3e46577dc273 185 * If a temporary DMA channel has been allocated, peripheral is in use.
MikamiUitOpen 0:3e46577dc273 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
MikamiUitOpen 0:3e46577dc273 187 * channel were allocated.
MikamiUitOpen 0:3e46577dc273 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
MikamiUitOpen 0:3e46577dc273 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
MikamiUitOpen 0:3e46577dc273 190 * there are any bytes in the FIFOs.
MikamiUitOpen 0:3e46577dc273 191 * @param[in] obj The SPI object to check for activity
MikamiUitOpen 0:3e46577dc273 192 * @return non-zero if the SPI port is active or zero if it is not.
MikamiUitOpen 0:3e46577dc273 193 */
MikamiUitOpen 0:3e46577dc273 194 uint8_t spi_active(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 195
MikamiUitOpen 0:3e46577dc273 196 /** Abort an SPI transfer
MikamiUitOpen 0:3e46577dc273 197 *
MikamiUitOpen 0:3e46577dc273 198 * @param obj The SPI peripheral to stop
MikamiUitOpen 0:3e46577dc273 199 */
MikamiUitOpen 0:3e46577dc273 200 void spi_abort_asynch(spi_t *obj);
MikamiUitOpen 0:3e46577dc273 201
MikamiUitOpen 0:3e46577dc273 202
MikamiUitOpen 0:3e46577dc273 203 #endif
MikamiUitOpen 0:3e46577dc273 204
MikamiUitOpen 0:3e46577dc273 205 /**@}*/
MikamiUitOpen 0:3e46577dc273 206
MikamiUitOpen 0:3e46577dc273 207 #ifdef __cplusplus
MikamiUitOpen 0:3e46577dc273 208 }
MikamiUitOpen 0:3e46577dc273 209 #endif // __cplusplus
MikamiUitOpen 0:3e46577dc273 210
MikamiUitOpen 0:3e46577dc273 211 #endif // SPI_DEVICE
MikamiUitOpen 0:3e46577dc273 212
MikamiUitOpen 0:3e46577dc273 213 #endif // MBED_SPI_API_H