Tamura Mizuki / STM32F746_FFT

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Dependencies:   BSP_DISCO_F746NG SDFileSystem_Warning_Fixed

mbed_src_STM32F7/common/SPI.cpp@3:6f7e05dd8d15, 2020-03-06 (annotated)

Committer:
aria19970520
Date:
Fri Mar 06 06:52:14 2020 +0000
Revision:
3:6f7e05dd8d15
Parent:
0:3e46577dc273 
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 0:3e46577dc273 1 /* mbed Microcontroller Library
MikamiUitOpen 0:3e46577dc273 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 0:3e46577dc273 3 *
MikamiUitOpen 0:3e46577dc273 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 0:3e46577dc273 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 0:3e46577dc273 6 * You may obtain a copy of the License at
MikamiUitOpen 0:3e46577dc273 7 *
MikamiUitOpen 0:3e46577dc273 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 0:3e46577dc273 9 *
MikamiUitOpen 0:3e46577dc273 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 0:3e46577dc273 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 0:3e46577dc273 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 0:3e46577dc273 13 * See the License for the specific language governing permissions and
MikamiUitOpen 0:3e46577dc273 14 * limitations under the License.
MikamiUitOpen 0:3e46577dc273 15 */
MikamiUitOpen 0:3e46577dc273 16 #include "SPI.h"
MikamiUitOpen 0:3e46577dc273 17
MikamiUitOpen 0:3e46577dc273 18 #if DEVICE_SPI
MikamiUitOpen 0:3e46577dc273 19
MikamiUitOpen 0:3e46577dc273 20 namespace mbed {
MikamiUitOpen 0:3e46577dc273 21
MikamiUitOpen 0:3e46577dc273 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 0:3e46577dc273 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
MikamiUitOpen 0:3e46577dc273 24 #endif
MikamiUitOpen 0:3e46577dc273 25
MikamiUitOpen 0:3e46577dc273 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
MikamiUitOpen 0:3e46577dc273 27 _spi(),
MikamiUitOpen 0:3e46577dc273 28 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 0:3e46577dc273 29 _irq(this),
MikamiUitOpen 0:3e46577dc273 30 _usage(DMA_USAGE_NEVER),
MikamiUitOpen 0:3e46577dc273 31 #endif
MikamiUitOpen 0:3e46577dc273 32 _bits(8),
MikamiUitOpen 0:3e46577dc273 33 _mode(0),
MikamiUitOpen 0:3e46577dc273 34 _hz(1000000) {
MikamiUitOpen 0:3e46577dc273 35 spi_init(&_spi, mosi, miso, sclk, ssel);
MikamiUitOpen 0:3e46577dc273 36 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 0:3e46577dc273 37 spi_frequency(&_spi, _hz);
MikamiUitOpen 0:3e46577dc273 38 }
MikamiUitOpen 0:3e46577dc273 39
MikamiUitOpen 0:3e46577dc273 40 void SPI::format(int bits, int mode) {
MikamiUitOpen 0:3e46577dc273 41 _bits = bits;
MikamiUitOpen 0:3e46577dc273 42 _mode = mode;
MikamiUitOpen 0:3e46577dc273 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 0:3e46577dc273 44 aquire();
MikamiUitOpen 0:3e46577dc273 45 }
MikamiUitOpen 0:3e46577dc273 46
MikamiUitOpen 0:3e46577dc273 47 void SPI::frequency(int hz) {
MikamiUitOpen 0:3e46577dc273 48 _hz = hz;
MikamiUitOpen 0:3e46577dc273 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 0:3e46577dc273 50 aquire();
MikamiUitOpen 0:3e46577dc273 51 }
MikamiUitOpen 0:3e46577dc273 52
MikamiUitOpen 0:3e46577dc273 53 SPI* SPI::_owner = NULL;
MikamiUitOpen 0:3e46577dc273 54
MikamiUitOpen 0:3e46577dc273 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
MikamiUitOpen 0:3e46577dc273 56 void SPI::aquire() {
MikamiUitOpen 0:3e46577dc273 57 if (_owner != this) {
MikamiUitOpen 0:3e46577dc273 58 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 0:3e46577dc273 59 spi_frequency(&_spi, _hz);
MikamiUitOpen 0:3e46577dc273 60 _owner = this;
MikamiUitOpen 0:3e46577dc273 61 }
MikamiUitOpen 0:3e46577dc273 62 }
MikamiUitOpen 0:3e46577dc273 63
MikamiUitOpen 0:3e46577dc273 64 int SPI::write(int value) {
MikamiUitOpen 0:3e46577dc273 65 aquire();
MikamiUitOpen 0:3e46577dc273 66 return spi_master_write(&_spi, value);
MikamiUitOpen 0:3e46577dc273 67 }
MikamiUitOpen 0:3e46577dc273 68
MikamiUitOpen 0:3e46577dc273 69 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 0:3e46577dc273 70
MikamiUitOpen 0:3e46577dc273 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 0:3e46577dc273 72 {
MikamiUitOpen 0:3e46577dc273 73 if (spi_active(&_spi)) {
MikamiUitOpen 0:3e46577dc273 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 0:3e46577dc273 75 }
MikamiUitOpen 0:3e46577dc273 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 0:3e46577dc273 77 return 0;
MikamiUitOpen 0:3e46577dc273 78 }
MikamiUitOpen 0:3e46577dc273 79
MikamiUitOpen 0:3e46577dc273 80 void SPI::abort_transfer()
MikamiUitOpen 0:3e46577dc273 81 {
MikamiUitOpen 0:3e46577dc273 82 spi_abort_asynch(&_spi);
MikamiUitOpen 0:3e46577dc273 83 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 0:3e46577dc273 84 dequeue_transaction();
MikamiUitOpen 0:3e46577dc273 85 #endif
MikamiUitOpen 0:3e46577dc273 86 }
MikamiUitOpen 0:3e46577dc273 87
MikamiUitOpen 0:3e46577dc273 88
MikamiUitOpen 0:3e46577dc273 89 void SPI::clear_transfer_buffer()
MikamiUitOpen 0:3e46577dc273 90 {
MikamiUitOpen 0:3e46577dc273 91 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 0:3e46577dc273 92 _transaction_buffer.reset();
MikamiUitOpen 0:3e46577dc273 93 #endif
MikamiUitOpen 0:3e46577dc273 94 }
MikamiUitOpen 0:3e46577dc273 95
MikamiUitOpen 0:3e46577dc273 96 void SPI::abort_all_transfers()
MikamiUitOpen 0:3e46577dc273 97 {
MikamiUitOpen 0:3e46577dc273 98 clear_transfer_buffer();
MikamiUitOpen 0:3e46577dc273 99 abort_transfer();
MikamiUitOpen 0:3e46577dc273 100 }
MikamiUitOpen 0:3e46577dc273 101
MikamiUitOpen 0:3e46577dc273 102 int SPI::set_dma_usage(DMAUsage usage)
MikamiUitOpen 0:3e46577dc273 103 {
MikamiUitOpen 0:3e46577dc273 104 if (spi_active(&_spi)) {
MikamiUitOpen 0:3e46577dc273 105 return -1;
MikamiUitOpen 0:3e46577dc273 106 }
MikamiUitOpen 0:3e46577dc273 107 _usage = usage;
MikamiUitOpen 0:3e46577dc273 108 return 0;
MikamiUitOpen 0:3e46577dc273 109 }
MikamiUitOpen 0:3e46577dc273 110
MikamiUitOpen 0:3e46577dc273 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 0:3e46577dc273 112 {
MikamiUitOpen 0:3e46577dc273 113 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 0:3e46577dc273 114 transaction_t t;
MikamiUitOpen 0:3e46577dc273 115
MikamiUitOpen 0:3e46577dc273 116 t.tx_buffer = const_cast<void *>(tx_buffer);
MikamiUitOpen 0:3e46577dc273 117 t.tx_length = tx_length;
MikamiUitOpen 0:3e46577dc273 118 t.rx_buffer = rx_buffer;
MikamiUitOpen 0:3e46577dc273 119 t.rx_length = rx_length;
MikamiUitOpen 0:3e46577dc273 120 t.event = event;
MikamiUitOpen 0:3e46577dc273 121 t.callback = callback;
MikamiUitOpen 0:3e46577dc273 122 t.width = bit_width;
MikamiUitOpen 0:3e46577dc273 123 Transaction<SPI> transaction(this, t);
MikamiUitOpen 0:3e46577dc273 124 if (_transaction_buffer.full()) {
MikamiUitOpen 0:3e46577dc273 125 return -1; // the buffer is full
MikamiUitOpen 0:3e46577dc273 126 } else {
MikamiUitOpen 0:3e46577dc273 127 __disable_irq();
MikamiUitOpen 0:3e46577dc273 128 _transaction_buffer.push(transaction);
MikamiUitOpen 0:3e46577dc273 129 if (!spi_active(&_spi)) {
MikamiUitOpen 0:3e46577dc273 130 dequeue_transaction();
MikamiUitOpen 0:3e46577dc273 131 }
MikamiUitOpen 0:3e46577dc273 132 __enable_irq();
MikamiUitOpen 0:3e46577dc273 133 return 0;
MikamiUitOpen 0:3e46577dc273 134 }
MikamiUitOpen 0:3e46577dc273 135 #else
MikamiUitOpen 0:3e46577dc273 136 return -1;
MikamiUitOpen 0:3e46577dc273 137 #endif
MikamiUitOpen 0:3e46577dc273 138 }
MikamiUitOpen 0:3e46577dc273 139
MikamiUitOpen 0:3e46577dc273 140 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 0:3e46577dc273 141 {
MikamiUitOpen 0:3e46577dc273 142 aquire();
MikamiUitOpen 0:3e46577dc273 143 _callback = callback;
MikamiUitOpen 0:3e46577dc273 144 _irq.callback(&SPI::irq_handler_asynch);
MikamiUitOpen 0:3e46577dc273 145 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
MikamiUitOpen 0:3e46577dc273 146 }
MikamiUitOpen 0:3e46577dc273 147
MikamiUitOpen 0:3e46577dc273 148 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 0:3e46577dc273 149
MikamiUitOpen 0:3e46577dc273 150 void SPI::start_transaction(transaction_t *data)
MikamiUitOpen 0:3e46577dc273 151 {
MikamiUitOpen 0:3e46577dc273 152 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
MikamiUitOpen 0:3e46577dc273 153 }
MikamiUitOpen 0:3e46577dc273 154
MikamiUitOpen 0:3e46577dc273 155 void SPI::dequeue_transaction()
MikamiUitOpen 0:3e46577dc273 156 {
MikamiUitOpen 0:3e46577dc273 157 Transaction<SPI> t;
MikamiUitOpen 0:3e46577dc273 158 if (_transaction_buffer.pop(t)) {
MikamiUitOpen 0:3e46577dc273 159 SPI* obj = t.get_object();
MikamiUitOpen 0:3e46577dc273 160 transaction_t* data = t.get_transaction();
MikamiUitOpen 0:3e46577dc273 161 obj->start_transaction(data);
MikamiUitOpen 0:3e46577dc273 162 }
MikamiUitOpen 0:3e46577dc273 163 }
MikamiUitOpen 0:3e46577dc273 164
MikamiUitOpen 0:3e46577dc273 165 #endif
MikamiUitOpen 0:3e46577dc273 166
MikamiUitOpen 0:3e46577dc273 167 void SPI::irq_handler_asynch(void)
MikamiUitOpen 0:3e46577dc273 168 {
MikamiUitOpen 0:3e46577dc273 169 int event = spi_irq_handler_asynch(&_spi);
MikamiUitOpen 0:3e46577dc273 170 if (_callback && (event & SPI_EVENT_ALL)) {
MikamiUitOpen 0:3e46577dc273 171 _callback.call(event & SPI_EVENT_ALL);
MikamiUitOpen 0:3e46577dc273 172 }
MikamiUitOpen 0:3e46577dc273 173 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 0:3e46577dc273 174 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
MikamiUitOpen 0:3e46577dc273 175 // SPI peripheral is free (event happend), dequeue transaction
MikamiUitOpen 0:3e46577dc273 176 dequeue_transaction();
MikamiUitOpen 0:3e46577dc273 177 }
MikamiUitOpen 0:3e46577dc273 178 #endif
MikamiUitOpen 0:3e46577dc273 179 }
MikamiUitOpen 0:3e46577dc273 180
MikamiUitOpen 0:3e46577dc273 181 #endif
MikamiUitOpen 0:3e46577dc273 182
MikamiUitOpen 0:3e46577dc273 183 } // namespace mbed
MikamiUitOpen 0:3e46577dc273 184
MikamiUitOpen 0:3e46577dc273 185 #endif