Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c@0:ba7650f404af, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 02:26:59 2015 +0000
Revision:
0:ba7650f404af
Reduced HSE_STARTUP_TIMEOUT to 500 ms, fixed some compiler warnings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /*******************************************************************************
aravindsv 0:ba7650f404af 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
aravindsv 0:ba7650f404af 3 *
aravindsv 0:ba7650f404af 4 * Permission is hereby granted, free of charge, to any person obtaining a
aravindsv 0:ba7650f404af 5 * copy of this software and associated documentation files (the "Software"),
aravindsv 0:ba7650f404af 6 * to deal in the Software without restriction, including without limitation
aravindsv 0:ba7650f404af 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
aravindsv 0:ba7650f404af 8 * and/or sell copies of the Software, and to permit persons to whom the
aravindsv 0:ba7650f404af 9 * Software is furnished to do so, subject to the following conditions:
aravindsv 0:ba7650f404af 10 *
aravindsv 0:ba7650f404af 11 * The above copyright notice and this permission notice shall be included
aravindsv 0:ba7650f404af 12 * in all copies or substantial portions of the Software.
aravindsv 0:ba7650f404af 13 *
aravindsv 0:ba7650f404af 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
aravindsv 0:ba7650f404af 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
aravindsv 0:ba7650f404af 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
aravindsv 0:ba7650f404af 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
aravindsv 0:ba7650f404af 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
aravindsv 0:ba7650f404af 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
aravindsv 0:ba7650f404af 20 * OTHER DEALINGS IN THE SOFTWARE.
aravindsv 0:ba7650f404af 21 *
aravindsv 0:ba7650f404af 22 * Except as contained in this notice, the name of Maxim Integrated
aravindsv 0:ba7650f404af 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
aravindsv 0:ba7650f404af 24 * Products, Inc. Branding Policy.
aravindsv 0:ba7650f404af 25 *
aravindsv 0:ba7650f404af 26 * The mere transfer of this software does not imply any licenses
aravindsv 0:ba7650f404af 27 * of trade secrets, proprietary technology, copyrights, patents,
aravindsv 0:ba7650f404af 28 * trademarks, maskwork rights, or any other form of intellectual
aravindsv 0:ba7650f404af 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
aravindsv 0:ba7650f404af 30 * ownership rights.
aravindsv 0:ba7650f404af 31 *******************************************************************************
aravindsv 0:ba7650f404af 32 */
aravindsv 0:ba7650f404af 33
aravindsv 0:ba7650f404af 34 #include "sleep_api.h"
aravindsv 0:ba7650f404af 35 #include "cmsis.h"
aravindsv 0:ba7650f404af 36 #include "pwrman_regs.h"
aravindsv 0:ba7650f404af 37 #include "pwrseq_regs.h"
aravindsv 0:ba7650f404af 38 #include "ioman_regs.h"
aravindsv 0:ba7650f404af 39 #include "rtc_regs.h"
aravindsv 0:ba7650f404af 40
aravindsv 0:ba7650f404af 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
aravindsv 0:ba7650f404af 42
aravindsv 0:ba7650f404af 43 // Normal wait mode
aravindsv 0:ba7650f404af 44 void sleep(void)
aravindsv 0:ba7650f404af 45 {
aravindsv 0:ba7650f404af 46 // Normal sleep mode for ARM core
aravindsv 0:ba7650f404af 47 SCB->SCR = 0;
aravindsv 0:ba7650f404af 48
aravindsv 0:ba7650f404af 49 __DSB();
aravindsv 0:ba7650f404af 50 __WFI();
aravindsv 0:ba7650f404af 51 }
aravindsv 0:ba7650f404af 52
aravindsv 0:ba7650f404af 53 // Work-around for issue of clearing power sequencer I/O flag
aravindsv 0:ba7650f404af 54 static void clearAllGPIOWUD(void)
aravindsv 0:ba7650f404af 55 {
aravindsv 0:ba7650f404af 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
aravindsv 0:ba7650f404af 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
aravindsv 0:ba7650f404af 58
aravindsv 0:ba7650f404af 59 // I/O must be a wakeup detect to clear
aravindsv 0:ba7650f404af 60 MXC_IOMAN->wud_req0 = 0xffffffff;
aravindsv 0:ba7650f404af 61 MXC_IOMAN->wud_req1 = 0xffffffff;
aravindsv 0:ba7650f404af 62
aravindsv 0:ba7650f404af 63 // Clear all WUDs
aravindsv 0:ba7650f404af 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
aravindsv 0:ba7650f404af 65 MXC_PWRMAN->wud_pulse0 = 1;
aravindsv 0:ba7650f404af 66
aravindsv 0:ba7650f404af 67 // Restore WUD requests
aravindsv 0:ba7650f404af 68 MXC_IOMAN->wud_req0 = wud_req0;
aravindsv 0:ba7650f404af 69 MXC_IOMAN->wud_req1 = wud_req1;
aravindsv 0:ba7650f404af 70 }
aravindsv 0:ba7650f404af 71
aravindsv 0:ba7650f404af 72 // Low-power stop mode
aravindsv 0:ba7650f404af 73 void deepsleep(void)
aravindsv 0:ba7650f404af 74 {
aravindsv 0:ba7650f404af 75 __disable_irq();
aravindsv 0:ba7650f404af 76
aravindsv 0:ba7650f404af 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
aravindsv 0:ba7650f404af 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
aravindsv 0:ba7650f404af 79
aravindsv 0:ba7650f404af 80 // Prepare for LP1
aravindsv 0:ba7650f404af 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
aravindsv 0:ba7650f404af 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
aravindsv 0:ba7650f404af 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
aravindsv 0:ba7650f404af 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
aravindsv 0:ba7650f404af 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
aravindsv 0:ba7650f404af 86 } else {
aravindsv 0:ba7650f404af 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
aravindsv 0:ba7650f404af 88 }
aravindsv 0:ba7650f404af 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
aravindsv 0:ba7650f404af 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
aravindsv 0:ba7650f404af 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
aravindsv 0:ba7650f404af 92 MXC_PWRSEQ->reg0 = reg0;
aravindsv 0:ba7650f404af 93
aravindsv 0:ba7650f404af 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
aravindsv 0:ba7650f404af 95
aravindsv 0:ba7650f404af 96 // Deep sleep for ARM core
aravindsv 0:ba7650f404af 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
aravindsv 0:ba7650f404af 98
aravindsv 0:ba7650f404af 99 // clear latches for wakeup detect
aravindsv 0:ba7650f404af 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
aravindsv 0:ba7650f404af 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
aravindsv 0:ba7650f404af 102 // attempt work-around for I/O flag clearing issue
aravindsv 0:ba7650f404af 103 clearAllGPIOWUD();
aravindsv 0:ba7650f404af 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
aravindsv 0:ba7650f404af 105 }
aravindsv 0:ba7650f404af 106
aravindsv 0:ba7650f404af 107 // Wait for pending RTC transaction
aravindsv 0:ba7650f404af 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
aravindsv 0:ba7650f404af 109
aravindsv 0:ba7650f404af 110 // Ensure that the event register is clear
aravindsv 0:ba7650f404af 111 __SEV(); // set event
aravindsv 0:ba7650f404af 112 __WFE(); // clear event
aravindsv 0:ba7650f404af 113
aravindsv 0:ba7650f404af 114 // Enter LP1
aravindsv 0:ba7650f404af 115 __WFE();
aravindsv 0:ba7650f404af 116 // Woke up from LP1
aravindsv 0:ba7650f404af 117
aravindsv 0:ba7650f404af 118 // The RTC timer does not update until the next tick
aravindsv 0:ba7650f404af 119 uint32_t temp = MXC_RTCTMR->timer;
aravindsv 0:ba7650f404af 120 while (MXC_RTCTMR->timer == temp);
aravindsv 0:ba7650f404af 121
aravindsv 0:ba7650f404af 122 __enable_irq();
aravindsv 0:ba7650f404af 123 }