Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c@0:ba7650f404af, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 02:26:59 2015 +0000
Revision:
0:ba7650f404af
Reduced HSE_STARTUP_TIMEOUT to 500 ms, fixed some compiler warnings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /* mbed Microcontroller Library
aravindsv 0:ba7650f404af 2 * Copyright (c) 2006-2013 ARM Limited
aravindsv 0:ba7650f404af 3 *
aravindsv 0:ba7650f404af 4 * Licensed under the Apache License, Version 2.0 (the "License");
aravindsv 0:ba7650f404af 5 * you may not use this file except in compliance with the License.
aravindsv 0:ba7650f404af 6 * You may obtain a copy of the License at
aravindsv 0:ba7650f404af 7 *
aravindsv 0:ba7650f404af 8 * http://www.apache.org/licenses/LICENSE-2.0
aravindsv 0:ba7650f404af 9 *
aravindsv 0:ba7650f404af 10 * Unless required by applicable law or agreed to in writing, software
aravindsv 0:ba7650f404af 11 * distributed under the License is distributed on an "AS IS" BASIS,
aravindsv 0:ba7650f404af 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
aravindsv 0:ba7650f404af 13 * See the License for the specific language governing permissions and
aravindsv 0:ba7650f404af 14 * limitations under the License.
aravindsv 0:ba7650f404af 15 */
aravindsv 0:ba7650f404af 16 #include "sleep_api.h"
aravindsv 0:ba7650f404af 17 #include "cmsis.h"
aravindsv 0:ba7650f404af 18 #include "PeripheralPins.h"
aravindsv 0:ba7650f404af 19
aravindsv 0:ba7650f404af 20 //Normal wait mode
aravindsv 0:ba7650f404af 21 void sleep(void)
aravindsv 0:ba7650f404af 22 {
aravindsv 0:ba7650f404af 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
aravindsv 0:ba7650f404af 24
aravindsv 0:ba7650f404af 25 //Normal sleep mode for ARM core:
aravindsv 0:ba7650f404af 26 SCB->SCR = 0;
aravindsv 0:ba7650f404af 27 __WFI();
aravindsv 0:ba7650f404af 28 }
aravindsv 0:ba7650f404af 29
aravindsv 0:ba7650f404af 30 //Very low-power stop mode
aravindsv 0:ba7650f404af 31 void deepsleep(void)
aravindsv 0:ba7650f404af 32 {
aravindsv 0:ba7650f404af 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
aravindsv 0:ba7650f404af 34 uint8_t ADC_HSC = 0;
aravindsv 0:ba7650f404af 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
aravindsv 0:ba7650f404af 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
aravindsv 0:ba7650f404af 37 ADC_HSC = 1;
aravindsv 0:ba7650f404af 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
aravindsv 0:ba7650f404af 39 }
aravindsv 0:ba7650f404af 40 }
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42 #if ! defined(TARGET_KL43Z)
aravindsv 0:ba7650f404af 43 //Check if PLL/FLL is enabled:
aravindsv 0:ba7650f404af 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
aravindsv 0:ba7650f404af 45 #endif
aravindsv 0:ba7650f404af 46
aravindsv 0:ba7650f404af 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
aravindsv 0:ba7650f404af 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
aravindsv 0:ba7650f404af 49
aravindsv 0:ba7650f404af 50 //Deep sleep for ARM core:
aravindsv 0:ba7650f404af 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
aravindsv 0:ba7650f404af 52
aravindsv 0:ba7650f404af 53 __WFI();
aravindsv 0:ba7650f404af 54
aravindsv 0:ba7650f404af 55 #if ! defined(TARGET_KL43Z)
aravindsv 0:ba7650f404af 56 //Switch back to PLL as clock source if needed
aravindsv 0:ba7650f404af 57 //The interrupt that woke up the device will run at reduced speed
aravindsv 0:ba7650f404af 58 if (PLL_FLL_en) {
aravindsv 0:ba7650f404af 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
aravindsv 0:ba7650f404af 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
aravindsv 0:ba7650f404af 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
aravindsv 0:ba7650f404af 62 #endif
aravindsv 0:ba7650f404af 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
aravindsv 0:ba7650f404af 64 }
aravindsv 0:ba7650f404af 65 #endif
aravindsv 0:ba7650f404af 66
aravindsv 0:ba7650f404af 67 if (ADC_HSC) {
aravindsv 0:ba7650f404af 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
aravindsv 0:ba7650f404af 69 }
aravindsv 0:ba7650f404af 70 }