Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/core_cm4.h@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**************************************************************************//**
aravindsv 0:ba7650f404af 2 * @file core_cm4.h
aravindsv 0:ba7650f404af 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
aravindsv 0:ba7650f404af 4 * @version V3.20
aravindsv 0:ba7650f404af 5 * @date 25. February 2013
aravindsv 0:ba7650f404af 6 *
aravindsv 0:ba7650f404af 7 * @note
aravindsv 0:ba7650f404af 8 *
aravindsv 0:ba7650f404af 9 ******************************************************************************/
aravindsv 0:ba7650f404af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
aravindsv 0:ba7650f404af 11
aravindsv 0:ba7650f404af 12 All rights reserved.
aravindsv 0:ba7650f404af 13 Redistribution and use in source and binary forms, with or without
aravindsv 0:ba7650f404af 14 modification, are permitted provided that the following conditions are met:
aravindsv 0:ba7650f404af 15 - Redistributions of source code must retain the above copyright
aravindsv 0:ba7650f404af 16 notice, this list of conditions and the following disclaimer.
aravindsv 0:ba7650f404af 17 - Redistributions in binary form must reproduce the above copyright
aravindsv 0:ba7650f404af 18 notice, this list of conditions and the following disclaimer in the
aravindsv 0:ba7650f404af 19 documentation and/or other materials provided with the distribution.
aravindsv 0:ba7650f404af 20 - Neither the name of ARM nor the names of its contributors may be used
aravindsv 0:ba7650f404af 21 to endorse or promote products derived from this software without
aravindsv 0:ba7650f404af 22 specific prior written permission.
aravindsv 0:ba7650f404af 23 *
aravindsv 0:ba7650f404af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
aravindsv 0:ba7650f404af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
aravindsv 0:ba7650f404af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
aravindsv 0:ba7650f404af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
aravindsv 0:ba7650f404af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
aravindsv 0:ba7650f404af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
aravindsv 0:ba7650f404af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
aravindsv 0:ba7650f404af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
aravindsv 0:ba7650f404af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
aravindsv 0:ba7650f404af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
aravindsv 0:ba7650f404af 34 POSSIBILITY OF SUCH DAMAGE.
aravindsv 0:ba7650f404af 35 ---------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 36
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 #if defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 39 #pragma system_include /* treat file as system include file for MISRA check */
aravindsv 0:ba7650f404af 40 #endif
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42 #ifdef __cplusplus
aravindsv 0:ba7650f404af 43 extern "C" {
aravindsv 0:ba7650f404af 44 #endif
aravindsv 0:ba7650f404af 45
aravindsv 0:ba7650f404af 46 #ifndef __CORE_CM4_H_GENERIC
aravindsv 0:ba7650f404af 47 #define __CORE_CM4_H_GENERIC
aravindsv 0:ba7650f404af 48
aravindsv 0:ba7650f404af 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
aravindsv 0:ba7650f404af 50 CMSIS violates the following MISRA-C:2004 rules:
aravindsv 0:ba7650f404af 51
aravindsv 0:ba7650f404af 52 \li Required Rule 8.5, object/function definition in header file.<br>
aravindsv 0:ba7650f404af 53 Function definitions in header files are used to allow 'inlining'.
aravindsv 0:ba7650f404af 54
aravindsv 0:ba7650f404af 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
aravindsv 0:ba7650f404af 56 Unions are used for effective representation of core registers.
aravindsv 0:ba7650f404af 57
aravindsv 0:ba7650f404af 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
aravindsv 0:ba7650f404af 59 Function-like macros are used to allow more efficient code.
aravindsv 0:ba7650f404af 60 */
aravindsv 0:ba7650f404af 61
aravindsv 0:ba7650f404af 62
aravindsv 0:ba7650f404af 63 /*******************************************************************************
aravindsv 0:ba7650f404af 64 * CMSIS definitions
aravindsv 0:ba7650f404af 65 ******************************************************************************/
aravindsv 0:ba7650f404af 66 /** \ingroup Cortex_M4
aravindsv 0:ba7650f404af 67 @{
aravindsv 0:ba7650f404af 68 */
aravindsv 0:ba7650f404af 69
aravindsv 0:ba7650f404af 70 /* CMSIS CM4 definitions */
aravindsv 0:ba7650f404af 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
aravindsv 0:ba7650f404af 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
aravindsv 0:ba7650f404af 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
aravindsv 0:ba7650f404af 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
aravindsv 0:ba7650f404af 75
aravindsv 0:ba7650f404af 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
aravindsv 0:ba7650f404af 77
aravindsv 0:ba7650f404af 78
aravindsv 0:ba7650f404af 79 #if defined ( __CC_ARM )
aravindsv 0:ba7650f404af 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
aravindsv 0:ba7650f404af 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
aravindsv 0:ba7650f404af 82 #define __STATIC_INLINE static __inline
aravindsv 0:ba7650f404af 83
aravindsv 0:ba7650f404af 84 #elif defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
aravindsv 0:ba7650f404af 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
aravindsv 0:ba7650f404af 87 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 88
aravindsv 0:ba7650f404af 89 #elif defined ( __TMS470__ )
aravindsv 0:ba7650f404af 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
aravindsv 0:ba7650f404af 91 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 92
aravindsv 0:ba7650f404af 93 #elif defined ( __GNUC__ )
aravindsv 0:ba7650f404af 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
aravindsv 0:ba7650f404af 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
aravindsv 0:ba7650f404af 96 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 97
aravindsv 0:ba7650f404af 98 #elif defined ( __TASKING__ )
aravindsv 0:ba7650f404af 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
aravindsv 0:ba7650f404af 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
aravindsv 0:ba7650f404af 101 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 102
aravindsv 0:ba7650f404af 103 #endif
aravindsv 0:ba7650f404af 104
aravindsv 0:ba7650f404af 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
aravindsv 0:ba7650f404af 106 */
aravindsv 0:ba7650f404af 107 #if defined ( __CC_ARM )
aravindsv 0:ba7650f404af 108 #if defined __TARGET_FPU_VFP
aravindsv 0:ba7650f404af 109 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 110 #define __FPU_USED 1
aravindsv 0:ba7650f404af 111 #else
aravindsv 0:ba7650f404af 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 113 #define __FPU_USED 0
aravindsv 0:ba7650f404af 114 #endif
aravindsv 0:ba7650f404af 115 #else
aravindsv 0:ba7650f404af 116 #define __FPU_USED 0
aravindsv 0:ba7650f404af 117 #endif
aravindsv 0:ba7650f404af 118
aravindsv 0:ba7650f404af 119 #elif defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 120 #if defined __ARMVFP__
aravindsv 0:ba7650f404af 121 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 122 #define __FPU_USED 1
aravindsv 0:ba7650f404af 123 #else
aravindsv 0:ba7650f404af 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 125 #define __FPU_USED 0
aravindsv 0:ba7650f404af 126 #endif
aravindsv 0:ba7650f404af 127 #else
aravindsv 0:ba7650f404af 128 #define __FPU_USED 0
aravindsv 0:ba7650f404af 129 #endif
aravindsv 0:ba7650f404af 130
aravindsv 0:ba7650f404af 131 #elif defined ( __TMS470__ )
aravindsv 0:ba7650f404af 132 #if defined __TI_VFP_SUPPORT__
aravindsv 0:ba7650f404af 133 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 134 #define __FPU_USED 1
aravindsv 0:ba7650f404af 135 #else
aravindsv 0:ba7650f404af 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 137 #define __FPU_USED 0
aravindsv 0:ba7650f404af 138 #endif
aravindsv 0:ba7650f404af 139 #else
aravindsv 0:ba7650f404af 140 #define __FPU_USED 0
aravindsv 0:ba7650f404af 141 #endif
aravindsv 0:ba7650f404af 142
aravindsv 0:ba7650f404af 143 #elif defined ( __GNUC__ )
aravindsv 0:ba7650f404af 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
aravindsv 0:ba7650f404af 145 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 146 #define __FPU_USED 1
aravindsv 0:ba7650f404af 147 #else
aravindsv 0:ba7650f404af 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 149 #define __FPU_USED 0
aravindsv 0:ba7650f404af 150 #endif
aravindsv 0:ba7650f404af 151 #else
aravindsv 0:ba7650f404af 152 #define __FPU_USED 0
aravindsv 0:ba7650f404af 153 #endif
aravindsv 0:ba7650f404af 154
aravindsv 0:ba7650f404af 155 #elif defined ( __TASKING__ )
aravindsv 0:ba7650f404af 156 #if defined __FPU_VFP__
aravindsv 0:ba7650f404af 157 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 158 #define __FPU_USED 1
aravindsv 0:ba7650f404af 159 #else
aravindsv 0:ba7650f404af 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 161 #define __FPU_USED 0
aravindsv 0:ba7650f404af 162 #endif
aravindsv 0:ba7650f404af 163 #else
aravindsv 0:ba7650f404af 164 #define __FPU_USED 0
aravindsv 0:ba7650f404af 165 #endif
aravindsv 0:ba7650f404af 166 #endif
aravindsv 0:ba7650f404af 167
aravindsv 0:ba7650f404af 168 #include <stdint.h> /* standard types definitions */
aravindsv 0:ba7650f404af 169 #include <core_cmInstr.h> /* Core Instruction Access */
aravindsv 0:ba7650f404af 170 #include <core_cmFunc.h> /* Core Function Access */
aravindsv 0:ba7650f404af 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
aravindsv 0:ba7650f404af 172
aravindsv 0:ba7650f404af 173 #endif /* __CORE_CM4_H_GENERIC */
aravindsv 0:ba7650f404af 174
aravindsv 0:ba7650f404af 175 #ifndef __CMSIS_GENERIC
aravindsv 0:ba7650f404af 176
aravindsv 0:ba7650f404af 177 #ifndef __CORE_CM4_H_DEPENDANT
aravindsv 0:ba7650f404af 178 #define __CORE_CM4_H_DEPENDANT
aravindsv 0:ba7650f404af 179
aravindsv 0:ba7650f404af 180 /* check device defines and use defaults */
aravindsv 0:ba7650f404af 181 #if defined __CHECK_DEVICE_DEFINES
aravindsv 0:ba7650f404af 182 #ifndef __CM4_REV
aravindsv 0:ba7650f404af 183 #define __CM4_REV 0x0000
aravindsv 0:ba7650f404af 184 #warning "__CM4_REV not defined in device header file; using default!"
aravindsv 0:ba7650f404af 185 #endif
aravindsv 0:ba7650f404af 186
aravindsv 0:ba7650f404af 187 #ifndef __FPU_PRESENT
aravindsv 0:ba7650f404af 188 #define __FPU_PRESENT 0
aravindsv 0:ba7650f404af 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
aravindsv 0:ba7650f404af 190 #endif
aravindsv 0:ba7650f404af 191
aravindsv 0:ba7650f404af 192 #ifndef __MPU_PRESENT
aravindsv 0:ba7650f404af 193 #define __MPU_PRESENT 0
aravindsv 0:ba7650f404af 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
aravindsv 0:ba7650f404af 195 #endif
aravindsv 0:ba7650f404af 196
aravindsv 0:ba7650f404af 197 #ifndef __NVIC_PRIO_BITS
aravindsv 0:ba7650f404af 198 #define __NVIC_PRIO_BITS 4
aravindsv 0:ba7650f404af 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
aravindsv 0:ba7650f404af 200 #endif
aravindsv 0:ba7650f404af 201
aravindsv 0:ba7650f404af 202 #ifndef __Vendor_SysTickConfig
aravindsv 0:ba7650f404af 203 #define __Vendor_SysTickConfig 0
aravindsv 0:ba7650f404af 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
aravindsv 0:ba7650f404af 205 #endif
aravindsv 0:ba7650f404af 206 #endif
aravindsv 0:ba7650f404af 207
aravindsv 0:ba7650f404af 208 /* IO definitions (access restrictions to peripheral registers) */
aravindsv 0:ba7650f404af 209 /**
aravindsv 0:ba7650f404af 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
aravindsv 0:ba7650f404af 211
aravindsv 0:ba7650f404af 212 <strong>IO Type Qualifiers</strong> are used
aravindsv 0:ba7650f404af 213 \li to specify the access to peripheral variables.
aravindsv 0:ba7650f404af 214 \li for automatic generation of peripheral register debug information.
aravindsv 0:ba7650f404af 215 */
aravindsv 0:ba7650f404af 216 #ifdef __cplusplus
aravindsv 0:ba7650f404af 217 #define __I volatile /*!< Defines 'read only' permissions */
aravindsv 0:ba7650f404af 218 #else
aravindsv 0:ba7650f404af 219 #define __I volatile const /*!< Defines 'read only' permissions */
aravindsv 0:ba7650f404af 220 #endif
aravindsv 0:ba7650f404af 221 #define __O volatile /*!< Defines 'write only' permissions */
aravindsv 0:ba7650f404af 222 #define __IO volatile /*!< Defines 'read / write' permissions */
aravindsv 0:ba7650f404af 223
aravindsv 0:ba7650f404af 224 /*@} end of group Cortex_M4 */
aravindsv 0:ba7650f404af 225
aravindsv 0:ba7650f404af 226
aravindsv 0:ba7650f404af 227
aravindsv 0:ba7650f404af 228 /*******************************************************************************
aravindsv 0:ba7650f404af 229 * Register Abstraction
aravindsv 0:ba7650f404af 230 Core Register contain:
aravindsv 0:ba7650f404af 231 - Core Register
aravindsv 0:ba7650f404af 232 - Core NVIC Register
aravindsv 0:ba7650f404af 233 - Core SCB Register
aravindsv 0:ba7650f404af 234 - Core SysTick Register
aravindsv 0:ba7650f404af 235 - Core Debug Register
aravindsv 0:ba7650f404af 236 - Core MPU Register
aravindsv 0:ba7650f404af 237 - Core FPU Register
aravindsv 0:ba7650f404af 238 ******************************************************************************/
aravindsv 0:ba7650f404af 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
aravindsv 0:ba7650f404af 240 \brief Type definitions and defines for Cortex-M processor based devices.
aravindsv 0:ba7650f404af 241 */
aravindsv 0:ba7650f404af 242
aravindsv 0:ba7650f404af 243 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 244 \defgroup CMSIS_CORE Status and Control Registers
aravindsv 0:ba7650f404af 245 \brief Core Register type definitions.
aravindsv 0:ba7650f404af 246 @{
aravindsv 0:ba7650f404af 247 */
aravindsv 0:ba7650f404af 248
aravindsv 0:ba7650f404af 249 /** \brief Union type to access the Application Program Status Register (APSR).
aravindsv 0:ba7650f404af 250 */
aravindsv 0:ba7650f404af 251 typedef union
aravindsv 0:ba7650f404af 252 {
aravindsv 0:ba7650f404af 253 struct
aravindsv 0:ba7650f404af 254 {
aravindsv 0:ba7650f404af 255 #if (__CORTEX_M != 0x04)
aravindsv 0:ba7650f404af 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
aravindsv 0:ba7650f404af 257 #else
aravindsv 0:ba7650f404af 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
aravindsv 0:ba7650f404af 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
aravindsv 0:ba7650f404af 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
aravindsv 0:ba7650f404af 261 #endif
aravindsv 0:ba7650f404af 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
aravindsv 0:ba7650f404af 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
aravindsv 0:ba7650f404af 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
aravindsv 0:ba7650f404af 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
aravindsv 0:ba7650f404af 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
aravindsv 0:ba7650f404af 267 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 268 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 269 } APSR_Type;
aravindsv 0:ba7650f404af 270
aravindsv 0:ba7650f404af 271
aravindsv 0:ba7650f404af 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
aravindsv 0:ba7650f404af 273 */
aravindsv 0:ba7650f404af 274 typedef union
aravindsv 0:ba7650f404af 275 {
aravindsv 0:ba7650f404af 276 struct
aravindsv 0:ba7650f404af 277 {
aravindsv 0:ba7650f404af 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
aravindsv 0:ba7650f404af 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
aravindsv 0:ba7650f404af 280 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 281 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 282 } IPSR_Type;
aravindsv 0:ba7650f404af 283
aravindsv 0:ba7650f404af 284
aravindsv 0:ba7650f404af 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
aravindsv 0:ba7650f404af 286 */
aravindsv 0:ba7650f404af 287 typedef union
aravindsv 0:ba7650f404af 288 {
aravindsv 0:ba7650f404af 289 struct
aravindsv 0:ba7650f404af 290 {
aravindsv 0:ba7650f404af 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
aravindsv 0:ba7650f404af 292 #if (__CORTEX_M != 0x04)
aravindsv 0:ba7650f404af 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
aravindsv 0:ba7650f404af 294 #else
aravindsv 0:ba7650f404af 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
aravindsv 0:ba7650f404af 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
aravindsv 0:ba7650f404af 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
aravindsv 0:ba7650f404af 298 #endif
aravindsv 0:ba7650f404af 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
aravindsv 0:ba7650f404af 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
aravindsv 0:ba7650f404af 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
aravindsv 0:ba7650f404af 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
aravindsv 0:ba7650f404af 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
aravindsv 0:ba7650f404af 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
aravindsv 0:ba7650f404af 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
aravindsv 0:ba7650f404af 306 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 307 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 308 } xPSR_Type;
aravindsv 0:ba7650f404af 309
aravindsv 0:ba7650f404af 310
aravindsv 0:ba7650f404af 311 /** \brief Union type to access the Control Registers (CONTROL).
aravindsv 0:ba7650f404af 312 */
aravindsv 0:ba7650f404af 313 typedef union
aravindsv 0:ba7650f404af 314 {
aravindsv 0:ba7650f404af 315 struct
aravindsv 0:ba7650f404af 316 {
aravindsv 0:ba7650f404af 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
aravindsv 0:ba7650f404af 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
aravindsv 0:ba7650f404af 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
aravindsv 0:ba7650f404af 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
aravindsv 0:ba7650f404af 321 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 322 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 323 } CONTROL_Type;
aravindsv 0:ba7650f404af 324
aravindsv 0:ba7650f404af 325 /*@} end of group CMSIS_CORE */
aravindsv 0:ba7650f404af 326
aravindsv 0:ba7650f404af 327
aravindsv 0:ba7650f404af 328 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
aravindsv 0:ba7650f404af 330 \brief Type definitions for the NVIC Registers
aravindsv 0:ba7650f404af 331 @{
aravindsv 0:ba7650f404af 332 */
aravindsv 0:ba7650f404af 333
aravindsv 0:ba7650f404af 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
aravindsv 0:ba7650f404af 335 */
aravindsv 0:ba7650f404af 336 typedef struct
aravindsv 0:ba7650f404af 337 {
aravindsv 0:ba7650f404af 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
aravindsv 0:ba7650f404af 339 uint32_t RESERVED0[24];
aravindsv 0:ba7650f404af 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
aravindsv 0:ba7650f404af 341 uint32_t RSERVED1[24];
aravindsv 0:ba7650f404af 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
aravindsv 0:ba7650f404af 343 uint32_t RESERVED2[24];
aravindsv 0:ba7650f404af 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
aravindsv 0:ba7650f404af 345 uint32_t RESERVED3[24];
aravindsv 0:ba7650f404af 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
aravindsv 0:ba7650f404af 347 uint32_t RESERVED4[56];
aravindsv 0:ba7650f404af 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
aravindsv 0:ba7650f404af 349 uint32_t RESERVED5[644];
aravindsv 0:ba7650f404af 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
aravindsv 0:ba7650f404af 351 } NVIC_Type;
aravindsv 0:ba7650f404af 352
aravindsv 0:ba7650f404af 353 /* Software Triggered Interrupt Register Definitions */
aravindsv 0:ba7650f404af 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
aravindsv 0:ba7650f404af 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
aravindsv 0:ba7650f404af 356
aravindsv 0:ba7650f404af 357 /*@} end of group CMSIS_NVIC */
aravindsv 0:ba7650f404af 358
aravindsv 0:ba7650f404af 359
aravindsv 0:ba7650f404af 360 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 361 \defgroup CMSIS_SCB System Control Block (SCB)
aravindsv 0:ba7650f404af 362 \brief Type definitions for the System Control Block Registers
aravindsv 0:ba7650f404af 363 @{
aravindsv 0:ba7650f404af 364 */
aravindsv 0:ba7650f404af 365
aravindsv 0:ba7650f404af 366 /** \brief Structure type to access the System Control Block (SCB).
aravindsv 0:ba7650f404af 367 */
aravindsv 0:ba7650f404af 368 typedef struct
aravindsv 0:ba7650f404af 369 {
aravindsv 0:ba7650f404af 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
aravindsv 0:ba7650f404af 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
aravindsv 0:ba7650f404af 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
aravindsv 0:ba7650f404af 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
aravindsv 0:ba7650f404af 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
aravindsv 0:ba7650f404af 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
aravindsv 0:ba7650f404af 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
aravindsv 0:ba7650f404af 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
aravindsv 0:ba7650f404af 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
aravindsv 0:ba7650f404af 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
aravindsv 0:ba7650f404af 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
aravindsv 0:ba7650f404af 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
aravindsv 0:ba7650f404af 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
aravindsv 0:ba7650f404af 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
aravindsv 0:ba7650f404af 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
aravindsv 0:ba7650f404af 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
aravindsv 0:ba7650f404af 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
aravindsv 0:ba7650f404af 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
aravindsv 0:ba7650f404af 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
aravindsv 0:ba7650f404af 389 uint32_t RESERVED0[5];
aravindsv 0:ba7650f404af 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
aravindsv 0:ba7650f404af 391 } SCB_Type;
aravindsv 0:ba7650f404af 392
aravindsv 0:ba7650f404af 393 /* SCB CPUID Register Definitions */
aravindsv 0:ba7650f404af 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
aravindsv 0:ba7650f404af 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
aravindsv 0:ba7650f404af 396
aravindsv 0:ba7650f404af 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
aravindsv 0:ba7650f404af 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
aravindsv 0:ba7650f404af 399
aravindsv 0:ba7650f404af 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
aravindsv 0:ba7650f404af 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
aravindsv 0:ba7650f404af 402
aravindsv 0:ba7650f404af 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
aravindsv 0:ba7650f404af 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
aravindsv 0:ba7650f404af 405
aravindsv 0:ba7650f404af 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
aravindsv 0:ba7650f404af 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
aravindsv 0:ba7650f404af 408
aravindsv 0:ba7650f404af 409 /* SCB Interrupt Control State Register Definitions */
aravindsv 0:ba7650f404af 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
aravindsv 0:ba7650f404af 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
aravindsv 0:ba7650f404af 412
aravindsv 0:ba7650f404af 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
aravindsv 0:ba7650f404af 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
aravindsv 0:ba7650f404af 415
aravindsv 0:ba7650f404af 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
aravindsv 0:ba7650f404af 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
aravindsv 0:ba7650f404af 418
aravindsv 0:ba7650f404af 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
aravindsv 0:ba7650f404af 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
aravindsv 0:ba7650f404af 421
aravindsv 0:ba7650f404af 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
aravindsv 0:ba7650f404af 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
aravindsv 0:ba7650f404af 424
aravindsv 0:ba7650f404af 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
aravindsv 0:ba7650f404af 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
aravindsv 0:ba7650f404af 427
aravindsv 0:ba7650f404af 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
aravindsv 0:ba7650f404af 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
aravindsv 0:ba7650f404af 430
aravindsv 0:ba7650f404af 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
aravindsv 0:ba7650f404af 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
aravindsv 0:ba7650f404af 433
aravindsv 0:ba7650f404af 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
aravindsv 0:ba7650f404af 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
aravindsv 0:ba7650f404af 436
aravindsv 0:ba7650f404af 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
aravindsv 0:ba7650f404af 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
aravindsv 0:ba7650f404af 439
aravindsv 0:ba7650f404af 440 /* SCB Vector Table Offset Register Definitions */
aravindsv 0:ba7650f404af 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
aravindsv 0:ba7650f404af 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
aravindsv 0:ba7650f404af 443
aravindsv 0:ba7650f404af 444 /* SCB Application Interrupt and Reset Control Register Definitions */
aravindsv 0:ba7650f404af 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
aravindsv 0:ba7650f404af 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
aravindsv 0:ba7650f404af 447
aravindsv 0:ba7650f404af 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
aravindsv 0:ba7650f404af 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
aravindsv 0:ba7650f404af 450
aravindsv 0:ba7650f404af 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
aravindsv 0:ba7650f404af 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
aravindsv 0:ba7650f404af 453
aravindsv 0:ba7650f404af 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
aravindsv 0:ba7650f404af 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
aravindsv 0:ba7650f404af 456
aravindsv 0:ba7650f404af 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
aravindsv 0:ba7650f404af 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
aravindsv 0:ba7650f404af 459
aravindsv 0:ba7650f404af 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
aravindsv 0:ba7650f404af 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
aravindsv 0:ba7650f404af 462
aravindsv 0:ba7650f404af 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
aravindsv 0:ba7650f404af 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
aravindsv 0:ba7650f404af 465
aravindsv 0:ba7650f404af 466 /* SCB System Control Register Definitions */
aravindsv 0:ba7650f404af 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
aravindsv 0:ba7650f404af 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
aravindsv 0:ba7650f404af 469
aravindsv 0:ba7650f404af 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
aravindsv 0:ba7650f404af 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
aravindsv 0:ba7650f404af 472
aravindsv 0:ba7650f404af 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
aravindsv 0:ba7650f404af 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
aravindsv 0:ba7650f404af 475
aravindsv 0:ba7650f404af 476 /* SCB Configuration Control Register Definitions */
aravindsv 0:ba7650f404af 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
aravindsv 0:ba7650f404af 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
aravindsv 0:ba7650f404af 479
aravindsv 0:ba7650f404af 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
aravindsv 0:ba7650f404af 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
aravindsv 0:ba7650f404af 482
aravindsv 0:ba7650f404af 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
aravindsv 0:ba7650f404af 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
aravindsv 0:ba7650f404af 485
aravindsv 0:ba7650f404af 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
aravindsv 0:ba7650f404af 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
aravindsv 0:ba7650f404af 488
aravindsv 0:ba7650f404af 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
aravindsv 0:ba7650f404af 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
aravindsv 0:ba7650f404af 491
aravindsv 0:ba7650f404af 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
aravindsv 0:ba7650f404af 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
aravindsv 0:ba7650f404af 494
aravindsv 0:ba7650f404af 495 /* SCB System Handler Control and State Register Definitions */
aravindsv 0:ba7650f404af 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
aravindsv 0:ba7650f404af 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
aravindsv 0:ba7650f404af 498
aravindsv 0:ba7650f404af 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
aravindsv 0:ba7650f404af 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
aravindsv 0:ba7650f404af 501
aravindsv 0:ba7650f404af 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
aravindsv 0:ba7650f404af 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
aravindsv 0:ba7650f404af 504
aravindsv 0:ba7650f404af 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
aravindsv 0:ba7650f404af 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
aravindsv 0:ba7650f404af 507
aravindsv 0:ba7650f404af 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
aravindsv 0:ba7650f404af 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
aravindsv 0:ba7650f404af 510
aravindsv 0:ba7650f404af 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
aravindsv 0:ba7650f404af 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
aravindsv 0:ba7650f404af 513
aravindsv 0:ba7650f404af 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
aravindsv 0:ba7650f404af 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
aravindsv 0:ba7650f404af 516
aravindsv 0:ba7650f404af 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
aravindsv 0:ba7650f404af 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
aravindsv 0:ba7650f404af 519
aravindsv 0:ba7650f404af 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
aravindsv 0:ba7650f404af 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
aravindsv 0:ba7650f404af 522
aravindsv 0:ba7650f404af 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
aravindsv 0:ba7650f404af 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
aravindsv 0:ba7650f404af 525
aravindsv 0:ba7650f404af 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
aravindsv 0:ba7650f404af 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
aravindsv 0:ba7650f404af 528
aravindsv 0:ba7650f404af 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
aravindsv 0:ba7650f404af 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
aravindsv 0:ba7650f404af 531
aravindsv 0:ba7650f404af 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
aravindsv 0:ba7650f404af 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
aravindsv 0:ba7650f404af 534
aravindsv 0:ba7650f404af 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
aravindsv 0:ba7650f404af 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
aravindsv 0:ba7650f404af 537
aravindsv 0:ba7650f404af 538 /* SCB Configurable Fault Status Registers Definitions */
aravindsv 0:ba7650f404af 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
aravindsv 0:ba7650f404af 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
aravindsv 0:ba7650f404af 541
aravindsv 0:ba7650f404af 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
aravindsv 0:ba7650f404af 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
aravindsv 0:ba7650f404af 544
aravindsv 0:ba7650f404af 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
aravindsv 0:ba7650f404af 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
aravindsv 0:ba7650f404af 547
aravindsv 0:ba7650f404af 548 /* SCB Hard Fault Status Registers Definitions */
aravindsv 0:ba7650f404af 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
aravindsv 0:ba7650f404af 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
aravindsv 0:ba7650f404af 551
aravindsv 0:ba7650f404af 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
aravindsv 0:ba7650f404af 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
aravindsv 0:ba7650f404af 554
aravindsv 0:ba7650f404af 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
aravindsv 0:ba7650f404af 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
aravindsv 0:ba7650f404af 557
aravindsv 0:ba7650f404af 558 /* SCB Debug Fault Status Register Definitions */
aravindsv 0:ba7650f404af 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
aravindsv 0:ba7650f404af 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
aravindsv 0:ba7650f404af 561
aravindsv 0:ba7650f404af 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
aravindsv 0:ba7650f404af 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
aravindsv 0:ba7650f404af 564
aravindsv 0:ba7650f404af 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
aravindsv 0:ba7650f404af 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
aravindsv 0:ba7650f404af 567
aravindsv 0:ba7650f404af 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
aravindsv 0:ba7650f404af 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
aravindsv 0:ba7650f404af 570
aravindsv 0:ba7650f404af 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
aravindsv 0:ba7650f404af 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
aravindsv 0:ba7650f404af 573
aravindsv 0:ba7650f404af 574 /*@} end of group CMSIS_SCB */
aravindsv 0:ba7650f404af 575
aravindsv 0:ba7650f404af 576
aravindsv 0:ba7650f404af 577 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
aravindsv 0:ba7650f404af 579 \brief Type definitions for the System Control and ID Register not in the SCB
aravindsv 0:ba7650f404af 580 @{
aravindsv 0:ba7650f404af 581 */
aravindsv 0:ba7650f404af 582
aravindsv 0:ba7650f404af 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
aravindsv 0:ba7650f404af 584 */
aravindsv 0:ba7650f404af 585 typedef struct
aravindsv 0:ba7650f404af 586 {
aravindsv 0:ba7650f404af 587 uint32_t RESERVED0[1];
aravindsv 0:ba7650f404af 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
aravindsv 0:ba7650f404af 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
aravindsv 0:ba7650f404af 590 } SCnSCB_Type;
aravindsv 0:ba7650f404af 591
aravindsv 0:ba7650f404af 592 /* Interrupt Controller Type Register Definitions */
aravindsv 0:ba7650f404af 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
aravindsv 0:ba7650f404af 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
aravindsv 0:ba7650f404af 595
aravindsv 0:ba7650f404af 596 /* Auxiliary Control Register Definitions */
aravindsv 0:ba7650f404af 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
aravindsv 0:ba7650f404af 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
aravindsv 0:ba7650f404af 599
aravindsv 0:ba7650f404af 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
aravindsv 0:ba7650f404af 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
aravindsv 0:ba7650f404af 602
aravindsv 0:ba7650f404af 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
aravindsv 0:ba7650f404af 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
aravindsv 0:ba7650f404af 605
aravindsv 0:ba7650f404af 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
aravindsv 0:ba7650f404af 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
aravindsv 0:ba7650f404af 608
aravindsv 0:ba7650f404af 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
aravindsv 0:ba7650f404af 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
aravindsv 0:ba7650f404af 611
aravindsv 0:ba7650f404af 612 /*@} end of group CMSIS_SCnotSCB */
aravindsv 0:ba7650f404af 613
aravindsv 0:ba7650f404af 614
aravindsv 0:ba7650f404af 615 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
aravindsv 0:ba7650f404af 617 \brief Type definitions for the System Timer Registers.
aravindsv 0:ba7650f404af 618 @{
aravindsv 0:ba7650f404af 619 */
aravindsv 0:ba7650f404af 620
aravindsv 0:ba7650f404af 621 /** \brief Structure type to access the System Timer (SysTick).
aravindsv 0:ba7650f404af 622 */
aravindsv 0:ba7650f404af 623 typedef struct
aravindsv 0:ba7650f404af 624 {
aravindsv 0:ba7650f404af 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
aravindsv 0:ba7650f404af 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
aravindsv 0:ba7650f404af 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
aravindsv 0:ba7650f404af 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
aravindsv 0:ba7650f404af 629 } SysTick_Type;
aravindsv 0:ba7650f404af 630
aravindsv 0:ba7650f404af 631 /* SysTick Control / Status Register Definitions */
aravindsv 0:ba7650f404af 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
aravindsv 0:ba7650f404af 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
aravindsv 0:ba7650f404af 634
aravindsv 0:ba7650f404af 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
aravindsv 0:ba7650f404af 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
aravindsv 0:ba7650f404af 637
aravindsv 0:ba7650f404af 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
aravindsv 0:ba7650f404af 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
aravindsv 0:ba7650f404af 640
aravindsv 0:ba7650f404af 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
aravindsv 0:ba7650f404af 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
aravindsv 0:ba7650f404af 643
aravindsv 0:ba7650f404af 644 /* SysTick Reload Register Definitions */
aravindsv 0:ba7650f404af 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
aravindsv 0:ba7650f404af 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
aravindsv 0:ba7650f404af 647
aravindsv 0:ba7650f404af 648 /* SysTick Current Register Definitions */
aravindsv 0:ba7650f404af 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
aravindsv 0:ba7650f404af 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
aravindsv 0:ba7650f404af 651
aravindsv 0:ba7650f404af 652 /* SysTick Calibration Register Definitions */
aravindsv 0:ba7650f404af 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
aravindsv 0:ba7650f404af 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
aravindsv 0:ba7650f404af 655
aravindsv 0:ba7650f404af 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
aravindsv 0:ba7650f404af 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
aravindsv 0:ba7650f404af 658
aravindsv 0:ba7650f404af 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
aravindsv 0:ba7650f404af 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
aravindsv 0:ba7650f404af 661
aravindsv 0:ba7650f404af 662 /*@} end of group CMSIS_SysTick */
aravindsv 0:ba7650f404af 663
aravindsv 0:ba7650f404af 664
aravindsv 0:ba7650f404af 665 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
aravindsv 0:ba7650f404af 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
aravindsv 0:ba7650f404af 668 @{
aravindsv 0:ba7650f404af 669 */
aravindsv 0:ba7650f404af 670
aravindsv 0:ba7650f404af 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
aravindsv 0:ba7650f404af 672 */
aravindsv 0:ba7650f404af 673 typedef struct
aravindsv 0:ba7650f404af 674 {
aravindsv 0:ba7650f404af 675 __O union
aravindsv 0:ba7650f404af 676 {
aravindsv 0:ba7650f404af 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
aravindsv 0:ba7650f404af 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
aravindsv 0:ba7650f404af 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
aravindsv 0:ba7650f404af 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
aravindsv 0:ba7650f404af 681 uint32_t RESERVED0[864];
aravindsv 0:ba7650f404af 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
aravindsv 0:ba7650f404af 683 uint32_t RESERVED1[15];
aravindsv 0:ba7650f404af 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
aravindsv 0:ba7650f404af 685 uint32_t RESERVED2[15];
aravindsv 0:ba7650f404af 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
aravindsv 0:ba7650f404af 687 uint32_t RESERVED3[29];
aravindsv 0:ba7650f404af 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
aravindsv 0:ba7650f404af 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
aravindsv 0:ba7650f404af 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
aravindsv 0:ba7650f404af 691 uint32_t RESERVED4[43];
aravindsv 0:ba7650f404af 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
aravindsv 0:ba7650f404af 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
aravindsv 0:ba7650f404af 694 uint32_t RESERVED5[6];
aravindsv 0:ba7650f404af 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
aravindsv 0:ba7650f404af 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
aravindsv 0:ba7650f404af 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
aravindsv 0:ba7650f404af 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
aravindsv 0:ba7650f404af 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
aravindsv 0:ba7650f404af 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
aravindsv 0:ba7650f404af 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
aravindsv 0:ba7650f404af 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
aravindsv 0:ba7650f404af 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
aravindsv 0:ba7650f404af 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
aravindsv 0:ba7650f404af 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
aravindsv 0:ba7650f404af 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
aravindsv 0:ba7650f404af 707 } ITM_Type;
aravindsv 0:ba7650f404af 708
aravindsv 0:ba7650f404af 709 /* ITM Trace Privilege Register Definitions */
aravindsv 0:ba7650f404af 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
aravindsv 0:ba7650f404af 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
aravindsv 0:ba7650f404af 712
aravindsv 0:ba7650f404af 713 /* ITM Trace Control Register Definitions */
aravindsv 0:ba7650f404af 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
aravindsv 0:ba7650f404af 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
aravindsv 0:ba7650f404af 716
aravindsv 0:ba7650f404af 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
aravindsv 0:ba7650f404af 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
aravindsv 0:ba7650f404af 719
aravindsv 0:ba7650f404af 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
aravindsv 0:ba7650f404af 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
aravindsv 0:ba7650f404af 722
aravindsv 0:ba7650f404af 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
aravindsv 0:ba7650f404af 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
aravindsv 0:ba7650f404af 725
aravindsv 0:ba7650f404af 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
aravindsv 0:ba7650f404af 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
aravindsv 0:ba7650f404af 728
aravindsv 0:ba7650f404af 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
aravindsv 0:ba7650f404af 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
aravindsv 0:ba7650f404af 731
aravindsv 0:ba7650f404af 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
aravindsv 0:ba7650f404af 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
aravindsv 0:ba7650f404af 734
aravindsv 0:ba7650f404af 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
aravindsv 0:ba7650f404af 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
aravindsv 0:ba7650f404af 737
aravindsv 0:ba7650f404af 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
aravindsv 0:ba7650f404af 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
aravindsv 0:ba7650f404af 740
aravindsv 0:ba7650f404af 741 /* ITM Integration Write Register Definitions */
aravindsv 0:ba7650f404af 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
aravindsv 0:ba7650f404af 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
aravindsv 0:ba7650f404af 744
aravindsv 0:ba7650f404af 745 /* ITM Integration Read Register Definitions */
aravindsv 0:ba7650f404af 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
aravindsv 0:ba7650f404af 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
aravindsv 0:ba7650f404af 748
aravindsv 0:ba7650f404af 749 /* ITM Integration Mode Control Register Definitions */
aravindsv 0:ba7650f404af 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
aravindsv 0:ba7650f404af 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
aravindsv 0:ba7650f404af 752
aravindsv 0:ba7650f404af 753 /* ITM Lock Status Register Definitions */
aravindsv 0:ba7650f404af 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
aravindsv 0:ba7650f404af 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
aravindsv 0:ba7650f404af 756
aravindsv 0:ba7650f404af 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
aravindsv 0:ba7650f404af 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
aravindsv 0:ba7650f404af 759
aravindsv 0:ba7650f404af 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
aravindsv 0:ba7650f404af 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
aravindsv 0:ba7650f404af 762
aravindsv 0:ba7650f404af 763 /*@}*/ /* end of group CMSIS_ITM */
aravindsv 0:ba7650f404af 764
aravindsv 0:ba7650f404af 765
aravindsv 0:ba7650f404af 766 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
aravindsv 0:ba7650f404af 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
aravindsv 0:ba7650f404af 769 @{
aravindsv 0:ba7650f404af 770 */
aravindsv 0:ba7650f404af 771
aravindsv 0:ba7650f404af 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
aravindsv 0:ba7650f404af 773 */
aravindsv 0:ba7650f404af 774 typedef struct
aravindsv 0:ba7650f404af 775 {
aravindsv 0:ba7650f404af 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
aravindsv 0:ba7650f404af 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
aravindsv 0:ba7650f404af 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
aravindsv 0:ba7650f404af 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
aravindsv 0:ba7650f404af 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
aravindsv 0:ba7650f404af 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
aravindsv 0:ba7650f404af 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
aravindsv 0:ba7650f404af 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
aravindsv 0:ba7650f404af 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
aravindsv 0:ba7650f404af 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
aravindsv 0:ba7650f404af 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
aravindsv 0:ba7650f404af 787 uint32_t RESERVED0[1];
aravindsv 0:ba7650f404af 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
aravindsv 0:ba7650f404af 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
aravindsv 0:ba7650f404af 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
aravindsv 0:ba7650f404af 791 uint32_t RESERVED1[1];
aravindsv 0:ba7650f404af 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
aravindsv 0:ba7650f404af 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
aravindsv 0:ba7650f404af 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
aravindsv 0:ba7650f404af 795 uint32_t RESERVED2[1];
aravindsv 0:ba7650f404af 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
aravindsv 0:ba7650f404af 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
aravindsv 0:ba7650f404af 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
aravindsv 0:ba7650f404af 799 } DWT_Type;
aravindsv 0:ba7650f404af 800
aravindsv 0:ba7650f404af 801 /* DWT Control Register Definitions */
aravindsv 0:ba7650f404af 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
aravindsv 0:ba7650f404af 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
aravindsv 0:ba7650f404af 804
aravindsv 0:ba7650f404af 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
aravindsv 0:ba7650f404af 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
aravindsv 0:ba7650f404af 807
aravindsv 0:ba7650f404af 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
aravindsv 0:ba7650f404af 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
aravindsv 0:ba7650f404af 810
aravindsv 0:ba7650f404af 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
aravindsv 0:ba7650f404af 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
aravindsv 0:ba7650f404af 813
aravindsv 0:ba7650f404af 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
aravindsv 0:ba7650f404af 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
aravindsv 0:ba7650f404af 816
aravindsv 0:ba7650f404af 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
aravindsv 0:ba7650f404af 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
aravindsv 0:ba7650f404af 819
aravindsv 0:ba7650f404af 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
aravindsv 0:ba7650f404af 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
aravindsv 0:ba7650f404af 822
aravindsv 0:ba7650f404af 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
aravindsv 0:ba7650f404af 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
aravindsv 0:ba7650f404af 825
aravindsv 0:ba7650f404af 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
aravindsv 0:ba7650f404af 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
aravindsv 0:ba7650f404af 828
aravindsv 0:ba7650f404af 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
aravindsv 0:ba7650f404af 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
aravindsv 0:ba7650f404af 831
aravindsv 0:ba7650f404af 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
aravindsv 0:ba7650f404af 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
aravindsv 0:ba7650f404af 834
aravindsv 0:ba7650f404af 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
aravindsv 0:ba7650f404af 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
aravindsv 0:ba7650f404af 837
aravindsv 0:ba7650f404af 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
aravindsv 0:ba7650f404af 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
aravindsv 0:ba7650f404af 840
aravindsv 0:ba7650f404af 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
aravindsv 0:ba7650f404af 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
aravindsv 0:ba7650f404af 843
aravindsv 0:ba7650f404af 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
aravindsv 0:ba7650f404af 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
aravindsv 0:ba7650f404af 846
aravindsv 0:ba7650f404af 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
aravindsv 0:ba7650f404af 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
aravindsv 0:ba7650f404af 849
aravindsv 0:ba7650f404af 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
aravindsv 0:ba7650f404af 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
aravindsv 0:ba7650f404af 852
aravindsv 0:ba7650f404af 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
aravindsv 0:ba7650f404af 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
aravindsv 0:ba7650f404af 855
aravindsv 0:ba7650f404af 856 /* DWT CPI Count Register Definitions */
aravindsv 0:ba7650f404af 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
aravindsv 0:ba7650f404af 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
aravindsv 0:ba7650f404af 859
aravindsv 0:ba7650f404af 860 /* DWT Exception Overhead Count Register Definitions */
aravindsv 0:ba7650f404af 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
aravindsv 0:ba7650f404af 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
aravindsv 0:ba7650f404af 863
aravindsv 0:ba7650f404af 864 /* DWT Sleep Count Register Definitions */
aravindsv 0:ba7650f404af 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
aravindsv 0:ba7650f404af 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
aravindsv 0:ba7650f404af 867
aravindsv 0:ba7650f404af 868 /* DWT LSU Count Register Definitions */
aravindsv 0:ba7650f404af 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
aravindsv 0:ba7650f404af 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
aravindsv 0:ba7650f404af 871
aravindsv 0:ba7650f404af 872 /* DWT Folded-instruction Count Register Definitions */
aravindsv 0:ba7650f404af 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
aravindsv 0:ba7650f404af 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
aravindsv 0:ba7650f404af 875
aravindsv 0:ba7650f404af 876 /* DWT Comparator Mask Register Definitions */
aravindsv 0:ba7650f404af 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
aravindsv 0:ba7650f404af 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
aravindsv 0:ba7650f404af 879
aravindsv 0:ba7650f404af 880 /* DWT Comparator Function Register Definitions */
aravindsv 0:ba7650f404af 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
aravindsv 0:ba7650f404af 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
aravindsv 0:ba7650f404af 883
aravindsv 0:ba7650f404af 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
aravindsv 0:ba7650f404af 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
aravindsv 0:ba7650f404af 886
aravindsv 0:ba7650f404af 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
aravindsv 0:ba7650f404af 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
aravindsv 0:ba7650f404af 889
aravindsv 0:ba7650f404af 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
aravindsv 0:ba7650f404af 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
aravindsv 0:ba7650f404af 892
aravindsv 0:ba7650f404af 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
aravindsv 0:ba7650f404af 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
aravindsv 0:ba7650f404af 895
aravindsv 0:ba7650f404af 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
aravindsv 0:ba7650f404af 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
aravindsv 0:ba7650f404af 898
aravindsv 0:ba7650f404af 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
aravindsv 0:ba7650f404af 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
aravindsv 0:ba7650f404af 901
aravindsv 0:ba7650f404af 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
aravindsv 0:ba7650f404af 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
aravindsv 0:ba7650f404af 904
aravindsv 0:ba7650f404af 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
aravindsv 0:ba7650f404af 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
aravindsv 0:ba7650f404af 907
aravindsv 0:ba7650f404af 908 /*@}*/ /* end of group CMSIS_DWT */
aravindsv 0:ba7650f404af 909
aravindsv 0:ba7650f404af 910
aravindsv 0:ba7650f404af 911 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
aravindsv 0:ba7650f404af 913 \brief Type definitions for the Trace Port Interface (TPI)
aravindsv 0:ba7650f404af 914 @{
aravindsv 0:ba7650f404af 915 */
aravindsv 0:ba7650f404af 916
aravindsv 0:ba7650f404af 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
aravindsv 0:ba7650f404af 918 */
aravindsv 0:ba7650f404af 919 typedef struct
aravindsv 0:ba7650f404af 920 {
aravindsv 0:ba7650f404af 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
aravindsv 0:ba7650f404af 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
aravindsv 0:ba7650f404af 923 uint32_t RESERVED0[2];
aravindsv 0:ba7650f404af 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
aravindsv 0:ba7650f404af 925 uint32_t RESERVED1[55];
aravindsv 0:ba7650f404af 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
aravindsv 0:ba7650f404af 927 uint32_t RESERVED2[131];
aravindsv 0:ba7650f404af 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
aravindsv 0:ba7650f404af 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
aravindsv 0:ba7650f404af 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
aravindsv 0:ba7650f404af 931 uint32_t RESERVED3[759];
aravindsv 0:ba7650f404af 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
aravindsv 0:ba7650f404af 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
aravindsv 0:ba7650f404af 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
aravindsv 0:ba7650f404af 935 uint32_t RESERVED4[1];
aravindsv 0:ba7650f404af 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
aravindsv 0:ba7650f404af 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
aravindsv 0:ba7650f404af 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
aravindsv 0:ba7650f404af 939 uint32_t RESERVED5[39];
aravindsv 0:ba7650f404af 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
aravindsv 0:ba7650f404af 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
aravindsv 0:ba7650f404af 942 uint32_t RESERVED7[8];
aravindsv 0:ba7650f404af 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
aravindsv 0:ba7650f404af 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
aravindsv 0:ba7650f404af 945 } TPI_Type;
aravindsv 0:ba7650f404af 946
aravindsv 0:ba7650f404af 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
aravindsv 0:ba7650f404af 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
aravindsv 0:ba7650f404af 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
aravindsv 0:ba7650f404af 950
aravindsv 0:ba7650f404af 951 /* TPI Selected Pin Protocol Register Definitions */
aravindsv 0:ba7650f404af 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
aravindsv 0:ba7650f404af 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
aravindsv 0:ba7650f404af 954
aravindsv 0:ba7650f404af 955 /* TPI Formatter and Flush Status Register Definitions */
aravindsv 0:ba7650f404af 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
aravindsv 0:ba7650f404af 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
aravindsv 0:ba7650f404af 958
aravindsv 0:ba7650f404af 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
aravindsv 0:ba7650f404af 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
aravindsv 0:ba7650f404af 961
aravindsv 0:ba7650f404af 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
aravindsv 0:ba7650f404af 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
aravindsv 0:ba7650f404af 964
aravindsv 0:ba7650f404af 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
aravindsv 0:ba7650f404af 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
aravindsv 0:ba7650f404af 967
aravindsv 0:ba7650f404af 968 /* TPI Formatter and Flush Control Register Definitions */
aravindsv 0:ba7650f404af 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
aravindsv 0:ba7650f404af 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
aravindsv 0:ba7650f404af 971
aravindsv 0:ba7650f404af 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
aravindsv 0:ba7650f404af 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
aravindsv 0:ba7650f404af 974
aravindsv 0:ba7650f404af 975 /* TPI TRIGGER Register Definitions */
aravindsv 0:ba7650f404af 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
aravindsv 0:ba7650f404af 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
aravindsv 0:ba7650f404af 978
aravindsv 0:ba7650f404af 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
aravindsv 0:ba7650f404af 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
aravindsv 0:ba7650f404af 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
aravindsv 0:ba7650f404af 982
aravindsv 0:ba7650f404af 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
aravindsv 0:ba7650f404af 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
aravindsv 0:ba7650f404af 985
aravindsv 0:ba7650f404af 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
aravindsv 0:ba7650f404af 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
aravindsv 0:ba7650f404af 988
aravindsv 0:ba7650f404af 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
aravindsv 0:ba7650f404af 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
aravindsv 0:ba7650f404af 991
aravindsv 0:ba7650f404af 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
aravindsv 0:ba7650f404af 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
aravindsv 0:ba7650f404af 994
aravindsv 0:ba7650f404af 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
aravindsv 0:ba7650f404af 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
aravindsv 0:ba7650f404af 997
aravindsv 0:ba7650f404af 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
aravindsv 0:ba7650f404af 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
aravindsv 0:ba7650f404af 1000
aravindsv 0:ba7650f404af 1001 /* TPI ITATBCTR2 Register Definitions */
aravindsv 0:ba7650f404af 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
aravindsv 0:ba7650f404af 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
aravindsv 0:ba7650f404af 1004
aravindsv 0:ba7650f404af 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
aravindsv 0:ba7650f404af 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
aravindsv 0:ba7650f404af 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
aravindsv 0:ba7650f404af 1008
aravindsv 0:ba7650f404af 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
aravindsv 0:ba7650f404af 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
aravindsv 0:ba7650f404af 1011
aravindsv 0:ba7650f404af 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
aravindsv 0:ba7650f404af 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
aravindsv 0:ba7650f404af 1014
aravindsv 0:ba7650f404af 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
aravindsv 0:ba7650f404af 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
aravindsv 0:ba7650f404af 1017
aravindsv 0:ba7650f404af 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
aravindsv 0:ba7650f404af 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
aravindsv 0:ba7650f404af 1020
aravindsv 0:ba7650f404af 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
aravindsv 0:ba7650f404af 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
aravindsv 0:ba7650f404af 1023
aravindsv 0:ba7650f404af 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
aravindsv 0:ba7650f404af 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
aravindsv 0:ba7650f404af 1026
aravindsv 0:ba7650f404af 1027 /* TPI ITATBCTR0 Register Definitions */
aravindsv 0:ba7650f404af 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
aravindsv 0:ba7650f404af 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
aravindsv 0:ba7650f404af 1030
aravindsv 0:ba7650f404af 1031 /* TPI Integration Mode Control Register Definitions */
aravindsv 0:ba7650f404af 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
aravindsv 0:ba7650f404af 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
aravindsv 0:ba7650f404af 1034
aravindsv 0:ba7650f404af 1035 /* TPI DEVID Register Definitions */
aravindsv 0:ba7650f404af 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
aravindsv 0:ba7650f404af 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
aravindsv 0:ba7650f404af 1038
aravindsv 0:ba7650f404af 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
aravindsv 0:ba7650f404af 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
aravindsv 0:ba7650f404af 1041
aravindsv 0:ba7650f404af 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
aravindsv 0:ba7650f404af 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
aravindsv 0:ba7650f404af 1044
aravindsv 0:ba7650f404af 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
aravindsv 0:ba7650f404af 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
aravindsv 0:ba7650f404af 1047
aravindsv 0:ba7650f404af 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
aravindsv 0:ba7650f404af 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
aravindsv 0:ba7650f404af 1050
aravindsv 0:ba7650f404af 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
aravindsv 0:ba7650f404af 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
aravindsv 0:ba7650f404af 1053
aravindsv 0:ba7650f404af 1054 /* TPI DEVTYPE Register Definitions */
aravindsv 0:ba7650f404af 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
aravindsv 0:ba7650f404af 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
aravindsv 0:ba7650f404af 1057
aravindsv 0:ba7650f404af 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
aravindsv 0:ba7650f404af 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
aravindsv 0:ba7650f404af 1060
aravindsv 0:ba7650f404af 1061 /*@}*/ /* end of group CMSIS_TPI */
aravindsv 0:ba7650f404af 1062
aravindsv 0:ba7650f404af 1063
aravindsv 0:ba7650f404af 1064 #if (__MPU_PRESENT == 1)
aravindsv 0:ba7650f404af 1065 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
aravindsv 0:ba7650f404af 1067 \brief Type definitions for the Memory Protection Unit (MPU)
aravindsv 0:ba7650f404af 1068 @{
aravindsv 0:ba7650f404af 1069 */
aravindsv 0:ba7650f404af 1070
aravindsv 0:ba7650f404af 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
aravindsv 0:ba7650f404af 1072 */
aravindsv 0:ba7650f404af 1073 typedef struct
aravindsv 0:ba7650f404af 1074 {
aravindsv 0:ba7650f404af 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
aravindsv 0:ba7650f404af 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
aravindsv 0:ba7650f404af 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
aravindsv 0:ba7650f404af 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
aravindsv 0:ba7650f404af 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
aravindsv 0:ba7650f404af 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
aravindsv 0:ba7650f404af 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
aravindsv 0:ba7650f404af 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
aravindsv 0:ba7650f404af 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
aravindsv 0:ba7650f404af 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
aravindsv 0:ba7650f404af 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
aravindsv 0:ba7650f404af 1086 } MPU_Type;
aravindsv 0:ba7650f404af 1087
aravindsv 0:ba7650f404af 1088 /* MPU Type Register */
aravindsv 0:ba7650f404af 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
aravindsv 0:ba7650f404af 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
aravindsv 0:ba7650f404af 1091
aravindsv 0:ba7650f404af 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
aravindsv 0:ba7650f404af 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
aravindsv 0:ba7650f404af 1094
aravindsv 0:ba7650f404af 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
aravindsv 0:ba7650f404af 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
aravindsv 0:ba7650f404af 1097
aravindsv 0:ba7650f404af 1098 /* MPU Control Register */
aravindsv 0:ba7650f404af 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
aravindsv 0:ba7650f404af 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
aravindsv 0:ba7650f404af 1101
aravindsv 0:ba7650f404af 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
aravindsv 0:ba7650f404af 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
aravindsv 0:ba7650f404af 1104
aravindsv 0:ba7650f404af 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
aravindsv 0:ba7650f404af 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
aravindsv 0:ba7650f404af 1107
aravindsv 0:ba7650f404af 1108 /* MPU Region Number Register */
aravindsv 0:ba7650f404af 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
aravindsv 0:ba7650f404af 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
aravindsv 0:ba7650f404af 1111
aravindsv 0:ba7650f404af 1112 /* MPU Region Base Address Register */
aravindsv 0:ba7650f404af 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
aravindsv 0:ba7650f404af 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
aravindsv 0:ba7650f404af 1115
aravindsv 0:ba7650f404af 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
aravindsv 0:ba7650f404af 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
aravindsv 0:ba7650f404af 1118
aravindsv 0:ba7650f404af 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
aravindsv 0:ba7650f404af 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
aravindsv 0:ba7650f404af 1121
aravindsv 0:ba7650f404af 1122 /* MPU Region Attribute and Size Register */
aravindsv 0:ba7650f404af 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
aravindsv 0:ba7650f404af 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
aravindsv 0:ba7650f404af 1125
aravindsv 0:ba7650f404af 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
aravindsv 0:ba7650f404af 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
aravindsv 0:ba7650f404af 1128
aravindsv 0:ba7650f404af 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
aravindsv 0:ba7650f404af 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
aravindsv 0:ba7650f404af 1131
aravindsv 0:ba7650f404af 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
aravindsv 0:ba7650f404af 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
aravindsv 0:ba7650f404af 1134
aravindsv 0:ba7650f404af 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
aravindsv 0:ba7650f404af 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
aravindsv 0:ba7650f404af 1137
aravindsv 0:ba7650f404af 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
aravindsv 0:ba7650f404af 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
aravindsv 0:ba7650f404af 1140
aravindsv 0:ba7650f404af 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
aravindsv 0:ba7650f404af 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
aravindsv 0:ba7650f404af 1143
aravindsv 0:ba7650f404af 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
aravindsv 0:ba7650f404af 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
aravindsv 0:ba7650f404af 1146
aravindsv 0:ba7650f404af 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
aravindsv 0:ba7650f404af 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
aravindsv 0:ba7650f404af 1149
aravindsv 0:ba7650f404af 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
aravindsv 0:ba7650f404af 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
aravindsv 0:ba7650f404af 1152
aravindsv 0:ba7650f404af 1153 /*@} end of group CMSIS_MPU */
aravindsv 0:ba7650f404af 1154 #endif
aravindsv 0:ba7650f404af 1155
aravindsv 0:ba7650f404af 1156
aravindsv 0:ba7650f404af 1157 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 1158 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
aravindsv 0:ba7650f404af 1160 \brief Type definitions for the Floating Point Unit (FPU)
aravindsv 0:ba7650f404af 1161 @{
aravindsv 0:ba7650f404af 1162 */
aravindsv 0:ba7650f404af 1163
aravindsv 0:ba7650f404af 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
aravindsv 0:ba7650f404af 1165 */
aravindsv 0:ba7650f404af 1166 typedef struct
aravindsv 0:ba7650f404af 1167 {
aravindsv 0:ba7650f404af 1168 uint32_t RESERVED0[1];
aravindsv 0:ba7650f404af 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
aravindsv 0:ba7650f404af 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
aravindsv 0:ba7650f404af 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
aravindsv 0:ba7650f404af 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
aravindsv 0:ba7650f404af 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
aravindsv 0:ba7650f404af 1174 } FPU_Type;
aravindsv 0:ba7650f404af 1175
aravindsv 0:ba7650f404af 1176 /* Floating-Point Context Control Register */
aravindsv 0:ba7650f404af 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
aravindsv 0:ba7650f404af 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
aravindsv 0:ba7650f404af 1179
aravindsv 0:ba7650f404af 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
aravindsv 0:ba7650f404af 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
aravindsv 0:ba7650f404af 1182
aravindsv 0:ba7650f404af 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
aravindsv 0:ba7650f404af 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
aravindsv 0:ba7650f404af 1185
aravindsv 0:ba7650f404af 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
aravindsv 0:ba7650f404af 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
aravindsv 0:ba7650f404af 1188
aravindsv 0:ba7650f404af 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
aravindsv 0:ba7650f404af 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
aravindsv 0:ba7650f404af 1191
aravindsv 0:ba7650f404af 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
aravindsv 0:ba7650f404af 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
aravindsv 0:ba7650f404af 1194
aravindsv 0:ba7650f404af 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
aravindsv 0:ba7650f404af 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
aravindsv 0:ba7650f404af 1197
aravindsv 0:ba7650f404af 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
aravindsv 0:ba7650f404af 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
aravindsv 0:ba7650f404af 1200
aravindsv 0:ba7650f404af 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
aravindsv 0:ba7650f404af 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
aravindsv 0:ba7650f404af 1203
aravindsv 0:ba7650f404af 1204 /* Floating-Point Context Address Register */
aravindsv 0:ba7650f404af 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
aravindsv 0:ba7650f404af 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
aravindsv 0:ba7650f404af 1207
aravindsv 0:ba7650f404af 1208 /* Floating-Point Default Status Control Register */
aravindsv 0:ba7650f404af 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
aravindsv 0:ba7650f404af 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
aravindsv 0:ba7650f404af 1211
aravindsv 0:ba7650f404af 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
aravindsv 0:ba7650f404af 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
aravindsv 0:ba7650f404af 1214
aravindsv 0:ba7650f404af 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
aravindsv 0:ba7650f404af 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
aravindsv 0:ba7650f404af 1217
aravindsv 0:ba7650f404af 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
aravindsv 0:ba7650f404af 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
aravindsv 0:ba7650f404af 1220
aravindsv 0:ba7650f404af 1221 /* Media and FP Feature Register 0 */
aravindsv 0:ba7650f404af 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
aravindsv 0:ba7650f404af 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
aravindsv 0:ba7650f404af 1224
aravindsv 0:ba7650f404af 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
aravindsv 0:ba7650f404af 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
aravindsv 0:ba7650f404af 1227
aravindsv 0:ba7650f404af 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
aravindsv 0:ba7650f404af 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
aravindsv 0:ba7650f404af 1230
aravindsv 0:ba7650f404af 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
aravindsv 0:ba7650f404af 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
aravindsv 0:ba7650f404af 1233
aravindsv 0:ba7650f404af 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
aravindsv 0:ba7650f404af 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
aravindsv 0:ba7650f404af 1236
aravindsv 0:ba7650f404af 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
aravindsv 0:ba7650f404af 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
aravindsv 0:ba7650f404af 1239
aravindsv 0:ba7650f404af 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
aravindsv 0:ba7650f404af 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
aravindsv 0:ba7650f404af 1242
aravindsv 0:ba7650f404af 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
aravindsv 0:ba7650f404af 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
aravindsv 0:ba7650f404af 1245
aravindsv 0:ba7650f404af 1246 /* Media and FP Feature Register 1 */
aravindsv 0:ba7650f404af 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
aravindsv 0:ba7650f404af 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
aravindsv 0:ba7650f404af 1249
aravindsv 0:ba7650f404af 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
aravindsv 0:ba7650f404af 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
aravindsv 0:ba7650f404af 1252
aravindsv 0:ba7650f404af 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
aravindsv 0:ba7650f404af 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
aravindsv 0:ba7650f404af 1255
aravindsv 0:ba7650f404af 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
aravindsv 0:ba7650f404af 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
aravindsv 0:ba7650f404af 1258
aravindsv 0:ba7650f404af 1259 /*@} end of group CMSIS_FPU */
aravindsv 0:ba7650f404af 1260 #endif
aravindsv 0:ba7650f404af 1261
aravindsv 0:ba7650f404af 1262
aravindsv 0:ba7650f404af 1263 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
aravindsv 0:ba7650f404af 1265 \brief Type definitions for the Core Debug Registers
aravindsv 0:ba7650f404af 1266 @{
aravindsv 0:ba7650f404af 1267 */
aravindsv 0:ba7650f404af 1268
aravindsv 0:ba7650f404af 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
aravindsv 0:ba7650f404af 1270 */
aravindsv 0:ba7650f404af 1271 typedef struct
aravindsv 0:ba7650f404af 1272 {
aravindsv 0:ba7650f404af 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
aravindsv 0:ba7650f404af 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
aravindsv 0:ba7650f404af 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
aravindsv 0:ba7650f404af 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
aravindsv 0:ba7650f404af 1277 } CoreDebug_Type;
aravindsv 0:ba7650f404af 1278
aravindsv 0:ba7650f404af 1279 /* Debug Halting Control and Status Register */
aravindsv 0:ba7650f404af 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
aravindsv 0:ba7650f404af 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
aravindsv 0:ba7650f404af 1282
aravindsv 0:ba7650f404af 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
aravindsv 0:ba7650f404af 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
aravindsv 0:ba7650f404af 1285
aravindsv 0:ba7650f404af 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
aravindsv 0:ba7650f404af 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
aravindsv 0:ba7650f404af 1288
aravindsv 0:ba7650f404af 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
aravindsv 0:ba7650f404af 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
aravindsv 0:ba7650f404af 1291
aravindsv 0:ba7650f404af 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
aravindsv 0:ba7650f404af 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
aravindsv 0:ba7650f404af 1294
aravindsv 0:ba7650f404af 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
aravindsv 0:ba7650f404af 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
aravindsv 0:ba7650f404af 1297
aravindsv 0:ba7650f404af 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
aravindsv 0:ba7650f404af 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
aravindsv 0:ba7650f404af 1300
aravindsv 0:ba7650f404af 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
aravindsv 0:ba7650f404af 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
aravindsv 0:ba7650f404af 1303
aravindsv 0:ba7650f404af 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
aravindsv 0:ba7650f404af 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
aravindsv 0:ba7650f404af 1306
aravindsv 0:ba7650f404af 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
aravindsv 0:ba7650f404af 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
aravindsv 0:ba7650f404af 1309
aravindsv 0:ba7650f404af 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
aravindsv 0:ba7650f404af 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
aravindsv 0:ba7650f404af 1312
aravindsv 0:ba7650f404af 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
aravindsv 0:ba7650f404af 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
aravindsv 0:ba7650f404af 1315
aravindsv 0:ba7650f404af 1316 /* Debug Core Register Selector Register */
aravindsv 0:ba7650f404af 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
aravindsv 0:ba7650f404af 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
aravindsv 0:ba7650f404af 1319
aravindsv 0:ba7650f404af 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
aravindsv 0:ba7650f404af 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
aravindsv 0:ba7650f404af 1322
aravindsv 0:ba7650f404af 1323 /* Debug Exception and Monitor Control Register */
aravindsv 0:ba7650f404af 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
aravindsv 0:ba7650f404af 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
aravindsv 0:ba7650f404af 1326
aravindsv 0:ba7650f404af 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
aravindsv 0:ba7650f404af 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
aravindsv 0:ba7650f404af 1329
aravindsv 0:ba7650f404af 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
aravindsv 0:ba7650f404af 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
aravindsv 0:ba7650f404af 1332
aravindsv 0:ba7650f404af 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
aravindsv 0:ba7650f404af 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
aravindsv 0:ba7650f404af 1335
aravindsv 0:ba7650f404af 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
aravindsv 0:ba7650f404af 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
aravindsv 0:ba7650f404af 1338
aravindsv 0:ba7650f404af 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
aravindsv 0:ba7650f404af 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
aravindsv 0:ba7650f404af 1341
aravindsv 0:ba7650f404af 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
aravindsv 0:ba7650f404af 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
aravindsv 0:ba7650f404af 1344
aravindsv 0:ba7650f404af 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
aravindsv 0:ba7650f404af 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
aravindsv 0:ba7650f404af 1347
aravindsv 0:ba7650f404af 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
aravindsv 0:ba7650f404af 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
aravindsv 0:ba7650f404af 1350
aravindsv 0:ba7650f404af 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
aravindsv 0:ba7650f404af 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
aravindsv 0:ba7650f404af 1353
aravindsv 0:ba7650f404af 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
aravindsv 0:ba7650f404af 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
aravindsv 0:ba7650f404af 1356
aravindsv 0:ba7650f404af 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
aravindsv 0:ba7650f404af 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
aravindsv 0:ba7650f404af 1359
aravindsv 0:ba7650f404af 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
aravindsv 0:ba7650f404af 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
aravindsv 0:ba7650f404af 1362
aravindsv 0:ba7650f404af 1363 /*@} end of group CMSIS_CoreDebug */
aravindsv 0:ba7650f404af 1364
aravindsv 0:ba7650f404af 1365
aravindsv 0:ba7650f404af 1366 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 1367 \defgroup CMSIS_core_base Core Definitions
aravindsv 0:ba7650f404af 1368 \brief Definitions for base addresses, unions, and structures.
aravindsv 0:ba7650f404af 1369 @{
aravindsv 0:ba7650f404af 1370 */
aravindsv 0:ba7650f404af 1371
aravindsv 0:ba7650f404af 1372 /* Memory mapping of Cortex-M4 Hardware */
aravindsv 0:ba7650f404af 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
aravindsv 0:ba7650f404af 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
aravindsv 0:ba7650f404af 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
aravindsv 0:ba7650f404af 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
aravindsv 0:ba7650f404af 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
aravindsv 0:ba7650f404af 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
aravindsv 0:ba7650f404af 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
aravindsv 0:ba7650f404af 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
aravindsv 0:ba7650f404af 1381
aravindsv 0:ba7650f404af 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
aravindsv 0:ba7650f404af 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
aravindsv 0:ba7650f404af 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
aravindsv 0:ba7650f404af 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
aravindsv 0:ba7650f404af 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
aravindsv 0:ba7650f404af 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
aravindsv 0:ba7650f404af 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
aravindsv 0:ba7650f404af 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
aravindsv 0:ba7650f404af 1390
aravindsv 0:ba7650f404af 1391 #if (__MPU_PRESENT == 1)
aravindsv 0:ba7650f404af 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
aravindsv 0:ba7650f404af 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
aravindsv 0:ba7650f404af 1394 #endif
aravindsv 0:ba7650f404af 1395
aravindsv 0:ba7650f404af 1396 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
aravindsv 0:ba7650f404af 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
aravindsv 0:ba7650f404af 1399 #endif
aravindsv 0:ba7650f404af 1400
aravindsv 0:ba7650f404af 1401 /*@} */
aravindsv 0:ba7650f404af 1402
aravindsv 0:ba7650f404af 1403
aravindsv 0:ba7650f404af 1404
aravindsv 0:ba7650f404af 1405 /*******************************************************************************
aravindsv 0:ba7650f404af 1406 * Hardware Abstraction Layer
aravindsv 0:ba7650f404af 1407 Core Function Interface contains:
aravindsv 0:ba7650f404af 1408 - Core NVIC Functions
aravindsv 0:ba7650f404af 1409 - Core SysTick Functions
aravindsv 0:ba7650f404af 1410 - Core Debug Functions
aravindsv 0:ba7650f404af 1411 - Core Register Access Functions
aravindsv 0:ba7650f404af 1412 ******************************************************************************/
aravindsv 0:ba7650f404af 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
aravindsv 0:ba7650f404af 1414 */
aravindsv 0:ba7650f404af 1415
aravindsv 0:ba7650f404af 1416
aravindsv 0:ba7650f404af 1417
aravindsv 0:ba7650f404af 1418 /* ########################## NVIC functions #################################### */
aravindsv 0:ba7650f404af 1419 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
aravindsv 0:ba7650f404af 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
aravindsv 0:ba7650f404af 1422 @{
aravindsv 0:ba7650f404af 1423 */
aravindsv 0:ba7650f404af 1424
aravindsv 0:ba7650f404af 1425 /** \brief Set Priority Grouping
aravindsv 0:ba7650f404af 1426
aravindsv 0:ba7650f404af 1427 The function sets the priority grouping field using the required unlock sequence.
aravindsv 0:ba7650f404af 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
aravindsv 0:ba7650f404af 1429 Only values from 0..7 are used.
aravindsv 0:ba7650f404af 1430 In case of a conflict between priority grouping and available
aravindsv 0:ba7650f404af 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
aravindsv 0:ba7650f404af 1432
aravindsv 0:ba7650f404af 1433 \param [in] PriorityGroup Priority grouping field.
aravindsv 0:ba7650f404af 1434 */
aravindsv 0:ba7650f404af 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
aravindsv 0:ba7650f404af 1436 {
aravindsv 0:ba7650f404af 1437 uint32_t reg_value;
aravindsv 0:ba7650f404af 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
aravindsv 0:ba7650f404af 1439
aravindsv 0:ba7650f404af 1440 reg_value = SCB->AIRCR; /* read old register configuration */
aravindsv 0:ba7650f404af 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
aravindsv 0:ba7650f404af 1442 reg_value = (reg_value |
aravindsv 0:ba7650f404af 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
aravindsv 0:ba7650f404af 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
aravindsv 0:ba7650f404af 1445 SCB->AIRCR = reg_value;
aravindsv 0:ba7650f404af 1446 }
aravindsv 0:ba7650f404af 1447
aravindsv 0:ba7650f404af 1448
aravindsv 0:ba7650f404af 1449 /** \brief Get Priority Grouping
aravindsv 0:ba7650f404af 1450
aravindsv 0:ba7650f404af 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
aravindsv 0:ba7650f404af 1452
aravindsv 0:ba7650f404af 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
aravindsv 0:ba7650f404af 1454 */
aravindsv 0:ba7650f404af 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
aravindsv 0:ba7650f404af 1456 {
aravindsv 0:ba7650f404af 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
aravindsv 0:ba7650f404af 1458 }
aravindsv 0:ba7650f404af 1459
aravindsv 0:ba7650f404af 1460
aravindsv 0:ba7650f404af 1461 /** \brief Enable External Interrupt
aravindsv 0:ba7650f404af 1462
aravindsv 0:ba7650f404af 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
aravindsv 0:ba7650f404af 1464
aravindsv 0:ba7650f404af 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 1466 */
aravindsv 0:ba7650f404af 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1468 {
aravindsv 0:ba7650f404af 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
aravindsv 0:ba7650f404af 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
aravindsv 0:ba7650f404af 1471 }
aravindsv 0:ba7650f404af 1472
aravindsv 0:ba7650f404af 1473
aravindsv 0:ba7650f404af 1474 /** \brief Disable External Interrupt
aravindsv 0:ba7650f404af 1475
aravindsv 0:ba7650f404af 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
aravindsv 0:ba7650f404af 1477
aravindsv 0:ba7650f404af 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 1479 */
aravindsv 0:ba7650f404af 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1481 {
aravindsv 0:ba7650f404af 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
aravindsv 0:ba7650f404af 1483 }
aravindsv 0:ba7650f404af 1484
aravindsv 0:ba7650f404af 1485
aravindsv 0:ba7650f404af 1486 /** \brief Get Pending Interrupt
aravindsv 0:ba7650f404af 1487
aravindsv 0:ba7650f404af 1488 The function reads the pending register in the NVIC and returns the pending bit
aravindsv 0:ba7650f404af 1489 for the specified interrupt.
aravindsv 0:ba7650f404af 1490
aravindsv 0:ba7650f404af 1491 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 1492
aravindsv 0:ba7650f404af 1493 \return 0 Interrupt status is not pending.
aravindsv 0:ba7650f404af 1494 \return 1 Interrupt status is pending.
aravindsv 0:ba7650f404af 1495 */
aravindsv 0:ba7650f404af 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1497 {
aravindsv 0:ba7650f404af 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
aravindsv 0:ba7650f404af 1499 }
aravindsv 0:ba7650f404af 1500
aravindsv 0:ba7650f404af 1501
aravindsv 0:ba7650f404af 1502 /** \brief Set Pending Interrupt
aravindsv 0:ba7650f404af 1503
aravindsv 0:ba7650f404af 1504 The function sets the pending bit of an external interrupt.
aravindsv 0:ba7650f404af 1505
aravindsv 0:ba7650f404af 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 1507 */
aravindsv 0:ba7650f404af 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1509 {
aravindsv 0:ba7650f404af 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
aravindsv 0:ba7650f404af 1511 }
aravindsv 0:ba7650f404af 1512
aravindsv 0:ba7650f404af 1513
aravindsv 0:ba7650f404af 1514 /** \brief Clear Pending Interrupt
aravindsv 0:ba7650f404af 1515
aravindsv 0:ba7650f404af 1516 The function clears the pending bit of an external interrupt.
aravindsv 0:ba7650f404af 1517
aravindsv 0:ba7650f404af 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 1519 */
aravindsv 0:ba7650f404af 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1521 {
aravindsv 0:ba7650f404af 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
aravindsv 0:ba7650f404af 1523 }
aravindsv 0:ba7650f404af 1524
aravindsv 0:ba7650f404af 1525
aravindsv 0:ba7650f404af 1526 /** \brief Get Active Interrupt
aravindsv 0:ba7650f404af 1527
aravindsv 0:ba7650f404af 1528 The function reads the active register in NVIC and returns the active bit.
aravindsv 0:ba7650f404af 1529
aravindsv 0:ba7650f404af 1530 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 1531
aravindsv 0:ba7650f404af 1532 \return 0 Interrupt status is not active.
aravindsv 0:ba7650f404af 1533 \return 1 Interrupt status is active.
aravindsv 0:ba7650f404af 1534 */
aravindsv 0:ba7650f404af 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1536 {
aravindsv 0:ba7650f404af 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
aravindsv 0:ba7650f404af 1538 }
aravindsv 0:ba7650f404af 1539
aravindsv 0:ba7650f404af 1540
aravindsv 0:ba7650f404af 1541 /** \brief Set Interrupt Priority
aravindsv 0:ba7650f404af 1542
aravindsv 0:ba7650f404af 1543 The function sets the priority of an interrupt.
aravindsv 0:ba7650f404af 1544
aravindsv 0:ba7650f404af 1545 \note The priority cannot be set for every core interrupt.
aravindsv 0:ba7650f404af 1546
aravindsv 0:ba7650f404af 1547 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 1548 \param [in] priority Priority to set.
aravindsv 0:ba7650f404af 1549 */
aravindsv 0:ba7650f404af 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
aravindsv 0:ba7650f404af 1551 {
aravindsv 0:ba7650f404af 1552 if(IRQn < 0) {
aravindsv 0:ba7650f404af 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
aravindsv 0:ba7650f404af 1554 else {
aravindsv 0:ba7650f404af 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
aravindsv 0:ba7650f404af 1556 }
aravindsv 0:ba7650f404af 1557
aravindsv 0:ba7650f404af 1558
aravindsv 0:ba7650f404af 1559 /** \brief Get Interrupt Priority
aravindsv 0:ba7650f404af 1560
aravindsv 0:ba7650f404af 1561 The function reads the priority of an interrupt. The interrupt
aravindsv 0:ba7650f404af 1562 number can be positive to specify an external (device specific)
aravindsv 0:ba7650f404af 1563 interrupt, or negative to specify an internal (core) interrupt.
aravindsv 0:ba7650f404af 1564
aravindsv 0:ba7650f404af 1565
aravindsv 0:ba7650f404af 1566 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
aravindsv 0:ba7650f404af 1568 priority bits of the microcontroller.
aravindsv 0:ba7650f404af 1569 */
aravindsv 0:ba7650f404af 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 1571 {
aravindsv 0:ba7650f404af 1572
aravindsv 0:ba7650f404af 1573 if(IRQn < 0) {
aravindsv 0:ba7650f404af 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
aravindsv 0:ba7650f404af 1575 else {
aravindsv 0:ba7650f404af 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
aravindsv 0:ba7650f404af 1577 }
aravindsv 0:ba7650f404af 1578
aravindsv 0:ba7650f404af 1579
aravindsv 0:ba7650f404af 1580 /** \brief Encode Priority
aravindsv 0:ba7650f404af 1581
aravindsv 0:ba7650f404af 1582 The function encodes the priority for an interrupt with the given priority group,
aravindsv 0:ba7650f404af 1583 preemptive priority value, and subpriority value.
aravindsv 0:ba7650f404af 1584 In case of a conflict between priority grouping and available
aravindsv 0:ba7650f404af 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
aravindsv 0:ba7650f404af 1586
aravindsv 0:ba7650f404af 1587 \param [in] PriorityGroup Used priority group.
aravindsv 0:ba7650f404af 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
aravindsv 0:ba7650f404af 1589 \param [in] SubPriority Subpriority value (starting from 0).
aravindsv 0:ba7650f404af 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
aravindsv 0:ba7650f404af 1591 */
aravindsv 0:ba7650f404af 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
aravindsv 0:ba7650f404af 1593 {
aravindsv 0:ba7650f404af 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
aravindsv 0:ba7650f404af 1595 uint32_t PreemptPriorityBits;
aravindsv 0:ba7650f404af 1596 uint32_t SubPriorityBits;
aravindsv 0:ba7650f404af 1597
aravindsv 0:ba7650f404af 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
aravindsv 0:ba7650f404af 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
aravindsv 0:ba7650f404af 1600
aravindsv 0:ba7650f404af 1601 return (
aravindsv 0:ba7650f404af 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
aravindsv 0:ba7650f404af 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
aravindsv 0:ba7650f404af 1604 );
aravindsv 0:ba7650f404af 1605 }
aravindsv 0:ba7650f404af 1606
aravindsv 0:ba7650f404af 1607
aravindsv 0:ba7650f404af 1608 /** \brief Decode Priority
aravindsv 0:ba7650f404af 1609
aravindsv 0:ba7650f404af 1610 The function decodes an interrupt priority value with a given priority group to
aravindsv 0:ba7650f404af 1611 preemptive priority value and subpriority value.
aravindsv 0:ba7650f404af 1612 In case of a conflict between priority grouping and available
aravindsv 0:ba7650f404af 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
aravindsv 0:ba7650f404af 1614
aravindsv 0:ba7650f404af 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
aravindsv 0:ba7650f404af 1616 \param [in] PriorityGroup Used priority group.
aravindsv 0:ba7650f404af 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
aravindsv 0:ba7650f404af 1618 \param [out] pSubPriority Subpriority value (starting from 0).
aravindsv 0:ba7650f404af 1619 */
aravindsv 0:ba7650f404af 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
aravindsv 0:ba7650f404af 1621 {
aravindsv 0:ba7650f404af 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
aravindsv 0:ba7650f404af 1623 uint32_t PreemptPriorityBits;
aravindsv 0:ba7650f404af 1624 uint32_t SubPriorityBits;
aravindsv 0:ba7650f404af 1625
aravindsv 0:ba7650f404af 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
aravindsv 0:ba7650f404af 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
aravindsv 0:ba7650f404af 1628
aravindsv 0:ba7650f404af 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
aravindsv 0:ba7650f404af 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
aravindsv 0:ba7650f404af 1631 }
aravindsv 0:ba7650f404af 1632
aravindsv 0:ba7650f404af 1633
aravindsv 0:ba7650f404af 1634 /** \brief System Reset
aravindsv 0:ba7650f404af 1635
aravindsv 0:ba7650f404af 1636 The function initiates a system reset request to reset the MCU.
aravindsv 0:ba7650f404af 1637 */
aravindsv 0:ba7650f404af 1638 __STATIC_INLINE void NVIC_SystemReset(void)
aravindsv 0:ba7650f404af 1639 {
aravindsv 0:ba7650f404af 1640 __DSB(); /* Ensure all outstanding memory accesses included
aravindsv 0:ba7650f404af 1641 buffered write are completed before reset */
aravindsv 0:ba7650f404af 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
aravindsv 0:ba7650f404af 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
aravindsv 0:ba7650f404af 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
aravindsv 0:ba7650f404af 1645 __DSB(); /* Ensure completion of memory access */
aravindsv 0:ba7650f404af 1646 while(1); /* wait until reset */
aravindsv 0:ba7650f404af 1647 }
aravindsv 0:ba7650f404af 1648
aravindsv 0:ba7650f404af 1649 /*@} end of CMSIS_Core_NVICFunctions */
aravindsv 0:ba7650f404af 1650
aravindsv 0:ba7650f404af 1651
aravindsv 0:ba7650f404af 1652
aravindsv 0:ba7650f404af 1653 /* ################################## SysTick function ############################################ */
aravindsv 0:ba7650f404af 1654 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
aravindsv 0:ba7650f404af 1656 \brief Functions that configure the System.
aravindsv 0:ba7650f404af 1657 @{
aravindsv 0:ba7650f404af 1658 */
aravindsv 0:ba7650f404af 1659
aravindsv 0:ba7650f404af 1660 #if (__Vendor_SysTickConfig == 0)
aravindsv 0:ba7650f404af 1661
aravindsv 0:ba7650f404af 1662 /** \brief System Tick Configuration
aravindsv 0:ba7650f404af 1663
aravindsv 0:ba7650f404af 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
aravindsv 0:ba7650f404af 1665 Counter is in free running mode to generate periodic interrupts.
aravindsv 0:ba7650f404af 1666
aravindsv 0:ba7650f404af 1667 \param [in] ticks Number of ticks between two interrupts.
aravindsv 0:ba7650f404af 1668
aravindsv 0:ba7650f404af 1669 \return 0 Function succeeded.
aravindsv 0:ba7650f404af 1670 \return 1 Function failed.
aravindsv 0:ba7650f404af 1671
aravindsv 0:ba7650f404af 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
aravindsv 0:ba7650f404af 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
aravindsv 0:ba7650f404af 1674 must contain a vendor-specific implementation of this function.
aravindsv 0:ba7650f404af 1675
aravindsv 0:ba7650f404af 1676 */
aravindsv 0:ba7650f404af 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
aravindsv 0:ba7650f404af 1678 {
aravindsv 0:ba7650f404af 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
aravindsv 0:ba7650f404af 1680
aravindsv 0:ba7650f404af 1681 SysTick->LOAD = ticks - 1; /* set reload register */
aravindsv 0:ba7650f404af 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
aravindsv 0:ba7650f404af 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
aravindsv 0:ba7650f404af 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
aravindsv 0:ba7650f404af 1685 SysTick_CTRL_TICKINT_Msk |
aravindsv 0:ba7650f404af 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
aravindsv 0:ba7650f404af 1687 return (0); /* Function successful */
aravindsv 0:ba7650f404af 1688 }
aravindsv 0:ba7650f404af 1689
aravindsv 0:ba7650f404af 1690 #endif
aravindsv 0:ba7650f404af 1691
aravindsv 0:ba7650f404af 1692 /*@} end of CMSIS_Core_SysTickFunctions */
aravindsv 0:ba7650f404af 1693
aravindsv 0:ba7650f404af 1694
aravindsv 0:ba7650f404af 1695
aravindsv 0:ba7650f404af 1696 /* ##################################### Debug In/Output function ########################################### */
aravindsv 0:ba7650f404af 1697 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
aravindsv 0:ba7650f404af 1699 \brief Functions that access the ITM debug interface.
aravindsv 0:ba7650f404af 1700 @{
aravindsv 0:ba7650f404af 1701 */
aravindsv 0:ba7650f404af 1702
aravindsv 0:ba7650f404af 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
aravindsv 0:ba7650f404af 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
aravindsv 0:ba7650f404af 1705
aravindsv 0:ba7650f404af 1706
aravindsv 0:ba7650f404af 1707 /** \brief ITM Send Character
aravindsv 0:ba7650f404af 1708
aravindsv 0:ba7650f404af 1709 The function transmits a character via the ITM channel 0, and
aravindsv 0:ba7650f404af 1710 \li Just returns when no debugger is connected that has booked the output.
aravindsv 0:ba7650f404af 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
aravindsv 0:ba7650f404af 1712
aravindsv 0:ba7650f404af 1713 \param [in] ch Character to transmit.
aravindsv 0:ba7650f404af 1714
aravindsv 0:ba7650f404af 1715 \returns Character to transmit.
aravindsv 0:ba7650f404af 1716 */
aravindsv 0:ba7650f404af 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
aravindsv 0:ba7650f404af 1718 {
aravindsv 0:ba7650f404af 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
aravindsv 0:ba7650f404af 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
aravindsv 0:ba7650f404af 1721 {
aravindsv 0:ba7650f404af 1722 while (ITM->PORT[0].u32 == 0);
aravindsv 0:ba7650f404af 1723 ITM->PORT[0].u8 = (uint8_t) ch;
aravindsv 0:ba7650f404af 1724 }
aravindsv 0:ba7650f404af 1725 return (ch);
aravindsv 0:ba7650f404af 1726 }
aravindsv 0:ba7650f404af 1727
aravindsv 0:ba7650f404af 1728
aravindsv 0:ba7650f404af 1729 /** \brief ITM Receive Character
aravindsv 0:ba7650f404af 1730
aravindsv 0:ba7650f404af 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
aravindsv 0:ba7650f404af 1732
aravindsv 0:ba7650f404af 1733 \return Received character.
aravindsv 0:ba7650f404af 1734 \return -1 No character pending.
aravindsv 0:ba7650f404af 1735 */
aravindsv 0:ba7650f404af 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
aravindsv 0:ba7650f404af 1737 int32_t ch = -1; /* no character available */
aravindsv 0:ba7650f404af 1738
aravindsv 0:ba7650f404af 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
aravindsv 0:ba7650f404af 1740 ch = ITM_RxBuffer;
aravindsv 0:ba7650f404af 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
aravindsv 0:ba7650f404af 1742 }
aravindsv 0:ba7650f404af 1743
aravindsv 0:ba7650f404af 1744 return (ch);
aravindsv 0:ba7650f404af 1745 }
aravindsv 0:ba7650f404af 1746
aravindsv 0:ba7650f404af 1747
aravindsv 0:ba7650f404af 1748 /** \brief ITM Check Character
aravindsv 0:ba7650f404af 1749
aravindsv 0:ba7650f404af 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
aravindsv 0:ba7650f404af 1751
aravindsv 0:ba7650f404af 1752 \return 0 No character available.
aravindsv 0:ba7650f404af 1753 \return 1 Character available.
aravindsv 0:ba7650f404af 1754 */
aravindsv 0:ba7650f404af 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
aravindsv 0:ba7650f404af 1756
aravindsv 0:ba7650f404af 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
aravindsv 0:ba7650f404af 1758 return (0); /* no character available */
aravindsv 0:ba7650f404af 1759 } else {
aravindsv 0:ba7650f404af 1760 return (1); /* character available */
aravindsv 0:ba7650f404af 1761 }
aravindsv 0:ba7650f404af 1762 }
aravindsv 0:ba7650f404af 1763
aravindsv 0:ba7650f404af 1764 /*@} end of CMSIS_core_DebugFunctions */
aravindsv 0:ba7650f404af 1765
aravindsv 0:ba7650f404af 1766 #endif /* __CORE_CM4_H_DEPENDANT */
aravindsv 0:ba7650f404af 1767
aravindsv 0:ba7650f404af 1768 #endif /* __CMSIS_GENERIC */
aravindsv 0:ba7650f404af 1769
aravindsv 0:ba7650f404af 1770 #ifdef __cplusplus
aravindsv 0:ba7650f404af 1771 }
aravindsv 0:ba7650f404af 1772 #endif