Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/core_caFunc.h@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**************************************************************************//**
aravindsv 0:ba7650f404af 2 * @file core_caFunc.h
aravindsv 0:ba7650f404af 3 * @brief CMSIS Cortex-A Core Function Access Header File
aravindsv 0:ba7650f404af 4 * @version V3.10
aravindsv 0:ba7650f404af 5 * @date 30 Oct 2013
aravindsv 0:ba7650f404af 6 *
aravindsv 0:ba7650f404af 7 * @note
aravindsv 0:ba7650f404af 8 *
aravindsv 0:ba7650f404af 9 ******************************************************************************/
aravindsv 0:ba7650f404af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
aravindsv 0:ba7650f404af 11
aravindsv 0:ba7650f404af 12 All rights reserved.
aravindsv 0:ba7650f404af 13 Redistribution and use in source and binary forms, with or without
aravindsv 0:ba7650f404af 14 modification, are permitted provided that the following conditions are met:
aravindsv 0:ba7650f404af 15 - Redistributions of source code must retain the above copyright
aravindsv 0:ba7650f404af 16 notice, this list of conditions and the following disclaimer.
aravindsv 0:ba7650f404af 17 - Redistributions in binary form must reproduce the above copyright
aravindsv 0:ba7650f404af 18 notice, this list of conditions and the following disclaimer in the
aravindsv 0:ba7650f404af 19 documentation and/or other materials provided with the distribution.
aravindsv 0:ba7650f404af 20 - Neither the name of ARM nor the names of its contributors may be used
aravindsv 0:ba7650f404af 21 to endorse or promote products derived from this software without
aravindsv 0:ba7650f404af 22 specific prior written permission.
aravindsv 0:ba7650f404af 23 *
aravindsv 0:ba7650f404af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
aravindsv 0:ba7650f404af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
aravindsv 0:ba7650f404af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
aravindsv 0:ba7650f404af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
aravindsv 0:ba7650f404af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
aravindsv 0:ba7650f404af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
aravindsv 0:ba7650f404af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
aravindsv 0:ba7650f404af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
aravindsv 0:ba7650f404af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
aravindsv 0:ba7650f404af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
aravindsv 0:ba7650f404af 34 POSSIBILITY OF SUCH DAMAGE.
aravindsv 0:ba7650f404af 35 ---------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 36
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 #ifndef __CORE_CAFUNC_H__
aravindsv 0:ba7650f404af 39 #define __CORE_CAFUNC_H__
aravindsv 0:ba7650f404af 40
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42 /* ########################### Core Function Access ########################### */
aravindsv 0:ba7650f404af 43 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
aravindsv 0:ba7650f404af 45 @{
aravindsv 0:ba7650f404af 46 */
aravindsv 0:ba7650f404af 47
aravindsv 0:ba7650f404af 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
aravindsv 0:ba7650f404af 49 /* ARM armcc specific functions */
aravindsv 0:ba7650f404af 50
aravindsv 0:ba7650f404af 51 #if (__ARMCC_VERSION < 400677)
aravindsv 0:ba7650f404af 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
aravindsv 0:ba7650f404af 53 #endif
aravindsv 0:ba7650f404af 54
aravindsv 0:ba7650f404af 55 #define MODE_USR 0x10
aravindsv 0:ba7650f404af 56 #define MODE_FIQ 0x11
aravindsv 0:ba7650f404af 57 #define MODE_IRQ 0x12
aravindsv 0:ba7650f404af 58 #define MODE_SVC 0x13
aravindsv 0:ba7650f404af 59 #define MODE_MON 0x16
aravindsv 0:ba7650f404af 60 #define MODE_ABT 0x17
aravindsv 0:ba7650f404af 61 #define MODE_HYP 0x1A
aravindsv 0:ba7650f404af 62 #define MODE_UND 0x1B
aravindsv 0:ba7650f404af 63 #define MODE_SYS 0x1F
aravindsv 0:ba7650f404af 64
aravindsv 0:ba7650f404af 65 /** \brief Get APSR Register
aravindsv 0:ba7650f404af 66
aravindsv 0:ba7650f404af 67 This function returns the content of the APSR Register.
aravindsv 0:ba7650f404af 68
aravindsv 0:ba7650f404af 69 \return APSR Register value
aravindsv 0:ba7650f404af 70 */
aravindsv 0:ba7650f404af 71 __STATIC_INLINE uint32_t __get_APSR(void)
aravindsv 0:ba7650f404af 72 {
aravindsv 0:ba7650f404af 73 register uint32_t __regAPSR __ASM("apsr");
aravindsv 0:ba7650f404af 74 return(__regAPSR);
aravindsv 0:ba7650f404af 75 }
aravindsv 0:ba7650f404af 76
aravindsv 0:ba7650f404af 77
aravindsv 0:ba7650f404af 78 /** \brief Get CPSR Register
aravindsv 0:ba7650f404af 79
aravindsv 0:ba7650f404af 80 This function returns the content of the CPSR Register.
aravindsv 0:ba7650f404af 81
aravindsv 0:ba7650f404af 82 \return CPSR Register value
aravindsv 0:ba7650f404af 83 */
aravindsv 0:ba7650f404af 84 __STATIC_INLINE uint32_t __get_CPSR(void)
aravindsv 0:ba7650f404af 85 {
aravindsv 0:ba7650f404af 86 register uint32_t __regCPSR __ASM("cpsr");
aravindsv 0:ba7650f404af 87 return(__regCPSR);
aravindsv 0:ba7650f404af 88 }
aravindsv 0:ba7650f404af 89
aravindsv 0:ba7650f404af 90 /** \brief Set Stack Pointer
aravindsv 0:ba7650f404af 91
aravindsv 0:ba7650f404af 92 This function assigns the given value to the current stack pointer.
aravindsv 0:ba7650f404af 93
aravindsv 0:ba7650f404af 94 \param [in] topOfStack Stack Pointer value to set
aravindsv 0:ba7650f404af 95 */
aravindsv 0:ba7650f404af 96 register uint32_t __regSP __ASM("sp");
aravindsv 0:ba7650f404af 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
aravindsv 0:ba7650f404af 98 {
aravindsv 0:ba7650f404af 99 __regSP = topOfStack;
aravindsv 0:ba7650f404af 100 }
aravindsv 0:ba7650f404af 101
aravindsv 0:ba7650f404af 102
aravindsv 0:ba7650f404af 103 /** \brief Get link register
aravindsv 0:ba7650f404af 104
aravindsv 0:ba7650f404af 105 This function returns the value of the link register
aravindsv 0:ba7650f404af 106
aravindsv 0:ba7650f404af 107 \return Value of link register
aravindsv 0:ba7650f404af 108 */
aravindsv 0:ba7650f404af 109 register uint32_t __reglr __ASM("lr");
aravindsv 0:ba7650f404af 110 __STATIC_INLINE uint32_t __get_LR(void)
aravindsv 0:ba7650f404af 111 {
aravindsv 0:ba7650f404af 112 return(__reglr);
aravindsv 0:ba7650f404af 113 }
aravindsv 0:ba7650f404af 114
aravindsv 0:ba7650f404af 115 /** \brief Set link register
aravindsv 0:ba7650f404af 116
aravindsv 0:ba7650f404af 117 This function sets the value of the link register
aravindsv 0:ba7650f404af 118
aravindsv 0:ba7650f404af 119 \param [in] lr LR value to set
aravindsv 0:ba7650f404af 120 */
aravindsv 0:ba7650f404af 121 __STATIC_INLINE void __set_LR(uint32_t lr)
aravindsv 0:ba7650f404af 122 {
aravindsv 0:ba7650f404af 123 __reglr = lr;
aravindsv 0:ba7650f404af 124 }
aravindsv 0:ba7650f404af 125
aravindsv 0:ba7650f404af 126 /** \brief Set Process Stack Pointer
aravindsv 0:ba7650f404af 127
aravindsv 0:ba7650f404af 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
aravindsv 0:ba7650f404af 129
aravindsv 0:ba7650f404af 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
aravindsv 0:ba7650f404af 131 */
aravindsv 0:ba7650f404af 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
aravindsv 0:ba7650f404af 133 {
aravindsv 0:ba7650f404af 134 ARM
aravindsv 0:ba7650f404af 135 PRESERVE8
aravindsv 0:ba7650f404af 136
aravindsv 0:ba7650f404af 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
aravindsv 0:ba7650f404af 138 MRS R1, CPSR
aravindsv 0:ba7650f404af 139 CPS #MODE_SYS ;no effect in USR mode
aravindsv 0:ba7650f404af 140 MOV SP, R0
aravindsv 0:ba7650f404af 141 MSR CPSR_c, R1 ;no effect in USR mode
aravindsv 0:ba7650f404af 142 ISB
aravindsv 0:ba7650f404af 143 BX LR
aravindsv 0:ba7650f404af 144
aravindsv 0:ba7650f404af 145 }
aravindsv 0:ba7650f404af 146
aravindsv 0:ba7650f404af 147 /** \brief Set User Mode
aravindsv 0:ba7650f404af 148
aravindsv 0:ba7650f404af 149 This function changes the processor state to User Mode
aravindsv 0:ba7650f404af 150 */
aravindsv 0:ba7650f404af 151 __STATIC_ASM void __set_CPS_USR(void)
aravindsv 0:ba7650f404af 152 {
aravindsv 0:ba7650f404af 153 ARM
aravindsv 0:ba7650f404af 154
aravindsv 0:ba7650f404af 155 CPS #MODE_USR
aravindsv 0:ba7650f404af 156 BX LR
aravindsv 0:ba7650f404af 157 }
aravindsv 0:ba7650f404af 158
aravindsv 0:ba7650f404af 159
aravindsv 0:ba7650f404af 160 /** \brief Enable FIQ
aravindsv 0:ba7650f404af 161
aravindsv 0:ba7650f404af 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
aravindsv 0:ba7650f404af 163 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 164 */
aravindsv 0:ba7650f404af 165 #define __enable_fault_irq __enable_fiq
aravindsv 0:ba7650f404af 166
aravindsv 0:ba7650f404af 167
aravindsv 0:ba7650f404af 168 /** \brief Disable FIQ
aravindsv 0:ba7650f404af 169
aravindsv 0:ba7650f404af 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
aravindsv 0:ba7650f404af 171 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 172 */
aravindsv 0:ba7650f404af 173 #define __disable_fault_irq __disable_fiq
aravindsv 0:ba7650f404af 174
aravindsv 0:ba7650f404af 175
aravindsv 0:ba7650f404af 176 /** \brief Get FPSCR
aravindsv 0:ba7650f404af 177
aravindsv 0:ba7650f404af 178 This function returns the current value of the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 179
aravindsv 0:ba7650f404af 180 \return Floating Point Status/Control register value
aravindsv 0:ba7650f404af 181 */
aravindsv 0:ba7650f404af 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
aravindsv 0:ba7650f404af 183 {
aravindsv 0:ba7650f404af 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 185 register uint32_t __regfpscr __ASM("fpscr");
aravindsv 0:ba7650f404af 186 return(__regfpscr);
aravindsv 0:ba7650f404af 187 #else
aravindsv 0:ba7650f404af 188 return(0);
aravindsv 0:ba7650f404af 189 #endif
aravindsv 0:ba7650f404af 190 }
aravindsv 0:ba7650f404af 191
aravindsv 0:ba7650f404af 192
aravindsv 0:ba7650f404af 193 /** \brief Set FPSCR
aravindsv 0:ba7650f404af 194
aravindsv 0:ba7650f404af 195 This function assigns the given value to the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 196
aravindsv 0:ba7650f404af 197 \param [in] fpscr Floating Point Status/Control value to set
aravindsv 0:ba7650f404af 198 */
aravindsv 0:ba7650f404af 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
aravindsv 0:ba7650f404af 200 {
aravindsv 0:ba7650f404af 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 202 register uint32_t __regfpscr __ASM("fpscr");
aravindsv 0:ba7650f404af 203 __regfpscr = (fpscr);
aravindsv 0:ba7650f404af 204 #endif
aravindsv 0:ba7650f404af 205 }
aravindsv 0:ba7650f404af 206
aravindsv 0:ba7650f404af 207 /** \brief Get FPEXC
aravindsv 0:ba7650f404af 208
aravindsv 0:ba7650f404af 209 This function returns the current value of the Floating Point Exception Control register.
aravindsv 0:ba7650f404af 210
aravindsv 0:ba7650f404af 211 \return Floating Point Exception Control register value
aravindsv 0:ba7650f404af 212 */
aravindsv 0:ba7650f404af 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
aravindsv 0:ba7650f404af 214 {
aravindsv 0:ba7650f404af 215 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 216 register uint32_t __regfpexc __ASM("fpexc");
aravindsv 0:ba7650f404af 217 return(__regfpexc);
aravindsv 0:ba7650f404af 218 #else
aravindsv 0:ba7650f404af 219 return(0);
aravindsv 0:ba7650f404af 220 #endif
aravindsv 0:ba7650f404af 221 }
aravindsv 0:ba7650f404af 222
aravindsv 0:ba7650f404af 223
aravindsv 0:ba7650f404af 224 /** \brief Set FPEXC
aravindsv 0:ba7650f404af 225
aravindsv 0:ba7650f404af 226 This function assigns the given value to the Floating Point Exception Control register.
aravindsv 0:ba7650f404af 227
aravindsv 0:ba7650f404af 228 \param [in] fpscr Floating Point Exception Control value to set
aravindsv 0:ba7650f404af 229 */
aravindsv 0:ba7650f404af 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
aravindsv 0:ba7650f404af 231 {
aravindsv 0:ba7650f404af 232 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 233 register uint32_t __regfpexc __ASM("fpexc");
aravindsv 0:ba7650f404af 234 __regfpexc = (fpexc);
aravindsv 0:ba7650f404af 235 #endif
aravindsv 0:ba7650f404af 236 }
aravindsv 0:ba7650f404af 237
aravindsv 0:ba7650f404af 238 /** \brief Get CPACR
aravindsv 0:ba7650f404af 239
aravindsv 0:ba7650f404af 240 This function returns the current value of the Coprocessor Access Control register.
aravindsv 0:ba7650f404af 241
aravindsv 0:ba7650f404af 242 \return Coprocessor Access Control register value
aravindsv 0:ba7650f404af 243 */
aravindsv 0:ba7650f404af 244 __STATIC_INLINE uint32_t __get_CPACR(void)
aravindsv 0:ba7650f404af 245 {
aravindsv 0:ba7650f404af 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
aravindsv 0:ba7650f404af 247 return __regCPACR;
aravindsv 0:ba7650f404af 248 }
aravindsv 0:ba7650f404af 249
aravindsv 0:ba7650f404af 250 /** \brief Set CPACR
aravindsv 0:ba7650f404af 251
aravindsv 0:ba7650f404af 252 This function assigns the given value to the Coprocessor Access Control register.
aravindsv 0:ba7650f404af 253
aravindsv 0:ba7650f404af 254 \param [in] cpacr Coprocessor Acccess Control value to set
aravindsv 0:ba7650f404af 255 */
aravindsv 0:ba7650f404af 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
aravindsv 0:ba7650f404af 257 {
aravindsv 0:ba7650f404af 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
aravindsv 0:ba7650f404af 259 __regCPACR = cpacr;
aravindsv 0:ba7650f404af 260 __ISB();
aravindsv 0:ba7650f404af 261 }
aravindsv 0:ba7650f404af 262
aravindsv 0:ba7650f404af 263 /** \brief Get CBAR
aravindsv 0:ba7650f404af 264
aravindsv 0:ba7650f404af 265 This function returns the value of the Configuration Base Address register.
aravindsv 0:ba7650f404af 266
aravindsv 0:ba7650f404af 267 \return Configuration Base Address register value
aravindsv 0:ba7650f404af 268 */
aravindsv 0:ba7650f404af 269 __STATIC_INLINE uint32_t __get_CBAR() {
aravindsv 0:ba7650f404af 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
aravindsv 0:ba7650f404af 271 return(__regCBAR);
aravindsv 0:ba7650f404af 272 }
aravindsv 0:ba7650f404af 273
aravindsv 0:ba7650f404af 274 /** \brief Get TTBR0
aravindsv 0:ba7650f404af 275
aravindsv 0:ba7650f404af 276 This function returns the value of the Translation Table Base Register 0.
aravindsv 0:ba7650f404af 277
aravindsv 0:ba7650f404af 278 \return Translation Table Base Register 0 value
aravindsv 0:ba7650f404af 279 */
aravindsv 0:ba7650f404af 280 __STATIC_INLINE uint32_t __get_TTBR0() {
aravindsv 0:ba7650f404af 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
aravindsv 0:ba7650f404af 282 return(__regTTBR0);
aravindsv 0:ba7650f404af 283 }
aravindsv 0:ba7650f404af 284
aravindsv 0:ba7650f404af 285 /** \brief Set TTBR0
aravindsv 0:ba7650f404af 286
aravindsv 0:ba7650f404af 287 This function assigns the given value to the Translation Table Base Register 0.
aravindsv 0:ba7650f404af 288
aravindsv 0:ba7650f404af 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
aravindsv 0:ba7650f404af 290 */
aravindsv 0:ba7650f404af 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
aravindsv 0:ba7650f404af 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
aravindsv 0:ba7650f404af 293 __regTTBR0 = ttbr0;
aravindsv 0:ba7650f404af 294 __ISB();
aravindsv 0:ba7650f404af 295 }
aravindsv 0:ba7650f404af 296
aravindsv 0:ba7650f404af 297 /** \brief Get DACR
aravindsv 0:ba7650f404af 298
aravindsv 0:ba7650f404af 299 This function returns the value of the Domain Access Control Register.
aravindsv 0:ba7650f404af 300
aravindsv 0:ba7650f404af 301 \return Domain Access Control Register value
aravindsv 0:ba7650f404af 302 */
aravindsv 0:ba7650f404af 303 __STATIC_INLINE uint32_t __get_DACR() {
aravindsv 0:ba7650f404af 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
aravindsv 0:ba7650f404af 305 return(__regDACR);
aravindsv 0:ba7650f404af 306 }
aravindsv 0:ba7650f404af 307
aravindsv 0:ba7650f404af 308 /** \brief Set DACR
aravindsv 0:ba7650f404af 309
aravindsv 0:ba7650f404af 310 This function assigns the given value to the Domain Access Control Register.
aravindsv 0:ba7650f404af 311
aravindsv 0:ba7650f404af 312 \param [in] dacr Domain Access Control Register value to set
aravindsv 0:ba7650f404af 313 */
aravindsv 0:ba7650f404af 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
aravindsv 0:ba7650f404af 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
aravindsv 0:ba7650f404af 316 __regDACR = dacr;
aravindsv 0:ba7650f404af 317 __ISB();
aravindsv 0:ba7650f404af 318 }
aravindsv 0:ba7650f404af 319
aravindsv 0:ba7650f404af 320 /******************************** Cache and BTAC enable ****************************************************/
aravindsv 0:ba7650f404af 321
aravindsv 0:ba7650f404af 322 /** \brief Set SCTLR
aravindsv 0:ba7650f404af 323
aravindsv 0:ba7650f404af 324 This function assigns the given value to the System Control Register.
aravindsv 0:ba7650f404af 325
aravindsv 0:ba7650f404af 326 \param [in] sctlr System Control Register value to set
aravindsv 0:ba7650f404af 327 */
aravindsv 0:ba7650f404af 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
aravindsv 0:ba7650f404af 329 {
aravindsv 0:ba7650f404af 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
aravindsv 0:ba7650f404af 331 __regSCTLR = sctlr;
aravindsv 0:ba7650f404af 332 }
aravindsv 0:ba7650f404af 333
aravindsv 0:ba7650f404af 334 /** \brief Get SCTLR
aravindsv 0:ba7650f404af 335
aravindsv 0:ba7650f404af 336 This function returns the value of the System Control Register.
aravindsv 0:ba7650f404af 337
aravindsv 0:ba7650f404af 338 \return System Control Register value
aravindsv 0:ba7650f404af 339 */
aravindsv 0:ba7650f404af 340 __STATIC_INLINE uint32_t __get_SCTLR() {
aravindsv 0:ba7650f404af 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
aravindsv 0:ba7650f404af 342 return(__regSCTLR);
aravindsv 0:ba7650f404af 343 }
aravindsv 0:ba7650f404af 344
aravindsv 0:ba7650f404af 345 /** \brief Enable Caches
aravindsv 0:ba7650f404af 346
aravindsv 0:ba7650f404af 347 Enable Caches
aravindsv 0:ba7650f404af 348 */
aravindsv 0:ba7650f404af 349 __STATIC_INLINE void __enable_caches(void) {
aravindsv 0:ba7650f404af 350 // Set I bit 12 to enable I Cache
aravindsv 0:ba7650f404af 351 // Set C bit 2 to enable D Cache
aravindsv 0:ba7650f404af 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
aravindsv 0:ba7650f404af 353 }
aravindsv 0:ba7650f404af 354
aravindsv 0:ba7650f404af 355 /** \brief Disable Caches
aravindsv 0:ba7650f404af 356
aravindsv 0:ba7650f404af 357 Disable Caches
aravindsv 0:ba7650f404af 358 */
aravindsv 0:ba7650f404af 359 __STATIC_INLINE void __disable_caches(void) {
aravindsv 0:ba7650f404af 360 // Clear I bit 12 to disable I Cache
aravindsv 0:ba7650f404af 361 // Clear C bit 2 to disable D Cache
aravindsv 0:ba7650f404af 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
aravindsv 0:ba7650f404af 363 __ISB();
aravindsv 0:ba7650f404af 364 }
aravindsv 0:ba7650f404af 365
aravindsv 0:ba7650f404af 366 /** \brief Enable BTAC
aravindsv 0:ba7650f404af 367
aravindsv 0:ba7650f404af 368 Enable BTAC
aravindsv 0:ba7650f404af 369 */
aravindsv 0:ba7650f404af 370 __STATIC_INLINE void __enable_btac(void) {
aravindsv 0:ba7650f404af 371 // Set Z bit 11 to enable branch prediction
aravindsv 0:ba7650f404af 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
aravindsv 0:ba7650f404af 373 __ISB();
aravindsv 0:ba7650f404af 374 }
aravindsv 0:ba7650f404af 375
aravindsv 0:ba7650f404af 376 /** \brief Disable BTAC
aravindsv 0:ba7650f404af 377
aravindsv 0:ba7650f404af 378 Disable BTAC
aravindsv 0:ba7650f404af 379 */
aravindsv 0:ba7650f404af 380 __STATIC_INLINE void __disable_btac(void) {
aravindsv 0:ba7650f404af 381 // Clear Z bit 11 to disable branch prediction
aravindsv 0:ba7650f404af 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
aravindsv 0:ba7650f404af 383 }
aravindsv 0:ba7650f404af 384
aravindsv 0:ba7650f404af 385
aravindsv 0:ba7650f404af 386 /** \brief Enable MMU
aravindsv 0:ba7650f404af 387
aravindsv 0:ba7650f404af 388 Enable MMU
aravindsv 0:ba7650f404af 389 */
aravindsv 0:ba7650f404af 390 __STATIC_INLINE void __enable_mmu(void) {
aravindsv 0:ba7650f404af 391 // Set M bit 0 to enable the MMU
aravindsv 0:ba7650f404af 392 // Set AFE bit to enable simplified access permissions model
aravindsv 0:ba7650f404af 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
aravindsv 0:ba7650f404af 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
aravindsv 0:ba7650f404af 395 __ISB();
aravindsv 0:ba7650f404af 396 }
aravindsv 0:ba7650f404af 397
aravindsv 0:ba7650f404af 398 /** \brief Disable MMU
aravindsv 0:ba7650f404af 399
aravindsv 0:ba7650f404af 400 Disable MMU
aravindsv 0:ba7650f404af 401 */
aravindsv 0:ba7650f404af 402 __STATIC_INLINE void __disable_mmu(void) {
aravindsv 0:ba7650f404af 403 // Clear M bit 0 to disable the MMU
aravindsv 0:ba7650f404af 404 __set_SCTLR( __get_SCTLR() & ~1);
aravindsv 0:ba7650f404af 405 __ISB();
aravindsv 0:ba7650f404af 406 }
aravindsv 0:ba7650f404af 407
aravindsv 0:ba7650f404af 408 /******************************** TLB maintenance operations ************************************************/
aravindsv 0:ba7650f404af 409 /** \brief Invalidate the whole tlb
aravindsv 0:ba7650f404af 410
aravindsv 0:ba7650f404af 411 TLBIALL. Invalidate the whole tlb
aravindsv 0:ba7650f404af 412 */
aravindsv 0:ba7650f404af 413
aravindsv 0:ba7650f404af 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
aravindsv 0:ba7650f404af 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
aravindsv 0:ba7650f404af 416 __TLBIALL = 0;
aravindsv 0:ba7650f404af 417 __DSB();
aravindsv 0:ba7650f404af 418 __ISB();
aravindsv 0:ba7650f404af 419 }
aravindsv 0:ba7650f404af 420
aravindsv 0:ba7650f404af 421 /******************************** BTB maintenance operations ************************************************/
aravindsv 0:ba7650f404af 422 /** \brief Invalidate entire branch predictor array
aravindsv 0:ba7650f404af 423
aravindsv 0:ba7650f404af 424 BPIALL. Branch Predictor Invalidate All.
aravindsv 0:ba7650f404af 425 */
aravindsv 0:ba7650f404af 426
aravindsv 0:ba7650f404af 427 __STATIC_INLINE void __v7_inv_btac(void) {
aravindsv 0:ba7650f404af 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
aravindsv 0:ba7650f404af 429 __BPIALL = 0;
aravindsv 0:ba7650f404af 430 __DSB(); //ensure completion of the invalidation
aravindsv 0:ba7650f404af 431 __ISB(); //ensure instruction fetch path sees new state
aravindsv 0:ba7650f404af 432 }
aravindsv 0:ba7650f404af 433
aravindsv 0:ba7650f404af 434
aravindsv 0:ba7650f404af 435 /******************************** L1 cache operations ******************************************************/
aravindsv 0:ba7650f404af 436
aravindsv 0:ba7650f404af 437 /** \brief Invalidate the whole I$
aravindsv 0:ba7650f404af 438
aravindsv 0:ba7650f404af 439 ICIALLU. Instruction Cache Invalidate All to PoU
aravindsv 0:ba7650f404af 440 */
aravindsv 0:ba7650f404af 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
aravindsv 0:ba7650f404af 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
aravindsv 0:ba7650f404af 443 __ICIALLU = 0;
aravindsv 0:ba7650f404af 444 __DSB(); //ensure completion of the invalidation
aravindsv 0:ba7650f404af 445 __ISB(); //ensure instruction fetch path sees new I cache state
aravindsv 0:ba7650f404af 446 }
aravindsv 0:ba7650f404af 447
aravindsv 0:ba7650f404af 448 /** \brief Clean D$ by MVA
aravindsv 0:ba7650f404af 449
aravindsv 0:ba7650f404af 450 DCCMVAC. Data cache clean by MVA to PoC
aravindsv 0:ba7650f404af 451 */
aravindsv 0:ba7650f404af 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
aravindsv 0:ba7650f404af 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
aravindsv 0:ba7650f404af 454 __DCCMVAC = (uint32_t)va;
aravindsv 0:ba7650f404af 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
aravindsv 0:ba7650f404af 456 }
aravindsv 0:ba7650f404af 457
aravindsv 0:ba7650f404af 458 /** \brief Invalidate D$ by MVA
aravindsv 0:ba7650f404af 459
aravindsv 0:ba7650f404af 460 DCIMVAC. Data cache invalidate by MVA to PoC
aravindsv 0:ba7650f404af 461 */
aravindsv 0:ba7650f404af 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
aravindsv 0:ba7650f404af 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
aravindsv 0:ba7650f404af 464 __DCIMVAC = (uint32_t)va;
aravindsv 0:ba7650f404af 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
aravindsv 0:ba7650f404af 466 }
aravindsv 0:ba7650f404af 467
aravindsv 0:ba7650f404af 468 /** \brief Clean and Invalidate D$ by MVA
aravindsv 0:ba7650f404af 469
aravindsv 0:ba7650f404af 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
aravindsv 0:ba7650f404af 471 */
aravindsv 0:ba7650f404af 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
aravindsv 0:ba7650f404af 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
aravindsv 0:ba7650f404af 474 __DCCIMVAC = (uint32_t)va;
aravindsv 0:ba7650f404af 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
aravindsv 0:ba7650f404af 476 }
aravindsv 0:ba7650f404af 477
aravindsv 0:ba7650f404af 478 /** \brief Clean and Invalidate the entire data or unified cache
aravindsv 0:ba7650f404af 479
aravindsv 0:ba7650f404af 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
aravindsv 0:ba7650f404af 481 */
aravindsv 0:ba7650f404af 482 #pragma push
aravindsv 0:ba7650f404af 483 #pragma arm
aravindsv 0:ba7650f404af 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
aravindsv 0:ba7650f404af 485 ARM
aravindsv 0:ba7650f404af 486
aravindsv 0:ba7650f404af 487 PUSH {R4-R11}
aravindsv 0:ba7650f404af 488
aravindsv 0:ba7650f404af 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
aravindsv 0:ba7650f404af 490 ANDS R3, R6, #0x07000000 // Extract coherency level
aravindsv 0:ba7650f404af 491 MOV R3, R3, LSR #23 // Total cache levels << 1
aravindsv 0:ba7650f404af 492 BEQ Finished // If 0, no need to clean
aravindsv 0:ba7650f404af 493
aravindsv 0:ba7650f404af 494 MOV R10, #0 // R10 holds current cache level << 1
aravindsv 0:ba7650f404af 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
aravindsv 0:ba7650f404af 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
aravindsv 0:ba7650f404af 497 AND R1, R1, #7 // Isolate those lower 3 bits
aravindsv 0:ba7650f404af 498 CMP R1, #2
aravindsv 0:ba7650f404af 499 BLT Skip // No cache or only instruction cache at this level
aravindsv 0:ba7650f404af 500
aravindsv 0:ba7650f404af 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
aravindsv 0:ba7650f404af 502 ISB // ISB to sync the change to the CacheSizeID reg
aravindsv 0:ba7650f404af 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
aravindsv 0:ba7650f404af 504 AND R2, R1, #7 // Extract the line length field
aravindsv 0:ba7650f404af 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
aravindsv 0:ba7650f404af 506 LDR R4, =0x3FF
aravindsv 0:ba7650f404af 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
aravindsv 0:ba7650f404af 508 CLZ R5, R4 // R5 is the bit position of the way size increment
aravindsv 0:ba7650f404af 509 LDR R7, =0x7FFF
aravindsv 0:ba7650f404af 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
aravindsv 0:ba7650f404af 511
aravindsv 0:ba7650f404af 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
aravindsv 0:ba7650f404af 513
aravindsv 0:ba7650f404af 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
aravindsv 0:ba7650f404af 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
aravindsv 0:ba7650f404af 516 CMP R0, #0
aravindsv 0:ba7650f404af 517 BNE Dccsw
aravindsv 0:ba7650f404af 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
aravindsv 0:ba7650f404af 519 B cont
aravindsv 0:ba7650f404af 520 Dccsw CMP R0, #1
aravindsv 0:ba7650f404af 521 BNE Dccisw
aravindsv 0:ba7650f404af 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
aravindsv 0:ba7650f404af 523 B cont
aravindsv 0:ba7650f404af 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
aravindsv 0:ba7650f404af 525 cont SUBS R9, R9, #1 // Decrement the Way number
aravindsv 0:ba7650f404af 526 BGE Loop3
aravindsv 0:ba7650f404af 527 SUBS R7, R7, #1 // Decrement the Set number
aravindsv 0:ba7650f404af 528 BGE Loop2
aravindsv 0:ba7650f404af 529 Skip ADD R10, R10, #2 // Increment the cache number
aravindsv 0:ba7650f404af 530 CMP R3, R10
aravindsv 0:ba7650f404af 531 BGT Loop1
aravindsv 0:ba7650f404af 532
aravindsv 0:ba7650f404af 533 Finished
aravindsv 0:ba7650f404af 534 DSB
aravindsv 0:ba7650f404af 535 POP {R4-R11}
aravindsv 0:ba7650f404af 536 BX lr
aravindsv 0:ba7650f404af 537
aravindsv 0:ba7650f404af 538 }
aravindsv 0:ba7650f404af 539 #pragma pop
aravindsv 0:ba7650f404af 540
aravindsv 0:ba7650f404af 541
aravindsv 0:ba7650f404af 542 /** \brief Invalidate the whole D$
aravindsv 0:ba7650f404af 543
aravindsv 0:ba7650f404af 544 DCISW. Invalidate by Set/Way
aravindsv 0:ba7650f404af 545 */
aravindsv 0:ba7650f404af 546
aravindsv 0:ba7650f404af 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
aravindsv 0:ba7650f404af 548 __v7_all_cache(0);
aravindsv 0:ba7650f404af 549 }
aravindsv 0:ba7650f404af 550
aravindsv 0:ba7650f404af 551 /** \brief Clean the whole D$
aravindsv 0:ba7650f404af 552
aravindsv 0:ba7650f404af 553 DCCSW. Clean by Set/Way
aravindsv 0:ba7650f404af 554 */
aravindsv 0:ba7650f404af 555
aravindsv 0:ba7650f404af 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
aravindsv 0:ba7650f404af 557 __v7_all_cache(1);
aravindsv 0:ba7650f404af 558 }
aravindsv 0:ba7650f404af 559
aravindsv 0:ba7650f404af 560 /** \brief Clean and invalidate the whole D$
aravindsv 0:ba7650f404af 561
aravindsv 0:ba7650f404af 562 DCCISW. Clean and Invalidate by Set/Way
aravindsv 0:ba7650f404af 563 */
aravindsv 0:ba7650f404af 564
aravindsv 0:ba7650f404af 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
aravindsv 0:ba7650f404af 566 __v7_all_cache(2);
aravindsv 0:ba7650f404af 567 }
aravindsv 0:ba7650f404af 568
aravindsv 0:ba7650f404af 569 #include "core_ca_mmu.h"
aravindsv 0:ba7650f404af 570
aravindsv 0:ba7650f404af 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
aravindsv 0:ba7650f404af 572
aravindsv 0:ba7650f404af 573 #error IAR Compiler support not implemented for Cortex-A
aravindsv 0:ba7650f404af 574
aravindsv 0:ba7650f404af 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
aravindsv 0:ba7650f404af 576 /* GNU gcc specific functions */
aravindsv 0:ba7650f404af 577
aravindsv 0:ba7650f404af 578 #define MODE_USR 0x10
aravindsv 0:ba7650f404af 579 #define MODE_FIQ 0x11
aravindsv 0:ba7650f404af 580 #define MODE_IRQ 0x12
aravindsv 0:ba7650f404af 581 #define MODE_SVC 0x13
aravindsv 0:ba7650f404af 582 #define MODE_MON 0x16
aravindsv 0:ba7650f404af 583 #define MODE_ABT 0x17
aravindsv 0:ba7650f404af 584 #define MODE_HYP 0x1A
aravindsv 0:ba7650f404af 585 #define MODE_UND 0x1B
aravindsv 0:ba7650f404af 586 #define MODE_SYS 0x1F
aravindsv 0:ba7650f404af 587
aravindsv 0:ba7650f404af 588
aravindsv 0:ba7650f404af 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
aravindsv 0:ba7650f404af 590 {
aravindsv 0:ba7650f404af 591 __ASM volatile ("cpsie i");
aravindsv 0:ba7650f404af 592 }
aravindsv 0:ba7650f404af 593
aravindsv 0:ba7650f404af 594 /** \brief Disable IRQ Interrupts
aravindsv 0:ba7650f404af 595
aravindsv 0:ba7650f404af 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
aravindsv 0:ba7650f404af 597 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 598 */
aravindsv 0:ba7650f404af 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
aravindsv 0:ba7650f404af 600 {
aravindsv 0:ba7650f404af 601 uint32_t result;
aravindsv 0:ba7650f404af 602
aravindsv 0:ba7650f404af 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
aravindsv 0:ba7650f404af 604 __ASM volatile ("cpsid i");
aravindsv 0:ba7650f404af 605 return(result & 0x80);
aravindsv 0:ba7650f404af 606 }
aravindsv 0:ba7650f404af 607
aravindsv 0:ba7650f404af 608
aravindsv 0:ba7650f404af 609 /** \brief Get APSR Register
aravindsv 0:ba7650f404af 610
aravindsv 0:ba7650f404af 611 This function returns the content of the APSR Register.
aravindsv 0:ba7650f404af 612
aravindsv 0:ba7650f404af 613 \return APSR Register value
aravindsv 0:ba7650f404af 614 */
aravindsv 0:ba7650f404af 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
aravindsv 0:ba7650f404af 616 {
aravindsv 0:ba7650f404af 617 #if 1
aravindsv 0:ba7650f404af 618 register uint32_t __regAPSR;
aravindsv 0:ba7650f404af 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
aravindsv 0:ba7650f404af 620 #else
aravindsv 0:ba7650f404af 621 register uint32_t __regAPSR __ASM("apsr");
aravindsv 0:ba7650f404af 622 #endif
aravindsv 0:ba7650f404af 623 return(__regAPSR);
aravindsv 0:ba7650f404af 624 }
aravindsv 0:ba7650f404af 625
aravindsv 0:ba7650f404af 626
aravindsv 0:ba7650f404af 627 /** \brief Get CPSR Register
aravindsv 0:ba7650f404af 628
aravindsv 0:ba7650f404af 629 This function returns the content of the CPSR Register.
aravindsv 0:ba7650f404af 630
aravindsv 0:ba7650f404af 631 \return CPSR Register value
aravindsv 0:ba7650f404af 632 */
aravindsv 0:ba7650f404af 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
aravindsv 0:ba7650f404af 634 {
aravindsv 0:ba7650f404af 635 #if 1
aravindsv 0:ba7650f404af 636 register uint32_t __regCPSR;
aravindsv 0:ba7650f404af 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
aravindsv 0:ba7650f404af 638 #else
aravindsv 0:ba7650f404af 639 register uint32_t __regCPSR __ASM("cpsr");
aravindsv 0:ba7650f404af 640 #endif
aravindsv 0:ba7650f404af 641 return(__regCPSR);
aravindsv 0:ba7650f404af 642 }
aravindsv 0:ba7650f404af 643
aravindsv 0:ba7650f404af 644 #if 0
aravindsv 0:ba7650f404af 645 /** \brief Set Stack Pointer
aravindsv 0:ba7650f404af 646
aravindsv 0:ba7650f404af 647 This function assigns the given value to the current stack pointer.
aravindsv 0:ba7650f404af 648
aravindsv 0:ba7650f404af 649 \param [in] topOfStack Stack Pointer value to set
aravindsv 0:ba7650f404af 650 */
aravindsv 0:ba7650f404af 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
aravindsv 0:ba7650f404af 652 {
aravindsv 0:ba7650f404af 653 register uint32_t __regSP __ASM("sp");
aravindsv 0:ba7650f404af 654 __regSP = topOfStack;
aravindsv 0:ba7650f404af 655 }
aravindsv 0:ba7650f404af 656 #endif
aravindsv 0:ba7650f404af 657
aravindsv 0:ba7650f404af 658 /** \brief Get link register
aravindsv 0:ba7650f404af 659
aravindsv 0:ba7650f404af 660 This function returns the value of the link register
aravindsv 0:ba7650f404af 661
aravindsv 0:ba7650f404af 662 \return Value of link register
aravindsv 0:ba7650f404af 663 */
aravindsv 0:ba7650f404af 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
aravindsv 0:ba7650f404af 665 {
aravindsv 0:ba7650f404af 666 register uint32_t __reglr __ASM("lr");
aravindsv 0:ba7650f404af 667 return(__reglr);
aravindsv 0:ba7650f404af 668 }
aravindsv 0:ba7650f404af 669
aravindsv 0:ba7650f404af 670 #if 0
aravindsv 0:ba7650f404af 671 /** \brief Set link register
aravindsv 0:ba7650f404af 672
aravindsv 0:ba7650f404af 673 This function sets the value of the link register
aravindsv 0:ba7650f404af 674
aravindsv 0:ba7650f404af 675 \param [in] lr LR value to set
aravindsv 0:ba7650f404af 676 */
aravindsv 0:ba7650f404af 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
aravindsv 0:ba7650f404af 678 {
aravindsv 0:ba7650f404af 679 register uint32_t __reglr __ASM("lr");
aravindsv 0:ba7650f404af 680 __reglr = lr;
aravindsv 0:ba7650f404af 681 }
aravindsv 0:ba7650f404af 682 #endif
aravindsv 0:ba7650f404af 683
aravindsv 0:ba7650f404af 684 /** \brief Set Process Stack Pointer
aravindsv 0:ba7650f404af 685
aravindsv 0:ba7650f404af 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
aravindsv 0:ba7650f404af 687
aravindsv 0:ba7650f404af 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
aravindsv 0:ba7650f404af 689 */
aravindsv 0:ba7650f404af 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
aravindsv 0:ba7650f404af 691 {
aravindsv 0:ba7650f404af 692 __asm__ volatile (
aravindsv 0:ba7650f404af 693 ".ARM;"
aravindsv 0:ba7650f404af 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
aravindsv 0:ba7650f404af 695
aravindsv 0:ba7650f404af 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
aravindsv 0:ba7650f404af 697 "MRS R1, CPSR;"
aravindsv 0:ba7650f404af 698 "CPS %0;" /* ;no effect in USR mode */
aravindsv 0:ba7650f404af 699 "MOV SP, R0;"
aravindsv 0:ba7650f404af 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
aravindsv 0:ba7650f404af 701 "ISB;"
aravindsv 0:ba7650f404af 702 //"BX LR;"
aravindsv 0:ba7650f404af 703 :
aravindsv 0:ba7650f404af 704 : "i"(MODE_SYS)
aravindsv 0:ba7650f404af 705 : "r0", "r1");
aravindsv 0:ba7650f404af 706 return;
aravindsv 0:ba7650f404af 707 }
aravindsv 0:ba7650f404af 708
aravindsv 0:ba7650f404af 709 /** \brief Set User Mode
aravindsv 0:ba7650f404af 710
aravindsv 0:ba7650f404af 711 This function changes the processor state to User Mode
aravindsv 0:ba7650f404af 712 */
aravindsv 0:ba7650f404af 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
aravindsv 0:ba7650f404af 714 {
aravindsv 0:ba7650f404af 715 __asm__ volatile (
aravindsv 0:ba7650f404af 716 ".ARM;"
aravindsv 0:ba7650f404af 717
aravindsv 0:ba7650f404af 718 "CPS %0;"
aravindsv 0:ba7650f404af 719 //"BX LR;"
aravindsv 0:ba7650f404af 720 :
aravindsv 0:ba7650f404af 721 : "i"(MODE_USR)
aravindsv 0:ba7650f404af 722 : );
aravindsv 0:ba7650f404af 723 return;
aravindsv 0:ba7650f404af 724 }
aravindsv 0:ba7650f404af 725
aravindsv 0:ba7650f404af 726
aravindsv 0:ba7650f404af 727 /** \brief Enable FIQ
aravindsv 0:ba7650f404af 728
aravindsv 0:ba7650f404af 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
aravindsv 0:ba7650f404af 730 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 731 */
aravindsv 0:ba7650f404af 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
aravindsv 0:ba7650f404af 733
aravindsv 0:ba7650f404af 734
aravindsv 0:ba7650f404af 735 /** \brief Disable FIQ
aravindsv 0:ba7650f404af 736
aravindsv 0:ba7650f404af 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
aravindsv 0:ba7650f404af 738 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 739 */
aravindsv 0:ba7650f404af 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
aravindsv 0:ba7650f404af 741
aravindsv 0:ba7650f404af 742
aravindsv 0:ba7650f404af 743 /** \brief Get FPSCR
aravindsv 0:ba7650f404af 744
aravindsv 0:ba7650f404af 745 This function returns the current value of the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 746
aravindsv 0:ba7650f404af 747 \return Floating Point Status/Control register value
aravindsv 0:ba7650f404af 748 */
aravindsv 0:ba7650f404af 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
aravindsv 0:ba7650f404af 750 {
aravindsv 0:ba7650f404af 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 752 #if 1
aravindsv 0:ba7650f404af 753 uint32_t result;
aravindsv 0:ba7650f404af 754
aravindsv 0:ba7650f404af 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
aravindsv 0:ba7650f404af 756 return (result);
aravindsv 0:ba7650f404af 757 #else
aravindsv 0:ba7650f404af 758 register uint32_t __regfpscr __ASM("fpscr");
aravindsv 0:ba7650f404af 759 return(__regfpscr);
aravindsv 0:ba7650f404af 760 #endif
aravindsv 0:ba7650f404af 761 #else
aravindsv 0:ba7650f404af 762 return(0);
aravindsv 0:ba7650f404af 763 #endif
aravindsv 0:ba7650f404af 764 }
aravindsv 0:ba7650f404af 765
aravindsv 0:ba7650f404af 766
aravindsv 0:ba7650f404af 767 /** \brief Set FPSCR
aravindsv 0:ba7650f404af 768
aravindsv 0:ba7650f404af 769 This function assigns the given value to the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 770
aravindsv 0:ba7650f404af 771 \param [in] fpscr Floating Point Status/Control value to set
aravindsv 0:ba7650f404af 772 */
aravindsv 0:ba7650f404af 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
aravindsv 0:ba7650f404af 774 {
aravindsv 0:ba7650f404af 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 776 #if 1
aravindsv 0:ba7650f404af 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
aravindsv 0:ba7650f404af 778 #else
aravindsv 0:ba7650f404af 779 register uint32_t __regfpscr __ASM("fpscr");
aravindsv 0:ba7650f404af 780 __regfpscr = (fpscr);
aravindsv 0:ba7650f404af 781 #endif
aravindsv 0:ba7650f404af 782 #endif
aravindsv 0:ba7650f404af 783 }
aravindsv 0:ba7650f404af 784
aravindsv 0:ba7650f404af 785 /** \brief Get FPEXC
aravindsv 0:ba7650f404af 786
aravindsv 0:ba7650f404af 787 This function returns the current value of the Floating Point Exception Control register.
aravindsv 0:ba7650f404af 788
aravindsv 0:ba7650f404af 789 \return Floating Point Exception Control register value
aravindsv 0:ba7650f404af 790 */
aravindsv 0:ba7650f404af 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
aravindsv 0:ba7650f404af 792 {
aravindsv 0:ba7650f404af 793 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 794 #if 1
aravindsv 0:ba7650f404af 795 uint32_t result;
aravindsv 0:ba7650f404af 796
aravindsv 0:ba7650f404af 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
aravindsv 0:ba7650f404af 798 return (result);
aravindsv 0:ba7650f404af 799 #else
aravindsv 0:ba7650f404af 800 register uint32_t __regfpexc __ASM("fpexc");
aravindsv 0:ba7650f404af 801 return(__regfpexc);
aravindsv 0:ba7650f404af 802 #endif
aravindsv 0:ba7650f404af 803 #else
aravindsv 0:ba7650f404af 804 return(0);
aravindsv 0:ba7650f404af 805 #endif
aravindsv 0:ba7650f404af 806 }
aravindsv 0:ba7650f404af 807
aravindsv 0:ba7650f404af 808
aravindsv 0:ba7650f404af 809 /** \brief Set FPEXC
aravindsv 0:ba7650f404af 810
aravindsv 0:ba7650f404af 811 This function assigns the given value to the Floating Point Exception Control register.
aravindsv 0:ba7650f404af 812
aravindsv 0:ba7650f404af 813 \param [in] fpscr Floating Point Exception Control value to set
aravindsv 0:ba7650f404af 814 */
aravindsv 0:ba7650f404af 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
aravindsv 0:ba7650f404af 816 {
aravindsv 0:ba7650f404af 817 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 818 #if 1
aravindsv 0:ba7650f404af 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
aravindsv 0:ba7650f404af 820 #else
aravindsv 0:ba7650f404af 821 register uint32_t __regfpexc __ASM("fpexc");
aravindsv 0:ba7650f404af 822 __regfpexc = (fpexc);
aravindsv 0:ba7650f404af 823 #endif
aravindsv 0:ba7650f404af 824 #endif
aravindsv 0:ba7650f404af 825 }
aravindsv 0:ba7650f404af 826
aravindsv 0:ba7650f404af 827 /** \brief Get CPACR
aravindsv 0:ba7650f404af 828
aravindsv 0:ba7650f404af 829 This function returns the current value of the Coprocessor Access Control register.
aravindsv 0:ba7650f404af 830
aravindsv 0:ba7650f404af 831 \return Coprocessor Access Control register value
aravindsv 0:ba7650f404af 832 */
aravindsv 0:ba7650f404af 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
aravindsv 0:ba7650f404af 834 {
aravindsv 0:ba7650f404af 835 #if 1
aravindsv 0:ba7650f404af 836 register uint32_t __regCPACR;
aravindsv 0:ba7650f404af 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
aravindsv 0:ba7650f404af 838 #else
aravindsv 0:ba7650f404af 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
aravindsv 0:ba7650f404af 840 #endif
aravindsv 0:ba7650f404af 841 return __regCPACR;
aravindsv 0:ba7650f404af 842 }
aravindsv 0:ba7650f404af 843
aravindsv 0:ba7650f404af 844 /** \brief Set CPACR
aravindsv 0:ba7650f404af 845
aravindsv 0:ba7650f404af 846 This function assigns the given value to the Coprocessor Access Control register.
aravindsv 0:ba7650f404af 847
aravindsv 0:ba7650f404af 848 \param [in] cpacr Coprocessor Acccess Control value to set
aravindsv 0:ba7650f404af 849 */
aravindsv 0:ba7650f404af 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
aravindsv 0:ba7650f404af 851 {
aravindsv 0:ba7650f404af 852 #if 1
aravindsv 0:ba7650f404af 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
aravindsv 0:ba7650f404af 854 #else
aravindsv 0:ba7650f404af 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
aravindsv 0:ba7650f404af 856 __regCPACR = cpacr;
aravindsv 0:ba7650f404af 857 #endif
aravindsv 0:ba7650f404af 858 __ISB();
aravindsv 0:ba7650f404af 859 }
aravindsv 0:ba7650f404af 860
aravindsv 0:ba7650f404af 861 /** \brief Get CBAR
aravindsv 0:ba7650f404af 862
aravindsv 0:ba7650f404af 863 This function returns the value of the Configuration Base Address register.
aravindsv 0:ba7650f404af 864
aravindsv 0:ba7650f404af 865 \return Configuration Base Address register value
aravindsv 0:ba7650f404af 866 */
aravindsv 0:ba7650f404af 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
aravindsv 0:ba7650f404af 868 #if 1
aravindsv 0:ba7650f404af 869 register uint32_t __regCBAR;
aravindsv 0:ba7650f404af 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
aravindsv 0:ba7650f404af 871 #else
aravindsv 0:ba7650f404af 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
aravindsv 0:ba7650f404af 873 #endif
aravindsv 0:ba7650f404af 874 return(__regCBAR);
aravindsv 0:ba7650f404af 875 }
aravindsv 0:ba7650f404af 876
aravindsv 0:ba7650f404af 877 /** \brief Get TTBR0
aravindsv 0:ba7650f404af 878
aravindsv 0:ba7650f404af 879 This function returns the value of the Translation Table Base Register 0.
aravindsv 0:ba7650f404af 880
aravindsv 0:ba7650f404af 881 \return Translation Table Base Register 0 value
aravindsv 0:ba7650f404af 882 */
aravindsv 0:ba7650f404af 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
aravindsv 0:ba7650f404af 884 #if 1
aravindsv 0:ba7650f404af 885 register uint32_t __regTTBR0;
aravindsv 0:ba7650f404af 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
aravindsv 0:ba7650f404af 887 #else
aravindsv 0:ba7650f404af 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
aravindsv 0:ba7650f404af 889 #endif
aravindsv 0:ba7650f404af 890 return(__regTTBR0);
aravindsv 0:ba7650f404af 891 }
aravindsv 0:ba7650f404af 892
aravindsv 0:ba7650f404af 893 /** \brief Set TTBR0
aravindsv 0:ba7650f404af 894
aravindsv 0:ba7650f404af 895 This function assigns the given value to the Translation Table Base Register 0.
aravindsv 0:ba7650f404af 896
aravindsv 0:ba7650f404af 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
aravindsv 0:ba7650f404af 898 */
aravindsv 0:ba7650f404af 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
aravindsv 0:ba7650f404af 900 #if 1
aravindsv 0:ba7650f404af 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
aravindsv 0:ba7650f404af 902 #else
aravindsv 0:ba7650f404af 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
aravindsv 0:ba7650f404af 904 __regTTBR0 = ttbr0;
aravindsv 0:ba7650f404af 905 #endif
aravindsv 0:ba7650f404af 906 __ISB();
aravindsv 0:ba7650f404af 907 }
aravindsv 0:ba7650f404af 908
aravindsv 0:ba7650f404af 909 /** \brief Get DACR
aravindsv 0:ba7650f404af 910
aravindsv 0:ba7650f404af 911 This function returns the value of the Domain Access Control Register.
aravindsv 0:ba7650f404af 912
aravindsv 0:ba7650f404af 913 \return Domain Access Control Register value
aravindsv 0:ba7650f404af 914 */
aravindsv 0:ba7650f404af 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
aravindsv 0:ba7650f404af 916 #if 1
aravindsv 0:ba7650f404af 917 register uint32_t __regDACR;
aravindsv 0:ba7650f404af 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
aravindsv 0:ba7650f404af 919 #else
aravindsv 0:ba7650f404af 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
aravindsv 0:ba7650f404af 921 #endif
aravindsv 0:ba7650f404af 922 return(__regDACR);
aravindsv 0:ba7650f404af 923 }
aravindsv 0:ba7650f404af 924
aravindsv 0:ba7650f404af 925 /** \brief Set DACR
aravindsv 0:ba7650f404af 926
aravindsv 0:ba7650f404af 927 This function assigns the given value to the Domain Access Control Register.
aravindsv 0:ba7650f404af 928
aravindsv 0:ba7650f404af 929 \param [in] dacr Domain Access Control Register value to set
aravindsv 0:ba7650f404af 930 */
aravindsv 0:ba7650f404af 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
aravindsv 0:ba7650f404af 932 #if 1
aravindsv 0:ba7650f404af 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
aravindsv 0:ba7650f404af 934 #else
aravindsv 0:ba7650f404af 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
aravindsv 0:ba7650f404af 936 __regDACR = dacr;
aravindsv 0:ba7650f404af 937 #endif
aravindsv 0:ba7650f404af 938 __ISB();
aravindsv 0:ba7650f404af 939 }
aravindsv 0:ba7650f404af 940
aravindsv 0:ba7650f404af 941 /******************************** Cache and BTAC enable ****************************************************/
aravindsv 0:ba7650f404af 942
aravindsv 0:ba7650f404af 943 /** \brief Set SCTLR
aravindsv 0:ba7650f404af 944
aravindsv 0:ba7650f404af 945 This function assigns the given value to the System Control Register.
aravindsv 0:ba7650f404af 946
aravindsv 0:ba7650f404af 947 \param [in] sctlr System Control Register value to set
aravindsv 0:ba7650f404af 948 */
aravindsv 0:ba7650f404af 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
aravindsv 0:ba7650f404af 950 {
aravindsv 0:ba7650f404af 951 #if 1
aravindsv 0:ba7650f404af 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
aravindsv 0:ba7650f404af 953 #else
aravindsv 0:ba7650f404af 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
aravindsv 0:ba7650f404af 955 __regSCTLR = sctlr;
aravindsv 0:ba7650f404af 956 #endif
aravindsv 0:ba7650f404af 957 }
aravindsv 0:ba7650f404af 958
aravindsv 0:ba7650f404af 959 /** \brief Get SCTLR
aravindsv 0:ba7650f404af 960
aravindsv 0:ba7650f404af 961 This function returns the value of the System Control Register.
aravindsv 0:ba7650f404af 962
aravindsv 0:ba7650f404af 963 \return System Control Register value
aravindsv 0:ba7650f404af 964 */
aravindsv 0:ba7650f404af 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
aravindsv 0:ba7650f404af 966 #if 1
aravindsv 0:ba7650f404af 967 register uint32_t __regSCTLR;
aravindsv 0:ba7650f404af 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
aravindsv 0:ba7650f404af 969 #else
aravindsv 0:ba7650f404af 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
aravindsv 0:ba7650f404af 971 #endif
aravindsv 0:ba7650f404af 972 return(__regSCTLR);
aravindsv 0:ba7650f404af 973 }
aravindsv 0:ba7650f404af 974
aravindsv 0:ba7650f404af 975 /** \brief Enable Caches
aravindsv 0:ba7650f404af 976
aravindsv 0:ba7650f404af 977 Enable Caches
aravindsv 0:ba7650f404af 978 */
aravindsv 0:ba7650f404af 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
aravindsv 0:ba7650f404af 980 // Set I bit 12 to enable I Cache
aravindsv 0:ba7650f404af 981 // Set C bit 2 to enable D Cache
aravindsv 0:ba7650f404af 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
aravindsv 0:ba7650f404af 983 }
aravindsv 0:ba7650f404af 984
aravindsv 0:ba7650f404af 985 /** \brief Disable Caches
aravindsv 0:ba7650f404af 986
aravindsv 0:ba7650f404af 987 Disable Caches
aravindsv 0:ba7650f404af 988 */
aravindsv 0:ba7650f404af 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
aravindsv 0:ba7650f404af 990 // Clear I bit 12 to disable I Cache
aravindsv 0:ba7650f404af 991 // Clear C bit 2 to disable D Cache
aravindsv 0:ba7650f404af 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
aravindsv 0:ba7650f404af 993 __ISB();
aravindsv 0:ba7650f404af 994 }
aravindsv 0:ba7650f404af 995
aravindsv 0:ba7650f404af 996 /** \brief Enable BTAC
aravindsv 0:ba7650f404af 997
aravindsv 0:ba7650f404af 998 Enable BTAC
aravindsv 0:ba7650f404af 999 */
aravindsv 0:ba7650f404af 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
aravindsv 0:ba7650f404af 1001 // Set Z bit 11 to enable branch prediction
aravindsv 0:ba7650f404af 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
aravindsv 0:ba7650f404af 1003 __ISB();
aravindsv 0:ba7650f404af 1004 }
aravindsv 0:ba7650f404af 1005
aravindsv 0:ba7650f404af 1006 /** \brief Disable BTAC
aravindsv 0:ba7650f404af 1007
aravindsv 0:ba7650f404af 1008 Disable BTAC
aravindsv 0:ba7650f404af 1009 */
aravindsv 0:ba7650f404af 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
aravindsv 0:ba7650f404af 1011 // Clear Z bit 11 to disable branch prediction
aravindsv 0:ba7650f404af 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
aravindsv 0:ba7650f404af 1013 }
aravindsv 0:ba7650f404af 1014
aravindsv 0:ba7650f404af 1015
aravindsv 0:ba7650f404af 1016 /** \brief Enable MMU
aravindsv 0:ba7650f404af 1017
aravindsv 0:ba7650f404af 1018 Enable MMU
aravindsv 0:ba7650f404af 1019 */
aravindsv 0:ba7650f404af 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
aravindsv 0:ba7650f404af 1021 // Set M bit 0 to enable the MMU
aravindsv 0:ba7650f404af 1022 // Set AFE bit to enable simplified access permissions model
aravindsv 0:ba7650f404af 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
aravindsv 0:ba7650f404af 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
aravindsv 0:ba7650f404af 1025 __ISB();
aravindsv 0:ba7650f404af 1026 }
aravindsv 0:ba7650f404af 1027
aravindsv 0:ba7650f404af 1028 /** \brief Disable MMU
aravindsv 0:ba7650f404af 1029
aravindsv 0:ba7650f404af 1030 Disable MMU
aravindsv 0:ba7650f404af 1031 */
aravindsv 0:ba7650f404af 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
aravindsv 0:ba7650f404af 1033 // Clear M bit 0 to disable the MMU
aravindsv 0:ba7650f404af 1034 __set_SCTLR( __get_SCTLR() & ~1);
aravindsv 0:ba7650f404af 1035 __ISB();
aravindsv 0:ba7650f404af 1036 }
aravindsv 0:ba7650f404af 1037
aravindsv 0:ba7650f404af 1038 /******************************** TLB maintenance operations ************************************************/
aravindsv 0:ba7650f404af 1039 /** \brief Invalidate the whole tlb
aravindsv 0:ba7650f404af 1040
aravindsv 0:ba7650f404af 1041 TLBIALL. Invalidate the whole tlb
aravindsv 0:ba7650f404af 1042 */
aravindsv 0:ba7650f404af 1043
aravindsv 0:ba7650f404af 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
aravindsv 0:ba7650f404af 1045 #if 1
aravindsv 0:ba7650f404af 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
aravindsv 0:ba7650f404af 1047 #else
aravindsv 0:ba7650f404af 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
aravindsv 0:ba7650f404af 1049 __TLBIALL = 0;
aravindsv 0:ba7650f404af 1050 #endif
aravindsv 0:ba7650f404af 1051 __DSB();
aravindsv 0:ba7650f404af 1052 __ISB();
aravindsv 0:ba7650f404af 1053 }
aravindsv 0:ba7650f404af 1054
aravindsv 0:ba7650f404af 1055 /******************************** BTB maintenance operations ************************************************/
aravindsv 0:ba7650f404af 1056 /** \brief Invalidate entire branch predictor array
aravindsv 0:ba7650f404af 1057
aravindsv 0:ba7650f404af 1058 BPIALL. Branch Predictor Invalidate All.
aravindsv 0:ba7650f404af 1059 */
aravindsv 0:ba7650f404af 1060
aravindsv 0:ba7650f404af 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
aravindsv 0:ba7650f404af 1062 #if 1
aravindsv 0:ba7650f404af 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
aravindsv 0:ba7650f404af 1064 #else
aravindsv 0:ba7650f404af 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
aravindsv 0:ba7650f404af 1066 __BPIALL = 0;
aravindsv 0:ba7650f404af 1067 #endif
aravindsv 0:ba7650f404af 1068 __DSB(); //ensure completion of the invalidation
aravindsv 0:ba7650f404af 1069 __ISB(); //ensure instruction fetch path sees new state
aravindsv 0:ba7650f404af 1070 }
aravindsv 0:ba7650f404af 1071
aravindsv 0:ba7650f404af 1072
aravindsv 0:ba7650f404af 1073 /******************************** L1 cache operations ******************************************************/
aravindsv 0:ba7650f404af 1074
aravindsv 0:ba7650f404af 1075 /** \brief Invalidate the whole I$
aravindsv 0:ba7650f404af 1076
aravindsv 0:ba7650f404af 1077 ICIALLU. Instruction Cache Invalidate All to PoU
aravindsv 0:ba7650f404af 1078 */
aravindsv 0:ba7650f404af 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
aravindsv 0:ba7650f404af 1080 #if 1
aravindsv 0:ba7650f404af 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
aravindsv 0:ba7650f404af 1082 #else
aravindsv 0:ba7650f404af 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
aravindsv 0:ba7650f404af 1084 __ICIALLU = 0;
aravindsv 0:ba7650f404af 1085 #endif
aravindsv 0:ba7650f404af 1086 __DSB(); //ensure completion of the invalidation
aravindsv 0:ba7650f404af 1087 __ISB(); //ensure instruction fetch path sees new I cache state
aravindsv 0:ba7650f404af 1088 }
aravindsv 0:ba7650f404af 1089
aravindsv 0:ba7650f404af 1090 /** \brief Clean D$ by MVA
aravindsv 0:ba7650f404af 1091
aravindsv 0:ba7650f404af 1092 DCCMVAC. Data cache clean by MVA to PoC
aravindsv 0:ba7650f404af 1093 */
aravindsv 0:ba7650f404af 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
aravindsv 0:ba7650f404af 1095 #if 1
aravindsv 0:ba7650f404af 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
aravindsv 0:ba7650f404af 1097 #else
aravindsv 0:ba7650f404af 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
aravindsv 0:ba7650f404af 1099 __DCCMVAC = (uint32_t)va;
aravindsv 0:ba7650f404af 1100 #endif
aravindsv 0:ba7650f404af 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
aravindsv 0:ba7650f404af 1102 }
aravindsv 0:ba7650f404af 1103
aravindsv 0:ba7650f404af 1104 /** \brief Invalidate D$ by MVA
aravindsv 0:ba7650f404af 1105
aravindsv 0:ba7650f404af 1106 DCIMVAC. Data cache invalidate by MVA to PoC
aravindsv 0:ba7650f404af 1107 */
aravindsv 0:ba7650f404af 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
aravindsv 0:ba7650f404af 1109 #if 1
aravindsv 0:ba7650f404af 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
aravindsv 0:ba7650f404af 1111 #else
aravindsv 0:ba7650f404af 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
aravindsv 0:ba7650f404af 1113 __DCIMVAC = (uint32_t)va;
aravindsv 0:ba7650f404af 1114 #endif
aravindsv 0:ba7650f404af 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
aravindsv 0:ba7650f404af 1116 }
aravindsv 0:ba7650f404af 1117
aravindsv 0:ba7650f404af 1118 /** \brief Clean and Invalidate D$ by MVA
aravindsv 0:ba7650f404af 1119
aravindsv 0:ba7650f404af 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
aravindsv 0:ba7650f404af 1121 */
aravindsv 0:ba7650f404af 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
aravindsv 0:ba7650f404af 1123 #if 1
aravindsv 0:ba7650f404af 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
aravindsv 0:ba7650f404af 1125 #else
aravindsv 0:ba7650f404af 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
aravindsv 0:ba7650f404af 1127 __DCCIMVAC = (uint32_t)va;
aravindsv 0:ba7650f404af 1128 #endif
aravindsv 0:ba7650f404af 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
aravindsv 0:ba7650f404af 1130 }
aravindsv 0:ba7650f404af 1131
aravindsv 0:ba7650f404af 1132 /** \brief Clean and Invalidate the entire data or unified cache
aravindsv 0:ba7650f404af 1133
aravindsv 0:ba7650f404af 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
aravindsv 0:ba7650f404af 1135 */
aravindsv 0:ba7650f404af 1136 extern void __v7_all_cache(uint32_t op);
aravindsv 0:ba7650f404af 1137
aravindsv 0:ba7650f404af 1138
aravindsv 0:ba7650f404af 1139 /** \brief Invalidate the whole D$
aravindsv 0:ba7650f404af 1140
aravindsv 0:ba7650f404af 1141 DCISW. Invalidate by Set/Way
aravindsv 0:ba7650f404af 1142 */
aravindsv 0:ba7650f404af 1143
aravindsv 0:ba7650f404af 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
aravindsv 0:ba7650f404af 1145 __v7_all_cache(0);
aravindsv 0:ba7650f404af 1146 }
aravindsv 0:ba7650f404af 1147
aravindsv 0:ba7650f404af 1148 /** \brief Clean the whole D$
aravindsv 0:ba7650f404af 1149
aravindsv 0:ba7650f404af 1150 DCCSW. Clean by Set/Way
aravindsv 0:ba7650f404af 1151 */
aravindsv 0:ba7650f404af 1152
aravindsv 0:ba7650f404af 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
aravindsv 0:ba7650f404af 1154 __v7_all_cache(1);
aravindsv 0:ba7650f404af 1155 }
aravindsv 0:ba7650f404af 1156
aravindsv 0:ba7650f404af 1157 /** \brief Clean and invalidate the whole D$
aravindsv 0:ba7650f404af 1158
aravindsv 0:ba7650f404af 1159 DCCISW. Clean and Invalidate by Set/Way
aravindsv 0:ba7650f404af 1160 */
aravindsv 0:ba7650f404af 1161
aravindsv 0:ba7650f404af 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
aravindsv 0:ba7650f404af 1163 __v7_all_cache(2);
aravindsv 0:ba7650f404af 1164 }
aravindsv 0:ba7650f404af 1165
aravindsv 0:ba7650f404af 1166 #include "core_ca_mmu.h"
aravindsv 0:ba7650f404af 1167
aravindsv 0:ba7650f404af 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
aravindsv 0:ba7650f404af 1169
aravindsv 0:ba7650f404af 1170 #error TASKING Compiler support not implemented for Cortex-A
aravindsv 0:ba7650f404af 1171
aravindsv 0:ba7650f404af 1172 #endif
aravindsv 0:ba7650f404af 1173
aravindsv 0:ba7650f404af 1174 /*@} end of CMSIS_Core_RegAccFunctions */
aravindsv 0:ba7650f404af 1175
aravindsv 0:ba7650f404af 1176
aravindsv 0:ba7650f404af 1177 #endif /* __CORE_CAFUNC_H__ */