Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/core_ca9.h@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**************************************************************************//**
aravindsv 0:ba7650f404af 2 * @file core_ca9.h
aravindsv 0:ba7650f404af 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
aravindsv 0:ba7650f404af 4 * @version
aravindsv 0:ba7650f404af 5 * @date 25 March 2013
aravindsv 0:ba7650f404af 6 *
aravindsv 0:ba7650f404af 7 * @note
aravindsv 0:ba7650f404af 8 *
aravindsv 0:ba7650f404af 9 ******************************************************************************/
aravindsv 0:ba7650f404af 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
aravindsv 0:ba7650f404af 11
aravindsv 0:ba7650f404af 12 All rights reserved.
aravindsv 0:ba7650f404af 13 Redistribution and use in source and binary forms, with or without
aravindsv 0:ba7650f404af 14 modification, are permitted provided that the following conditions are met:
aravindsv 0:ba7650f404af 15 - Redistributions of source code must retain the above copyright
aravindsv 0:ba7650f404af 16 notice, this list of conditions and the following disclaimer.
aravindsv 0:ba7650f404af 17 - Redistributions in binary form must reproduce the above copyright
aravindsv 0:ba7650f404af 18 notice, this list of conditions and the following disclaimer in the
aravindsv 0:ba7650f404af 19 documentation and/or other materials provided with the distribution.
aravindsv 0:ba7650f404af 20 - Neither the name of ARM nor the names of its contributors may be used
aravindsv 0:ba7650f404af 21 to endorse or promote products derived from this software without
aravindsv 0:ba7650f404af 22 specific prior written permission.
aravindsv 0:ba7650f404af 23 *
aravindsv 0:ba7650f404af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
aravindsv 0:ba7650f404af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
aravindsv 0:ba7650f404af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
aravindsv 0:ba7650f404af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
aravindsv 0:ba7650f404af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
aravindsv 0:ba7650f404af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
aravindsv 0:ba7650f404af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
aravindsv 0:ba7650f404af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
aravindsv 0:ba7650f404af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
aravindsv 0:ba7650f404af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
aravindsv 0:ba7650f404af 34 POSSIBILITY OF SUCH DAMAGE.
aravindsv 0:ba7650f404af 35 ---------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 36
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 #if defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 39 #pragma system_include /* treat file as system include file for MISRA check */
aravindsv 0:ba7650f404af 40 #endif
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42 #ifdef __cplusplus
aravindsv 0:ba7650f404af 43 extern "C" {
aravindsv 0:ba7650f404af 44 #endif
aravindsv 0:ba7650f404af 45
aravindsv 0:ba7650f404af 46 #ifndef __CORE_CA9_H_GENERIC
aravindsv 0:ba7650f404af 47 #define __CORE_CA9_H_GENERIC
aravindsv 0:ba7650f404af 48
aravindsv 0:ba7650f404af 49
aravindsv 0:ba7650f404af 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
aravindsv 0:ba7650f404af 51 CMSIS violates the following MISRA-C:2004 rules:
aravindsv 0:ba7650f404af 52
aravindsv 0:ba7650f404af 53 \li Required Rule 8.5, object/function definition in header file.<br>
aravindsv 0:ba7650f404af 54 Function definitions in header files are used to allow 'inlining'.
aravindsv 0:ba7650f404af 55
aravindsv 0:ba7650f404af 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
aravindsv 0:ba7650f404af 57 Unions are used for effective representation of core registers.
aravindsv 0:ba7650f404af 58
aravindsv 0:ba7650f404af 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
aravindsv 0:ba7650f404af 60 Function-like macros are used to allow more efficient code.
aravindsv 0:ba7650f404af 61 */
aravindsv 0:ba7650f404af 62
aravindsv 0:ba7650f404af 63
aravindsv 0:ba7650f404af 64 /*******************************************************************************
aravindsv 0:ba7650f404af 65 * CMSIS definitions
aravindsv 0:ba7650f404af 66 ******************************************************************************/
aravindsv 0:ba7650f404af 67 /** \ingroup Cortex_A9
aravindsv 0:ba7650f404af 68 @{
aravindsv 0:ba7650f404af 69 */
aravindsv 0:ba7650f404af 70
aravindsv 0:ba7650f404af 71 /* CMSIS CA9 definitions */
aravindsv 0:ba7650f404af 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
aravindsv 0:ba7650f404af 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
aravindsv 0:ba7650f404af 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
aravindsv 0:ba7650f404af 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
aravindsv 0:ba7650f404af 76
aravindsv 0:ba7650f404af 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
aravindsv 0:ba7650f404af 78
aravindsv 0:ba7650f404af 79
aravindsv 0:ba7650f404af 80 #if defined ( __CC_ARM )
aravindsv 0:ba7650f404af 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
aravindsv 0:ba7650f404af 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
aravindsv 0:ba7650f404af 83 #define __STATIC_INLINE static __inline
aravindsv 0:ba7650f404af 84 #define __STATIC_ASM static __asm
aravindsv 0:ba7650f404af 85
aravindsv 0:ba7650f404af 86 #elif defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
aravindsv 0:ba7650f404af 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
aravindsv 0:ba7650f404af 89 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 90 #define __STATIC_ASM static __asm
aravindsv 0:ba7650f404af 91
aravindsv 0:ba7650f404af 92 #elif defined ( __TMS470__ )
aravindsv 0:ba7650f404af 93 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
aravindsv 0:ba7650f404af 94 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 95 #define __STATIC_ASM static __asm
aravindsv 0:ba7650f404af 96
aravindsv 0:ba7650f404af 97 #elif defined ( __GNUC__ )
aravindsv 0:ba7650f404af 98 #define __ASM __asm /*!< asm keyword for GNU Compiler */
aravindsv 0:ba7650f404af 99 #define __INLINE inline /*!< inline keyword for GNU Compiler */
aravindsv 0:ba7650f404af 100 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 101 #define __STATIC_ASM static __asm
aravindsv 0:ba7650f404af 102
aravindsv 0:ba7650f404af 103 #elif defined ( __TASKING__ )
aravindsv 0:ba7650f404af 104 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
aravindsv 0:ba7650f404af 105 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
aravindsv 0:ba7650f404af 106 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 107 #define __STATIC_ASM static __asm
aravindsv 0:ba7650f404af 108
aravindsv 0:ba7650f404af 109 #endif
aravindsv 0:ba7650f404af 110
aravindsv 0:ba7650f404af 111 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
aravindsv 0:ba7650f404af 112 */
aravindsv 0:ba7650f404af 113 #if defined ( __CC_ARM )
aravindsv 0:ba7650f404af 114 #if defined __TARGET_FPU_VFP
aravindsv 0:ba7650f404af 115 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 116 #define __FPU_USED 1
aravindsv 0:ba7650f404af 117 #else
aravindsv 0:ba7650f404af 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 119 #define __FPU_USED 0
aravindsv 0:ba7650f404af 120 #endif
aravindsv 0:ba7650f404af 121 #else
aravindsv 0:ba7650f404af 122 #define __FPU_USED 0
aravindsv 0:ba7650f404af 123 #endif
aravindsv 0:ba7650f404af 124
aravindsv 0:ba7650f404af 125 #elif defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 126 #if defined __ARMVFP__
aravindsv 0:ba7650f404af 127 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 128 #define __FPU_USED 1
aravindsv 0:ba7650f404af 129 #else
aravindsv 0:ba7650f404af 130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 131 #define __FPU_USED 0
aravindsv 0:ba7650f404af 132 #endif
aravindsv 0:ba7650f404af 133 #else
aravindsv 0:ba7650f404af 134 #define __FPU_USED 0
aravindsv 0:ba7650f404af 135 #endif
aravindsv 0:ba7650f404af 136
aravindsv 0:ba7650f404af 137 #elif defined ( __TMS470__ )
aravindsv 0:ba7650f404af 138 #if defined __TI_VFP_SUPPORT__
aravindsv 0:ba7650f404af 139 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 140 #define __FPU_USED 1
aravindsv 0:ba7650f404af 141 #else
aravindsv 0:ba7650f404af 142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 143 #define __FPU_USED 0
aravindsv 0:ba7650f404af 144 #endif
aravindsv 0:ba7650f404af 145 #else
aravindsv 0:ba7650f404af 146 #define __FPU_USED 0
aravindsv 0:ba7650f404af 147 #endif
aravindsv 0:ba7650f404af 148
aravindsv 0:ba7650f404af 149 #elif defined ( __GNUC__ )
aravindsv 0:ba7650f404af 150 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
aravindsv 0:ba7650f404af 151 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 152 #define __FPU_USED 1
aravindsv 0:ba7650f404af 153 #else
aravindsv 0:ba7650f404af 154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 155 #define __FPU_USED 0
aravindsv 0:ba7650f404af 156 #endif
aravindsv 0:ba7650f404af 157 #else
aravindsv 0:ba7650f404af 158 #define __FPU_USED 0
aravindsv 0:ba7650f404af 159 #endif
aravindsv 0:ba7650f404af 160
aravindsv 0:ba7650f404af 161 #elif defined ( __TASKING__ )
aravindsv 0:ba7650f404af 162 #if defined __FPU_VFP__
aravindsv 0:ba7650f404af 163 #if (__FPU_PRESENT == 1)
aravindsv 0:ba7650f404af 164 #define __FPU_USED 1
aravindsv 0:ba7650f404af 165 #else
aravindsv 0:ba7650f404af 166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 167 #define __FPU_USED 0
aravindsv 0:ba7650f404af 168 #endif
aravindsv 0:ba7650f404af 169 #else
aravindsv 0:ba7650f404af 170 #define __FPU_USED 0
aravindsv 0:ba7650f404af 171 #endif
aravindsv 0:ba7650f404af 172 #endif
aravindsv 0:ba7650f404af 173
aravindsv 0:ba7650f404af 174 #include <stdint.h> /*!< standard types definitions */
aravindsv 0:ba7650f404af 175 #include "core_caInstr.h" /*!< Core Instruction Access */
aravindsv 0:ba7650f404af 176 #include "core_caFunc.h" /*!< Core Function Access */
aravindsv 0:ba7650f404af 177 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
aravindsv 0:ba7650f404af 178
aravindsv 0:ba7650f404af 179 #endif /* __CORE_CA9_H_GENERIC */
aravindsv 0:ba7650f404af 180
aravindsv 0:ba7650f404af 181 #ifndef __CMSIS_GENERIC
aravindsv 0:ba7650f404af 182
aravindsv 0:ba7650f404af 183 #ifndef __CORE_CA9_H_DEPENDANT
aravindsv 0:ba7650f404af 184 #define __CORE_CA9_H_DEPENDANT
aravindsv 0:ba7650f404af 185
aravindsv 0:ba7650f404af 186 /* check device defines and use defaults */
aravindsv 0:ba7650f404af 187 #if defined __CHECK_DEVICE_DEFINES
aravindsv 0:ba7650f404af 188 #ifndef __CA9_REV
aravindsv 0:ba7650f404af 189 #define __CA9_REV 0x0000
aravindsv 0:ba7650f404af 190 #warning "__CA9_REV not defined in device header file; using default!"
aravindsv 0:ba7650f404af 191 #endif
aravindsv 0:ba7650f404af 192
aravindsv 0:ba7650f404af 193 #ifndef __FPU_PRESENT
aravindsv 0:ba7650f404af 194 #define __FPU_PRESENT 1
aravindsv 0:ba7650f404af 195 #warning "__FPU_PRESENT not defined in device header file; using default!"
aravindsv 0:ba7650f404af 196 #endif
aravindsv 0:ba7650f404af 197
aravindsv 0:ba7650f404af 198 #ifndef __Vendor_SysTickConfig
aravindsv 0:ba7650f404af 199 #define __Vendor_SysTickConfig 1
aravindsv 0:ba7650f404af 200 #endif
aravindsv 0:ba7650f404af 201
aravindsv 0:ba7650f404af 202 #if __Vendor_SysTickConfig == 0
aravindsv 0:ba7650f404af 203 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
aravindsv 0:ba7650f404af 204 #endif
aravindsv 0:ba7650f404af 205 #endif
aravindsv 0:ba7650f404af 206
aravindsv 0:ba7650f404af 207 /* IO definitions (access restrictions to peripheral registers) */
aravindsv 0:ba7650f404af 208 /**
aravindsv 0:ba7650f404af 209 \defgroup CMSIS_glob_defs CMSIS Global Defines
aravindsv 0:ba7650f404af 210
aravindsv 0:ba7650f404af 211 <strong>IO Type Qualifiers</strong> are used
aravindsv 0:ba7650f404af 212 \li to specify the access to peripheral variables.
aravindsv 0:ba7650f404af 213 \li for automatic generation of peripheral register debug information.
aravindsv 0:ba7650f404af 214 */
aravindsv 0:ba7650f404af 215 #ifdef __cplusplus
aravindsv 0:ba7650f404af 216 #define __I volatile /*!< Defines 'read only' permissions */
aravindsv 0:ba7650f404af 217 #else
aravindsv 0:ba7650f404af 218 #define __I volatile const /*!< Defines 'read only' permissions */
aravindsv 0:ba7650f404af 219 #endif
aravindsv 0:ba7650f404af 220 #define __O volatile /*!< Defines 'write only' permissions */
aravindsv 0:ba7650f404af 221 #define __IO volatile /*!< Defines 'read / write' permissions */
aravindsv 0:ba7650f404af 222
aravindsv 0:ba7650f404af 223 /*@} end of group Cortex_A9 */
aravindsv 0:ba7650f404af 224
aravindsv 0:ba7650f404af 225
aravindsv 0:ba7650f404af 226 /*******************************************************************************
aravindsv 0:ba7650f404af 227 * Register Abstraction
aravindsv 0:ba7650f404af 228 ******************************************************************************/
aravindsv 0:ba7650f404af 229 /** \defgroup CMSIS_core_register Defines and Type Definitions
aravindsv 0:ba7650f404af 230 \brief Type definitions and defines for Cortex-A processor based devices.
aravindsv 0:ba7650f404af 231 */
aravindsv 0:ba7650f404af 232
aravindsv 0:ba7650f404af 233 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 234 \defgroup CMSIS_CORE Status and Control Registers
aravindsv 0:ba7650f404af 235 \brief Core Register type definitions.
aravindsv 0:ba7650f404af 236 @{
aravindsv 0:ba7650f404af 237 */
aravindsv 0:ba7650f404af 238
aravindsv 0:ba7650f404af 239 /** \brief Union type to access the Application Program Status Register (APSR).
aravindsv 0:ba7650f404af 240 */
aravindsv 0:ba7650f404af 241 typedef union
aravindsv 0:ba7650f404af 242 {
aravindsv 0:ba7650f404af 243 struct
aravindsv 0:ba7650f404af 244 {
aravindsv 0:ba7650f404af 245 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
aravindsv 0:ba7650f404af 246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
aravindsv 0:ba7650f404af 247 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
aravindsv 0:ba7650f404af 248 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
aravindsv 0:ba7650f404af 249 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
aravindsv 0:ba7650f404af 250 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
aravindsv 0:ba7650f404af 251 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
aravindsv 0:ba7650f404af 252 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
aravindsv 0:ba7650f404af 253 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 254 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 255 } APSR_Type;
aravindsv 0:ba7650f404af 256
aravindsv 0:ba7650f404af 257
aravindsv 0:ba7650f404af 258 /*@} end of group CMSIS_CORE */
aravindsv 0:ba7650f404af 259
aravindsv 0:ba7650f404af 260 /*@} end of CMSIS_Core_FPUFunctions */
aravindsv 0:ba7650f404af 261
aravindsv 0:ba7650f404af 262
aravindsv 0:ba7650f404af 263 #endif /* __CORE_CA9_H_GENERIC */
aravindsv 0:ba7650f404af 264
aravindsv 0:ba7650f404af 265 #endif /* __CMSIS_GENERIC */
aravindsv 0:ba7650f404af 266
aravindsv 0:ba7650f404af 267 #ifdef __cplusplus
aravindsv 0:ba7650f404af 268 }
aravindsv 0:ba7650f404af 269
aravindsv 0:ba7650f404af 270
aravindsv 0:ba7650f404af 271 #endif