Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x.h@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**************************************************************************//**
aravindsv 0:ba7650f404af 2 * @file W7500x.h
aravindsv 0:ba7650f404af 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
aravindsv 0:ba7650f404af 4 * Device W7500x
aravindsv 0:ba7650f404af 5 * @version V3.01
aravindsv 0:ba7650f404af 6 * @date 06. March 2012
aravindsv 0:ba7650f404af 7 *
aravindsv 0:ba7650f404af 8 * @note
aravindsv 0:ba7650f404af 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
aravindsv 0:ba7650f404af 10 *
aravindsv 0:ba7650f404af 11 * @par
aravindsv 0:ba7650f404af 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
aravindsv 0:ba7650f404af 13 * processor based microcontrollers. This file can be freely distributed
aravindsv 0:ba7650f404af 14 * within development tools that are supporting such ARM based processors.
aravindsv 0:ba7650f404af 15 *
aravindsv 0:ba7650f404af 16 * @par
aravindsv 0:ba7650f404af 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
aravindsv 0:ba7650f404af 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
aravindsv 0:ba7650f404af 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
aravindsv 0:ba7650f404af 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
aravindsv 0:ba7650f404af 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
aravindsv 0:ba7650f404af 22 *
aravindsv 0:ba7650f404af 23 ******************************************************************************/
aravindsv 0:ba7650f404af 24
aravindsv 0:ba7650f404af 25
aravindsv 0:ba7650f404af 26 #ifndef W7500x_H
aravindsv 0:ba7650f404af 27 #define W7500x_H
aravindsv 0:ba7650f404af 28
aravindsv 0:ba7650f404af 29 #ifdef __cplusplus
aravindsv 0:ba7650f404af 30 extern "C" {
aravindsv 0:ba7650f404af 31 #endif
aravindsv 0:ba7650f404af 32
aravindsv 0:ba7650f404af 33 /** @addtogroup W7500x_Definitions W7500x Definitions
aravindsv 0:ba7650f404af 34 This file defines all structures and symbols for W7500x:
aravindsv 0:ba7650f404af 35 - registers and bitfields
aravindsv 0:ba7650f404af 36 - peripheral base address
aravindsv 0:ba7650f404af 37 - peripheral ID
aravindsv 0:ba7650f404af 38 - Peripheral definitions
aravindsv 0:ba7650f404af 39 @{
aravindsv 0:ba7650f404af 40 */
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42
aravindsv 0:ba7650f404af 43 /******************************************************************************/
aravindsv 0:ba7650f404af 44 /* Processor and Core Peripherals */
aravindsv 0:ba7650f404af 45 /******************************************************************************/
aravindsv 0:ba7650f404af 46 /** @addtogroup W7500x_CMSIS Device CMSIS Definitions
aravindsv 0:ba7650f404af 47 Configuration of the Cortex-M0 Processor and Core Peripherals
aravindsv 0:ba7650f404af 48 @{
aravindsv 0:ba7650f404af 49 */
aravindsv 0:ba7650f404af 50
aravindsv 0:ba7650f404af 51 /*
aravindsv 0:ba7650f404af 52 * ==========================================================================
aravindsv 0:ba7650f404af 53 * ---------- Interrupt Number Definition -----------------------------------
aravindsv 0:ba7650f404af 54 * ==========================================================================
aravindsv 0:ba7650f404af 55 */
aravindsv 0:ba7650f404af 56
aravindsv 0:ba7650f404af 57 typedef enum IRQn
aravindsv 0:ba7650f404af 58 {
aravindsv 0:ba7650f404af 59 /****** Cortex-M0 Processor Exceptions Numbers **************************************************/
aravindsv 0:ba7650f404af 60
aravindsv 0:ba7650f404af 61 /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
aravindsv 0:ba7650f404af 62 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
aravindsv 0:ba7650f404af 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
aravindsv 0:ba7650f404af 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
aravindsv 0:ba7650f404af 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
aravindsv 0:ba7650f404af 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
aravindsv 0:ba7650f404af 67 /****** W7500x Specific Interrupt Numbers *********************************************************/
aravindsv 0:ba7650f404af 68 SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
aravindsv 0:ba7650f404af 69 SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
aravindsv 0:ba7650f404af 70 UART0_IRQn = 2, /*!< UART 0 Interrupt */
aravindsv 0:ba7650f404af 71 UART1_IRQn = 3, /*!< UART 1 Interrupt */
aravindsv 0:ba7650f404af 72 UART2_IRQn = 4, /*!< UART 2 Interrupt */
aravindsv 0:ba7650f404af 73 I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
aravindsv 0:ba7650f404af 74 I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
aravindsv 0:ba7650f404af 75 PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
aravindsv 0:ba7650f404af 76 PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
aravindsv 0:ba7650f404af 77 PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
aravindsv 0:ba7650f404af 78 PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
aravindsv 0:ba7650f404af 79 DMA_IRQn = 11, /*!< DMA combined Interrupt */
aravindsv 0:ba7650f404af 80 DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
aravindsv 0:ba7650f404af 81 DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
aravindsv 0:ba7650f404af 82 PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
aravindsv 0:ba7650f404af 83 PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
aravindsv 0:ba7650f404af 84 PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
aravindsv 0:ba7650f404af 85 PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
aravindsv 0:ba7650f404af 86 PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
aravindsv 0:ba7650f404af 87 PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
aravindsv 0:ba7650f404af 88 PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
aravindsv 0:ba7650f404af 89 PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
aravindsv 0:ba7650f404af 90 RTC_IRQn = 22, /*!< RTC Interrupt */
aravindsv 0:ba7650f404af 91 ADC_IRQn = 23, /*!< ADC Interrupt */
aravindsv 0:ba7650f404af 92 WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
aravindsv 0:ba7650f404af 93 EXTI_IRQn = 25 /*!< EXTI Interrupt */
aravindsv 0:ba7650f404af 94 } IRQn_Type;
aravindsv 0:ba7650f404af 95
aravindsv 0:ba7650f404af 96 /*
aravindsv 0:ba7650f404af 97 * ==========================================================================
aravindsv 0:ba7650f404af 98 * ----------- Processor and Core Peripheral Section ------------------------
aravindsv 0:ba7650f404af 99 * ==========================================================================
aravindsv 0:ba7650f404af 100 */
aravindsv 0:ba7650f404af 101
aravindsv 0:ba7650f404af 102 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
aravindsv 0:ba7650f404af 103 #define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
aravindsv 0:ba7650f404af 104 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
aravindsv 0:ba7650f404af 105 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
aravindsv 0:ba7650f404af 106 #define __MPU_PRESENT 0 /*!< MPU present or not */
aravindsv 0:ba7650f404af 107
aravindsv 0:ba7650f404af 108 /*@}*/ /* end of group W7500x_CMSIS */
aravindsv 0:ba7650f404af 109
aravindsv 0:ba7650f404af 110
aravindsv 0:ba7650f404af 111 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
aravindsv 0:ba7650f404af 112 #include "system_W7500x.h" /* W7500x System include file */
aravindsv 0:ba7650f404af 113
aravindsv 0:ba7650f404af 114
aravindsv 0:ba7650f404af 115 /** @addtogroup Exported_types
aravindsv 0:ba7650f404af 116 * @{
aravindsv 0:ba7650f404af 117 */
aravindsv 0:ba7650f404af 118
aravindsv 0:ba7650f404af 119 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
aravindsv 0:ba7650f404af 120 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
aravindsv 0:ba7650f404af 121 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
aravindsv 0:ba7650f404af 122
aravindsv 0:ba7650f404af 123 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
aravindsv 0:ba7650f404af 124
aravindsv 0:ba7650f404af 125
aravindsv 0:ba7650f404af 126
aravindsv 0:ba7650f404af 127
aravindsv 0:ba7650f404af 128 /**
aravindsv 0:ba7650f404af 129 * @}
aravindsv 0:ba7650f404af 130 */
aravindsv 0:ba7650f404af 131
aravindsv 0:ba7650f404af 132
aravindsv 0:ba7650f404af 133
aravindsv 0:ba7650f404af 134
aravindsv 0:ba7650f404af 135 /** @addtogroup Peripheral_registers_structures
aravindsv 0:ba7650f404af 136 * @{
aravindsv 0:ba7650f404af 137 */
aravindsv 0:ba7650f404af 138
aravindsv 0:ba7650f404af 139 /**
aravindsv 0:ba7650f404af 140 * @brief Clock Reset Generator
aravindsv 0:ba7650f404af 141 */
aravindsv 0:ba7650f404af 142 typedef struct
aravindsv 0:ba7650f404af 143 {
aravindsv 0:ba7650f404af 144 __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
aravindsv 0:ba7650f404af 145 uint32_t RESERVED0[3];
aravindsv 0:ba7650f404af 146 __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
aravindsv 0:ba7650f404af 147 __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
aravindsv 0:ba7650f404af 148 __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
aravindsv 0:ba7650f404af 149 __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
aravindsv 0:ba7650f404af 150 __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
aravindsv 0:ba7650f404af 151 uint32_t RESERVED1[3];
aravindsv 0:ba7650f404af 152 __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
aravindsv 0:ba7650f404af 153 __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
aravindsv 0:ba7650f404af 154 uint32_t RESERVED2[2];
aravindsv 0:ba7650f404af 155 __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
aravindsv 0:ba7650f404af 156 __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
aravindsv 0:ba7650f404af 157 uint32_t RESERVED3[6];
aravindsv 0:ba7650f404af 158 __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
aravindsv 0:ba7650f404af 159 __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
aravindsv 0:ba7650f404af 160 uint32_t RESERVED4[2];
aravindsv 0:ba7650f404af 161 __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
aravindsv 0:ba7650f404af 162 __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
aravindsv 0:ba7650f404af 163 uint32_t RESERVED5[2];
aravindsv 0:ba7650f404af 164 __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
aravindsv 0:ba7650f404af 165 __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
aravindsv 0:ba7650f404af 166 uint32_t RESERVED6[10];
aravindsv 0:ba7650f404af 167 __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
aravindsv 0:ba7650f404af 168 __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
aravindsv 0:ba7650f404af 169 uint32_t RESERVED7[2];
aravindsv 0:ba7650f404af 170 __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
aravindsv 0:ba7650f404af 171 __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
aravindsv 0:ba7650f404af 172 uint32_t RESERVED8[2];
aravindsv 0:ba7650f404af 173 __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
aravindsv 0:ba7650f404af 174 __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
aravindsv 0:ba7650f404af 175 uint32_t RESERVED9[2];
aravindsv 0:ba7650f404af 176 __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
aravindsv 0:ba7650f404af 177 __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
aravindsv 0:ba7650f404af 178 uint32_t RESERVED10[2];
aravindsv 0:ba7650f404af 179 __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
aravindsv 0:ba7650f404af 180 __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
aravindsv 0:ba7650f404af 181 uint32_t RESERVED11[2];
aravindsv 0:ba7650f404af 182 __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
aravindsv 0:ba7650f404af 183 __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
aravindsv 0:ba7650f404af 184 uint32_t RESERVED12[2];
aravindsv 0:ba7650f404af 185 __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
aravindsv 0:ba7650f404af 186 __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
aravindsv 0:ba7650f404af 187 uint32_t RESERVED13[2];
aravindsv 0:ba7650f404af 188 __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
aravindsv 0:ba7650f404af 189 __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
aravindsv 0:ba7650f404af 190 uint32_t RESERVED14[2];
aravindsv 0:ba7650f404af 191 __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
aravindsv 0:ba7650f404af 192 __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
aravindsv 0:ba7650f404af 193 uint32_t RESERVED15;
aravindsv 0:ba7650f404af 194 __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
aravindsv 0:ba7650f404af 195
aravindsv 0:ba7650f404af 196 __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
aravindsv 0:ba7650f404af 197 __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
aravindsv 0:ba7650f404af 198 uint32_t RESERVED16;
aravindsv 0:ba7650f404af 199 __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
aravindsv 0:ba7650f404af 200
aravindsv 0:ba7650f404af 201 __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
aravindsv 0:ba7650f404af 202 __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
aravindsv 0:ba7650f404af 203 uint32_t RESERVED17[2];
aravindsv 0:ba7650f404af 204 __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
aravindsv 0:ba7650f404af 205 uint32_t RESERVED18[3];
aravindsv 0:ba7650f404af 206 __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
aravindsv 0:ba7650f404af 207 }CRG_TypeDef;
aravindsv 0:ba7650f404af 208
aravindsv 0:ba7650f404af 209
aravindsv 0:ba7650f404af 210 /**
aravindsv 0:ba7650f404af 211 * @brief UART
aravindsv 0:ba7650f404af 212 */
aravindsv 0:ba7650f404af 213 typedef struct
aravindsv 0:ba7650f404af 214 {
aravindsv 0:ba7650f404af 215 __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
aravindsv 0:ba7650f404af 216 union {
aravindsv 0:ba7650f404af 217 __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
aravindsv 0:ba7650f404af 218 __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
aravindsv 0:ba7650f404af 219 } STATUS;
aravindsv 0:ba7650f404af 220 uint32_t RESERVED0[4];
aravindsv 0:ba7650f404af 221 __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
aravindsv 0:ba7650f404af 222 uint32_t RESERVED1;
aravindsv 0:ba7650f404af 223 __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
aravindsv 0:ba7650f404af 224 __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
aravindsv 0:ba7650f404af 225 __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
aravindsv 0:ba7650f404af 226 __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
aravindsv 0:ba7650f404af 227 __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
aravindsv 0:ba7650f404af 228 __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
aravindsv 0:ba7650f404af 229 __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
aravindsv 0:ba7650f404af 230 __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
aravindsv 0:ba7650f404af 231 __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
aravindsv 0:ba7650f404af 232 __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
aravindsv 0:ba7650f404af 233 __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
aravindsv 0:ba7650f404af 234 } UART_TypeDef;
aravindsv 0:ba7650f404af 235
aravindsv 0:ba7650f404af 236
aravindsv 0:ba7650f404af 237 /**
aravindsv 0:ba7650f404af 238 * @brief Simple UART
aravindsv 0:ba7650f404af 239 */
aravindsv 0:ba7650f404af 240 typedef struct
aravindsv 0:ba7650f404af 241 {
aravindsv 0:ba7650f404af 242 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
aravindsv 0:ba7650f404af 243 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
aravindsv 0:ba7650f404af 244 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
aravindsv 0:ba7650f404af 245 union {
aravindsv 0:ba7650f404af 246 __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
aravindsv 0:ba7650f404af 247 __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
aravindsv 0:ba7650f404af 248 }INT;
aravindsv 0:ba7650f404af 249 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
aravindsv 0:ba7650f404af 250
aravindsv 0:ba7650f404af 251 } S_UART_TypeDef;
aravindsv 0:ba7650f404af 252
aravindsv 0:ba7650f404af 253 /**
aravindsv 0:ba7650f404af 254 * @brief Analog Digital Converter
aravindsv 0:ba7650f404af 255 */
aravindsv 0:ba7650f404af 256
aravindsv 0:ba7650f404af 257 typedef struct
aravindsv 0:ba7650f404af 258 {
aravindsv 0:ba7650f404af 259 __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
aravindsv 0:ba7650f404af 260 __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
aravindsv 0:ba7650f404af 261 __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
aravindsv 0:ba7650f404af 262 __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
aravindsv 0:ba7650f404af 263 __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
aravindsv 0:ba7650f404af 264 uint32_t RESERVED0[2];
aravindsv 0:ba7650f404af 265 __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
aravindsv 0:ba7650f404af 266 }ADC_TypeDef;
aravindsv 0:ba7650f404af 267
aravindsv 0:ba7650f404af 268 /**
aravindsv 0:ba7650f404af 269 * @brief dualtimer
aravindsv 0:ba7650f404af 270 */
aravindsv 0:ba7650f404af 271 typedef struct
aravindsv 0:ba7650f404af 272 {
aravindsv 0:ba7650f404af 273 __IO uint32_t TimerLoad; // <h> Timer Load </h>
aravindsv 0:ba7650f404af 274 __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
aravindsv 0:ba7650f404af 275 __IO uint32_t TimerControl; // <h> Timer Control
aravindsv 0:ba7650f404af 276 // <o.7> TimerEn: Timer Enable
aravindsv 0:ba7650f404af 277 // <o.6> TimerMode: Timer Mode
aravindsv 0:ba7650f404af 278 // <0=> Freerunning-mode
aravindsv 0:ba7650f404af 279 // <1=> Periodic mode
aravindsv 0:ba7650f404af 280 // <o.5> IntEnable: Interrupt Enable
aravindsv 0:ba7650f404af 281 // <o.2..3> TimerPre: Timer Prescale
aravindsv 0:ba7650f404af 282 // <0=> / 1
aravindsv 0:ba7650f404af 283 // <1=> / 16
aravindsv 0:ba7650f404af 284 // <2=> / 256
aravindsv 0:ba7650f404af 285 // <3=> Undefined!
aravindsv 0:ba7650f404af 286 // <o.1> TimerSize: Timer Size
aravindsv 0:ba7650f404af 287 // <0=> 16-bit counter
aravindsv 0:ba7650f404af 288 // <1=> 32-bit counter
aravindsv 0:ba7650f404af 289 // <o.0> OneShot: One-shoot mode
aravindsv 0:ba7650f404af 290 // <0=> Wrapping mode
aravindsv 0:ba7650f404af 291 // <1=> One-shot mode
aravindsv 0:ba7650f404af 292 // </h>
aravindsv 0:ba7650f404af 293 __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
aravindsv 0:ba7650f404af 294 __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
aravindsv 0:ba7650f404af 295 __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
aravindsv 0:ba7650f404af 296 __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
aravindsv 0:ba7650f404af 297 } DUALTIMER_TypeDef;
aravindsv 0:ba7650f404af 298
aravindsv 0:ba7650f404af 299 /**
aravindsv 0:ba7650f404af 300 * @brief GPIO
aravindsv 0:ba7650f404af 301 */
aravindsv 0:ba7650f404af 302 typedef struct
aravindsv 0:ba7650f404af 303 {
aravindsv 0:ba7650f404af 304 __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
aravindsv 0:ba7650f404af 305 __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
aravindsv 0:ba7650f404af 306 uint32_t RESERVED0[2];
aravindsv 0:ba7650f404af 307 __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
aravindsv 0:ba7650f404af 308 __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
aravindsv 0:ba7650f404af 309 __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
aravindsv 0:ba7650f404af 310 __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
aravindsv 0:ba7650f404af 311 __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
aravindsv 0:ba7650f404af 312 __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
aravindsv 0:ba7650f404af 313 __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
aravindsv 0:ba7650f404af 314 __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
aravindsv 0:ba7650f404af 315 __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
aravindsv 0:ba7650f404af 316 __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
aravindsv 0:ba7650f404af 317 union {
aravindsv 0:ba7650f404af 318 __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
aravindsv 0:ba7650f404af 319 __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
aravindsv 0:ba7650f404af 320 }Interrupt;
aravindsv 0:ba7650f404af 321 uint32_t RESERVED3[241];
aravindsv 0:ba7650f404af 322 __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
aravindsv 0:ba7650f404af 323 __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
aravindsv 0:ba7650f404af 324 } GPIO_TypeDef;
aravindsv 0:ba7650f404af 325
aravindsv 0:ba7650f404af 326 typedef struct
aravindsv 0:ba7650f404af 327 {
aravindsv 0:ba7650f404af 328 __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
aravindsv 0:ba7650f404af 329 /* Port_01, offset : 0x04 */
aravindsv 0:ba7650f404af 330 /* Port_02, offset : 0x08 */
aravindsv 0:ba7650f404af 331 /* Port_03, offset : 0x0C */
aravindsv 0:ba7650f404af 332 /* Port_04, offset : 0x10 */
aravindsv 0:ba7650f404af 333 /* Port_05, offset : 0x14 */
aravindsv 0:ba7650f404af 334 /* Port_06, offset : 0x18 */
aravindsv 0:ba7650f404af 335 /* Port_07, offset : 0x1C */
aravindsv 0:ba7650f404af 336 /* Port_08, offset : 0x20 */
aravindsv 0:ba7650f404af 337 /* Port_09, offset : 0x24 */
aravindsv 0:ba7650f404af 338 /* Port_10, offset : 0x28 */
aravindsv 0:ba7650f404af 339 /* Port_11, offset : 0x2C */
aravindsv 0:ba7650f404af 340 /* Port_12, offset : 0x30 */
aravindsv 0:ba7650f404af 341 /* Port_13, offset : 0x34 */
aravindsv 0:ba7650f404af 342 /* Port_14, offset : 0x38 */
aravindsv 0:ba7650f404af 343 /* Port_15, offset : 0x3C */
aravindsv 0:ba7650f404af 344 } P_Port_Def;
aravindsv 0:ba7650f404af 345
aravindsv 0:ba7650f404af 346 typedef struct
aravindsv 0:ba7650f404af 347 {
aravindsv 0:ba7650f404af 348 __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
aravindsv 0:ba7650f404af 349 /* Port_01, offset : 0x04 */
aravindsv 0:ba7650f404af 350 /* Port_02, offset : 0x08 */
aravindsv 0:ba7650f404af 351 /* Port_03, offset : 0x0C */
aravindsv 0:ba7650f404af 352 /* Port_04, offset : 0x10 */
aravindsv 0:ba7650f404af 353 } P_Port_D_Def;
aravindsv 0:ba7650f404af 354
aravindsv 0:ba7650f404af 355 /**
aravindsv 0:ba7650f404af 356 * @brief I2C Register structure definition
aravindsv 0:ba7650f404af 357 */
aravindsv 0:ba7650f404af 358 typedef struct
aravindsv 0:ba7650f404af 359 {
aravindsv 0:ba7650f404af 360 __IO uint32_t PRER; //0x00
aravindsv 0:ba7650f404af 361 __IO uint32_t CTR; //0x04
aravindsv 0:ba7650f404af 362 __IO uint32_t CMDR; //0x08
aravindsv 0:ba7650f404af 363 __I uint32_t SR; //0x0C
aravindsv 0:ba7650f404af 364 __IO uint32_t TSR; //0x10
aravindsv 0:ba7650f404af 365 __IO uint32_t SADDR; //0x14
aravindsv 0:ba7650f404af 366 __IO uint32_t TXR; //0x18
aravindsv 0:ba7650f404af 367 __I uint32_t RXR; //0x1C
aravindsv 0:ba7650f404af 368 __I uint32_t ISR; //0x20
aravindsv 0:ba7650f404af 369 __IO uint32_t ISCR; //0x24
aravindsv 0:ba7650f404af 370 __IO uint32_t ISMR; //0x28
aravindsv 0:ba7650f404af 371 }I2C_TypeDef;
aravindsv 0:ba7650f404af 372
aravindsv 0:ba7650f404af 373 /**
aravindsv 0:ba7650f404af 374 * @brief PWM Register structure definition
aravindsv 0:ba7650f404af 375 */
aravindsv 0:ba7650f404af 376 typedef struct
aravindsv 0:ba7650f404af 377 {
aravindsv 0:ba7650f404af 378 __IO uint32_t IER; //Interrupt enable register
aravindsv 0:ba7650f404af 379 // <7> IE7 : Channel 7 interrupt enable <R/W>
aravindsv 0:ba7650f404af 380 // <6> IE6 : Channel 6 interrupt enable <R/W>
aravindsv 0:ba7650f404af 381 // <5> IE5 : Channel 5 interrupt enable <R/W>
aravindsv 0:ba7650f404af 382 // <4> IE4 : Channel 4 interrupt enable <R/W>
aravindsv 0:ba7650f404af 383 // <3> IE3 : Channel 3 interrupt enable <R/W>
aravindsv 0:ba7650f404af 384 // <2> IE2 : Channel 2 interrupt enable <R/W>
aravindsv 0:ba7650f404af 385 // <1> IE1 : Channel 1 interrupt enable <R/W>
aravindsv 0:ba7650f404af 386 // <0> IE0 : Channel 0 interrupt enable <R/W>
aravindsv 0:ba7650f404af 387
aravindsv 0:ba7650f404af 388 __IO uint32_t SSR; //Start Stop register
aravindsv 0:ba7650f404af 389 // <7> SS7 : Channel 7 TC start or stop <R/W>
aravindsv 0:ba7650f404af 390 // <6> SS6 : Channel 6 TC start or stop <R/W>
aravindsv 0:ba7650f404af 391 // <5> SS5 : Channel 5 TC start or stop <R/W>
aravindsv 0:ba7650f404af 392 // <4> SS4 : Channel 4 TC start or stop <R/W>
aravindsv 0:ba7650f404af 393 // <3> SS3 : Channel 3 TC start or stop <R/W>
aravindsv 0:ba7650f404af 394 // <2> SS2 : Channel 2 TC start or stop <R/W>
aravindsv 0:ba7650f404af 395 // <1> SS1 : Channel 1 TC start or stop <R/W>
aravindsv 0:ba7650f404af 396 // <0> SS0 : Channel 0 TC start or stop <R/W>
aravindsv 0:ba7650f404af 397
aravindsv 0:ba7650f404af 398 __IO uint32_t PSR; //Pause register
aravindsv 0:ba7650f404af 399 // <7> PS7 : Channel 7 TC pasue <R/W>
aravindsv 0:ba7650f404af 400 // <6> PS6 : Channel 6 TC pasue <R/W>
aravindsv 0:ba7650f404af 401 // <5> PS5 : Channel 5 TC pasue <R/W>
aravindsv 0:ba7650f404af 402 // <4> PS4 : Channel 4 TC pasue <R/W>
aravindsv 0:ba7650f404af 403 // <3> PS3 : Channel 3 TC pasue <R/W>
aravindsv 0:ba7650f404af 404 // <2> PS2 : Channel 2 TC pasue <R/W>
aravindsv 0:ba7650f404af 405 // <1> PS1 : Channel 1 TC pasue <R/W>
aravindsv 0:ba7650f404af 406 // <0> PS0 : Channel 0 TC pasue <R/W>
aravindsv 0:ba7650f404af 407 } PWM_TypeDef;
aravindsv 0:ba7650f404af 408
aravindsv 0:ba7650f404af 409 typedef struct
aravindsv 0:ba7650f404af 410 {
aravindsv 0:ba7650f404af 411 __I uint32_t IR; //Interrupt register
aravindsv 0:ba7650f404af 412 // <2> CI : Capture interrupt <R>
aravindsv 0:ba7650f404af 413 // <1> OI : Overflow interrupt <R>
aravindsv 0:ba7650f404af 414 // <0> MI : Match interrupt <R>
aravindsv 0:ba7650f404af 415
aravindsv 0:ba7650f404af 416 __IO uint32_t IER; //Interrupt enable register
aravindsv 0:ba7650f404af 417 // <2> CIE : Capture interrupt enable <R/W>
aravindsv 0:ba7650f404af 418 // <1> OIE : Overflow interrupt enable <R/W>
aravindsv 0:ba7650f404af 419 // <0> MIE : Match interrupt enable <R/W>
aravindsv 0:ba7650f404af 420
aravindsv 0:ba7650f404af 421 __O uint32_t ICR; //Interrupt clear register
aravindsv 0:ba7650f404af 422 // <2> CIC : Capture interrupt clear <W>
aravindsv 0:ba7650f404af 423 // <1> OIC : Overflow interrupt clear <W>
aravindsv 0:ba7650f404af 424 // <0> MIC : Match interrupt clear <W>
aravindsv 0:ba7650f404af 425
aravindsv 0:ba7650f404af 426 __I uint32_t TCR; //Timer/Counter register
aravindsv 0:ba7650f404af 427 // <0..31> TCR : Timer/Counter register <R>
aravindsv 0:ba7650f404af 428
aravindsv 0:ba7650f404af 429 __I uint32_t PCR; //Prescale counter register
aravindsv 0:ba7650f404af 430 // <0..5> PCR : Prescale Counter register <R>
aravindsv 0:ba7650f404af 431
aravindsv 0:ba7650f404af 432 __IO uint32_t PR; //Prescale register
aravindsv 0:ba7650f404af 433 // <0..5> PR : prescale register <R/W>
aravindsv 0:ba7650f404af 434
aravindsv 0:ba7650f404af 435 __IO uint32_t MR; //Match register
aravindsv 0:ba7650f404af 436 // <0..31> MR : Match register <R/W>
aravindsv 0:ba7650f404af 437
aravindsv 0:ba7650f404af 438 __IO uint32_t LR; //Limit register
aravindsv 0:ba7650f404af 439 // <0..31> LR : Limit register <R/W>
aravindsv 0:ba7650f404af 440 __IO uint32_t UDMR; //Up-Down mode register
aravindsv 0:ba7650f404af 441 // <0> UDM : Up-down mode <R/W>
aravindsv 0:ba7650f404af 442
aravindsv 0:ba7650f404af 443 __IO uint32_t TCMR; //Timer/Counter mode register
aravindsv 0:ba7650f404af 444 // <0> TCM : Timer/Counter mode <R/W>
aravindsv 0:ba7650f404af 445
aravindsv 0:ba7650f404af 446 __IO uint32_t PEEER; //PWM output enable and external input enable register
aravindsv 0:ba7650f404af 447 // <0..1> PEEE : PWM output enable and external input enable <R/W>
aravindsv 0:ba7650f404af 448
aravindsv 0:ba7650f404af 449 __IO uint32_t CMR; //Capture mode register
aravindsv 0:ba7650f404af 450 // <0> CM : Capture mode <R/W>
aravindsv 0:ba7650f404af 451
aravindsv 0:ba7650f404af 452 __IO uint32_t CR; //Capture register
aravindsv 0:ba7650f404af 453 // <0..31> CR : Capture register <R>
aravindsv 0:ba7650f404af 454
aravindsv 0:ba7650f404af 455 __IO uint32_t PDMR; //Periodic mode register
aravindsv 0:ba7650f404af 456 // <0> PDM : Periodic mode <R/W>
aravindsv 0:ba7650f404af 457
aravindsv 0:ba7650f404af 458 __IO uint32_t DZER; //Dead-zone enable register
aravindsv 0:ba7650f404af 459 // <0> DZE : Dead-zone enable <R/W>
aravindsv 0:ba7650f404af 460
aravindsv 0:ba7650f404af 461 __IO uint32_t DZCR; //Dead-zone counter register
aravindsv 0:ba7650f404af 462 // <0..9> DZC : Dead-zone counter <R/W>
aravindsv 0:ba7650f404af 463 } PWM_CHn_TypeDef;
aravindsv 0:ba7650f404af 464
aravindsv 0:ba7650f404af 465 typedef struct
aravindsv 0:ba7650f404af 466 {
aravindsv 0:ba7650f404af 467 __IO uint32_t PWM_CHn_PR; //Prescale register
aravindsv 0:ba7650f404af 468 // <0..5> PR : prescale register <R/W>
aravindsv 0:ba7650f404af 469 __IO uint32_t PWM_CHn_MR; //Match register
aravindsv 0:ba7650f404af 470 // <0..31> MR : Match register <R/W>
aravindsv 0:ba7650f404af 471 __IO uint32_t PWM_CHn_LR; //Limit register
aravindsv 0:ba7650f404af 472 // <0..31> LR : Limit register <R/W>
aravindsv 0:ba7650f404af 473 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
aravindsv 0:ba7650f404af 474 // <0> UDM : Up-down mode <R/W>
aravindsv 0:ba7650f404af 475 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
aravindsv 0:ba7650f404af 476 // <0> PDM : Periodic mode <R/W>
aravindsv 0:ba7650f404af 477 }PWM_TimerModeInitTypeDef;
aravindsv 0:ba7650f404af 478
aravindsv 0:ba7650f404af 479 typedef struct
aravindsv 0:ba7650f404af 480 {
aravindsv 0:ba7650f404af 481 __IO uint32_t PWM_CHn_PR; //Prescale register
aravindsv 0:ba7650f404af 482 // <0..5> PR : prescale register <R/W>
aravindsv 0:ba7650f404af 483 __IO uint32_t PWM_CHn_MR; //Match register
aravindsv 0:ba7650f404af 484 // <0..31> MR : Match register <R/W>
aravindsv 0:ba7650f404af 485 __IO uint32_t PWM_CHn_LR; //Limit register
aravindsv 0:ba7650f404af 486 // <0..31> LR : Limit register <R/W>
aravindsv 0:ba7650f404af 487 __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
aravindsv 0:ba7650f404af 488 // <0> UDM : Up-down mode <R/W>
aravindsv 0:ba7650f404af 489 __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
aravindsv 0:ba7650f404af 490 // <0> PDM : Peiodic mode <R/W>
aravindsv 0:ba7650f404af 491 __IO uint32_t PWM_CHn_CMR; //Capture mode register
aravindsv 0:ba7650f404af 492 // <0> CM : Capture mode <R/W>
aravindsv 0:ba7650f404af 493 }PWM_CaptureModeInitTypeDef;
aravindsv 0:ba7650f404af 494
aravindsv 0:ba7650f404af 495 typedef struct
aravindsv 0:ba7650f404af 496 {
aravindsv 0:ba7650f404af 497 __IO uint32_t PWM_CHn_MR;
aravindsv 0:ba7650f404af 498 __IO uint32_t PWM_CHn_LR;
aravindsv 0:ba7650f404af 499 __IO uint32_t PWM_CHn_UDMR;
aravindsv 0:ba7650f404af 500 __IO uint32_t PWM_CHn_PDMR;
aravindsv 0:ba7650f404af 501 __IO uint32_t PWM_CHn_TCMR;
aravindsv 0:ba7650f404af 502 }PWM_CounterModeInitTypeDef;
aravindsv 0:ba7650f404af 503
aravindsv 0:ba7650f404af 504
aravindsv 0:ba7650f404af 505 /**
aravindsv 0:ba7650f404af 506 * @brief Random Number generator
aravindsv 0:ba7650f404af 507 */
aravindsv 0:ba7650f404af 508 typedef struct
aravindsv 0:ba7650f404af 509 {
aravindsv 0:ba7650f404af 510 __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
aravindsv 0:ba7650f404af 511 __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
aravindsv 0:ba7650f404af 512 __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
aravindsv 0:ba7650f404af 513 __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
aravindsv 0:ba7650f404af 514 __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
aravindsv 0:ba7650f404af 515 __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
aravindsv 0:ba7650f404af 516 }RNG_TypeDef;
aravindsv 0:ba7650f404af 517
aravindsv 0:ba7650f404af 518 /**
aravindsv 0:ba7650f404af 519 * @brief Serial Peripheral Interface
aravindsv 0:ba7650f404af 520 */
aravindsv 0:ba7650f404af 521 typedef struct
aravindsv 0:ba7650f404af 522 {
aravindsv 0:ba7650f404af 523 __IO uint32_t CR0;
aravindsv 0:ba7650f404af 524 __IO uint32_t CR1;
aravindsv 0:ba7650f404af 525 __IO uint32_t DR;
aravindsv 0:ba7650f404af 526 __IO uint32_t SR;
aravindsv 0:ba7650f404af 527 __IO uint32_t CPSR;
aravindsv 0:ba7650f404af 528 __IO uint32_t IMSC;
aravindsv 0:ba7650f404af 529 __IO uint32_t RIS;
aravindsv 0:ba7650f404af 530 __IO uint32_t MIS;
aravindsv 0:ba7650f404af 531 __IO uint32_t ICR;
aravindsv 0:ba7650f404af 532 __IO uint32_t DMACR;
aravindsv 0:ba7650f404af 533 } SSP_TypeDef;
aravindsv 0:ba7650f404af 534
aravindsv 0:ba7650f404af 535 typedef struct
aravindsv 0:ba7650f404af 536 {
aravindsv 0:ba7650f404af 537 __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
aravindsv 0:ba7650f404af 538 __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
aravindsv 0:ba7650f404af 539 __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
aravindsv 0:ba7650f404af 540 // <o.1> RESEN: Reset enable
aravindsv 0:ba7650f404af 541 // <o.0> INTEN: Interrupt enable
aravindsv 0:ba7650f404af 542 // </h>
aravindsv 0:ba7650f404af 543 __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
aravindsv 0:ba7650f404af 544 __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
aravindsv 0:ba7650f404af 545 __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
aravindsv 0:ba7650f404af 546 uint32_t RESERVED[762];
aravindsv 0:ba7650f404af 547 __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
aravindsv 0:ba7650f404af 548 }WATCHDOG_TypeDef;
aravindsv 0:ba7650f404af 549
aravindsv 0:ba7650f404af 550 /** @addtogroup Peripheral_memory_map
aravindsv 0:ba7650f404af 551 * @{
aravindsv 0:ba7650f404af 552 */
aravindsv 0:ba7650f404af 553
aravindsv 0:ba7650f404af 554 /* Peripheral and SRAM base address */
aravindsv 0:ba7650f404af 555 #define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
aravindsv 0:ba7650f404af 556 #define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
aravindsv 0:ba7650f404af 557 #define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
aravindsv 0:ba7650f404af 558
aravindsv 0:ba7650f404af 559 #define W7500x_RAM_BASE (0x20000000UL)
aravindsv 0:ba7650f404af 560 #define W7500x_APB1_BASE (0x40000000UL)
aravindsv 0:ba7650f404af 561 #define W7500x_APB2_BASE (0x41000000UL)
aravindsv 0:ba7650f404af 562 #define W7500x_AHB_BASE (0x42000000UL)
aravindsv 0:ba7650f404af 563
aravindsv 0:ba7650f404af 564 #define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
aravindsv 0:ba7650f404af 565 #define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
aravindsv 0:ba7650f404af 566 #define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
aravindsv 0:ba7650f404af 567
aravindsv 0:ba7650f404af 568 #define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
aravindsv 0:ba7650f404af 569 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
aravindsv 0:ba7650f404af 570
aravindsv 0:ba7650f404af 571 #define W7500x_INFO_BGT (0x0003FDB8)
aravindsv 0:ba7650f404af 572 #define W7500x_INFO_OSC (0x0003FDBC)
aravindsv 0:ba7650f404af 573
aravindsv 0:ba7650f404af 574 #define W7500x_TRIM_BGT (0x41001210)
aravindsv 0:ba7650f404af 575 #define W7500x_TRIM_OSC (0x41001004)
aravindsv 0:ba7650f404af 576
aravindsv 0:ba7650f404af 577 #define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
aravindsv 0:ba7650f404af 578 #define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
aravindsv 0:ba7650f404af 579
aravindsv 0:ba7650f404af 580 #define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
aravindsv 0:ba7650f404af 581
aravindsv 0:ba7650f404af 582 #define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
aravindsv 0:ba7650f404af 583 #define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
aravindsv 0:ba7650f404af 584 #define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
aravindsv 0:ba7650f404af 585 #define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
aravindsv 0:ba7650f404af 586
aravindsv 0:ba7650f404af 587 #define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
aravindsv 0:ba7650f404af 588
aravindsv 0:ba7650f404af 589 #define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
aravindsv 0:ba7650f404af 590
aravindsv 0:ba7650f404af 591 #define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
aravindsv 0:ba7650f404af 592 #define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
aravindsv 0:ba7650f404af 593
aravindsv 0:ba7650f404af 594 #define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
aravindsv 0:ba7650f404af 595
aravindsv 0:ba7650f404af 596 #define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
aravindsv 0:ba7650f404af 597
aravindsv 0:ba7650f404af 598 #define SSP0_BASE (0x4000A000)
aravindsv 0:ba7650f404af 599 #define SSP1_BASE (0x4000B000)
aravindsv 0:ba7650f404af 600
aravindsv 0:ba7650f404af 601 #define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
aravindsv 0:ba7650f404af 602
aravindsv 0:ba7650f404af 603 /**
aravindsv 0:ba7650f404af 604 * @}
aravindsv 0:ba7650f404af 605 */
aravindsv 0:ba7650f404af 606
aravindsv 0:ba7650f404af 607
aravindsv 0:ba7650f404af 608 /** @addtogroup Peripheral_declaration
aravindsv 0:ba7650f404af 609 * @{
aravindsv 0:ba7650f404af 610 */
aravindsv 0:ba7650f404af 611 #define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
aravindsv 0:ba7650f404af 612
aravindsv 0:ba7650f404af 613 #define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
aravindsv 0:ba7650f404af 614 #define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
aravindsv 0:ba7650f404af 615 #define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
aravindsv 0:ba7650f404af 616
aravindsv 0:ba7650f404af 617 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
aravindsv 0:ba7650f404af 618
aravindsv 0:ba7650f404af 619 #define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
aravindsv 0:ba7650f404af 620 #define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
aravindsv 0:ba7650f404af 621 #define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
aravindsv 0:ba7650f404af 622 #define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
aravindsv 0:ba7650f404af 623
aravindsv 0:ba7650f404af 624 #define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
aravindsv 0:ba7650f404af 625 #define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
aravindsv 0:ba7650f404af 626 #define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
aravindsv 0:ba7650f404af 627 #define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
aravindsv 0:ba7650f404af 628
aravindsv 0:ba7650f404af 629 #define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
aravindsv 0:ba7650f404af 630 #define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
aravindsv 0:ba7650f404af 631 #define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
aravindsv 0:ba7650f404af 632 #define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
aravindsv 0:ba7650f404af 633
aravindsv 0:ba7650f404af 634 #define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
aravindsv 0:ba7650f404af 635 #define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
aravindsv 0:ba7650f404af 636 #define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
aravindsv 0:ba7650f404af 637 #define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
aravindsv 0:ba7650f404af 638
aravindsv 0:ba7650f404af 639 #define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
aravindsv 0:ba7650f404af 640 #define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
aravindsv 0:ba7650f404af 641 #define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
aravindsv 0:ba7650f404af 642 #define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
aravindsv 0:ba7650f404af 643
aravindsv 0:ba7650f404af 644 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
aravindsv 0:ba7650f404af 645 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
aravindsv 0:ba7650f404af 646
aravindsv 0:ba7650f404af 647
aravindsv 0:ba7650f404af 648 #define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
aravindsv 0:ba7650f404af 649 #define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
aravindsv 0:ba7650f404af 650 #define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
aravindsv 0:ba7650f404af 651 #define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
aravindsv 0:ba7650f404af 652
aravindsv 0:ba7650f404af 653 #define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
aravindsv 0:ba7650f404af 654 #define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
aravindsv 0:ba7650f404af 655 #define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
aravindsv 0:ba7650f404af 656 #define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
aravindsv 0:ba7650f404af 657 #define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
aravindsv 0:ba7650f404af 658 #define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
aravindsv 0:ba7650f404af 659 #define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
aravindsv 0:ba7650f404af 660 #define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
aravindsv 0:ba7650f404af 661 #define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
aravindsv 0:ba7650f404af 662
aravindsv 0:ba7650f404af 663 #define PWM_CH0_BASE (W7500x_PWM_BASE)
aravindsv 0:ba7650f404af 664 #define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
aravindsv 0:ba7650f404af 665 #define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
aravindsv 0:ba7650f404af 666 #define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
aravindsv 0:ba7650f404af 667 #define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
aravindsv 0:ba7650f404af 668 #define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
aravindsv 0:ba7650f404af 669 #define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
aravindsv 0:ba7650f404af 670 #define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
aravindsv 0:ba7650f404af 671
aravindsv 0:ba7650f404af 672 #define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
aravindsv 0:ba7650f404af 673
aravindsv 0:ba7650f404af 674 #define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
aravindsv 0:ba7650f404af 675 #define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
aravindsv 0:ba7650f404af 676
aravindsv 0:ba7650f404af 677 #define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
aravindsv 0:ba7650f404af 678
aravindsv 0:ba7650f404af 679 /**
aravindsv 0:ba7650f404af 680 * @}
aravindsv 0:ba7650f404af 681 */
aravindsv 0:ba7650f404af 682
aravindsv 0:ba7650f404af 683
aravindsv 0:ba7650f404af 684
aravindsv 0:ba7650f404af 685 /******************************************************************************/
aravindsv 0:ba7650f404af 686 /* */
aravindsv 0:ba7650f404af 687 /* Clock Reset Generator */
aravindsv 0:ba7650f404af 688 /* */
aravindsv 0:ba7650f404af 689 /******************************************************************************/
aravindsv 0:ba7650f404af 690 /**************** Bit definition for CRG_OSC_PDR **************************/
aravindsv 0:ba7650f404af 691 #define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
aravindsv 0:ba7650f404af 692 #define CRG_OSC_PDR_PD (0x1ul) // Power Down
aravindsv 0:ba7650f404af 693 /**************** Bit definition for CRG_PLL_PDR **************************/
aravindsv 0:ba7650f404af 694 #define CRG_PLL_PDR_PD (0x0ul) // Power Down
aravindsv 0:ba7650f404af 695 #define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
aravindsv 0:ba7650f404af 696 /**************** Bit definition for CRG_PLL_FCR **************************/
aravindsv 0:ba7650f404af 697 //ToDo
aravindsv 0:ba7650f404af 698 /**************** Bit definition for CRG_PLL_OER **************************/
aravindsv 0:ba7650f404af 699 #define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
aravindsv 0:ba7650f404af 700 #define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
aravindsv 0:ba7650f404af 701 /**************** Bit definition for CRG_PLL_BPR **************************/
aravindsv 0:ba7650f404af 702 #define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
aravindsv 0:ba7650f404af 703 #define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
aravindsv 0:ba7650f404af 704 /**************** Bit definition for CRG_PLL_IFSR **************************/
aravindsv 0:ba7650f404af 705 #define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 706 #define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 707 /**************** Bit definition for CRG_FCLK_SSR **************************/
aravindsv 0:ba7650f404af 708 #define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
aravindsv 0:ba7650f404af 709 #define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 710 #define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 711 /**************** Bit definition for CRG_FCLK_PVSR **************************/
aravindsv 0:ba7650f404af 712 #define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 713 #define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 714 #define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 715 #define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 716 /**************** Bit definition for CRG_SSPCLK_SSR **************************/
aravindsv 0:ba7650f404af 717 #define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 718 #define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 719 #define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 720 #define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 721 /**************** Bit definition for CRG_SSPCLK_PVSR **************************/
aravindsv 0:ba7650f404af 722 #define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 723 #define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 724 #define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 725 #define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 726 /**************** Bit definition for CRG_ADCCLK_SSR **************************/
aravindsv 0:ba7650f404af 727 #define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 728 #define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 729 #define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 730 #define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 731 /**************** Bit definition for CRG_ADCCLK_PVSR **************************/
aravindsv 0:ba7650f404af 732 #define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 733 #define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 734 #define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 735 #define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 736 /**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
aravindsv 0:ba7650f404af 737 #define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 738 #define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 739 #define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 740 #define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 741 /**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
aravindsv 0:ba7650f404af 742 #define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 743 #define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 744 #define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 745 #define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 746 #define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
aravindsv 0:ba7650f404af 747 #define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
aravindsv 0:ba7650f404af 748 #define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
aravindsv 0:ba7650f404af 749 #define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
aravindsv 0:ba7650f404af 750 /**************** Bit definition for CRG_PWMnCLK_SSR **************************/
aravindsv 0:ba7650f404af 751 #define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 752 #define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 753 #define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 754 #define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 755 /**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
aravindsv 0:ba7650f404af 756 #define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 757 #define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 758 #define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 759 #define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 760 #define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
aravindsv 0:ba7650f404af 761 #define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
aravindsv 0:ba7650f404af 762 #define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
aravindsv 0:ba7650f404af 763 #define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
aravindsv 0:ba7650f404af 764 /**************** Bit definition for CRG_RTC_HS_SSR **************************/
aravindsv 0:ba7650f404af 765 #define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 766 #define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 767 #define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 768 #define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 769 /**************** Bit definition for CRG_RTC_HS_PVSR **************************/
aravindsv 0:ba7650f404af 770 #define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 771 #define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 772 #define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 773 #define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 774 #define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
aravindsv 0:ba7650f404af 775 #define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
aravindsv 0:ba7650f404af 776 #define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
aravindsv 0:ba7650f404af 777 #define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
aravindsv 0:ba7650f404af 778 /**************** Bit definition for CRG_RTC_SSR **************************/
aravindsv 0:ba7650f404af 779 #define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
aravindsv 0:ba7650f404af 780 #define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
aravindsv 0:ba7650f404af 781 /**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
aravindsv 0:ba7650f404af 782 #define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 783 #define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 784 #define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 785 #define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 786 /**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
aravindsv 0:ba7650f404af 787 #define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 788 #define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 789 #define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 790 #define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 791 #define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
aravindsv 0:ba7650f404af 792 #define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
aravindsv 0:ba7650f404af 793 #define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
aravindsv 0:ba7650f404af 794 #define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
aravindsv 0:ba7650f404af 795 /**************** Bit definition for CRG_WDOGCLK_SSR **************************/
aravindsv 0:ba7650f404af 796 #define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
aravindsv 0:ba7650f404af 797 #define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
aravindsv 0:ba7650f404af 798 /**************** Bit definition for CRG_UARTCLK_SSR **************************/
aravindsv 0:ba7650f404af 799 #define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
aravindsv 0:ba7650f404af 800 #define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
aravindsv 0:ba7650f404af 801 #define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 802 #define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 803 /**************** Bit definition for CRG_UARTCLK_PVSR **************************/
aravindsv 0:ba7650f404af 804 #define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
aravindsv 0:ba7650f404af 805 #define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
aravindsv 0:ba7650f404af 806 #define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
aravindsv 0:ba7650f404af 807 #define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
aravindsv 0:ba7650f404af 808 /**************** Bit definition for CRG_MIICLK_ECR **************************/
aravindsv 0:ba7650f404af 809 #define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
aravindsv 0:ba7650f404af 810 #define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
aravindsv 0:ba7650f404af 811 /**************** Bit definition for CRG_MONCLK_SSR **************************/
aravindsv 0:ba7650f404af 812 #define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
aravindsv 0:ba7650f404af 813 #define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
aravindsv 0:ba7650f404af 814 #define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
aravindsv 0:ba7650f404af 815 #define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
aravindsv 0:ba7650f404af 816 #define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
aravindsv 0:ba7650f404af 817 #define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
aravindsv 0:ba7650f404af 818 #define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
aravindsv 0:ba7650f404af 819 #define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
aravindsv 0:ba7650f404af 820 #define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
aravindsv 0:ba7650f404af 821 #define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
aravindsv 0:ba7650f404af 822 #define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
aravindsv 0:ba7650f404af 823 #define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
aravindsv 0:ba7650f404af 824 #define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
aravindsv 0:ba7650f404af 825 #define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
aravindsv 0:ba7650f404af 826 #define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
aravindsv 0:ba7650f404af 827 #define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
aravindsv 0:ba7650f404af 828 #define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
aravindsv 0:ba7650f404af 829 #define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
aravindsv 0:ba7650f404af 830 #define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
aravindsv 0:ba7650f404af 831 #define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
aravindsv 0:ba7650f404af 832
aravindsv 0:ba7650f404af 833 /******************************************************************************/
aravindsv 0:ba7650f404af 834 /* */
aravindsv 0:ba7650f404af 835 /* UART */
aravindsv 0:ba7650f404af 836 /* */
aravindsv 0:ba7650f404af 837 /******************************************************************************/
aravindsv 0:ba7650f404af 838 /****************** Bit definition for UART Data(UARTDR) register *************************/
aravindsv 0:ba7650f404af 839 #define UART_DR_OE (0x01ul << 11) // Overrun Error
aravindsv 0:ba7650f404af 840 #define UART_DR_BE (0x01ul << 10) // Break Error
aravindsv 0:ba7650f404af 841 #define UART_DR_PE (0x01ul << 9) // Parity Error
aravindsv 0:ba7650f404af 842 #define UART_DR_FE (0x01ul << 8) // Framing Error
aravindsv 0:ba7650f404af 843 //#define UART_DR_DR // ToDo
aravindsv 0:ba7650f404af 844 /***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
aravindsv 0:ba7650f404af 845 #define UARTR_SR_OE (0x01ul << 3) // Overrun Error
aravindsv 0:ba7650f404af 846 #define UARTR_SR_BE (0x01ul << 2) // Break Error
aravindsv 0:ba7650f404af 847 #define UARTR_SR_PE (0x01ul << 1) // Parity Error
aravindsv 0:ba7650f404af 848 #define UARTR_SR_FE (0x01ul << 0) // Framing Error
aravindsv 0:ba7650f404af 849 /***************** Bit definition for UART Error Clear(UARTECR) register ******************/
aravindsv 0:ba7650f404af 850 #define UARTE_CR_OE (0x01ul << 3) // Overrun Error
aravindsv 0:ba7650f404af 851 #define UARTE_CR_BE (0x01ul << 2) // Break Error
aravindsv 0:ba7650f404af 852 #define UARTE_CR_PE (0x01ul << 1) // Parity Error
aravindsv 0:ba7650f404af 853 #define UARTE_CR_FE (0x01ul << 0) // Framing Error
aravindsv 0:ba7650f404af 854 /****************** Bit definition for UART Flags(UARTFR) register ************************/
aravindsv 0:ba7650f404af 855 #define UART_FR_RI (0x01ul << 8) // Ring indicator
aravindsv 0:ba7650f404af 856 #define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
aravindsv 0:ba7650f404af 857 #define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
aravindsv 0:ba7650f404af 858 #define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
aravindsv 0:ba7650f404af 859 #define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
aravindsv 0:ba7650f404af 860 #define UART_FR_BUSY (0x01ul << 3) // UART busy
aravindsv 0:ba7650f404af 861 #define UART_FR_DCD (0x01ul << 2) // Data carrier detect
aravindsv 0:ba7650f404af 862 #define UART_FR_DSR (0x01ul << 1) // Data set ready
aravindsv 0:ba7650f404af 863 #define UART_FR_CTS (0x01ul << 0) // Clear to send
aravindsv 0:ba7650f404af 864 /********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
aravindsv 0:ba7650f404af 865 #define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
aravindsv 0:ba7650f404af 866 /********************* Bit definition for Line Control(UARTLCR_H) register *****************/
aravindsv 0:ba7650f404af 867 #define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
aravindsv 0:ba7650f404af 868 #define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
aravindsv 0:ba7650f404af 869 #define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
aravindsv 0:ba7650f404af 870 #define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
aravindsv 0:ba7650f404af 871 #define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
aravindsv 0:ba7650f404af 872 #define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
aravindsv 0:ba7650f404af 873 #define UART_LCR_H_BRK (0x1ul << 0) // Send break
aravindsv 0:ba7650f404af 874 /********************* Bit definition for Contro(UARTCR) register *************************/
aravindsv 0:ba7650f404af 875 #define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
aravindsv 0:ba7650f404af 876 #define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
aravindsv 0:ba7650f404af 877 #define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
aravindsv 0:ba7650f404af 878 #define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
aravindsv 0:ba7650f404af 879 #define UART_CR_RTS (0x1ul << 11) // Request to send
aravindsv 0:ba7650f404af 880 #define UART_CR_DTR (0x1ul << 10) // Data transmit ready
aravindsv 0:ba7650f404af 881 #define UART_CR_RXE (0x1ul << 9) // Receive enable
aravindsv 0:ba7650f404af 882 #define UART_CR_TXE (0x1ul << 8) // Transmit enable
aravindsv 0:ba7650f404af 883 #define UART_CR_LBE (0x1ul << 7) // Loop-back enable
aravindsv 0:ba7650f404af 884 #define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
aravindsv 0:ba7650f404af 885 #define UART_CR_SIREN (0x1ul << 1) // SIR enable
aravindsv 0:ba7650f404af 886 #define UART_CR_UARTEN (0x1ul << 0) // UART enable
aravindsv 0:ba7650f404af 887 /******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
aravindsv 0:ba7650f404af 888 #define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
aravindsv 0:ba7650f404af 889 #define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
aravindsv 0:ba7650f404af 890 /******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
aravindsv 0:ba7650f404af 891 #define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
aravindsv 0:ba7650f404af 892 #define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
aravindsv 0:ba7650f404af 893 #define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
aravindsv 0:ba7650f404af 894 #define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
aravindsv 0:ba7650f404af 895 #define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
aravindsv 0:ba7650f404af 896 #define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
aravindsv 0:ba7650f404af 897 #define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
aravindsv 0:ba7650f404af 898 #define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
aravindsv 0:ba7650f404af 899 #define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
aravindsv 0:ba7650f404af 900 #define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
aravindsv 0:ba7650f404af 901 #define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
aravindsv 0:ba7650f404af 902 /*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
aravindsv 0:ba7650f404af 903 #define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
aravindsv 0:ba7650f404af 904 #define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
aravindsv 0:ba7650f404af 905 #define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
aravindsv 0:ba7650f404af 906 #define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
aravindsv 0:ba7650f404af 907 #define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
aravindsv 0:ba7650f404af 908 #define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
aravindsv 0:ba7650f404af 909 #define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
aravindsv 0:ba7650f404af 910 #define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
aravindsv 0:ba7650f404af 911 #define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
aravindsv 0:ba7650f404af 912 #define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
aravindsv 0:ba7650f404af 913 #define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
aravindsv 0:ba7650f404af 914 /************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
aravindsv 0:ba7650f404af 915 #define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
aravindsv 0:ba7650f404af 916 #define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
aravindsv 0:ba7650f404af 917 #define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
aravindsv 0:ba7650f404af 918 #define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
aravindsv 0:ba7650f404af 919 #define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
aravindsv 0:ba7650f404af 920 #define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
aravindsv 0:ba7650f404af 921 #define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
aravindsv 0:ba7650f404af 922 #define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
aravindsv 0:ba7650f404af 923 #define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
aravindsv 0:ba7650f404af 924 #define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
aravindsv 0:ba7650f404af 925 #define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
aravindsv 0:ba7650f404af 926 /*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
aravindsv 0:ba7650f404af 927 #define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
aravindsv 0:ba7650f404af 928 #define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
aravindsv 0:ba7650f404af 929 #define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
aravindsv 0:ba7650f404af 930 #define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
aravindsv 0:ba7650f404af 931 #define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
aravindsv 0:ba7650f404af 932 #define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
aravindsv 0:ba7650f404af 933 #define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
aravindsv 0:ba7650f404af 934 #define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
aravindsv 0:ba7650f404af 935 #define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
aravindsv 0:ba7650f404af 936 #define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
aravindsv 0:ba7650f404af 937 #define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
aravindsv 0:ba7650f404af 938 /***************** Bit definition for DMA Control(UARTDMACR) register ************************/
aravindsv 0:ba7650f404af 939 #define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
aravindsv 0:ba7650f404af 940 #define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
aravindsv 0:ba7650f404af 941 #define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
aravindsv 0:ba7650f404af 942
aravindsv 0:ba7650f404af 943 /******************************************************************************/
aravindsv 0:ba7650f404af 944 /* */
aravindsv 0:ba7650f404af 945 /* Simple UART */
aravindsv 0:ba7650f404af 946 /* */
aravindsv 0:ba7650f404af 947 /******************************************************************************/
aravindsv 0:ba7650f404af 948 /***************** Bit definition for S_UART Data () register ************************/
aravindsv 0:ba7650f404af 949 #define S_UART_DATA (0xFFul << 0)
aravindsv 0:ba7650f404af 950 /***************** Bit definition for S_UART State() register ************************/
aravindsv 0:ba7650f404af 951 #define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
aravindsv 0:ba7650f404af 952 #define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
aravindsv 0:ba7650f404af 953 #define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
aravindsv 0:ba7650f404af 954 /***************** Bit definition for S_UART Control() register ************************/
aravindsv 0:ba7650f404af 955 #define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
aravindsv 0:ba7650f404af 956 #define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
aravindsv 0:ba7650f404af 957 #define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
aravindsv 0:ba7650f404af 958 #define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
aravindsv 0:ba7650f404af 959 #define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
aravindsv 0:ba7650f404af 960 #define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
aravindsv 0:ba7650f404af 961 #define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
aravindsv 0:ba7650f404af 962 /***************** Bit definition for S_UART Interrupt() register ************************/
aravindsv 0:ba7650f404af 963 #define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
aravindsv 0:ba7650f404af 964 #define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
aravindsv 0:ba7650f404af 965 #define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
aravindsv 0:ba7650f404af 966 #define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
aravindsv 0:ba7650f404af 967
aravindsv 0:ba7650f404af 968 /******************************************************************************/
aravindsv 0:ba7650f404af 969 /* */
aravindsv 0:ba7650f404af 970 /* Analog Digital Register */
aravindsv 0:ba7650f404af 971 /* */
aravindsv 0:ba7650f404af 972 /******************************************************************************/
aravindsv 0:ba7650f404af 973
aravindsv 0:ba7650f404af 974 /*********************** Bit definition for ADC_CTR ***********************/
aravindsv 0:ba7650f404af 975 //#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
aravindsv 0:ba7650f404af 976 //#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
aravindsv 0:ba7650f404af 977 #define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
aravindsv 0:ba7650f404af 978 #define ADC_CTR_PWD_PD (0x3ul) // Power down
aravindsv 0:ba7650f404af 979 /*********************** Bit definition for ADC_CHSEL ***********************/
aravindsv 0:ba7650f404af 980 #define ADC_CHSEL_CH0 (0x0ul) // Channel 0
aravindsv 0:ba7650f404af 981 #define ADC_CHSEL_CH1 (0x1ul) // Channel 1
aravindsv 0:ba7650f404af 982 #define ADC_CHSEL_CH2 (0x2ul) // Channel 2
aravindsv 0:ba7650f404af 983 #define ADC_CHSEL_CH3 (0x3ul) // Channel 3
aravindsv 0:ba7650f404af 984 #define ADC_CHSEL_CH4 (0x4ul) // Channel 4
aravindsv 0:ba7650f404af 985 #define ADC_CHSEL_CH5 (0x5ul) // Channel 5
aravindsv 0:ba7650f404af 986 #define ADC_CHSEL_CH6 (0x6ul) // Channel 6
aravindsv 0:ba7650f404af 987 #define ADC_CHSEL_CH7 (0x7ul) // Channel 7
aravindsv 0:ba7650f404af 988 #define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
aravindsv 0:ba7650f404af 989 /*********************** Bit definition for ADC_START ***********************/
aravindsv 0:ba7650f404af 990 #define ADC_START_START (0x1ul) // ADC conversion start
aravindsv 0:ba7650f404af 991 /*********************** Bit definition for ADC_DATA ***********************/
aravindsv 0:ba7650f404af 992 //ToDo (Readonly)
aravindsv 0:ba7650f404af 993
aravindsv 0:ba7650f404af 994 /*********************** Bit definition for ADC_INT ***********************/
aravindsv 0:ba7650f404af 995 #define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
aravindsv 0:ba7650f404af 996 #define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
aravindsv 0:ba7650f404af 997 //ToDo (Readonly)
aravindsv 0:ba7650f404af 998
aravindsv 0:ba7650f404af 999 /*********************** Bit definition for ADC_INTCLR ***********************/
aravindsv 0:ba7650f404af 1000 #define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
aravindsv 0:ba7650f404af 1001
aravindsv 0:ba7650f404af 1002 #define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
aravindsv 0:ba7650f404af 1003 #define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
aravindsv 0:ba7650f404af 1004
aravindsv 0:ba7650f404af 1005 /******************************************************************************/
aravindsv 0:ba7650f404af 1006 /* */
aravindsv 0:ba7650f404af 1007 /* Dual Timer */
aravindsv 0:ba7650f404af 1008 /* */
aravindsv 0:ba7650f404af 1009 /******************************************************************************/
aravindsv 0:ba7650f404af 1010
aravindsv 0:ba7650f404af 1011 /*********************** Bit definition for dualtimer ***********************/
aravindsv 0:ba7650f404af 1012 #define DUALTIMER_TimerControl_TimerDIsable 0x0ul
aravindsv 0:ba7650f404af 1013 #define DUALTIMER_TimerControl_TimerEnable 0x1ul
aravindsv 0:ba7650f404af 1014 #define DUALTIMER_TimerControl_TimerEnable_Pos 7
aravindsv 0:ba7650f404af 1015
aravindsv 0:ba7650f404af 1016 #define DUALTIMER_TimerControl_FreeRunning 0x0ul
aravindsv 0:ba7650f404af 1017 #define DUALTIMER_TimerControl_Periodic 0x1ul
aravindsv 0:ba7650f404af 1018 #define DUALTIMER_TimerControl_TimerMode_Pos 6
aravindsv 0:ba7650f404af 1019
aravindsv 0:ba7650f404af 1020 #define DUALTIMER_TimerControl_IntDisable 0x0ul
aravindsv 0:ba7650f404af 1021 #define DUALTIMER_TimerControl_IntEnable 0x1ul
aravindsv 0:ba7650f404af 1022 #define DUALTIMER_TimerControl_IntEnable_Pos 5
aravindsv 0:ba7650f404af 1023
aravindsv 0:ba7650f404af 1024 #define DUALTIMER_TimerControl_Pre_1 0x0ul
aravindsv 0:ba7650f404af 1025 #define DUALTIMER_TimerControl_Pre_16 0x1ul
aravindsv 0:ba7650f404af 1026 #define DUALTIMER_TimerControl_Pre_256 0x2ul
aravindsv 0:ba7650f404af 1027 #define DUALTIMER_TimerControl_Pre_Pos 2
aravindsv 0:ba7650f404af 1028
aravindsv 0:ba7650f404af 1029 #define DUALTIMER_TimerControl_Size_16 0x0ul
aravindsv 0:ba7650f404af 1030 #define DUALTIMER_TimerControl_Size_32 0x1ul
aravindsv 0:ba7650f404af 1031 #define DUALTIMER_TimerControl_Size_Pos 1
aravindsv 0:ba7650f404af 1032
aravindsv 0:ba7650f404af 1033 #define DUALTIMER_TimerControl_Wrapping 0x0ul
aravindsv 0:ba7650f404af 1034 #define DUALTIMER_TimerControl_OneShot 0x1ul
aravindsv 0:ba7650f404af 1035 #define DUALTIMER_TimerControl_OneShot_Pos 0
aravindsv 0:ba7650f404af 1036
aravindsv 0:ba7650f404af 1037 /******************************************************************************/
aravindsv 0:ba7650f404af 1038 /* */
aravindsv 0:ba7650f404af 1039 /* External Interrupt */
aravindsv 0:ba7650f404af 1040 /* */
aravindsv 0:ba7650f404af 1041 /******************************************************************************/
aravindsv 0:ba7650f404af 1042
aravindsv 0:ba7650f404af 1043 /**************** Bit definition for Px_IER **************************/
aravindsv 0:ba7650f404af 1044 #define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
aravindsv 0:ba7650f404af 1045 #define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
aravindsv 0:ba7650f404af 1046 #define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
aravindsv 0:ba7650f404af 1047 #define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
aravindsv 0:ba7650f404af 1048
aravindsv 0:ba7650f404af 1049 /******************************************************************************/
aravindsv 0:ba7650f404af 1050 /* */
aravindsv 0:ba7650f404af 1051 /* GPIO */
aravindsv 0:ba7650f404af 1052 /* */
aravindsv 0:ba7650f404af 1053 /******************************************************************************/
aravindsv 0:ba7650f404af 1054
aravindsv 0:ba7650f404af 1055 /**************** Bit definition for Px_AFSR **************************/
aravindsv 0:ba7650f404af 1056 #define Px_AFSR_AF0 (0x00ul)
aravindsv 0:ba7650f404af 1057 #define Px_AFSR_AF1 (0x01ul)
aravindsv 0:ba7650f404af 1058 #define Px_AFSR_AF2 (0x02ul)
aravindsv 0:ba7650f404af 1059 #define Px_AFSR_AF3 (0x03ul)
aravindsv 0:ba7650f404af 1060 /**************** Bit definition for Px_PCR **************************/
aravindsv 0:ba7650f404af 1061 #define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
aravindsv 0:ba7650f404af 1062 #define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
aravindsv 0:ba7650f404af 1063 #define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
aravindsv 0:ba7650f404af 1064 #define Px_PCR_OD (0x01ul << 3) // Open Drain
aravindsv 0:ba7650f404af 1065 #define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
aravindsv 0:ba7650f404af 1066 #define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
aravindsv 0:ba7650f404af 1067
aravindsv 0:ba7650f404af 1068 /******************************************************************************/
aravindsv 0:ba7650f404af 1069 /* */
aravindsv 0:ba7650f404af 1070 /* I2C */
aravindsv 0:ba7650f404af 1071 /* */
aravindsv 0:ba7650f404af 1072 /******************************************************************************/
aravindsv 0:ba7650f404af 1073
aravindsv 0:ba7650f404af 1074 /**************** Bit definition for I2C_CTR **************************/
aravindsv 0:ba7650f404af 1075 #define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
aravindsv 0:ba7650f404af 1076 #define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
aravindsv 0:ba7650f404af 1077 #define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
aravindsv 0:ba7650f404af 1078 #define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
aravindsv 0:ba7650f404af 1079 #define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
aravindsv 0:ba7650f404af 1080 #define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
aravindsv 0:ba7650f404af 1081
aravindsv 0:ba7650f404af 1082 /**************** Bit definition for I2C_CMDR **************************/
aravindsv 0:ba7650f404af 1083 #define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
aravindsv 0:ba7650f404af 1084 #define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
aravindsv 0:ba7650f404af 1085 #define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
aravindsv 0:ba7650f404af 1086 #define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
aravindsv 0:ba7650f404af 1087
aravindsv 0:ba7650f404af 1088 /**************** Bit definition for I2C_ISCR **************************/
aravindsv 0:ba7650f404af 1089 #define I2C_ISCR_RST (0x01ul << 1) // 0x01
aravindsv 0:ba7650f404af 1090
aravindsv 0:ba7650f404af 1091 /**************** Bit definition for I2C_SR **************************/
aravindsv 0:ba7650f404af 1092 #define I2C_SR_TX (0x01ul << 9 ) // 0x200
aravindsv 0:ba7650f404af 1093 #define I2C_SR_RX (0x01ul << 8 ) // 0x100
aravindsv 0:ba7650f404af 1094 #define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
aravindsv 0:ba7650f404af 1095 #define I2C_SR_BT (0x01ul << 6 ) // 0x040
aravindsv 0:ba7650f404af 1096 #define I2C_SR_SA (0x01ul << 5 ) // 0x020
aravindsv 0:ba7650f404af 1097 #define I2C_SR_SB (0x01ul << 4 ) // 0x010
aravindsv 0:ba7650f404af 1098 #define I2C_SR_AL (0x01ul << 3 ) // 0x008
aravindsv 0:ba7650f404af 1099 #define I2C_SR_TO (0x01ul << 2 ) // 0x004
aravindsv 0:ba7650f404af 1100 #define I2C_SR_SRW (0x01ul << 1 ) // 0x002
aravindsv 0:ba7650f404af 1101 #define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
aravindsv 0:ba7650f404af 1102
aravindsv 0:ba7650f404af 1103 /**************** Bit definition for I2C_ISR **************************/
aravindsv 0:ba7650f404af 1104 #define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
aravindsv 0:ba7650f404af 1105 #define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
aravindsv 0:ba7650f404af 1106 #define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
aravindsv 0:ba7650f404af 1107 #define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
aravindsv 0:ba7650f404af 1108 #define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
aravindsv 0:ba7650f404af 1109
aravindsv 0:ba7650f404af 1110 /**************** Bit definition for I2C_ISMR **************************/
aravindsv 0:ba7650f404af 1111 #define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
aravindsv 0:ba7650f404af 1112 #define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
aravindsv 0:ba7650f404af 1113 #define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
aravindsv 0:ba7650f404af 1114 #define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
aravindsv 0:ba7650f404af 1115 #define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
aravindsv 0:ba7650f404af 1116
aravindsv 0:ba7650f404af 1117 /******************************************************************************/
aravindsv 0:ba7650f404af 1118 /* */
aravindsv 0:ba7650f404af 1119 /* PWM */
aravindsv 0:ba7650f404af 1120 /* */
aravindsv 0:ba7650f404af 1121 /******************************************************************************/
aravindsv 0:ba7650f404af 1122
aravindsv 0:ba7650f404af 1123 /******************************************************************************/
aravindsv 0:ba7650f404af 1124 /* */
aravindsv 0:ba7650f404af 1125 /* Random number generator Register */
aravindsv 0:ba7650f404af 1126 /* */
aravindsv 0:ba7650f404af 1127 /******************************************************************************/
aravindsv 0:ba7650f404af 1128
aravindsv 0:ba7650f404af 1129 /*********************** Bit definition for RNG_RUN ***********************/
aravindsv 0:ba7650f404af 1130 #define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
aravindsv 0:ba7650f404af 1131 #define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
aravindsv 0:ba7650f404af 1132 /*********************** Bit definition for RNG_SEED ***********************/
aravindsv 0:ba7650f404af 1133 //ToDo
aravindsv 0:ba7650f404af 1134
aravindsv 0:ba7650f404af 1135 /*********************** Bit definition for RNG_CLKSEL ***********************/
aravindsv 0:ba7650f404af 1136 #define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
aravindsv 0:ba7650f404af 1137 #define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
aravindsv 0:ba7650f404af 1138 /*********************** Bit definition for RNG_ENABLE ***********************/
aravindsv 0:ba7650f404af 1139 #define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
aravindsv 0:ba7650f404af 1140 #define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
aravindsv 0:ba7650f404af 1141 /*********************** Bit definition for RNG_RN ***********************/
aravindsv 0:ba7650f404af 1142 //ToDo
aravindsv 0:ba7650f404af 1143
aravindsv 0:ba7650f404af 1144 /*********************** Bit definition for RNG_POLY ***********************/
aravindsv 0:ba7650f404af 1145 //ToDo
aravindsv 0:ba7650f404af 1146
aravindsv 0:ba7650f404af 1147
aravindsv 0:ba7650f404af 1148
aravindsv 0:ba7650f404af 1149 typedef enum
aravindsv 0:ba7650f404af 1150 {
aravindsv 0:ba7650f404af 1151 PAD_PA = 0,
aravindsv 0:ba7650f404af 1152 PAD_PB,
aravindsv 0:ba7650f404af 1153 PAD_PC,
aravindsv 0:ba7650f404af 1154 PAD_PD
aravindsv 0:ba7650f404af 1155 }PAD_Type;
aravindsv 0:ba7650f404af 1156
aravindsv 0:ba7650f404af 1157 typedef enum
aravindsv 0:ba7650f404af 1158 {
aravindsv 0:ba7650f404af 1159 PAD_AF0 = Px_AFSR_AF0,
aravindsv 0:ba7650f404af 1160 PAD_AF1 = Px_AFSR_AF1,
aravindsv 0:ba7650f404af 1161 PAD_AF2 = Px_AFSR_AF2,
aravindsv 0:ba7650f404af 1162 PAD_AF3 = Px_AFSR_AF3
aravindsv 0:ba7650f404af 1163 }PAD_AF_TypeDef;
aravindsv 0:ba7650f404af 1164
aravindsv 0:ba7650f404af 1165
aravindsv 0:ba7650f404af 1166 #if !defined (USE_HAL_DRIVER)
aravindsv 0:ba7650f404af 1167 #define USE_HAL_DRIVER
aravindsv 0:ba7650f404af 1168 #endif /* USE_HAL_DRIVER */
aravindsv 0:ba7650f404af 1169
aravindsv 0:ba7650f404af 1170
aravindsv 0:ba7650f404af 1171
aravindsv 0:ba7650f404af 1172 #if defined (USE_HAL_DRIVER)
aravindsv 0:ba7650f404af 1173 // #include "system_W7500x.h"
aravindsv 0:ba7650f404af 1174 // #include "W7500x_conf.h"
aravindsv 0:ba7650f404af 1175 #endif
aravindsv 0:ba7650f404af 1176
aravindsv 0:ba7650f404af 1177 #ifdef USE_FULL_ASSERT
aravindsv 0:ba7650f404af 1178 #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
aravindsv 0:ba7650f404af 1179 #else
aravindsv 0:ba7650f404af 1180 #define assert_param(expr) ((void)0)
aravindsv 0:ba7650f404af 1181 #endif /* USE_FULL_ASSERT */
aravindsv 0:ba7650f404af 1182
aravindsv 0:ba7650f404af 1183 #ifdef __cplusplus
aravindsv 0:ba7650f404af 1184 }
aravindsv 0:ba7650f404af 1185 #endif
aravindsv 0:ba7650f404af 1186
aravindsv 0:ba7650f404af 1187 #endif /* W7500x_H */
aravindsv 0:ba7650f404af 1188
aravindsv 0:ba7650f404af 1189
aravindsv 0:ba7650f404af 1190
aravindsv 0:ba7650f404af 1191 /************************ (C) COPYRIGHT Wiznet *****END OF FILE****/