Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

common/SPI.cpp@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /* mbed Microcontroller Library
aravindsv 0:ba7650f404af 2 * Copyright (c) 2006-2013 ARM Limited
aravindsv 0:ba7650f404af 3 *
aravindsv 0:ba7650f404af 4 * Licensed under the Apache License, Version 2.0 (the "License");
aravindsv 0:ba7650f404af 5 * you may not use this file except in compliance with the License.
aravindsv 0:ba7650f404af 6 * You may obtain a copy of the License at
aravindsv 0:ba7650f404af 7 *
aravindsv 0:ba7650f404af 8 * http://www.apache.org/licenses/LICENSE-2.0
aravindsv 0:ba7650f404af 9 *
aravindsv 0:ba7650f404af 10 * Unless required by applicable law or agreed to in writing, software
aravindsv 0:ba7650f404af 11 * distributed under the License is distributed on an "AS IS" BASIS,
aravindsv 0:ba7650f404af 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
aravindsv 0:ba7650f404af 13 * See the License for the specific language governing permissions and
aravindsv 0:ba7650f404af 14 * limitations under the License.
aravindsv 0:ba7650f404af 15 */
aravindsv 0:ba7650f404af 16 #include "SPI.h"
aravindsv 0:ba7650f404af 17
aravindsv 0:ba7650f404af 18 #if DEVICE_SPI
aravindsv 0:ba7650f404af 19
aravindsv 0:ba7650f404af 20 namespace mbed {
aravindsv 0:ba7650f404af 21
aravindsv 0:ba7650f404af 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
aravindsv 0:ba7650f404af 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
aravindsv 0:ba7650f404af 24 #endif
aravindsv 0:ba7650f404af 25
aravindsv 0:ba7650f404af 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
aravindsv 0:ba7650f404af 27 _spi(),
aravindsv 0:ba7650f404af 28 #if DEVICE_SPI_ASYNCH
aravindsv 0:ba7650f404af 29 _irq(this),
aravindsv 0:ba7650f404af 30 _usage(DMA_USAGE_NEVER),
aravindsv 0:ba7650f404af 31 #endif
aravindsv 0:ba7650f404af 32 _bits(8),
aravindsv 0:ba7650f404af 33 _mode(0),
aravindsv 0:ba7650f404af 34 _hz(1000000) {
aravindsv 0:ba7650f404af 35 spi_init(&_spi, mosi, miso, sclk, ssel);
aravindsv 0:ba7650f404af 36 spi_format(&_spi, _bits, _mode, 0);
aravindsv 0:ba7650f404af 37 spi_frequency(&_spi, _hz);
aravindsv 0:ba7650f404af 38 }
aravindsv 0:ba7650f404af 39
aravindsv 0:ba7650f404af 40 void SPI::format(int bits, int mode) {
aravindsv 0:ba7650f404af 41 _bits = bits;
aravindsv 0:ba7650f404af 42 _mode = mode;
aravindsv 0:ba7650f404af 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
aravindsv 0:ba7650f404af 44 aquire();
aravindsv 0:ba7650f404af 45 }
aravindsv 0:ba7650f404af 46
aravindsv 0:ba7650f404af 47 void SPI::frequency(int hz) {
aravindsv 0:ba7650f404af 48 _hz = hz;
aravindsv 0:ba7650f404af 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
aravindsv 0:ba7650f404af 50 aquire();
aravindsv 0:ba7650f404af 51 }
aravindsv 0:ba7650f404af 52
aravindsv 0:ba7650f404af 53 SPI* SPI::_owner = NULL;
aravindsv 0:ba7650f404af 54
aravindsv 0:ba7650f404af 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
aravindsv 0:ba7650f404af 56 void SPI::aquire() {
aravindsv 0:ba7650f404af 57 if (_owner != this) {
aravindsv 0:ba7650f404af 58 spi_format(&_spi, _bits, _mode, 0);
aravindsv 0:ba7650f404af 59 spi_frequency(&_spi, _hz);
aravindsv 0:ba7650f404af 60 _owner = this;
aravindsv 0:ba7650f404af 61 }
aravindsv 0:ba7650f404af 62 }
aravindsv 0:ba7650f404af 63
aravindsv 0:ba7650f404af 64 int SPI::write(int value) {
aravindsv 0:ba7650f404af 65 aquire();
aravindsv 0:ba7650f404af 66 return spi_master_write(&_spi, value);
aravindsv 0:ba7650f404af 67 }
aravindsv 0:ba7650f404af 68
aravindsv 0:ba7650f404af 69 #if DEVICE_SPI_ASYNCH
aravindsv 0:ba7650f404af 70
aravindsv 0:ba7650f404af 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
aravindsv 0:ba7650f404af 72 {
aravindsv 0:ba7650f404af 73 if (spi_active(&_spi)) {
aravindsv 0:ba7650f404af 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
aravindsv 0:ba7650f404af 75 }
aravindsv 0:ba7650f404af 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
aravindsv 0:ba7650f404af 77 return 0;
aravindsv 0:ba7650f404af 78 }
aravindsv 0:ba7650f404af 79
aravindsv 0:ba7650f404af 80 void SPI::abort_transfer()
aravindsv 0:ba7650f404af 81 {
aravindsv 0:ba7650f404af 82 spi_abort_asynch(&_spi);
aravindsv 0:ba7650f404af 83 #if TRANSACTION_QUEUE_SIZE_SPI
aravindsv 0:ba7650f404af 84 dequeue_transaction();
aravindsv 0:ba7650f404af 85 #endif
aravindsv 0:ba7650f404af 86 }
aravindsv 0:ba7650f404af 87
aravindsv 0:ba7650f404af 88
aravindsv 0:ba7650f404af 89 void SPI::clear_transfer_buffer()
aravindsv 0:ba7650f404af 90 {
aravindsv 0:ba7650f404af 91 #if TRANSACTION_QUEUE_SIZE_SPI
aravindsv 0:ba7650f404af 92 _transaction_buffer.reset();
aravindsv 0:ba7650f404af 93 #endif
aravindsv 0:ba7650f404af 94 }
aravindsv 0:ba7650f404af 95
aravindsv 0:ba7650f404af 96 void SPI::abort_all_transfers()
aravindsv 0:ba7650f404af 97 {
aravindsv 0:ba7650f404af 98 clear_transfer_buffer();
aravindsv 0:ba7650f404af 99 abort_transfer();
aravindsv 0:ba7650f404af 100 }
aravindsv 0:ba7650f404af 101
aravindsv 0:ba7650f404af 102 int SPI::set_dma_usage(DMAUsage usage)
aravindsv 0:ba7650f404af 103 {
aravindsv 0:ba7650f404af 104 if (spi_active(&_spi)) {
aravindsv 0:ba7650f404af 105 return -1;
aravindsv 0:ba7650f404af 106 }
aravindsv 0:ba7650f404af 107 _usage = usage;
aravindsv 0:ba7650f404af 108 return 0;
aravindsv 0:ba7650f404af 109 }
aravindsv 0:ba7650f404af 110
aravindsv 0:ba7650f404af 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
aravindsv 0:ba7650f404af 112 {
aravindsv 0:ba7650f404af 113 #if TRANSACTION_QUEUE_SIZE_SPI
aravindsv 0:ba7650f404af 114 transaction_t t;
aravindsv 0:ba7650f404af 115
aravindsv 0:ba7650f404af 116 t.tx_buffer = const_cast<void *>(tx_buffer);
aravindsv 0:ba7650f404af 117 t.tx_length = tx_length;
aravindsv 0:ba7650f404af 118 t.rx_buffer = rx_buffer;
aravindsv 0:ba7650f404af 119 t.rx_length = rx_length;
aravindsv 0:ba7650f404af 120 t.event = event;
aravindsv 0:ba7650f404af 121 t.callback = callback;
aravindsv 0:ba7650f404af 122 t.width = bit_width;
aravindsv 0:ba7650f404af 123 Transaction<SPI> transaction(this, t);
aravindsv 0:ba7650f404af 124 if (_transaction_buffer.full()) {
aravindsv 0:ba7650f404af 125 return -1; // the buffer is full
aravindsv 0:ba7650f404af 126 } else {
aravindsv 0:ba7650f404af 127 _transaction_buffer.push(transaction);
aravindsv 0:ba7650f404af 128 return 0;
aravindsv 0:ba7650f404af 129 }
aravindsv 0:ba7650f404af 130 #else
aravindsv 0:ba7650f404af 131 return -1;
aravindsv 0:ba7650f404af 132 #endif
aravindsv 0:ba7650f404af 133 }
aravindsv 0:ba7650f404af 134
aravindsv 0:ba7650f404af 135 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
aravindsv 0:ba7650f404af 136 {
aravindsv 0:ba7650f404af 137 aquire();
aravindsv 0:ba7650f404af 138 _callback = callback;
aravindsv 0:ba7650f404af 139 _irq.callback(&SPI::irq_handler_asynch);
aravindsv 0:ba7650f404af 140 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
aravindsv 0:ba7650f404af 141 }
aravindsv 0:ba7650f404af 142
aravindsv 0:ba7650f404af 143 #if TRANSACTION_QUEUE_SIZE_SPI
aravindsv 0:ba7650f404af 144
aravindsv 0:ba7650f404af 145 void SPI::start_transaction(transaction_t *data)
aravindsv 0:ba7650f404af 146 {
aravindsv 0:ba7650f404af 147 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
aravindsv 0:ba7650f404af 148 }
aravindsv 0:ba7650f404af 149
aravindsv 0:ba7650f404af 150 void SPI::dequeue_transaction()
aravindsv 0:ba7650f404af 151 {
aravindsv 0:ba7650f404af 152 Transaction<SPI> t;
aravindsv 0:ba7650f404af 153 if (_transaction_buffer.pop(t)) {
aravindsv 0:ba7650f404af 154 SPI* obj = t.get_object();
aravindsv 0:ba7650f404af 155 transaction_t* data = t.get_transaction();
aravindsv 0:ba7650f404af 156 obj->start_transaction(data);
aravindsv 0:ba7650f404af 157 }
aravindsv 0:ba7650f404af 158 }
aravindsv 0:ba7650f404af 159
aravindsv 0:ba7650f404af 160 #endif
aravindsv 0:ba7650f404af 161
aravindsv 0:ba7650f404af 162 void SPI::irq_handler_asynch(void)
aravindsv 0:ba7650f404af 163 {
aravindsv 0:ba7650f404af 164 int event = spi_irq_handler_asynch(&_spi);
aravindsv 0:ba7650f404af 165 if (_callback && (event & SPI_EVENT_ALL)) {
aravindsv 0:ba7650f404af 166 _callback.call(event & SPI_EVENT_ALL);
aravindsv 0:ba7650f404af 167 }
aravindsv 0:ba7650f404af 168 #if TRANSACTION_QUEUE_SIZE_SPI
aravindsv 0:ba7650f404af 169 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
aravindsv 0:ba7650f404af 170 // SPI peripheral is free (event happend), dequeue transaction
aravindsv 0:ba7650f404af 171 dequeue_transaction();
aravindsv 0:ba7650f404af 172 }
aravindsv 0:ba7650f404af 173 #endif
aravindsv 0:ba7650f404af 174 }
aravindsv 0:ba7650f404af 175
aravindsv 0:ba7650f404af 176 #endif
aravindsv 0:ba7650f404af 177
aravindsv 0:ba7650f404af 178 } // namespace mbed
aravindsv 0:ba7650f404af 179
aravindsv 0:ba7650f404af 180 #endif