Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/core_cmFunc.h@0:ba7650f404af, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 02:26:59 2015 +0000
Revision:
0:ba7650f404af
Reduced HSE_STARTUP_TIMEOUT to 500 ms, fixed some compiler warnings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**************************************************************************//**
aravindsv 0:ba7650f404af 2 * @file core_cmFunc.h
aravindsv 0:ba7650f404af 3 * @brief CMSIS Cortex-M Core Function Access Header File
aravindsv 0:ba7650f404af 4 * @version V3.20
aravindsv 0:ba7650f404af 5 * @date 25. February 2013
aravindsv 0:ba7650f404af 6 *
aravindsv 0:ba7650f404af 7 * @note
aravindsv 0:ba7650f404af 8 *
aravindsv 0:ba7650f404af 9 ******************************************************************************/
aravindsv 0:ba7650f404af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
aravindsv 0:ba7650f404af 11
aravindsv 0:ba7650f404af 12 All rights reserved.
aravindsv 0:ba7650f404af 13 Redistribution and use in source and binary forms, with or without
aravindsv 0:ba7650f404af 14 modification, are permitted provided that the following conditions are met:
aravindsv 0:ba7650f404af 15 - Redistributions of source code must retain the above copyright
aravindsv 0:ba7650f404af 16 notice, this list of conditions and the following disclaimer.
aravindsv 0:ba7650f404af 17 - Redistributions in binary form must reproduce the above copyright
aravindsv 0:ba7650f404af 18 notice, this list of conditions and the following disclaimer in the
aravindsv 0:ba7650f404af 19 documentation and/or other materials provided with the distribution.
aravindsv 0:ba7650f404af 20 - Neither the name of ARM nor the names of its contributors may be used
aravindsv 0:ba7650f404af 21 to endorse or promote products derived from this software without
aravindsv 0:ba7650f404af 22 specific prior written permission.
aravindsv 0:ba7650f404af 23 *
aravindsv 0:ba7650f404af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
aravindsv 0:ba7650f404af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
aravindsv 0:ba7650f404af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
aravindsv 0:ba7650f404af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
aravindsv 0:ba7650f404af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
aravindsv 0:ba7650f404af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
aravindsv 0:ba7650f404af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
aravindsv 0:ba7650f404af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
aravindsv 0:ba7650f404af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
aravindsv 0:ba7650f404af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
aravindsv 0:ba7650f404af 34 POSSIBILITY OF SUCH DAMAGE.
aravindsv 0:ba7650f404af 35 ---------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 36
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 #ifndef __CORE_CMFUNC_H
aravindsv 0:ba7650f404af 39 #define __CORE_CMFUNC_H
aravindsv 0:ba7650f404af 40
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42 /* ########################### Core Function Access ########################### */
aravindsv 0:ba7650f404af 43 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
aravindsv 0:ba7650f404af 45 @{
aravindsv 0:ba7650f404af 46 */
aravindsv 0:ba7650f404af 47
aravindsv 0:ba7650f404af 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
aravindsv 0:ba7650f404af 49 /* ARM armcc specific functions */
aravindsv 0:ba7650f404af 50
aravindsv 0:ba7650f404af 51 #if (__ARMCC_VERSION < 400677)
aravindsv 0:ba7650f404af 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
aravindsv 0:ba7650f404af 53 #endif
aravindsv 0:ba7650f404af 54
aravindsv 0:ba7650f404af 55 /* intrinsic void __enable_irq(); */
aravindsv 0:ba7650f404af 56 /* intrinsic void __disable_irq(); */
aravindsv 0:ba7650f404af 57
aravindsv 0:ba7650f404af 58 /** \brief Get Control Register
aravindsv 0:ba7650f404af 59
aravindsv 0:ba7650f404af 60 This function returns the content of the Control Register.
aravindsv 0:ba7650f404af 61
aravindsv 0:ba7650f404af 62 \return Control Register value
aravindsv 0:ba7650f404af 63 */
aravindsv 0:ba7650f404af 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
aravindsv 0:ba7650f404af 65 {
aravindsv 0:ba7650f404af 66 register uint32_t __regControl __ASM("control");
aravindsv 0:ba7650f404af 67 return(__regControl);
aravindsv 0:ba7650f404af 68 }
aravindsv 0:ba7650f404af 69
aravindsv 0:ba7650f404af 70
aravindsv 0:ba7650f404af 71 /** \brief Set Control Register
aravindsv 0:ba7650f404af 72
aravindsv 0:ba7650f404af 73 This function writes the given value to the Control Register.
aravindsv 0:ba7650f404af 74
aravindsv 0:ba7650f404af 75 \param [in] control Control Register value to set
aravindsv 0:ba7650f404af 76 */
aravindsv 0:ba7650f404af 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
aravindsv 0:ba7650f404af 78 {
aravindsv 0:ba7650f404af 79 register uint32_t __regControl __ASM("control");
aravindsv 0:ba7650f404af 80 __regControl = control;
aravindsv 0:ba7650f404af 81 }
aravindsv 0:ba7650f404af 82
aravindsv 0:ba7650f404af 83
aravindsv 0:ba7650f404af 84 /** \brief Get IPSR Register
aravindsv 0:ba7650f404af 85
aravindsv 0:ba7650f404af 86 This function returns the content of the IPSR Register.
aravindsv 0:ba7650f404af 87
aravindsv 0:ba7650f404af 88 \return IPSR Register value
aravindsv 0:ba7650f404af 89 */
aravindsv 0:ba7650f404af 90 __STATIC_INLINE uint32_t __get_IPSR(void)
aravindsv 0:ba7650f404af 91 {
aravindsv 0:ba7650f404af 92 register uint32_t __regIPSR __ASM("ipsr");
aravindsv 0:ba7650f404af 93 return(__regIPSR);
aravindsv 0:ba7650f404af 94 }
aravindsv 0:ba7650f404af 95
aravindsv 0:ba7650f404af 96
aravindsv 0:ba7650f404af 97 /** \brief Get APSR Register
aravindsv 0:ba7650f404af 98
aravindsv 0:ba7650f404af 99 This function returns the content of the APSR Register.
aravindsv 0:ba7650f404af 100
aravindsv 0:ba7650f404af 101 \return APSR Register value
aravindsv 0:ba7650f404af 102 */
aravindsv 0:ba7650f404af 103 __STATIC_INLINE uint32_t __get_APSR(void)
aravindsv 0:ba7650f404af 104 {
aravindsv 0:ba7650f404af 105 register uint32_t __regAPSR __ASM("apsr");
aravindsv 0:ba7650f404af 106 return(__regAPSR);
aravindsv 0:ba7650f404af 107 }
aravindsv 0:ba7650f404af 108
aravindsv 0:ba7650f404af 109
aravindsv 0:ba7650f404af 110 /** \brief Get xPSR Register
aravindsv 0:ba7650f404af 111
aravindsv 0:ba7650f404af 112 This function returns the content of the xPSR Register.
aravindsv 0:ba7650f404af 113
aravindsv 0:ba7650f404af 114 \return xPSR Register value
aravindsv 0:ba7650f404af 115 */
aravindsv 0:ba7650f404af 116 __STATIC_INLINE uint32_t __get_xPSR(void)
aravindsv 0:ba7650f404af 117 {
aravindsv 0:ba7650f404af 118 register uint32_t __regXPSR __ASM("xpsr");
aravindsv 0:ba7650f404af 119 return(__regXPSR);
aravindsv 0:ba7650f404af 120 }
aravindsv 0:ba7650f404af 121
aravindsv 0:ba7650f404af 122
aravindsv 0:ba7650f404af 123 /** \brief Get Process Stack Pointer
aravindsv 0:ba7650f404af 124
aravindsv 0:ba7650f404af 125 This function returns the current value of the Process Stack Pointer (PSP).
aravindsv 0:ba7650f404af 126
aravindsv 0:ba7650f404af 127 \return PSP Register value
aravindsv 0:ba7650f404af 128 */
aravindsv 0:ba7650f404af 129 __STATIC_INLINE uint32_t __get_PSP(void)
aravindsv 0:ba7650f404af 130 {
aravindsv 0:ba7650f404af 131 register uint32_t __regProcessStackPointer __ASM("psp");
aravindsv 0:ba7650f404af 132 return(__regProcessStackPointer);
aravindsv 0:ba7650f404af 133 }
aravindsv 0:ba7650f404af 134
aravindsv 0:ba7650f404af 135
aravindsv 0:ba7650f404af 136 /** \brief Set Process Stack Pointer
aravindsv 0:ba7650f404af 137
aravindsv 0:ba7650f404af 138 This function assigns the given value to the Process Stack Pointer (PSP).
aravindsv 0:ba7650f404af 139
aravindsv 0:ba7650f404af 140 \param [in] topOfProcStack Process Stack Pointer value to set
aravindsv 0:ba7650f404af 141 */
aravindsv 0:ba7650f404af 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
aravindsv 0:ba7650f404af 143 {
aravindsv 0:ba7650f404af 144 register uint32_t __regProcessStackPointer __ASM("psp");
aravindsv 0:ba7650f404af 145 __regProcessStackPointer = topOfProcStack;
aravindsv 0:ba7650f404af 146 }
aravindsv 0:ba7650f404af 147
aravindsv 0:ba7650f404af 148
aravindsv 0:ba7650f404af 149 /** \brief Get Main Stack Pointer
aravindsv 0:ba7650f404af 150
aravindsv 0:ba7650f404af 151 This function returns the current value of the Main Stack Pointer (MSP).
aravindsv 0:ba7650f404af 152
aravindsv 0:ba7650f404af 153 \return MSP Register value
aravindsv 0:ba7650f404af 154 */
aravindsv 0:ba7650f404af 155 __STATIC_INLINE uint32_t __get_MSP(void)
aravindsv 0:ba7650f404af 156 {
aravindsv 0:ba7650f404af 157 register uint32_t __regMainStackPointer __ASM("msp");
aravindsv 0:ba7650f404af 158 return(__regMainStackPointer);
aravindsv 0:ba7650f404af 159 }
aravindsv 0:ba7650f404af 160
aravindsv 0:ba7650f404af 161
aravindsv 0:ba7650f404af 162 /** \brief Set Main Stack Pointer
aravindsv 0:ba7650f404af 163
aravindsv 0:ba7650f404af 164 This function assigns the given value to the Main Stack Pointer (MSP).
aravindsv 0:ba7650f404af 165
aravindsv 0:ba7650f404af 166 \param [in] topOfMainStack Main Stack Pointer value to set
aravindsv 0:ba7650f404af 167 */
aravindsv 0:ba7650f404af 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
aravindsv 0:ba7650f404af 169 {
aravindsv 0:ba7650f404af 170 register uint32_t __regMainStackPointer __ASM("msp");
aravindsv 0:ba7650f404af 171 __regMainStackPointer = topOfMainStack;
aravindsv 0:ba7650f404af 172 }
aravindsv 0:ba7650f404af 173
aravindsv 0:ba7650f404af 174
aravindsv 0:ba7650f404af 175 /** \brief Get Priority Mask
aravindsv 0:ba7650f404af 176
aravindsv 0:ba7650f404af 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
aravindsv 0:ba7650f404af 178
aravindsv 0:ba7650f404af 179 \return Priority Mask value
aravindsv 0:ba7650f404af 180 */
aravindsv 0:ba7650f404af 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
aravindsv 0:ba7650f404af 182 {
aravindsv 0:ba7650f404af 183 register uint32_t __regPriMask __ASM("primask");
aravindsv 0:ba7650f404af 184 return(__regPriMask);
aravindsv 0:ba7650f404af 185 }
aravindsv 0:ba7650f404af 186
aravindsv 0:ba7650f404af 187
aravindsv 0:ba7650f404af 188 /** \brief Set Priority Mask
aravindsv 0:ba7650f404af 189
aravindsv 0:ba7650f404af 190 This function assigns the given value to the Priority Mask Register.
aravindsv 0:ba7650f404af 191
aravindsv 0:ba7650f404af 192 \param [in] priMask Priority Mask
aravindsv 0:ba7650f404af 193 */
aravindsv 0:ba7650f404af 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
aravindsv 0:ba7650f404af 195 {
aravindsv 0:ba7650f404af 196 register uint32_t __regPriMask __ASM("primask");
aravindsv 0:ba7650f404af 197 __regPriMask = (priMask);
aravindsv 0:ba7650f404af 198 }
aravindsv 0:ba7650f404af 199
aravindsv 0:ba7650f404af 200
aravindsv 0:ba7650f404af 201 #if (__CORTEX_M >= 0x03)
aravindsv 0:ba7650f404af 202
aravindsv 0:ba7650f404af 203 /** \brief Enable FIQ
aravindsv 0:ba7650f404af 204
aravindsv 0:ba7650f404af 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
aravindsv 0:ba7650f404af 206 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 207 */
aravindsv 0:ba7650f404af 208 #define __enable_fault_irq __enable_fiq
aravindsv 0:ba7650f404af 209
aravindsv 0:ba7650f404af 210
aravindsv 0:ba7650f404af 211 /** \brief Disable FIQ
aravindsv 0:ba7650f404af 212
aravindsv 0:ba7650f404af 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
aravindsv 0:ba7650f404af 214 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 215 */
aravindsv 0:ba7650f404af 216 #define __disable_fault_irq __disable_fiq
aravindsv 0:ba7650f404af 217
aravindsv 0:ba7650f404af 218
aravindsv 0:ba7650f404af 219 /** \brief Get Base Priority
aravindsv 0:ba7650f404af 220
aravindsv 0:ba7650f404af 221 This function returns the current value of the Base Priority register.
aravindsv 0:ba7650f404af 222
aravindsv 0:ba7650f404af 223 \return Base Priority register value
aravindsv 0:ba7650f404af 224 */
aravindsv 0:ba7650f404af 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
aravindsv 0:ba7650f404af 226 {
aravindsv 0:ba7650f404af 227 register uint32_t __regBasePri __ASM("basepri");
aravindsv 0:ba7650f404af 228 return(__regBasePri);
aravindsv 0:ba7650f404af 229 }
aravindsv 0:ba7650f404af 230
aravindsv 0:ba7650f404af 231
aravindsv 0:ba7650f404af 232 /** \brief Set Base Priority
aravindsv 0:ba7650f404af 233
aravindsv 0:ba7650f404af 234 This function assigns the given value to the Base Priority register.
aravindsv 0:ba7650f404af 235
aravindsv 0:ba7650f404af 236 \param [in] basePri Base Priority value to set
aravindsv 0:ba7650f404af 237 */
aravindsv 0:ba7650f404af 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
aravindsv 0:ba7650f404af 239 {
aravindsv 0:ba7650f404af 240 register uint32_t __regBasePri __ASM("basepri");
aravindsv 0:ba7650f404af 241 __regBasePri = (basePri & 0xff);
aravindsv 0:ba7650f404af 242 }
aravindsv 0:ba7650f404af 243
aravindsv 0:ba7650f404af 244
aravindsv 0:ba7650f404af 245 /** \brief Get Fault Mask
aravindsv 0:ba7650f404af 246
aravindsv 0:ba7650f404af 247 This function returns the current value of the Fault Mask register.
aravindsv 0:ba7650f404af 248
aravindsv 0:ba7650f404af 249 \return Fault Mask register value
aravindsv 0:ba7650f404af 250 */
aravindsv 0:ba7650f404af 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
aravindsv 0:ba7650f404af 252 {
aravindsv 0:ba7650f404af 253 register uint32_t __regFaultMask __ASM("faultmask");
aravindsv 0:ba7650f404af 254 return(__regFaultMask);
aravindsv 0:ba7650f404af 255 }
aravindsv 0:ba7650f404af 256
aravindsv 0:ba7650f404af 257
aravindsv 0:ba7650f404af 258 /** \brief Set Fault Mask
aravindsv 0:ba7650f404af 259
aravindsv 0:ba7650f404af 260 This function assigns the given value to the Fault Mask register.
aravindsv 0:ba7650f404af 261
aravindsv 0:ba7650f404af 262 \param [in] faultMask Fault Mask value to set
aravindsv 0:ba7650f404af 263 */
aravindsv 0:ba7650f404af 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
aravindsv 0:ba7650f404af 265 {
aravindsv 0:ba7650f404af 266 register uint32_t __regFaultMask __ASM("faultmask");
aravindsv 0:ba7650f404af 267 __regFaultMask = (faultMask & (uint32_t)1);
aravindsv 0:ba7650f404af 268 }
aravindsv 0:ba7650f404af 269
aravindsv 0:ba7650f404af 270 #endif /* (__CORTEX_M >= 0x03) */
aravindsv 0:ba7650f404af 271
aravindsv 0:ba7650f404af 272
aravindsv 0:ba7650f404af 273 #if (__CORTEX_M == 0x04)
aravindsv 0:ba7650f404af 274
aravindsv 0:ba7650f404af 275 /** \brief Get FPSCR
aravindsv 0:ba7650f404af 276
aravindsv 0:ba7650f404af 277 This function returns the current value of the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 278
aravindsv 0:ba7650f404af 279 \return Floating Point Status/Control register value
aravindsv 0:ba7650f404af 280 */
aravindsv 0:ba7650f404af 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
aravindsv 0:ba7650f404af 282 {
aravindsv 0:ba7650f404af 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 284 register uint32_t __regfpscr __ASM("fpscr");
aravindsv 0:ba7650f404af 285 return(__regfpscr);
aravindsv 0:ba7650f404af 286 #else
aravindsv 0:ba7650f404af 287 return(0);
aravindsv 0:ba7650f404af 288 #endif
aravindsv 0:ba7650f404af 289 }
aravindsv 0:ba7650f404af 290
aravindsv 0:ba7650f404af 291
aravindsv 0:ba7650f404af 292 /** \brief Set FPSCR
aravindsv 0:ba7650f404af 293
aravindsv 0:ba7650f404af 294 This function assigns the given value to the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 295
aravindsv 0:ba7650f404af 296 \param [in] fpscr Floating Point Status/Control value to set
aravindsv 0:ba7650f404af 297 */
aravindsv 0:ba7650f404af 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
aravindsv 0:ba7650f404af 299 {
aravindsv 0:ba7650f404af 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 301 register uint32_t __regfpscr __ASM("fpscr");
aravindsv 0:ba7650f404af 302 __regfpscr = (fpscr);
aravindsv 0:ba7650f404af 303 #endif
aravindsv 0:ba7650f404af 304 }
aravindsv 0:ba7650f404af 305
aravindsv 0:ba7650f404af 306 #endif /* (__CORTEX_M == 0x04) */
aravindsv 0:ba7650f404af 307
aravindsv 0:ba7650f404af 308
aravindsv 0:ba7650f404af 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
aravindsv 0:ba7650f404af 310 /* IAR iccarm specific functions */
aravindsv 0:ba7650f404af 311
aravindsv 0:ba7650f404af 312 #include <cmsis_iar.h>
aravindsv 0:ba7650f404af 313
aravindsv 0:ba7650f404af 314
aravindsv 0:ba7650f404af 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
aravindsv 0:ba7650f404af 316 /* TI CCS specific functions */
aravindsv 0:ba7650f404af 317
aravindsv 0:ba7650f404af 318 #include <cmsis_ccs.h>
aravindsv 0:ba7650f404af 319
aravindsv 0:ba7650f404af 320
aravindsv 0:ba7650f404af 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
aravindsv 0:ba7650f404af 322 /* GNU gcc specific functions */
aravindsv 0:ba7650f404af 323
aravindsv 0:ba7650f404af 324 /** \brief Enable IRQ Interrupts
aravindsv 0:ba7650f404af 325
aravindsv 0:ba7650f404af 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
aravindsv 0:ba7650f404af 327 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 328 */
aravindsv 0:ba7650f404af 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
aravindsv 0:ba7650f404af 330 {
aravindsv 0:ba7650f404af 331 __ASM volatile ("cpsie i" : : : "memory");
aravindsv 0:ba7650f404af 332 }
aravindsv 0:ba7650f404af 333
aravindsv 0:ba7650f404af 334
aravindsv 0:ba7650f404af 335 /** \brief Disable IRQ Interrupts
aravindsv 0:ba7650f404af 336
aravindsv 0:ba7650f404af 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
aravindsv 0:ba7650f404af 338 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 339 */
aravindsv 0:ba7650f404af 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
aravindsv 0:ba7650f404af 341 {
aravindsv 0:ba7650f404af 342 __ASM volatile ("cpsid i" : : : "memory");
aravindsv 0:ba7650f404af 343 }
aravindsv 0:ba7650f404af 344
aravindsv 0:ba7650f404af 345
aravindsv 0:ba7650f404af 346 /** \brief Get Control Register
aravindsv 0:ba7650f404af 347
aravindsv 0:ba7650f404af 348 This function returns the content of the Control Register.
aravindsv 0:ba7650f404af 349
aravindsv 0:ba7650f404af 350 \return Control Register value
aravindsv 0:ba7650f404af 351 */
aravindsv 0:ba7650f404af 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
aravindsv 0:ba7650f404af 353 {
aravindsv 0:ba7650f404af 354 uint32_t result;
aravindsv 0:ba7650f404af 355
aravindsv 0:ba7650f404af 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
aravindsv 0:ba7650f404af 357 return(result);
aravindsv 0:ba7650f404af 358 }
aravindsv 0:ba7650f404af 359
aravindsv 0:ba7650f404af 360
aravindsv 0:ba7650f404af 361 /** \brief Set Control Register
aravindsv 0:ba7650f404af 362
aravindsv 0:ba7650f404af 363 This function writes the given value to the Control Register.
aravindsv 0:ba7650f404af 364
aravindsv 0:ba7650f404af 365 \param [in] control Control Register value to set
aravindsv 0:ba7650f404af 366 */
aravindsv 0:ba7650f404af 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
aravindsv 0:ba7650f404af 368 {
aravindsv 0:ba7650f404af 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
aravindsv 0:ba7650f404af 370 }
aravindsv 0:ba7650f404af 371
aravindsv 0:ba7650f404af 372
aravindsv 0:ba7650f404af 373 /** \brief Get IPSR Register
aravindsv 0:ba7650f404af 374
aravindsv 0:ba7650f404af 375 This function returns the content of the IPSR Register.
aravindsv 0:ba7650f404af 376
aravindsv 0:ba7650f404af 377 \return IPSR Register value
aravindsv 0:ba7650f404af 378 */
aravindsv 0:ba7650f404af 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
aravindsv 0:ba7650f404af 380 {
aravindsv 0:ba7650f404af 381 uint32_t result;
aravindsv 0:ba7650f404af 382
aravindsv 0:ba7650f404af 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
aravindsv 0:ba7650f404af 384 return(result);
aravindsv 0:ba7650f404af 385 }
aravindsv 0:ba7650f404af 386
aravindsv 0:ba7650f404af 387
aravindsv 0:ba7650f404af 388 /** \brief Get APSR Register
aravindsv 0:ba7650f404af 389
aravindsv 0:ba7650f404af 390 This function returns the content of the APSR Register.
aravindsv 0:ba7650f404af 391
aravindsv 0:ba7650f404af 392 \return APSR Register value
aravindsv 0:ba7650f404af 393 */
aravindsv 0:ba7650f404af 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
aravindsv 0:ba7650f404af 395 {
aravindsv 0:ba7650f404af 396 uint32_t result;
aravindsv 0:ba7650f404af 397
aravindsv 0:ba7650f404af 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
aravindsv 0:ba7650f404af 399 return(result);
aravindsv 0:ba7650f404af 400 }
aravindsv 0:ba7650f404af 401
aravindsv 0:ba7650f404af 402
aravindsv 0:ba7650f404af 403 /** \brief Get xPSR Register
aravindsv 0:ba7650f404af 404
aravindsv 0:ba7650f404af 405 This function returns the content of the xPSR Register.
aravindsv 0:ba7650f404af 406
aravindsv 0:ba7650f404af 407 \return xPSR Register value
aravindsv 0:ba7650f404af 408 */
aravindsv 0:ba7650f404af 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
aravindsv 0:ba7650f404af 410 {
aravindsv 0:ba7650f404af 411 uint32_t result;
aravindsv 0:ba7650f404af 412
aravindsv 0:ba7650f404af 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
aravindsv 0:ba7650f404af 414 return(result);
aravindsv 0:ba7650f404af 415 }
aravindsv 0:ba7650f404af 416
aravindsv 0:ba7650f404af 417
aravindsv 0:ba7650f404af 418 /** \brief Get Process Stack Pointer
aravindsv 0:ba7650f404af 419
aravindsv 0:ba7650f404af 420 This function returns the current value of the Process Stack Pointer (PSP).
aravindsv 0:ba7650f404af 421
aravindsv 0:ba7650f404af 422 \return PSP Register value
aravindsv 0:ba7650f404af 423 */
aravindsv 0:ba7650f404af 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
aravindsv 0:ba7650f404af 425 {
aravindsv 0:ba7650f404af 426 register uint32_t result;
aravindsv 0:ba7650f404af 427
aravindsv 0:ba7650f404af 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
aravindsv 0:ba7650f404af 429 return(result);
aravindsv 0:ba7650f404af 430 }
aravindsv 0:ba7650f404af 431
aravindsv 0:ba7650f404af 432
aravindsv 0:ba7650f404af 433 /** \brief Set Process Stack Pointer
aravindsv 0:ba7650f404af 434
aravindsv 0:ba7650f404af 435 This function assigns the given value to the Process Stack Pointer (PSP).
aravindsv 0:ba7650f404af 436
aravindsv 0:ba7650f404af 437 \param [in] topOfProcStack Process Stack Pointer value to set
aravindsv 0:ba7650f404af 438 */
aravindsv 0:ba7650f404af 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
aravindsv 0:ba7650f404af 440 {
aravindsv 0:ba7650f404af 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
aravindsv 0:ba7650f404af 442 }
aravindsv 0:ba7650f404af 443
aravindsv 0:ba7650f404af 444
aravindsv 0:ba7650f404af 445 /** \brief Get Main Stack Pointer
aravindsv 0:ba7650f404af 446
aravindsv 0:ba7650f404af 447 This function returns the current value of the Main Stack Pointer (MSP).
aravindsv 0:ba7650f404af 448
aravindsv 0:ba7650f404af 449 \return MSP Register value
aravindsv 0:ba7650f404af 450 */
aravindsv 0:ba7650f404af 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
aravindsv 0:ba7650f404af 452 {
aravindsv 0:ba7650f404af 453 register uint32_t result;
aravindsv 0:ba7650f404af 454
aravindsv 0:ba7650f404af 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
aravindsv 0:ba7650f404af 456 return(result);
aravindsv 0:ba7650f404af 457 }
aravindsv 0:ba7650f404af 458
aravindsv 0:ba7650f404af 459
aravindsv 0:ba7650f404af 460 /** \brief Set Main Stack Pointer
aravindsv 0:ba7650f404af 461
aravindsv 0:ba7650f404af 462 This function assigns the given value to the Main Stack Pointer (MSP).
aravindsv 0:ba7650f404af 463
aravindsv 0:ba7650f404af 464 \param [in] topOfMainStack Main Stack Pointer value to set
aravindsv 0:ba7650f404af 465 */
aravindsv 0:ba7650f404af 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
aravindsv 0:ba7650f404af 467 {
aravindsv 0:ba7650f404af 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
aravindsv 0:ba7650f404af 469 }
aravindsv 0:ba7650f404af 470
aravindsv 0:ba7650f404af 471
aravindsv 0:ba7650f404af 472 /** \brief Get Priority Mask
aravindsv 0:ba7650f404af 473
aravindsv 0:ba7650f404af 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
aravindsv 0:ba7650f404af 475
aravindsv 0:ba7650f404af 476 \return Priority Mask value
aravindsv 0:ba7650f404af 477 */
aravindsv 0:ba7650f404af 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
aravindsv 0:ba7650f404af 479 {
aravindsv 0:ba7650f404af 480 uint32_t result;
aravindsv 0:ba7650f404af 481
aravindsv 0:ba7650f404af 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
aravindsv 0:ba7650f404af 483 return(result);
aravindsv 0:ba7650f404af 484 }
aravindsv 0:ba7650f404af 485
aravindsv 0:ba7650f404af 486
aravindsv 0:ba7650f404af 487 /** \brief Set Priority Mask
aravindsv 0:ba7650f404af 488
aravindsv 0:ba7650f404af 489 This function assigns the given value to the Priority Mask Register.
aravindsv 0:ba7650f404af 490
aravindsv 0:ba7650f404af 491 \param [in] priMask Priority Mask
aravindsv 0:ba7650f404af 492 */
aravindsv 0:ba7650f404af 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
aravindsv 0:ba7650f404af 494 {
aravindsv 0:ba7650f404af 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
aravindsv 0:ba7650f404af 496 }
aravindsv 0:ba7650f404af 497
aravindsv 0:ba7650f404af 498
aravindsv 0:ba7650f404af 499 #if (__CORTEX_M >= 0x03)
aravindsv 0:ba7650f404af 500
aravindsv 0:ba7650f404af 501 /** \brief Enable FIQ
aravindsv 0:ba7650f404af 502
aravindsv 0:ba7650f404af 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
aravindsv 0:ba7650f404af 504 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 505 */
aravindsv 0:ba7650f404af 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
aravindsv 0:ba7650f404af 507 {
aravindsv 0:ba7650f404af 508 __ASM volatile ("cpsie f" : : : "memory");
aravindsv 0:ba7650f404af 509 }
aravindsv 0:ba7650f404af 510
aravindsv 0:ba7650f404af 511
aravindsv 0:ba7650f404af 512 /** \brief Disable FIQ
aravindsv 0:ba7650f404af 513
aravindsv 0:ba7650f404af 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
aravindsv 0:ba7650f404af 515 Can only be executed in Privileged modes.
aravindsv 0:ba7650f404af 516 */
aravindsv 0:ba7650f404af 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
aravindsv 0:ba7650f404af 518 {
aravindsv 0:ba7650f404af 519 __ASM volatile ("cpsid f" : : : "memory");
aravindsv 0:ba7650f404af 520 }
aravindsv 0:ba7650f404af 521
aravindsv 0:ba7650f404af 522
aravindsv 0:ba7650f404af 523 /** \brief Get Base Priority
aravindsv 0:ba7650f404af 524
aravindsv 0:ba7650f404af 525 This function returns the current value of the Base Priority register.
aravindsv 0:ba7650f404af 526
aravindsv 0:ba7650f404af 527 \return Base Priority register value
aravindsv 0:ba7650f404af 528 */
aravindsv 0:ba7650f404af 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
aravindsv 0:ba7650f404af 530 {
aravindsv 0:ba7650f404af 531 uint32_t result;
aravindsv 0:ba7650f404af 532
aravindsv 0:ba7650f404af 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
aravindsv 0:ba7650f404af 534 return(result);
aravindsv 0:ba7650f404af 535 }
aravindsv 0:ba7650f404af 536
aravindsv 0:ba7650f404af 537
aravindsv 0:ba7650f404af 538 /** \brief Set Base Priority
aravindsv 0:ba7650f404af 539
aravindsv 0:ba7650f404af 540 This function assigns the given value to the Base Priority register.
aravindsv 0:ba7650f404af 541
aravindsv 0:ba7650f404af 542 \param [in] basePri Base Priority value to set
aravindsv 0:ba7650f404af 543 */
aravindsv 0:ba7650f404af 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
aravindsv 0:ba7650f404af 545 {
aravindsv 0:ba7650f404af 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
aravindsv 0:ba7650f404af 547 }
aravindsv 0:ba7650f404af 548
aravindsv 0:ba7650f404af 549
aravindsv 0:ba7650f404af 550 /** \brief Get Fault Mask
aravindsv 0:ba7650f404af 551
aravindsv 0:ba7650f404af 552 This function returns the current value of the Fault Mask register.
aravindsv 0:ba7650f404af 553
aravindsv 0:ba7650f404af 554 \return Fault Mask register value
aravindsv 0:ba7650f404af 555 */
aravindsv 0:ba7650f404af 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
aravindsv 0:ba7650f404af 557 {
aravindsv 0:ba7650f404af 558 uint32_t result;
aravindsv 0:ba7650f404af 559
aravindsv 0:ba7650f404af 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
aravindsv 0:ba7650f404af 561 return(result);
aravindsv 0:ba7650f404af 562 }
aravindsv 0:ba7650f404af 563
aravindsv 0:ba7650f404af 564
aravindsv 0:ba7650f404af 565 /** \brief Set Fault Mask
aravindsv 0:ba7650f404af 566
aravindsv 0:ba7650f404af 567 This function assigns the given value to the Fault Mask register.
aravindsv 0:ba7650f404af 568
aravindsv 0:ba7650f404af 569 \param [in] faultMask Fault Mask value to set
aravindsv 0:ba7650f404af 570 */
aravindsv 0:ba7650f404af 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
aravindsv 0:ba7650f404af 572 {
aravindsv 0:ba7650f404af 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
aravindsv 0:ba7650f404af 574 }
aravindsv 0:ba7650f404af 575
aravindsv 0:ba7650f404af 576 #endif /* (__CORTEX_M >= 0x03) */
aravindsv 0:ba7650f404af 577
aravindsv 0:ba7650f404af 578
aravindsv 0:ba7650f404af 579 #if (__CORTEX_M == 0x04)
aravindsv 0:ba7650f404af 580
aravindsv 0:ba7650f404af 581 /** \brief Get FPSCR
aravindsv 0:ba7650f404af 582
aravindsv 0:ba7650f404af 583 This function returns the current value of the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 584
aravindsv 0:ba7650f404af 585 \return Floating Point Status/Control register value
aravindsv 0:ba7650f404af 586 */
aravindsv 0:ba7650f404af 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
aravindsv 0:ba7650f404af 588 {
aravindsv 0:ba7650f404af 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 590 uint32_t result;
aravindsv 0:ba7650f404af 591
aravindsv 0:ba7650f404af 592 /* Empty asm statement works as a scheduling barrier */
aravindsv 0:ba7650f404af 593 __ASM volatile ("");
aravindsv 0:ba7650f404af 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
aravindsv 0:ba7650f404af 595 __ASM volatile ("");
aravindsv 0:ba7650f404af 596 return(result);
aravindsv 0:ba7650f404af 597 #else
aravindsv 0:ba7650f404af 598 return(0);
aravindsv 0:ba7650f404af 599 #endif
aravindsv 0:ba7650f404af 600 }
aravindsv 0:ba7650f404af 601
aravindsv 0:ba7650f404af 602
aravindsv 0:ba7650f404af 603 /** \brief Set FPSCR
aravindsv 0:ba7650f404af 604
aravindsv 0:ba7650f404af 605 This function assigns the given value to the Floating Point Status/Control register.
aravindsv 0:ba7650f404af 606
aravindsv 0:ba7650f404af 607 \param [in] fpscr Floating Point Status/Control value to set
aravindsv 0:ba7650f404af 608 */
aravindsv 0:ba7650f404af 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
aravindsv 0:ba7650f404af 610 {
aravindsv 0:ba7650f404af 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
aravindsv 0:ba7650f404af 612 /* Empty asm statement works as a scheduling barrier */
aravindsv 0:ba7650f404af 613 __ASM volatile ("");
aravindsv 0:ba7650f404af 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
aravindsv 0:ba7650f404af 615 __ASM volatile ("");
aravindsv 0:ba7650f404af 616 #endif
aravindsv 0:ba7650f404af 617 }
aravindsv 0:ba7650f404af 618
aravindsv 0:ba7650f404af 619 #endif /* (__CORTEX_M == 0x04) */
aravindsv 0:ba7650f404af 620
aravindsv 0:ba7650f404af 621
aravindsv 0:ba7650f404af 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
aravindsv 0:ba7650f404af 623 /* TASKING carm specific functions */
aravindsv 0:ba7650f404af 624
aravindsv 0:ba7650f404af 625 /*
aravindsv 0:ba7650f404af 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
aravindsv 0:ba7650f404af 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
aravindsv 0:ba7650f404af 628 * Including the CMSIS ones.
aravindsv 0:ba7650f404af 629 */
aravindsv 0:ba7650f404af 630
aravindsv 0:ba7650f404af 631 #endif
aravindsv 0:ba7650f404af 632
aravindsv 0:ba7650f404af 633 /*@} end of CMSIS_Core_RegAccFunctions */
aravindsv 0:ba7650f404af 634
aravindsv 0:ba7650f404af 635
aravindsv 0:ba7650f404af 636 #endif /* __CORE_CMFUNC_H */