Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/core_cm0plus.h@0:ba7650f404af, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 02:26:59 2015 +0000
Revision:
0:ba7650f404af
Reduced HSE_STARTUP_TIMEOUT to 500 ms, fixed some compiler warnings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**************************************************************************//**
aravindsv 0:ba7650f404af 2 * @file core_cm0plus.h
aravindsv 0:ba7650f404af 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
aravindsv 0:ba7650f404af 4 * @version V3.20
aravindsv 0:ba7650f404af 5 * @date 25. February 2013
aravindsv 0:ba7650f404af 6 *
aravindsv 0:ba7650f404af 7 * @note
aravindsv 0:ba7650f404af 8 *
aravindsv 0:ba7650f404af 9 ******************************************************************************/
aravindsv 0:ba7650f404af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
aravindsv 0:ba7650f404af 11
aravindsv 0:ba7650f404af 12 All rights reserved.
aravindsv 0:ba7650f404af 13 Redistribution and use in source and binary forms, with or without
aravindsv 0:ba7650f404af 14 modification, are permitted provided that the following conditions are met:
aravindsv 0:ba7650f404af 15 - Redistributions of source code must retain the above copyright
aravindsv 0:ba7650f404af 16 notice, this list of conditions and the following disclaimer.
aravindsv 0:ba7650f404af 17 - Redistributions in binary form must reproduce the above copyright
aravindsv 0:ba7650f404af 18 notice, this list of conditions and the following disclaimer in the
aravindsv 0:ba7650f404af 19 documentation and/or other materials provided with the distribution.
aravindsv 0:ba7650f404af 20 - Neither the name of ARM nor the names of its contributors may be used
aravindsv 0:ba7650f404af 21 to endorse or promote products derived from this software without
aravindsv 0:ba7650f404af 22 specific prior written permission.
aravindsv 0:ba7650f404af 23 *
aravindsv 0:ba7650f404af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
aravindsv 0:ba7650f404af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
aravindsv 0:ba7650f404af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
aravindsv 0:ba7650f404af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
aravindsv 0:ba7650f404af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
aravindsv 0:ba7650f404af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
aravindsv 0:ba7650f404af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
aravindsv 0:ba7650f404af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
aravindsv 0:ba7650f404af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
aravindsv 0:ba7650f404af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
aravindsv 0:ba7650f404af 34 POSSIBILITY OF SUCH DAMAGE.
aravindsv 0:ba7650f404af 35 ---------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 36
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 #if defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 39 #pragma system_include /* treat file as system include file for MISRA check */
aravindsv 0:ba7650f404af 40 #endif
aravindsv 0:ba7650f404af 41
aravindsv 0:ba7650f404af 42 #ifdef __cplusplus
aravindsv 0:ba7650f404af 43 extern "C" {
aravindsv 0:ba7650f404af 44 #endif
aravindsv 0:ba7650f404af 45
aravindsv 0:ba7650f404af 46 #ifndef __CORE_CM0PLUS_H_GENERIC
aravindsv 0:ba7650f404af 47 #define __CORE_CM0PLUS_H_GENERIC
aravindsv 0:ba7650f404af 48
aravindsv 0:ba7650f404af 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
aravindsv 0:ba7650f404af 50 CMSIS violates the following MISRA-C:2004 rules:
aravindsv 0:ba7650f404af 51
aravindsv 0:ba7650f404af 52 \li Required Rule 8.5, object/function definition in header file.<br>
aravindsv 0:ba7650f404af 53 Function definitions in header files are used to allow 'inlining'.
aravindsv 0:ba7650f404af 54
aravindsv 0:ba7650f404af 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
aravindsv 0:ba7650f404af 56 Unions are used for effective representation of core registers.
aravindsv 0:ba7650f404af 57
aravindsv 0:ba7650f404af 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
aravindsv 0:ba7650f404af 59 Function-like macros are used to allow more efficient code.
aravindsv 0:ba7650f404af 60 */
aravindsv 0:ba7650f404af 61
aravindsv 0:ba7650f404af 62
aravindsv 0:ba7650f404af 63 /*******************************************************************************
aravindsv 0:ba7650f404af 64 * CMSIS definitions
aravindsv 0:ba7650f404af 65 ******************************************************************************/
aravindsv 0:ba7650f404af 66 /** \ingroup Cortex-M0+
aravindsv 0:ba7650f404af 67 @{
aravindsv 0:ba7650f404af 68 */
aravindsv 0:ba7650f404af 69
aravindsv 0:ba7650f404af 70 /* CMSIS CM0P definitions */
aravindsv 0:ba7650f404af 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
aravindsv 0:ba7650f404af 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
aravindsv 0:ba7650f404af 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
aravindsv 0:ba7650f404af 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
aravindsv 0:ba7650f404af 75
aravindsv 0:ba7650f404af 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
aravindsv 0:ba7650f404af 77
aravindsv 0:ba7650f404af 78
aravindsv 0:ba7650f404af 79 #if defined ( __CC_ARM )
aravindsv 0:ba7650f404af 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
aravindsv 0:ba7650f404af 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
aravindsv 0:ba7650f404af 82 #define __STATIC_INLINE static __inline
aravindsv 0:ba7650f404af 83
aravindsv 0:ba7650f404af 84 #elif defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
aravindsv 0:ba7650f404af 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
aravindsv 0:ba7650f404af 87 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 88
aravindsv 0:ba7650f404af 89 #elif defined ( __GNUC__ )
aravindsv 0:ba7650f404af 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
aravindsv 0:ba7650f404af 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
aravindsv 0:ba7650f404af 92 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 93
aravindsv 0:ba7650f404af 94 #elif defined ( __TASKING__ )
aravindsv 0:ba7650f404af 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
aravindsv 0:ba7650f404af 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
aravindsv 0:ba7650f404af 97 #define __STATIC_INLINE static inline
aravindsv 0:ba7650f404af 98
aravindsv 0:ba7650f404af 99 #endif
aravindsv 0:ba7650f404af 100
aravindsv 0:ba7650f404af 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
aravindsv 0:ba7650f404af 102 */
aravindsv 0:ba7650f404af 103 #define __FPU_USED 0
aravindsv 0:ba7650f404af 104
aravindsv 0:ba7650f404af 105 #if defined ( __CC_ARM )
aravindsv 0:ba7650f404af 106 #if defined __TARGET_FPU_VFP
aravindsv 0:ba7650f404af 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 108 #endif
aravindsv 0:ba7650f404af 109
aravindsv 0:ba7650f404af 110 #elif defined ( __ICCARM__ )
aravindsv 0:ba7650f404af 111 #if defined __ARMVFP__
aravindsv 0:ba7650f404af 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 113 #endif
aravindsv 0:ba7650f404af 114
aravindsv 0:ba7650f404af 115 #elif defined ( __GNUC__ )
aravindsv 0:ba7650f404af 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
aravindsv 0:ba7650f404af 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 118 #endif
aravindsv 0:ba7650f404af 119
aravindsv 0:ba7650f404af 120 #elif defined ( __TASKING__ )
aravindsv 0:ba7650f404af 121 #if defined __FPU_VFP__
aravindsv 0:ba7650f404af 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
aravindsv 0:ba7650f404af 123 #endif
aravindsv 0:ba7650f404af 124 #endif
aravindsv 0:ba7650f404af 125
aravindsv 0:ba7650f404af 126 #include <stdint.h> /* standard types definitions */
aravindsv 0:ba7650f404af 127 #include <core_cmInstr.h> /* Core Instruction Access */
aravindsv 0:ba7650f404af 128 #include <core_cmFunc.h> /* Core Function Access */
aravindsv 0:ba7650f404af 129
aravindsv 0:ba7650f404af 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
aravindsv 0:ba7650f404af 131
aravindsv 0:ba7650f404af 132 #ifndef __CMSIS_GENERIC
aravindsv 0:ba7650f404af 133
aravindsv 0:ba7650f404af 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
aravindsv 0:ba7650f404af 135 #define __CORE_CM0PLUS_H_DEPENDANT
aravindsv 0:ba7650f404af 136
aravindsv 0:ba7650f404af 137 /* check device defines and use defaults */
aravindsv 0:ba7650f404af 138 #if defined __CHECK_DEVICE_DEFINES
aravindsv 0:ba7650f404af 139 #ifndef __CM0PLUS_REV
aravindsv 0:ba7650f404af 140 #define __CM0PLUS_REV 0x0000
aravindsv 0:ba7650f404af 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
aravindsv 0:ba7650f404af 142 #endif
aravindsv 0:ba7650f404af 143
aravindsv 0:ba7650f404af 144 #ifndef __MPU_PRESENT
aravindsv 0:ba7650f404af 145 #define __MPU_PRESENT 0
aravindsv 0:ba7650f404af 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
aravindsv 0:ba7650f404af 147 #endif
aravindsv 0:ba7650f404af 148
aravindsv 0:ba7650f404af 149 #ifndef __VTOR_PRESENT
aravindsv 0:ba7650f404af 150 #define __VTOR_PRESENT 0
aravindsv 0:ba7650f404af 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
aravindsv 0:ba7650f404af 152 #endif
aravindsv 0:ba7650f404af 153
aravindsv 0:ba7650f404af 154 #ifndef __NVIC_PRIO_BITS
aravindsv 0:ba7650f404af 155 #define __NVIC_PRIO_BITS 2
aravindsv 0:ba7650f404af 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
aravindsv 0:ba7650f404af 157 #endif
aravindsv 0:ba7650f404af 158
aravindsv 0:ba7650f404af 159 #ifndef __Vendor_SysTickConfig
aravindsv 0:ba7650f404af 160 #define __Vendor_SysTickConfig 0
aravindsv 0:ba7650f404af 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
aravindsv 0:ba7650f404af 162 #endif
aravindsv 0:ba7650f404af 163 #endif
aravindsv 0:ba7650f404af 164
aravindsv 0:ba7650f404af 165 /* IO definitions (access restrictions to peripheral registers) */
aravindsv 0:ba7650f404af 166 /**
aravindsv 0:ba7650f404af 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
aravindsv 0:ba7650f404af 168
aravindsv 0:ba7650f404af 169 <strong>IO Type Qualifiers</strong> are used
aravindsv 0:ba7650f404af 170 \li to specify the access to peripheral variables.
aravindsv 0:ba7650f404af 171 \li for automatic generation of peripheral register debug information.
aravindsv 0:ba7650f404af 172 */
aravindsv 0:ba7650f404af 173 #ifdef __cplusplus
aravindsv 0:ba7650f404af 174 #define __I volatile /*!< Defines 'read only' permissions */
aravindsv 0:ba7650f404af 175 #else
aravindsv 0:ba7650f404af 176 #define __I volatile const /*!< Defines 'read only' permissions */
aravindsv 0:ba7650f404af 177 #endif
aravindsv 0:ba7650f404af 178 #define __O volatile /*!< Defines 'write only' permissions */
aravindsv 0:ba7650f404af 179 #define __IO volatile /*!< Defines 'read / write' permissions */
aravindsv 0:ba7650f404af 180
aravindsv 0:ba7650f404af 181 /*@} end of group Cortex-M0+ */
aravindsv 0:ba7650f404af 182
aravindsv 0:ba7650f404af 183
aravindsv 0:ba7650f404af 184
aravindsv 0:ba7650f404af 185 /*******************************************************************************
aravindsv 0:ba7650f404af 186 * Register Abstraction
aravindsv 0:ba7650f404af 187 Core Register contain:
aravindsv 0:ba7650f404af 188 - Core Register
aravindsv 0:ba7650f404af 189 - Core NVIC Register
aravindsv 0:ba7650f404af 190 - Core SCB Register
aravindsv 0:ba7650f404af 191 - Core SysTick Register
aravindsv 0:ba7650f404af 192 - Core MPU Register
aravindsv 0:ba7650f404af 193 ******************************************************************************/
aravindsv 0:ba7650f404af 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
aravindsv 0:ba7650f404af 195 \brief Type definitions and defines for Cortex-M processor based devices.
aravindsv 0:ba7650f404af 196 */
aravindsv 0:ba7650f404af 197
aravindsv 0:ba7650f404af 198 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 199 \defgroup CMSIS_CORE Status and Control Registers
aravindsv 0:ba7650f404af 200 \brief Core Register type definitions.
aravindsv 0:ba7650f404af 201 @{
aravindsv 0:ba7650f404af 202 */
aravindsv 0:ba7650f404af 203
aravindsv 0:ba7650f404af 204 /** \brief Union type to access the Application Program Status Register (APSR).
aravindsv 0:ba7650f404af 205 */
aravindsv 0:ba7650f404af 206 typedef union
aravindsv 0:ba7650f404af 207 {
aravindsv 0:ba7650f404af 208 struct
aravindsv 0:ba7650f404af 209 {
aravindsv 0:ba7650f404af 210 #if (__CORTEX_M != 0x04)
aravindsv 0:ba7650f404af 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
aravindsv 0:ba7650f404af 212 #else
aravindsv 0:ba7650f404af 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
aravindsv 0:ba7650f404af 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
aravindsv 0:ba7650f404af 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
aravindsv 0:ba7650f404af 216 #endif
aravindsv 0:ba7650f404af 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
aravindsv 0:ba7650f404af 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
aravindsv 0:ba7650f404af 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
aravindsv 0:ba7650f404af 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
aravindsv 0:ba7650f404af 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
aravindsv 0:ba7650f404af 222 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 223 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 224 } APSR_Type;
aravindsv 0:ba7650f404af 225
aravindsv 0:ba7650f404af 226
aravindsv 0:ba7650f404af 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
aravindsv 0:ba7650f404af 228 */
aravindsv 0:ba7650f404af 229 typedef union
aravindsv 0:ba7650f404af 230 {
aravindsv 0:ba7650f404af 231 struct
aravindsv 0:ba7650f404af 232 {
aravindsv 0:ba7650f404af 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
aravindsv 0:ba7650f404af 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
aravindsv 0:ba7650f404af 235 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 236 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 237 } IPSR_Type;
aravindsv 0:ba7650f404af 238
aravindsv 0:ba7650f404af 239
aravindsv 0:ba7650f404af 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
aravindsv 0:ba7650f404af 241 */
aravindsv 0:ba7650f404af 242 typedef union
aravindsv 0:ba7650f404af 243 {
aravindsv 0:ba7650f404af 244 struct
aravindsv 0:ba7650f404af 245 {
aravindsv 0:ba7650f404af 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
aravindsv 0:ba7650f404af 247 #if (__CORTEX_M != 0x04)
aravindsv 0:ba7650f404af 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
aravindsv 0:ba7650f404af 249 #else
aravindsv 0:ba7650f404af 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
aravindsv 0:ba7650f404af 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
aravindsv 0:ba7650f404af 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
aravindsv 0:ba7650f404af 253 #endif
aravindsv 0:ba7650f404af 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
aravindsv 0:ba7650f404af 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
aravindsv 0:ba7650f404af 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
aravindsv 0:ba7650f404af 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
aravindsv 0:ba7650f404af 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
aravindsv 0:ba7650f404af 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
aravindsv 0:ba7650f404af 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
aravindsv 0:ba7650f404af 261 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 262 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 263 } xPSR_Type;
aravindsv 0:ba7650f404af 264
aravindsv 0:ba7650f404af 265
aravindsv 0:ba7650f404af 266 /** \brief Union type to access the Control Registers (CONTROL).
aravindsv 0:ba7650f404af 267 */
aravindsv 0:ba7650f404af 268 typedef union
aravindsv 0:ba7650f404af 269 {
aravindsv 0:ba7650f404af 270 struct
aravindsv 0:ba7650f404af 271 {
aravindsv 0:ba7650f404af 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
aravindsv 0:ba7650f404af 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
aravindsv 0:ba7650f404af 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
aravindsv 0:ba7650f404af 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
aravindsv 0:ba7650f404af 276 } b; /*!< Structure used for bit access */
aravindsv 0:ba7650f404af 277 uint32_t w; /*!< Type used for word access */
aravindsv 0:ba7650f404af 278 } CONTROL_Type;
aravindsv 0:ba7650f404af 279
aravindsv 0:ba7650f404af 280 /*@} end of group CMSIS_CORE */
aravindsv 0:ba7650f404af 281
aravindsv 0:ba7650f404af 282
aravindsv 0:ba7650f404af 283 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
aravindsv 0:ba7650f404af 285 \brief Type definitions for the NVIC Registers
aravindsv 0:ba7650f404af 286 @{
aravindsv 0:ba7650f404af 287 */
aravindsv 0:ba7650f404af 288
aravindsv 0:ba7650f404af 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
aravindsv 0:ba7650f404af 290 */
aravindsv 0:ba7650f404af 291 typedef struct
aravindsv 0:ba7650f404af 292 {
aravindsv 0:ba7650f404af 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
aravindsv 0:ba7650f404af 294 uint32_t RESERVED0[31];
aravindsv 0:ba7650f404af 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
aravindsv 0:ba7650f404af 296 uint32_t RSERVED1[31];
aravindsv 0:ba7650f404af 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
aravindsv 0:ba7650f404af 298 uint32_t RESERVED2[31];
aravindsv 0:ba7650f404af 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
aravindsv 0:ba7650f404af 300 uint32_t RESERVED3[31];
aravindsv 0:ba7650f404af 301 uint32_t RESERVED4[64];
aravindsv 0:ba7650f404af 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
aravindsv 0:ba7650f404af 303 } NVIC_Type;
aravindsv 0:ba7650f404af 304
aravindsv 0:ba7650f404af 305 /*@} end of group CMSIS_NVIC */
aravindsv 0:ba7650f404af 306
aravindsv 0:ba7650f404af 307
aravindsv 0:ba7650f404af 308 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 309 \defgroup CMSIS_SCB System Control Block (SCB)
aravindsv 0:ba7650f404af 310 \brief Type definitions for the System Control Block Registers
aravindsv 0:ba7650f404af 311 @{
aravindsv 0:ba7650f404af 312 */
aravindsv 0:ba7650f404af 313
aravindsv 0:ba7650f404af 314 /** \brief Structure type to access the System Control Block (SCB).
aravindsv 0:ba7650f404af 315 */
aravindsv 0:ba7650f404af 316 typedef struct
aravindsv 0:ba7650f404af 317 {
aravindsv 0:ba7650f404af 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
aravindsv 0:ba7650f404af 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
aravindsv 0:ba7650f404af 320 #if (__VTOR_PRESENT == 1)
aravindsv 0:ba7650f404af 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
aravindsv 0:ba7650f404af 322 #else
aravindsv 0:ba7650f404af 323 uint32_t RESERVED0;
aravindsv 0:ba7650f404af 324 #endif
aravindsv 0:ba7650f404af 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
aravindsv 0:ba7650f404af 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
aravindsv 0:ba7650f404af 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
aravindsv 0:ba7650f404af 328 uint32_t RESERVED1;
aravindsv 0:ba7650f404af 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
aravindsv 0:ba7650f404af 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
aravindsv 0:ba7650f404af 331 } SCB_Type;
aravindsv 0:ba7650f404af 332
aravindsv 0:ba7650f404af 333 /* SCB CPUID Register Definitions */
aravindsv 0:ba7650f404af 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
aravindsv 0:ba7650f404af 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
aravindsv 0:ba7650f404af 336
aravindsv 0:ba7650f404af 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
aravindsv 0:ba7650f404af 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
aravindsv 0:ba7650f404af 339
aravindsv 0:ba7650f404af 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
aravindsv 0:ba7650f404af 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
aravindsv 0:ba7650f404af 342
aravindsv 0:ba7650f404af 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
aravindsv 0:ba7650f404af 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
aravindsv 0:ba7650f404af 345
aravindsv 0:ba7650f404af 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
aravindsv 0:ba7650f404af 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
aravindsv 0:ba7650f404af 348
aravindsv 0:ba7650f404af 349 /* SCB Interrupt Control State Register Definitions */
aravindsv 0:ba7650f404af 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
aravindsv 0:ba7650f404af 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
aravindsv 0:ba7650f404af 352
aravindsv 0:ba7650f404af 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
aravindsv 0:ba7650f404af 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
aravindsv 0:ba7650f404af 355
aravindsv 0:ba7650f404af 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
aravindsv 0:ba7650f404af 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
aravindsv 0:ba7650f404af 358
aravindsv 0:ba7650f404af 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
aravindsv 0:ba7650f404af 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
aravindsv 0:ba7650f404af 361
aravindsv 0:ba7650f404af 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
aravindsv 0:ba7650f404af 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
aravindsv 0:ba7650f404af 364
aravindsv 0:ba7650f404af 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
aravindsv 0:ba7650f404af 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
aravindsv 0:ba7650f404af 367
aravindsv 0:ba7650f404af 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
aravindsv 0:ba7650f404af 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
aravindsv 0:ba7650f404af 370
aravindsv 0:ba7650f404af 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
aravindsv 0:ba7650f404af 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
aravindsv 0:ba7650f404af 373
aravindsv 0:ba7650f404af 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
aravindsv 0:ba7650f404af 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
aravindsv 0:ba7650f404af 376
aravindsv 0:ba7650f404af 377 #if (__VTOR_PRESENT == 1)
aravindsv 0:ba7650f404af 378 /* SCB Interrupt Control State Register Definitions */
aravindsv 0:ba7650f404af 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
aravindsv 0:ba7650f404af 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
aravindsv 0:ba7650f404af 381 #endif
aravindsv 0:ba7650f404af 382
aravindsv 0:ba7650f404af 383 /* SCB Application Interrupt and Reset Control Register Definitions */
aravindsv 0:ba7650f404af 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
aravindsv 0:ba7650f404af 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
aravindsv 0:ba7650f404af 386
aravindsv 0:ba7650f404af 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
aravindsv 0:ba7650f404af 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
aravindsv 0:ba7650f404af 389
aravindsv 0:ba7650f404af 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
aravindsv 0:ba7650f404af 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
aravindsv 0:ba7650f404af 392
aravindsv 0:ba7650f404af 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
aravindsv 0:ba7650f404af 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
aravindsv 0:ba7650f404af 395
aravindsv 0:ba7650f404af 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
aravindsv 0:ba7650f404af 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
aravindsv 0:ba7650f404af 398
aravindsv 0:ba7650f404af 399 /* SCB System Control Register Definitions */
aravindsv 0:ba7650f404af 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
aravindsv 0:ba7650f404af 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
aravindsv 0:ba7650f404af 402
aravindsv 0:ba7650f404af 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
aravindsv 0:ba7650f404af 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
aravindsv 0:ba7650f404af 405
aravindsv 0:ba7650f404af 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
aravindsv 0:ba7650f404af 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
aravindsv 0:ba7650f404af 408
aravindsv 0:ba7650f404af 409 /* SCB Configuration Control Register Definitions */
aravindsv 0:ba7650f404af 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
aravindsv 0:ba7650f404af 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
aravindsv 0:ba7650f404af 412
aravindsv 0:ba7650f404af 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
aravindsv 0:ba7650f404af 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
aravindsv 0:ba7650f404af 415
aravindsv 0:ba7650f404af 416 /* SCB System Handler Control and State Register Definitions */
aravindsv 0:ba7650f404af 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
aravindsv 0:ba7650f404af 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
aravindsv 0:ba7650f404af 419
aravindsv 0:ba7650f404af 420 /*@} end of group CMSIS_SCB */
aravindsv 0:ba7650f404af 421
aravindsv 0:ba7650f404af 422
aravindsv 0:ba7650f404af 423 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
aravindsv 0:ba7650f404af 425 \brief Type definitions for the System Timer Registers.
aravindsv 0:ba7650f404af 426 @{
aravindsv 0:ba7650f404af 427 */
aravindsv 0:ba7650f404af 428
aravindsv 0:ba7650f404af 429 /** \brief Structure type to access the System Timer (SysTick).
aravindsv 0:ba7650f404af 430 */
aravindsv 0:ba7650f404af 431 typedef struct
aravindsv 0:ba7650f404af 432 {
aravindsv 0:ba7650f404af 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
aravindsv 0:ba7650f404af 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
aravindsv 0:ba7650f404af 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
aravindsv 0:ba7650f404af 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
aravindsv 0:ba7650f404af 437 } SysTick_Type;
aravindsv 0:ba7650f404af 438
aravindsv 0:ba7650f404af 439 /* SysTick Control / Status Register Definitions */
aravindsv 0:ba7650f404af 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
aravindsv 0:ba7650f404af 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
aravindsv 0:ba7650f404af 442
aravindsv 0:ba7650f404af 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
aravindsv 0:ba7650f404af 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
aravindsv 0:ba7650f404af 445
aravindsv 0:ba7650f404af 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
aravindsv 0:ba7650f404af 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
aravindsv 0:ba7650f404af 448
aravindsv 0:ba7650f404af 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
aravindsv 0:ba7650f404af 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
aravindsv 0:ba7650f404af 451
aravindsv 0:ba7650f404af 452 /* SysTick Reload Register Definitions */
aravindsv 0:ba7650f404af 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
aravindsv 0:ba7650f404af 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
aravindsv 0:ba7650f404af 455
aravindsv 0:ba7650f404af 456 /* SysTick Current Register Definitions */
aravindsv 0:ba7650f404af 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
aravindsv 0:ba7650f404af 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
aravindsv 0:ba7650f404af 459
aravindsv 0:ba7650f404af 460 /* SysTick Calibration Register Definitions */
aravindsv 0:ba7650f404af 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
aravindsv 0:ba7650f404af 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
aravindsv 0:ba7650f404af 463
aravindsv 0:ba7650f404af 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
aravindsv 0:ba7650f404af 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
aravindsv 0:ba7650f404af 466
aravindsv 0:ba7650f404af 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
aravindsv 0:ba7650f404af 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
aravindsv 0:ba7650f404af 469
aravindsv 0:ba7650f404af 470 /*@} end of group CMSIS_SysTick */
aravindsv 0:ba7650f404af 471
aravindsv 0:ba7650f404af 472 #if (__MPU_PRESENT == 1)
aravindsv 0:ba7650f404af 473 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
aravindsv 0:ba7650f404af 475 \brief Type definitions for the Memory Protection Unit (MPU)
aravindsv 0:ba7650f404af 476 @{
aravindsv 0:ba7650f404af 477 */
aravindsv 0:ba7650f404af 478
aravindsv 0:ba7650f404af 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
aravindsv 0:ba7650f404af 480 */
aravindsv 0:ba7650f404af 481 typedef struct
aravindsv 0:ba7650f404af 482 {
aravindsv 0:ba7650f404af 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
aravindsv 0:ba7650f404af 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
aravindsv 0:ba7650f404af 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
aravindsv 0:ba7650f404af 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
aravindsv 0:ba7650f404af 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
aravindsv 0:ba7650f404af 488 } MPU_Type;
aravindsv 0:ba7650f404af 489
aravindsv 0:ba7650f404af 490 /* MPU Type Register */
aravindsv 0:ba7650f404af 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
aravindsv 0:ba7650f404af 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
aravindsv 0:ba7650f404af 493
aravindsv 0:ba7650f404af 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
aravindsv 0:ba7650f404af 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
aravindsv 0:ba7650f404af 496
aravindsv 0:ba7650f404af 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
aravindsv 0:ba7650f404af 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
aravindsv 0:ba7650f404af 499
aravindsv 0:ba7650f404af 500 /* MPU Control Register */
aravindsv 0:ba7650f404af 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
aravindsv 0:ba7650f404af 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
aravindsv 0:ba7650f404af 503
aravindsv 0:ba7650f404af 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
aravindsv 0:ba7650f404af 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
aravindsv 0:ba7650f404af 506
aravindsv 0:ba7650f404af 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
aravindsv 0:ba7650f404af 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
aravindsv 0:ba7650f404af 509
aravindsv 0:ba7650f404af 510 /* MPU Region Number Register */
aravindsv 0:ba7650f404af 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
aravindsv 0:ba7650f404af 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
aravindsv 0:ba7650f404af 513
aravindsv 0:ba7650f404af 514 /* MPU Region Base Address Register */
aravindsv 0:ba7650f404af 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
aravindsv 0:ba7650f404af 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
aravindsv 0:ba7650f404af 517
aravindsv 0:ba7650f404af 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
aravindsv 0:ba7650f404af 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
aravindsv 0:ba7650f404af 520
aravindsv 0:ba7650f404af 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
aravindsv 0:ba7650f404af 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
aravindsv 0:ba7650f404af 523
aravindsv 0:ba7650f404af 524 /* MPU Region Attribute and Size Register */
aravindsv 0:ba7650f404af 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
aravindsv 0:ba7650f404af 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
aravindsv 0:ba7650f404af 527
aravindsv 0:ba7650f404af 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
aravindsv 0:ba7650f404af 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
aravindsv 0:ba7650f404af 530
aravindsv 0:ba7650f404af 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
aravindsv 0:ba7650f404af 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
aravindsv 0:ba7650f404af 533
aravindsv 0:ba7650f404af 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
aravindsv 0:ba7650f404af 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
aravindsv 0:ba7650f404af 536
aravindsv 0:ba7650f404af 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
aravindsv 0:ba7650f404af 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
aravindsv 0:ba7650f404af 539
aravindsv 0:ba7650f404af 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
aravindsv 0:ba7650f404af 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
aravindsv 0:ba7650f404af 542
aravindsv 0:ba7650f404af 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
aravindsv 0:ba7650f404af 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
aravindsv 0:ba7650f404af 545
aravindsv 0:ba7650f404af 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
aravindsv 0:ba7650f404af 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
aravindsv 0:ba7650f404af 548
aravindsv 0:ba7650f404af 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
aravindsv 0:ba7650f404af 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
aravindsv 0:ba7650f404af 551
aravindsv 0:ba7650f404af 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
aravindsv 0:ba7650f404af 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
aravindsv 0:ba7650f404af 554
aravindsv 0:ba7650f404af 555 /*@} end of group CMSIS_MPU */
aravindsv 0:ba7650f404af 556 #endif
aravindsv 0:ba7650f404af 557
aravindsv 0:ba7650f404af 558
aravindsv 0:ba7650f404af 559 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
aravindsv 0:ba7650f404af 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
aravindsv 0:ba7650f404af 562 are only accessible over DAP and not via processor. Therefore
aravindsv 0:ba7650f404af 563 they are not covered by the Cortex-M0 header file.
aravindsv 0:ba7650f404af 564 @{
aravindsv 0:ba7650f404af 565 */
aravindsv 0:ba7650f404af 566 /*@} end of group CMSIS_CoreDebug */
aravindsv 0:ba7650f404af 567
aravindsv 0:ba7650f404af 568
aravindsv 0:ba7650f404af 569 /** \ingroup CMSIS_core_register
aravindsv 0:ba7650f404af 570 \defgroup CMSIS_core_base Core Definitions
aravindsv 0:ba7650f404af 571 \brief Definitions for base addresses, unions, and structures.
aravindsv 0:ba7650f404af 572 @{
aravindsv 0:ba7650f404af 573 */
aravindsv 0:ba7650f404af 574
aravindsv 0:ba7650f404af 575 /* Memory mapping of Cortex-M0+ Hardware */
aravindsv 0:ba7650f404af 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
aravindsv 0:ba7650f404af 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
aravindsv 0:ba7650f404af 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
aravindsv 0:ba7650f404af 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
aravindsv 0:ba7650f404af 580
aravindsv 0:ba7650f404af 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
aravindsv 0:ba7650f404af 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
aravindsv 0:ba7650f404af 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
aravindsv 0:ba7650f404af 584
aravindsv 0:ba7650f404af 585 #if (__MPU_PRESENT == 1)
aravindsv 0:ba7650f404af 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
aravindsv 0:ba7650f404af 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
aravindsv 0:ba7650f404af 588 #endif
aravindsv 0:ba7650f404af 589
aravindsv 0:ba7650f404af 590 /*@} */
aravindsv 0:ba7650f404af 591
aravindsv 0:ba7650f404af 592
aravindsv 0:ba7650f404af 593
aravindsv 0:ba7650f404af 594 /*******************************************************************************
aravindsv 0:ba7650f404af 595 * Hardware Abstraction Layer
aravindsv 0:ba7650f404af 596 Core Function Interface contains:
aravindsv 0:ba7650f404af 597 - Core NVIC Functions
aravindsv 0:ba7650f404af 598 - Core SysTick Functions
aravindsv 0:ba7650f404af 599 - Core Register Access Functions
aravindsv 0:ba7650f404af 600 ******************************************************************************/
aravindsv 0:ba7650f404af 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
aravindsv 0:ba7650f404af 602 */
aravindsv 0:ba7650f404af 603
aravindsv 0:ba7650f404af 604
aravindsv 0:ba7650f404af 605
aravindsv 0:ba7650f404af 606 /* ########################## NVIC functions #################################### */
aravindsv 0:ba7650f404af 607 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
aravindsv 0:ba7650f404af 609 \brief Functions that manage interrupts and exceptions via the NVIC.
aravindsv 0:ba7650f404af 610 @{
aravindsv 0:ba7650f404af 611 */
aravindsv 0:ba7650f404af 612
aravindsv 0:ba7650f404af 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
aravindsv 0:ba7650f404af 614 /* The following MACROS handle generation of the register offset and byte masks */
aravindsv 0:ba7650f404af 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
aravindsv 0:ba7650f404af 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
aravindsv 0:ba7650f404af 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
aravindsv 0:ba7650f404af 618
aravindsv 0:ba7650f404af 619
aravindsv 0:ba7650f404af 620 /** \brief Enable External Interrupt
aravindsv 0:ba7650f404af 621
aravindsv 0:ba7650f404af 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
aravindsv 0:ba7650f404af 623
aravindsv 0:ba7650f404af 624 \param [in] IRQn External interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 625 */
aravindsv 0:ba7650f404af 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 627 {
aravindsv 0:ba7650f404af 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
aravindsv 0:ba7650f404af 629 }
aravindsv 0:ba7650f404af 630
aravindsv 0:ba7650f404af 631
aravindsv 0:ba7650f404af 632 /** \brief Disable External Interrupt
aravindsv 0:ba7650f404af 633
aravindsv 0:ba7650f404af 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
aravindsv 0:ba7650f404af 635
aravindsv 0:ba7650f404af 636 \param [in] IRQn External interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 637 */
aravindsv 0:ba7650f404af 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 639 {
aravindsv 0:ba7650f404af 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
aravindsv 0:ba7650f404af 641 }
aravindsv 0:ba7650f404af 642
aravindsv 0:ba7650f404af 643
aravindsv 0:ba7650f404af 644 /** \brief Get Pending Interrupt
aravindsv 0:ba7650f404af 645
aravindsv 0:ba7650f404af 646 The function reads the pending register in the NVIC and returns the pending bit
aravindsv 0:ba7650f404af 647 for the specified interrupt.
aravindsv 0:ba7650f404af 648
aravindsv 0:ba7650f404af 649 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 650
aravindsv 0:ba7650f404af 651 \return 0 Interrupt status is not pending.
aravindsv 0:ba7650f404af 652 \return 1 Interrupt status is pending.
aravindsv 0:ba7650f404af 653 */
aravindsv 0:ba7650f404af 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 655 {
aravindsv 0:ba7650f404af 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
aravindsv 0:ba7650f404af 657 }
aravindsv 0:ba7650f404af 658
aravindsv 0:ba7650f404af 659
aravindsv 0:ba7650f404af 660 /** \brief Set Pending Interrupt
aravindsv 0:ba7650f404af 661
aravindsv 0:ba7650f404af 662 The function sets the pending bit of an external interrupt.
aravindsv 0:ba7650f404af 663
aravindsv 0:ba7650f404af 664 \param [in] IRQn Interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 665 */
aravindsv 0:ba7650f404af 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 667 {
aravindsv 0:ba7650f404af 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
aravindsv 0:ba7650f404af 669 }
aravindsv 0:ba7650f404af 670
aravindsv 0:ba7650f404af 671
aravindsv 0:ba7650f404af 672 /** \brief Clear Pending Interrupt
aravindsv 0:ba7650f404af 673
aravindsv 0:ba7650f404af 674 The function clears the pending bit of an external interrupt.
aravindsv 0:ba7650f404af 675
aravindsv 0:ba7650f404af 676 \param [in] IRQn External interrupt number. Value cannot be negative.
aravindsv 0:ba7650f404af 677 */
aravindsv 0:ba7650f404af 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 679 {
aravindsv 0:ba7650f404af 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
aravindsv 0:ba7650f404af 681 }
aravindsv 0:ba7650f404af 682
aravindsv 0:ba7650f404af 683
aravindsv 0:ba7650f404af 684 /** \brief Set Interrupt Priority
aravindsv 0:ba7650f404af 685
aravindsv 0:ba7650f404af 686 The function sets the priority of an interrupt.
aravindsv 0:ba7650f404af 687
aravindsv 0:ba7650f404af 688 \note The priority cannot be set for every core interrupt.
aravindsv 0:ba7650f404af 689
aravindsv 0:ba7650f404af 690 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 691 \param [in] priority Priority to set.
aravindsv 0:ba7650f404af 692 */
aravindsv 0:ba7650f404af 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
aravindsv 0:ba7650f404af 694 {
aravindsv 0:ba7650f404af 695 if(IRQn < 0) {
aravindsv 0:ba7650f404af 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
aravindsv 0:ba7650f404af 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
aravindsv 0:ba7650f404af 698 else {
aravindsv 0:ba7650f404af 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
aravindsv 0:ba7650f404af 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
aravindsv 0:ba7650f404af 701 }
aravindsv 0:ba7650f404af 702
aravindsv 0:ba7650f404af 703
aravindsv 0:ba7650f404af 704 /** \brief Get Interrupt Priority
aravindsv 0:ba7650f404af 705
aravindsv 0:ba7650f404af 706 The function reads the priority of an interrupt. The interrupt
aravindsv 0:ba7650f404af 707 number can be positive to specify an external (device specific)
aravindsv 0:ba7650f404af 708 interrupt, or negative to specify an internal (core) interrupt.
aravindsv 0:ba7650f404af 709
aravindsv 0:ba7650f404af 710
aravindsv 0:ba7650f404af 711 \param [in] IRQn Interrupt number.
aravindsv 0:ba7650f404af 712 \return Interrupt Priority. Value is aligned automatically to the implemented
aravindsv 0:ba7650f404af 713 priority bits of the microcontroller.
aravindsv 0:ba7650f404af 714 */
aravindsv 0:ba7650f404af 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
aravindsv 0:ba7650f404af 716 {
aravindsv 0:ba7650f404af 717
aravindsv 0:ba7650f404af 718 if(IRQn < 0) {
aravindsv 0:ba7650f404af 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
aravindsv 0:ba7650f404af 720 else {
aravindsv 0:ba7650f404af 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
aravindsv 0:ba7650f404af 722 }
aravindsv 0:ba7650f404af 723
aravindsv 0:ba7650f404af 724
aravindsv 0:ba7650f404af 725 /** \brief System Reset
aravindsv 0:ba7650f404af 726
aravindsv 0:ba7650f404af 727 The function initiates a system reset request to reset the MCU.
aravindsv 0:ba7650f404af 728 */
aravindsv 0:ba7650f404af 729 __STATIC_INLINE void NVIC_SystemReset(void)
aravindsv 0:ba7650f404af 730 {
aravindsv 0:ba7650f404af 731 __DSB(); /* Ensure all outstanding memory accesses included
aravindsv 0:ba7650f404af 732 buffered write are completed before reset */
aravindsv 0:ba7650f404af 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
aravindsv 0:ba7650f404af 734 SCB_AIRCR_SYSRESETREQ_Msk);
aravindsv 0:ba7650f404af 735 __DSB(); /* Ensure completion of memory access */
aravindsv 0:ba7650f404af 736 while(1); /* wait until reset */
aravindsv 0:ba7650f404af 737 }
aravindsv 0:ba7650f404af 738
aravindsv 0:ba7650f404af 739 /*@} end of CMSIS_Core_NVICFunctions */
aravindsv 0:ba7650f404af 740
aravindsv 0:ba7650f404af 741
aravindsv 0:ba7650f404af 742
aravindsv 0:ba7650f404af 743 /* ################################## SysTick function ############################################ */
aravindsv 0:ba7650f404af 744 /** \ingroup CMSIS_Core_FunctionInterface
aravindsv 0:ba7650f404af 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
aravindsv 0:ba7650f404af 746 \brief Functions that configure the System.
aravindsv 0:ba7650f404af 747 @{
aravindsv 0:ba7650f404af 748 */
aravindsv 0:ba7650f404af 749
aravindsv 0:ba7650f404af 750 #if (__Vendor_SysTickConfig == 0)
aravindsv 0:ba7650f404af 751
aravindsv 0:ba7650f404af 752 /** \brief System Tick Configuration
aravindsv 0:ba7650f404af 753
aravindsv 0:ba7650f404af 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
aravindsv 0:ba7650f404af 755 Counter is in free running mode to generate periodic interrupts.
aravindsv 0:ba7650f404af 756
aravindsv 0:ba7650f404af 757 \param [in] ticks Number of ticks between two interrupts.
aravindsv 0:ba7650f404af 758
aravindsv 0:ba7650f404af 759 \return 0 Function succeeded.
aravindsv 0:ba7650f404af 760 \return 1 Function failed.
aravindsv 0:ba7650f404af 761
aravindsv 0:ba7650f404af 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
aravindsv 0:ba7650f404af 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
aravindsv 0:ba7650f404af 764 must contain a vendor-specific implementation of this function.
aravindsv 0:ba7650f404af 765
aravindsv 0:ba7650f404af 766 */
aravindsv 0:ba7650f404af 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
aravindsv 0:ba7650f404af 768 {
aravindsv 0:ba7650f404af 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
aravindsv 0:ba7650f404af 770
aravindsv 0:ba7650f404af 771 SysTick->LOAD = ticks - 1; /* set reload register */
aravindsv 0:ba7650f404af 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
aravindsv 0:ba7650f404af 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
aravindsv 0:ba7650f404af 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
aravindsv 0:ba7650f404af 775 SysTick_CTRL_TICKINT_Msk |
aravindsv 0:ba7650f404af 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
aravindsv 0:ba7650f404af 777 return (0); /* Function successful */
aravindsv 0:ba7650f404af 778 }
aravindsv 0:ba7650f404af 779
aravindsv 0:ba7650f404af 780 #endif
aravindsv 0:ba7650f404af 781
aravindsv 0:ba7650f404af 782 /*@} end of CMSIS_Core_SysTickFunctions */
aravindsv 0:ba7650f404af 783
aravindsv 0:ba7650f404af 784
aravindsv 0:ba7650f404af 785
aravindsv 0:ba7650f404af 786
aravindsv 0:ba7650f404af 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
aravindsv 0:ba7650f404af 788
aravindsv 0:ba7650f404af 789 #endif /* __CMSIS_GENERIC */
aravindsv 0:ba7650f404af 790
aravindsv 0:ba7650f404af 791 #ifdef __cplusplus
aravindsv 0:ba7650f404af 792 }
aravindsv 0:ba7650f404af 793 #endif