Thor Hall / mbed-dev_mbed_lib_v125

This fork captures the mbed lib v125 for ease of integration into older projects.

Fork of mbed-dev by mbed official

targets/cmsis/core_cmFunc.h@187:92cbb9eec47b, 2018-07-20 (annotated)

Committer:
apluscw
Date:
Fri Jul 20 21:24:42 2018 +0000
Revision:
187:92cbb9eec47b
Mbed library with source code from mbed lib v125. Posted to ease integration with some older projects.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
apluscw 187:92cbb9eec47b 1 /**************************************************************************//**
apluscw 187:92cbb9eec47b 2 * @file core_cmFunc.h
apluscw 187:92cbb9eec47b 3 * @brief CMSIS Cortex-M Core Function Access Header File
apluscw 187:92cbb9eec47b 4 * @version V4.10
apluscw 187:92cbb9eec47b 5 * @date 18. March 2015
apluscw 187:92cbb9eec47b 6 *
apluscw 187:92cbb9eec47b 7 * @note
apluscw 187:92cbb9eec47b 8 *
apluscw 187:92cbb9eec47b 9 ******************************************************************************/
apluscw 187:92cbb9eec47b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
apluscw 187:92cbb9eec47b 11
apluscw 187:92cbb9eec47b 12 All rights reserved.
apluscw 187:92cbb9eec47b 13 Redistribution and use in source and binary forms, with or without
apluscw 187:92cbb9eec47b 14 modification, are permitted provided that the following conditions are met:
apluscw 187:92cbb9eec47b 15 - Redistributions of source code must retain the above copyright
apluscw 187:92cbb9eec47b 16 notice, this list of conditions and the following disclaimer.
apluscw 187:92cbb9eec47b 17 - Redistributions in binary form must reproduce the above copyright
apluscw 187:92cbb9eec47b 18 notice, this list of conditions and the following disclaimer in the
apluscw 187:92cbb9eec47b 19 documentation and/or other materials provided with the distribution.
apluscw 187:92cbb9eec47b 20 - Neither the name of ARM nor the names of its contributors may be used
apluscw 187:92cbb9eec47b 21 to endorse or promote products derived from this software without
apluscw 187:92cbb9eec47b 22 specific prior written permission.
apluscw 187:92cbb9eec47b 23 *
apluscw 187:92cbb9eec47b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
apluscw 187:92cbb9eec47b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
apluscw 187:92cbb9eec47b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
apluscw 187:92cbb9eec47b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
apluscw 187:92cbb9eec47b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
apluscw 187:92cbb9eec47b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
apluscw 187:92cbb9eec47b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
apluscw 187:92cbb9eec47b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
apluscw 187:92cbb9eec47b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
apluscw 187:92cbb9eec47b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
apluscw 187:92cbb9eec47b 34 POSSIBILITY OF SUCH DAMAGE.
apluscw 187:92cbb9eec47b 35 ---------------------------------------------------------------------------*/
apluscw 187:92cbb9eec47b 36
apluscw 187:92cbb9eec47b 37
apluscw 187:92cbb9eec47b 38 #ifndef __CORE_CMFUNC_H
apluscw 187:92cbb9eec47b 39 #define __CORE_CMFUNC_H
apluscw 187:92cbb9eec47b 40
apluscw 187:92cbb9eec47b 41
apluscw 187:92cbb9eec47b 42 /* ########################### Core Function Access ########################### */
apluscw 187:92cbb9eec47b 43 /** \ingroup CMSIS_Core_FunctionInterface
apluscw 187:92cbb9eec47b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
apluscw 187:92cbb9eec47b 45 @{
apluscw 187:92cbb9eec47b 46 */
apluscw 187:92cbb9eec47b 47
apluscw 187:92cbb9eec47b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
apluscw 187:92cbb9eec47b 49 /* ARM armcc specific functions */
apluscw 187:92cbb9eec47b 50
apluscw 187:92cbb9eec47b 51 #if (__ARMCC_VERSION < 400677)
apluscw 187:92cbb9eec47b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
apluscw 187:92cbb9eec47b 53 #endif
apluscw 187:92cbb9eec47b 54
apluscw 187:92cbb9eec47b 55 /* intrinsic void __enable_irq(); */
apluscw 187:92cbb9eec47b 56 /* intrinsic void __disable_irq(); */
apluscw 187:92cbb9eec47b 57
apluscw 187:92cbb9eec47b 58 /** \brief Get Control Register
apluscw 187:92cbb9eec47b 59
apluscw 187:92cbb9eec47b 60 This function returns the content of the Control Register.
apluscw 187:92cbb9eec47b 61
apluscw 187:92cbb9eec47b 62 \return Control Register value
apluscw 187:92cbb9eec47b 63 */
apluscw 187:92cbb9eec47b 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
apluscw 187:92cbb9eec47b 65 {
apluscw 187:92cbb9eec47b 66 register uint32_t __regControl __ASM("control");
apluscw 187:92cbb9eec47b 67 return(__regControl);
apluscw 187:92cbb9eec47b 68 }
apluscw 187:92cbb9eec47b 69
apluscw 187:92cbb9eec47b 70
apluscw 187:92cbb9eec47b 71 /** \brief Set Control Register
apluscw 187:92cbb9eec47b 72
apluscw 187:92cbb9eec47b 73 This function writes the given value to the Control Register.
apluscw 187:92cbb9eec47b 74
apluscw 187:92cbb9eec47b 75 \param [in] control Control Register value to set
apluscw 187:92cbb9eec47b 76 */
apluscw 187:92cbb9eec47b 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
apluscw 187:92cbb9eec47b 78 {
apluscw 187:92cbb9eec47b 79 register uint32_t __regControl __ASM("control");
apluscw 187:92cbb9eec47b 80 __regControl = control;
apluscw 187:92cbb9eec47b 81 }
apluscw 187:92cbb9eec47b 82
apluscw 187:92cbb9eec47b 83
apluscw 187:92cbb9eec47b 84 /** \brief Get IPSR Register
apluscw 187:92cbb9eec47b 85
apluscw 187:92cbb9eec47b 86 This function returns the content of the IPSR Register.
apluscw 187:92cbb9eec47b 87
apluscw 187:92cbb9eec47b 88 \return IPSR Register value
apluscw 187:92cbb9eec47b 89 */
apluscw 187:92cbb9eec47b 90 __STATIC_INLINE uint32_t __get_IPSR(void)
apluscw 187:92cbb9eec47b 91 {
apluscw 187:92cbb9eec47b 92 register uint32_t __regIPSR __ASM("ipsr");
apluscw 187:92cbb9eec47b 93 return(__regIPSR);
apluscw 187:92cbb9eec47b 94 }
apluscw 187:92cbb9eec47b 95
apluscw 187:92cbb9eec47b 96
apluscw 187:92cbb9eec47b 97 /** \brief Get APSR Register
apluscw 187:92cbb9eec47b 98
apluscw 187:92cbb9eec47b 99 This function returns the content of the APSR Register.
apluscw 187:92cbb9eec47b 100
apluscw 187:92cbb9eec47b 101 \return APSR Register value
apluscw 187:92cbb9eec47b 102 */
apluscw 187:92cbb9eec47b 103 __STATIC_INLINE uint32_t __get_APSR(void)
apluscw 187:92cbb9eec47b 104 {
apluscw 187:92cbb9eec47b 105 register uint32_t __regAPSR __ASM("apsr");
apluscw 187:92cbb9eec47b 106 return(__regAPSR);
apluscw 187:92cbb9eec47b 107 }
apluscw 187:92cbb9eec47b 108
apluscw 187:92cbb9eec47b 109
apluscw 187:92cbb9eec47b 110 /** \brief Get xPSR Register
apluscw 187:92cbb9eec47b 111
apluscw 187:92cbb9eec47b 112 This function returns the content of the xPSR Register.
apluscw 187:92cbb9eec47b 113
apluscw 187:92cbb9eec47b 114 \return xPSR Register value
apluscw 187:92cbb9eec47b 115 */
apluscw 187:92cbb9eec47b 116 __STATIC_INLINE uint32_t __get_xPSR(void)
apluscw 187:92cbb9eec47b 117 {
apluscw 187:92cbb9eec47b 118 register uint32_t __regXPSR __ASM("xpsr");
apluscw 187:92cbb9eec47b 119 return(__regXPSR);
apluscw 187:92cbb9eec47b 120 }
apluscw 187:92cbb9eec47b 121
apluscw 187:92cbb9eec47b 122
apluscw 187:92cbb9eec47b 123 /** \brief Get Process Stack Pointer
apluscw 187:92cbb9eec47b 124
apluscw 187:92cbb9eec47b 125 This function returns the current value of the Process Stack Pointer (PSP).
apluscw 187:92cbb9eec47b 126
apluscw 187:92cbb9eec47b 127 \return PSP Register value
apluscw 187:92cbb9eec47b 128 */
apluscw 187:92cbb9eec47b 129 __STATIC_INLINE uint32_t __get_PSP(void)
apluscw 187:92cbb9eec47b 130 {
apluscw 187:92cbb9eec47b 131 register uint32_t __regProcessStackPointer __ASM("psp");
apluscw 187:92cbb9eec47b 132 return(__regProcessStackPointer);
apluscw 187:92cbb9eec47b 133 }
apluscw 187:92cbb9eec47b 134
apluscw 187:92cbb9eec47b 135
apluscw 187:92cbb9eec47b 136 /** \brief Set Process Stack Pointer
apluscw 187:92cbb9eec47b 137
apluscw 187:92cbb9eec47b 138 This function assigns the given value to the Process Stack Pointer (PSP).
apluscw 187:92cbb9eec47b 139
apluscw 187:92cbb9eec47b 140 \param [in] topOfProcStack Process Stack Pointer value to set
apluscw 187:92cbb9eec47b 141 */
apluscw 187:92cbb9eec47b 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
apluscw 187:92cbb9eec47b 143 {
apluscw 187:92cbb9eec47b 144 register uint32_t __regProcessStackPointer __ASM("psp");
apluscw 187:92cbb9eec47b 145 __regProcessStackPointer = topOfProcStack;
apluscw 187:92cbb9eec47b 146 }
apluscw 187:92cbb9eec47b 147
apluscw 187:92cbb9eec47b 148
apluscw 187:92cbb9eec47b 149 /** \brief Get Main Stack Pointer
apluscw 187:92cbb9eec47b 150
apluscw 187:92cbb9eec47b 151 This function returns the current value of the Main Stack Pointer (MSP).
apluscw 187:92cbb9eec47b 152
apluscw 187:92cbb9eec47b 153 \return MSP Register value
apluscw 187:92cbb9eec47b 154 */
apluscw 187:92cbb9eec47b 155 __STATIC_INLINE uint32_t __get_MSP(void)
apluscw 187:92cbb9eec47b 156 {
apluscw 187:92cbb9eec47b 157 register uint32_t __regMainStackPointer __ASM("msp");
apluscw 187:92cbb9eec47b 158 return(__regMainStackPointer);
apluscw 187:92cbb9eec47b 159 }
apluscw 187:92cbb9eec47b 160
apluscw 187:92cbb9eec47b 161
apluscw 187:92cbb9eec47b 162 /** \brief Set Main Stack Pointer
apluscw 187:92cbb9eec47b 163
apluscw 187:92cbb9eec47b 164 This function assigns the given value to the Main Stack Pointer (MSP).
apluscw 187:92cbb9eec47b 165
apluscw 187:92cbb9eec47b 166 \param [in] topOfMainStack Main Stack Pointer value to set
apluscw 187:92cbb9eec47b 167 */
apluscw 187:92cbb9eec47b 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
apluscw 187:92cbb9eec47b 169 {
apluscw 187:92cbb9eec47b 170 register uint32_t __regMainStackPointer __ASM("msp");
apluscw 187:92cbb9eec47b 171 __regMainStackPointer = topOfMainStack;
apluscw 187:92cbb9eec47b 172 }
apluscw 187:92cbb9eec47b 173
apluscw 187:92cbb9eec47b 174
apluscw 187:92cbb9eec47b 175 /** \brief Get Priority Mask
apluscw 187:92cbb9eec47b 176
apluscw 187:92cbb9eec47b 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
apluscw 187:92cbb9eec47b 178
apluscw 187:92cbb9eec47b 179 \return Priority Mask value
apluscw 187:92cbb9eec47b 180 */
apluscw 187:92cbb9eec47b 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
apluscw 187:92cbb9eec47b 182 {
apluscw 187:92cbb9eec47b 183 register uint32_t __regPriMask __ASM("primask");
apluscw 187:92cbb9eec47b 184 return(__regPriMask);
apluscw 187:92cbb9eec47b 185 }
apluscw 187:92cbb9eec47b 186
apluscw 187:92cbb9eec47b 187
apluscw 187:92cbb9eec47b 188 /** \brief Set Priority Mask
apluscw 187:92cbb9eec47b 189
apluscw 187:92cbb9eec47b 190 This function assigns the given value to the Priority Mask Register.
apluscw 187:92cbb9eec47b 191
apluscw 187:92cbb9eec47b 192 \param [in] priMask Priority Mask
apluscw 187:92cbb9eec47b 193 */
apluscw 187:92cbb9eec47b 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
apluscw 187:92cbb9eec47b 195 {
apluscw 187:92cbb9eec47b 196 register uint32_t __regPriMask __ASM("primask");
apluscw 187:92cbb9eec47b 197 __regPriMask = (priMask);
apluscw 187:92cbb9eec47b 198 }
apluscw 187:92cbb9eec47b 199
apluscw 187:92cbb9eec47b 200
apluscw 187:92cbb9eec47b 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
apluscw 187:92cbb9eec47b 202
apluscw 187:92cbb9eec47b 203 /** \brief Enable FIQ
apluscw 187:92cbb9eec47b 204
apluscw 187:92cbb9eec47b 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
apluscw 187:92cbb9eec47b 206 Can only be executed in Privileged modes.
apluscw 187:92cbb9eec47b 207 */
apluscw 187:92cbb9eec47b 208 #define __enable_fault_irq __enable_fiq
apluscw 187:92cbb9eec47b 209
apluscw 187:92cbb9eec47b 210
apluscw 187:92cbb9eec47b 211 /** \brief Disable FIQ
apluscw 187:92cbb9eec47b 212
apluscw 187:92cbb9eec47b 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
apluscw 187:92cbb9eec47b 214 Can only be executed in Privileged modes.
apluscw 187:92cbb9eec47b 215 */
apluscw 187:92cbb9eec47b 216 #define __disable_fault_irq __disable_fiq
apluscw 187:92cbb9eec47b 217
apluscw 187:92cbb9eec47b 218
apluscw 187:92cbb9eec47b 219 /** \brief Get Base Priority
apluscw 187:92cbb9eec47b 220
apluscw 187:92cbb9eec47b 221 This function returns the current value of the Base Priority register.
apluscw 187:92cbb9eec47b 222
apluscw 187:92cbb9eec47b 223 \return Base Priority register value
apluscw 187:92cbb9eec47b 224 */
apluscw 187:92cbb9eec47b 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
apluscw 187:92cbb9eec47b 226 {
apluscw 187:92cbb9eec47b 227 register uint32_t __regBasePri __ASM("basepri");
apluscw 187:92cbb9eec47b 228 return(__regBasePri);
apluscw 187:92cbb9eec47b 229 }
apluscw 187:92cbb9eec47b 230
apluscw 187:92cbb9eec47b 231
apluscw 187:92cbb9eec47b 232 /** \brief Set Base Priority
apluscw 187:92cbb9eec47b 233
apluscw 187:92cbb9eec47b 234 This function assigns the given value to the Base Priority register.
apluscw 187:92cbb9eec47b 235
apluscw 187:92cbb9eec47b 236 \param [in] basePri Base Priority value to set
apluscw 187:92cbb9eec47b 237 */
apluscw 187:92cbb9eec47b 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
apluscw 187:92cbb9eec47b 239 {
apluscw 187:92cbb9eec47b 240 register uint32_t __regBasePri __ASM("basepri");
apluscw 187:92cbb9eec47b 241 __regBasePri = (basePri & 0xff);
apluscw 187:92cbb9eec47b 242 }
apluscw 187:92cbb9eec47b 243
apluscw 187:92cbb9eec47b 244
apluscw 187:92cbb9eec47b 245 /** \brief Set Base Priority with condition
apluscw 187:92cbb9eec47b 246
apluscw 187:92cbb9eec47b 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
apluscw 187:92cbb9eec47b 248 or the new value increases the BASEPRI priority level.
apluscw 187:92cbb9eec47b 249
apluscw 187:92cbb9eec47b 250 \param [in] basePri Base Priority value to set
apluscw 187:92cbb9eec47b 251 */
apluscw 187:92cbb9eec47b 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
apluscw 187:92cbb9eec47b 253 {
apluscw 187:92cbb9eec47b 254 register uint32_t __regBasePriMax __ASM("basepri_max");
apluscw 187:92cbb9eec47b 255 __regBasePriMax = (basePri & 0xff);
apluscw 187:92cbb9eec47b 256 }
apluscw 187:92cbb9eec47b 257
apluscw 187:92cbb9eec47b 258
apluscw 187:92cbb9eec47b 259 /** \brief Get Fault Mask
apluscw 187:92cbb9eec47b 260
apluscw 187:92cbb9eec47b 261 This function returns the current value of the Fault Mask register.
apluscw 187:92cbb9eec47b 262
apluscw 187:92cbb9eec47b 263 \return Fault Mask register value
apluscw 187:92cbb9eec47b 264 */
apluscw 187:92cbb9eec47b 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
apluscw 187:92cbb9eec47b 266 {
apluscw 187:92cbb9eec47b 267 register uint32_t __regFaultMask __ASM("faultmask");
apluscw 187:92cbb9eec47b 268 return(__regFaultMask);
apluscw 187:92cbb9eec47b 269 }
apluscw 187:92cbb9eec47b 270
apluscw 187:92cbb9eec47b 271
apluscw 187:92cbb9eec47b 272 /** \brief Set Fault Mask
apluscw 187:92cbb9eec47b 273
apluscw 187:92cbb9eec47b 274 This function assigns the given value to the Fault Mask register.
apluscw 187:92cbb9eec47b 275
apluscw 187:92cbb9eec47b 276 \param [in] faultMask Fault Mask value to set
apluscw 187:92cbb9eec47b 277 */
apluscw 187:92cbb9eec47b 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
apluscw 187:92cbb9eec47b 279 {
apluscw 187:92cbb9eec47b 280 register uint32_t __regFaultMask __ASM("faultmask");
apluscw 187:92cbb9eec47b 281 __regFaultMask = (faultMask & (uint32_t)1);
apluscw 187:92cbb9eec47b 282 }
apluscw 187:92cbb9eec47b 283
apluscw 187:92cbb9eec47b 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
apluscw 187:92cbb9eec47b 285
apluscw 187:92cbb9eec47b 286
apluscw 187:92cbb9eec47b 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
apluscw 187:92cbb9eec47b 288
apluscw 187:92cbb9eec47b 289 /** \brief Get FPSCR
apluscw 187:92cbb9eec47b 290
apluscw 187:92cbb9eec47b 291 This function returns the current value of the Floating Point Status/Control register.
apluscw 187:92cbb9eec47b 292
apluscw 187:92cbb9eec47b 293 \return Floating Point Status/Control register value
apluscw 187:92cbb9eec47b 294 */
apluscw 187:92cbb9eec47b 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
apluscw 187:92cbb9eec47b 296 {
apluscw 187:92cbb9eec47b 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
apluscw 187:92cbb9eec47b 298 register uint32_t __regfpscr __ASM("fpscr");
apluscw 187:92cbb9eec47b 299 return(__regfpscr);
apluscw 187:92cbb9eec47b 300 #else
apluscw 187:92cbb9eec47b 301 return(0);
apluscw 187:92cbb9eec47b 302 #endif
apluscw 187:92cbb9eec47b 303 }
apluscw 187:92cbb9eec47b 304
apluscw 187:92cbb9eec47b 305
apluscw 187:92cbb9eec47b 306 /** \brief Set FPSCR
apluscw 187:92cbb9eec47b 307
apluscw 187:92cbb9eec47b 308 This function assigns the given value to the Floating Point Status/Control register.
apluscw 187:92cbb9eec47b 309
apluscw 187:92cbb9eec47b 310 \param [in] fpscr Floating Point Status/Control value to set
apluscw 187:92cbb9eec47b 311 */
apluscw 187:92cbb9eec47b 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
apluscw 187:92cbb9eec47b 313 {
apluscw 187:92cbb9eec47b 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
apluscw 187:92cbb9eec47b 315 register uint32_t __regfpscr __ASM("fpscr");
apluscw 187:92cbb9eec47b 316 __regfpscr = (fpscr);
apluscw 187:92cbb9eec47b 317 #endif
apluscw 187:92cbb9eec47b 318 }
apluscw 187:92cbb9eec47b 319
apluscw 187:92cbb9eec47b 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
apluscw 187:92cbb9eec47b 321
apluscw 187:92cbb9eec47b 322
apluscw 187:92cbb9eec47b 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
apluscw 187:92cbb9eec47b 324 /* GNU gcc specific functions */
apluscw 187:92cbb9eec47b 325
apluscw 187:92cbb9eec47b 326 /** \brief Enable IRQ Interrupts
apluscw 187:92cbb9eec47b 327
apluscw 187:92cbb9eec47b 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
apluscw 187:92cbb9eec47b 329 Can only be executed in Privileged modes.
apluscw 187:92cbb9eec47b 330 */
apluscw 187:92cbb9eec47b 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
apluscw 187:92cbb9eec47b 332 {
apluscw 187:92cbb9eec47b 333 __ASM volatile ("cpsie i" : : : "memory");
apluscw 187:92cbb9eec47b 334 }
apluscw 187:92cbb9eec47b 335
apluscw 187:92cbb9eec47b 336
apluscw 187:92cbb9eec47b 337 /** \brief Disable IRQ Interrupts
apluscw 187:92cbb9eec47b 338
apluscw 187:92cbb9eec47b 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
apluscw 187:92cbb9eec47b 340 Can only be executed in Privileged modes.
apluscw 187:92cbb9eec47b 341 */
apluscw 187:92cbb9eec47b 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
apluscw 187:92cbb9eec47b 343 {
apluscw 187:92cbb9eec47b 344 __ASM volatile ("cpsid i" : : : "memory");
apluscw 187:92cbb9eec47b 345 }
apluscw 187:92cbb9eec47b 346
apluscw 187:92cbb9eec47b 347
apluscw 187:92cbb9eec47b 348 /** \brief Get Control Register
apluscw 187:92cbb9eec47b 349
apluscw 187:92cbb9eec47b 350 This function returns the content of the Control Register.
apluscw 187:92cbb9eec47b 351
apluscw 187:92cbb9eec47b 352 \return Control Register value
apluscw 187:92cbb9eec47b 353 */
apluscw 187:92cbb9eec47b 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
apluscw 187:92cbb9eec47b 355 {
apluscw 187:92cbb9eec47b 356 uint32_t result;
apluscw 187:92cbb9eec47b 357
apluscw 187:92cbb9eec47b 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
apluscw 187:92cbb9eec47b 359 return(result);
apluscw 187:92cbb9eec47b 360 }
apluscw 187:92cbb9eec47b 361
apluscw 187:92cbb9eec47b 362
apluscw 187:92cbb9eec47b 363 /** \brief Set Control Register
apluscw 187:92cbb9eec47b 364
apluscw 187:92cbb9eec47b 365 This function writes the given value to the Control Register.
apluscw 187:92cbb9eec47b 366
apluscw 187:92cbb9eec47b 367 \param [in] control Control Register value to set
apluscw 187:92cbb9eec47b 368 */
apluscw 187:92cbb9eec47b 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
apluscw 187:92cbb9eec47b 370 {
apluscw 187:92cbb9eec47b 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
apluscw 187:92cbb9eec47b 372 }
apluscw 187:92cbb9eec47b 373
apluscw 187:92cbb9eec47b 374
apluscw 187:92cbb9eec47b 375 /** \brief Get IPSR Register
apluscw 187:92cbb9eec47b 376
apluscw 187:92cbb9eec47b 377 This function returns the content of the IPSR Register.
apluscw 187:92cbb9eec47b 378
apluscw 187:92cbb9eec47b 379 \return IPSR Register value
apluscw 187:92cbb9eec47b 380 */
apluscw 187:92cbb9eec47b 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
apluscw 187:92cbb9eec47b 382 {
apluscw 187:92cbb9eec47b 383 uint32_t result;
apluscw 187:92cbb9eec47b 384
apluscw 187:92cbb9eec47b 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
apluscw 187:92cbb9eec47b 386 return(result);
apluscw 187:92cbb9eec47b 387 }
apluscw 187:92cbb9eec47b 388
apluscw 187:92cbb9eec47b 389
apluscw 187:92cbb9eec47b 390 /** \brief Get APSR Register
apluscw 187:92cbb9eec47b 391
apluscw 187:92cbb9eec47b 392 This function returns the content of the APSR Register.
apluscw 187:92cbb9eec47b 393
apluscw 187:92cbb9eec47b 394 \return APSR Register value
apluscw 187:92cbb9eec47b 395 */
apluscw 187:92cbb9eec47b 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
apluscw 187:92cbb9eec47b 397 {
apluscw 187:92cbb9eec47b 398 uint32_t result;
apluscw 187:92cbb9eec47b 399
apluscw 187:92cbb9eec47b 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
apluscw 187:92cbb9eec47b 401 return(result);
apluscw 187:92cbb9eec47b 402 }
apluscw 187:92cbb9eec47b 403
apluscw 187:92cbb9eec47b 404
apluscw 187:92cbb9eec47b 405 /** \brief Get xPSR Register
apluscw 187:92cbb9eec47b 406
apluscw 187:92cbb9eec47b 407 This function returns the content of the xPSR Register.
apluscw 187:92cbb9eec47b 408
apluscw 187:92cbb9eec47b 409 \return xPSR Register value
apluscw 187:92cbb9eec47b 410 */
apluscw 187:92cbb9eec47b 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
apluscw 187:92cbb9eec47b 412 {
apluscw 187:92cbb9eec47b 413 uint32_t result;
apluscw 187:92cbb9eec47b 414
apluscw 187:92cbb9eec47b 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
apluscw 187:92cbb9eec47b 416 return(result);
apluscw 187:92cbb9eec47b 417 }
apluscw 187:92cbb9eec47b 418
apluscw 187:92cbb9eec47b 419
apluscw 187:92cbb9eec47b 420 /** \brief Get Process Stack Pointer
apluscw 187:92cbb9eec47b 421
apluscw 187:92cbb9eec47b 422 This function returns the current value of the Process Stack Pointer (PSP).
apluscw 187:92cbb9eec47b 423
apluscw 187:92cbb9eec47b 424 \return PSP Register value
apluscw 187:92cbb9eec47b 425 */
apluscw 187:92cbb9eec47b 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
apluscw 187:92cbb9eec47b 427 {
apluscw 187:92cbb9eec47b 428 register uint32_t result;
apluscw 187:92cbb9eec47b 429
apluscw 187:92cbb9eec47b 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
apluscw 187:92cbb9eec47b 431 return(result);
apluscw 187:92cbb9eec47b 432 }
apluscw 187:92cbb9eec47b 433
apluscw 187:92cbb9eec47b 434
apluscw 187:92cbb9eec47b 435 /** \brief Set Process Stack Pointer
apluscw 187:92cbb9eec47b 436
apluscw 187:92cbb9eec47b 437 This function assigns the given value to the Process Stack Pointer (PSP).
apluscw 187:92cbb9eec47b 438
apluscw 187:92cbb9eec47b 439 \param [in] topOfProcStack Process Stack Pointer value to set
apluscw 187:92cbb9eec47b 440 */
apluscw 187:92cbb9eec47b 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
apluscw 187:92cbb9eec47b 442 {
apluscw 187:92cbb9eec47b 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
apluscw 187:92cbb9eec47b 444 }
apluscw 187:92cbb9eec47b 445
apluscw 187:92cbb9eec47b 446
apluscw 187:92cbb9eec47b 447 /** \brief Get Main Stack Pointer
apluscw 187:92cbb9eec47b 448
apluscw 187:92cbb9eec47b 449 This function returns the current value of the Main Stack Pointer (MSP).
apluscw 187:92cbb9eec47b 450
apluscw 187:92cbb9eec47b 451 \return MSP Register value
apluscw 187:92cbb9eec47b 452 */
apluscw 187:92cbb9eec47b 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
apluscw 187:92cbb9eec47b 454 {
apluscw 187:92cbb9eec47b 455 register uint32_t result;
apluscw 187:92cbb9eec47b 456
apluscw 187:92cbb9eec47b 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
apluscw 187:92cbb9eec47b 458 return(result);
apluscw 187:92cbb9eec47b 459 }
apluscw 187:92cbb9eec47b 460
apluscw 187:92cbb9eec47b 461
apluscw 187:92cbb9eec47b 462 /** \brief Set Main Stack Pointer
apluscw 187:92cbb9eec47b 463
apluscw 187:92cbb9eec47b 464 This function assigns the given value to the Main Stack Pointer (MSP).
apluscw 187:92cbb9eec47b 465
apluscw 187:92cbb9eec47b 466 \param [in] topOfMainStack Main Stack Pointer value to set
apluscw 187:92cbb9eec47b 467 */
apluscw 187:92cbb9eec47b 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
apluscw 187:92cbb9eec47b 469 {
apluscw 187:92cbb9eec47b 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
apluscw 187:92cbb9eec47b 471 }
apluscw 187:92cbb9eec47b 472
apluscw 187:92cbb9eec47b 473
apluscw 187:92cbb9eec47b 474 /** \brief Get Priority Mask
apluscw 187:92cbb9eec47b 475
apluscw 187:92cbb9eec47b 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
apluscw 187:92cbb9eec47b 477
apluscw 187:92cbb9eec47b 478 \return Priority Mask value
apluscw 187:92cbb9eec47b 479 */
apluscw 187:92cbb9eec47b 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
apluscw 187:92cbb9eec47b 481 {
apluscw 187:92cbb9eec47b 482 uint32_t result;
apluscw 187:92cbb9eec47b 483
apluscw 187:92cbb9eec47b 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
apluscw 187:92cbb9eec47b 485 return(result);
apluscw 187:92cbb9eec47b 486 }
apluscw 187:92cbb9eec47b 487
apluscw 187:92cbb9eec47b 488
apluscw 187:92cbb9eec47b 489 /** \brief Set Priority Mask
apluscw 187:92cbb9eec47b 490
apluscw 187:92cbb9eec47b 491 This function assigns the given value to the Priority Mask Register.
apluscw 187:92cbb9eec47b 492
apluscw 187:92cbb9eec47b 493 \param [in] priMask Priority Mask
apluscw 187:92cbb9eec47b 494 */
apluscw 187:92cbb9eec47b 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
apluscw 187:92cbb9eec47b 496 {
apluscw 187:92cbb9eec47b 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
apluscw 187:92cbb9eec47b 498 }
apluscw 187:92cbb9eec47b 499
apluscw 187:92cbb9eec47b 500
apluscw 187:92cbb9eec47b 501 #if (__CORTEX_M >= 0x03)
apluscw 187:92cbb9eec47b 502
apluscw 187:92cbb9eec47b 503 /** \brief Enable FIQ
apluscw 187:92cbb9eec47b 504
apluscw 187:92cbb9eec47b 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
apluscw 187:92cbb9eec47b 506 Can only be executed in Privileged modes.
apluscw 187:92cbb9eec47b 507 */
apluscw 187:92cbb9eec47b 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
apluscw 187:92cbb9eec47b 509 {
apluscw 187:92cbb9eec47b 510 __ASM volatile ("cpsie f" : : : "memory");
apluscw 187:92cbb9eec47b 511 }
apluscw 187:92cbb9eec47b 512
apluscw 187:92cbb9eec47b 513
apluscw 187:92cbb9eec47b 514 /** \brief Disable FIQ
apluscw 187:92cbb9eec47b 515
apluscw 187:92cbb9eec47b 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
apluscw 187:92cbb9eec47b 517 Can only be executed in Privileged modes.
apluscw 187:92cbb9eec47b 518 */
apluscw 187:92cbb9eec47b 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
apluscw 187:92cbb9eec47b 520 {
apluscw 187:92cbb9eec47b 521 __ASM volatile ("cpsid f" : : : "memory");
apluscw 187:92cbb9eec47b 522 }
apluscw 187:92cbb9eec47b 523
apluscw 187:92cbb9eec47b 524
apluscw 187:92cbb9eec47b 525 /** \brief Get Base Priority
apluscw 187:92cbb9eec47b 526
apluscw 187:92cbb9eec47b 527 This function returns the current value of the Base Priority register.
apluscw 187:92cbb9eec47b 528
apluscw 187:92cbb9eec47b 529 \return Base Priority register value
apluscw 187:92cbb9eec47b 530 */
apluscw 187:92cbb9eec47b 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
apluscw 187:92cbb9eec47b 532 {
apluscw 187:92cbb9eec47b 533 uint32_t result;
apluscw 187:92cbb9eec47b 534
apluscw 187:92cbb9eec47b 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
apluscw 187:92cbb9eec47b 536 return(result);
apluscw 187:92cbb9eec47b 537 }
apluscw 187:92cbb9eec47b 538
apluscw 187:92cbb9eec47b 539
apluscw 187:92cbb9eec47b 540 /** \brief Set Base Priority
apluscw 187:92cbb9eec47b 541
apluscw 187:92cbb9eec47b 542 This function assigns the given value to the Base Priority register.
apluscw 187:92cbb9eec47b 543
apluscw 187:92cbb9eec47b 544 \param [in] basePri Base Priority value to set
apluscw 187:92cbb9eec47b 545 */
apluscw 187:92cbb9eec47b 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
apluscw 187:92cbb9eec47b 547 {
apluscw 187:92cbb9eec47b 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
apluscw 187:92cbb9eec47b 549 }
apluscw 187:92cbb9eec47b 550
apluscw 187:92cbb9eec47b 551
apluscw 187:92cbb9eec47b 552 /** \brief Set Base Priority with condition
apluscw 187:92cbb9eec47b 553
apluscw 187:92cbb9eec47b 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
apluscw 187:92cbb9eec47b 555 or the new value increases the BASEPRI priority level.
apluscw 187:92cbb9eec47b 556
apluscw 187:92cbb9eec47b 557 \param [in] basePri Base Priority value to set
apluscw 187:92cbb9eec47b 558 */
apluscw 187:92cbb9eec47b 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
apluscw 187:92cbb9eec47b 560 {
apluscw 187:92cbb9eec47b 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
apluscw 187:92cbb9eec47b 562 }
apluscw 187:92cbb9eec47b 563
apluscw 187:92cbb9eec47b 564
apluscw 187:92cbb9eec47b 565 /** \brief Get Fault Mask
apluscw 187:92cbb9eec47b 566
apluscw 187:92cbb9eec47b 567 This function returns the current value of the Fault Mask register.
apluscw 187:92cbb9eec47b 568
apluscw 187:92cbb9eec47b 569 \return Fault Mask register value
apluscw 187:92cbb9eec47b 570 */
apluscw 187:92cbb9eec47b 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
apluscw 187:92cbb9eec47b 572 {
apluscw 187:92cbb9eec47b 573 uint32_t result;
apluscw 187:92cbb9eec47b 574
apluscw 187:92cbb9eec47b 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
apluscw 187:92cbb9eec47b 576 return(result);
apluscw 187:92cbb9eec47b 577 }
apluscw 187:92cbb9eec47b 578
apluscw 187:92cbb9eec47b 579
apluscw 187:92cbb9eec47b 580 /** \brief Set Fault Mask
apluscw 187:92cbb9eec47b 581
apluscw 187:92cbb9eec47b 582 This function assigns the given value to the Fault Mask register.
apluscw 187:92cbb9eec47b 583
apluscw 187:92cbb9eec47b 584 \param [in] faultMask Fault Mask value to set
apluscw 187:92cbb9eec47b 585 */
apluscw 187:92cbb9eec47b 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
apluscw 187:92cbb9eec47b 587 {
apluscw 187:92cbb9eec47b 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
apluscw 187:92cbb9eec47b 589 }
apluscw 187:92cbb9eec47b 590
apluscw 187:92cbb9eec47b 591 #endif /* (__CORTEX_M >= 0x03) */
apluscw 187:92cbb9eec47b 592
apluscw 187:92cbb9eec47b 593
apluscw 187:92cbb9eec47b 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
apluscw 187:92cbb9eec47b 595
apluscw 187:92cbb9eec47b 596 /** \brief Get FPSCR
apluscw 187:92cbb9eec47b 597
apluscw 187:92cbb9eec47b 598 This function returns the current value of the Floating Point Status/Control register.
apluscw 187:92cbb9eec47b 599
apluscw 187:92cbb9eec47b 600 \return Floating Point Status/Control register value
apluscw 187:92cbb9eec47b 601 */
apluscw 187:92cbb9eec47b 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
apluscw 187:92cbb9eec47b 603 {
apluscw 187:92cbb9eec47b 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
apluscw 187:92cbb9eec47b 605 uint32_t result;
apluscw 187:92cbb9eec47b 606
apluscw 187:92cbb9eec47b 607 /* Empty asm statement works as a scheduling barrier */
apluscw 187:92cbb9eec47b 608 __ASM volatile ("");
apluscw 187:92cbb9eec47b 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
apluscw 187:92cbb9eec47b 610 __ASM volatile ("");
apluscw 187:92cbb9eec47b 611 return(result);
apluscw 187:92cbb9eec47b 612 #else
apluscw 187:92cbb9eec47b 613 return(0);
apluscw 187:92cbb9eec47b 614 #endif
apluscw 187:92cbb9eec47b 615 }
apluscw 187:92cbb9eec47b 616
apluscw 187:92cbb9eec47b 617
apluscw 187:92cbb9eec47b 618 /** \brief Set FPSCR
apluscw 187:92cbb9eec47b 619
apluscw 187:92cbb9eec47b 620 This function assigns the given value to the Floating Point Status/Control register.
apluscw 187:92cbb9eec47b 621
apluscw 187:92cbb9eec47b 622 \param [in] fpscr Floating Point Status/Control value to set
apluscw 187:92cbb9eec47b 623 */
apluscw 187:92cbb9eec47b 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
apluscw 187:92cbb9eec47b 625 {
apluscw 187:92cbb9eec47b 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
apluscw 187:92cbb9eec47b 627 /* Empty asm statement works as a scheduling barrier */
apluscw 187:92cbb9eec47b 628 __ASM volatile ("");
apluscw 187:92cbb9eec47b 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
apluscw 187:92cbb9eec47b 630 __ASM volatile ("");
apluscw 187:92cbb9eec47b 631 #endif
apluscw 187:92cbb9eec47b 632 }
apluscw 187:92cbb9eec47b 633
apluscw 187:92cbb9eec47b 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
apluscw 187:92cbb9eec47b 635
apluscw 187:92cbb9eec47b 636
apluscw 187:92cbb9eec47b 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
apluscw 187:92cbb9eec47b 638 /* IAR iccarm specific functions */
apluscw 187:92cbb9eec47b 639 #include <cmsis_iar.h>
apluscw 187:92cbb9eec47b 640
apluscw 187:92cbb9eec47b 641
apluscw 187:92cbb9eec47b 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
apluscw 187:92cbb9eec47b 643 /* TI CCS specific functions */
apluscw 187:92cbb9eec47b 644 #include <cmsis_ccs.h>
apluscw 187:92cbb9eec47b 645
apluscw 187:92cbb9eec47b 646
apluscw 187:92cbb9eec47b 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
apluscw 187:92cbb9eec47b 648 /* TASKING carm specific functions */
apluscw 187:92cbb9eec47b 649 /*
apluscw 187:92cbb9eec47b 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
apluscw 187:92cbb9eec47b 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
apluscw 187:92cbb9eec47b 652 * Including the CMSIS ones.
apluscw 187:92cbb9eec47b 653 */
apluscw 187:92cbb9eec47b 654
apluscw 187:92cbb9eec47b 655
apluscw 187:92cbb9eec47b 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
apluscw 187:92cbb9eec47b 657 /* Cosmic specific functions */
apluscw 187:92cbb9eec47b 658 #include <cmsis_csm.h>
apluscw 187:92cbb9eec47b 659
apluscw 187:92cbb9eec47b 660 #endif
apluscw 187:92cbb9eec47b 661
apluscw 187:92cbb9eec47b 662 /*@} end of CMSIS_Core_RegAccFunctions */
apluscw 187:92cbb9eec47b 663
apluscw 187:92cbb9eec47b 664 #endif /* __CORE_CMFUNC_H */