Thor Hall / mbed-dev_mbed_lib_v125

This fork captures the mbed lib v125 for ease of integration into older projects.

Fork of mbed-dev by mbed official

targets/cmsis/core_cm0.h@187:92cbb9eec47b, 2018-07-20 (annotated)

Committer:
apluscw
Date:
Fri Jul 20 21:24:42 2018 +0000
Revision:
187:92cbb9eec47b
Mbed library with source code from mbed lib v125. Posted to ease integration with some older projects.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
apluscw 187:92cbb9eec47b 1 /**************************************************************************//**
apluscw 187:92cbb9eec47b 2 * @file core_cm0.h
apluscw 187:92cbb9eec47b 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
apluscw 187:92cbb9eec47b 4 * @version V4.10
apluscw 187:92cbb9eec47b 5 * @date 18. March 2015
apluscw 187:92cbb9eec47b 6 *
apluscw 187:92cbb9eec47b 7 * @note
apluscw 187:92cbb9eec47b 8 *
apluscw 187:92cbb9eec47b 9 ******************************************************************************/
apluscw 187:92cbb9eec47b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
apluscw 187:92cbb9eec47b 11
apluscw 187:92cbb9eec47b 12 All rights reserved.
apluscw 187:92cbb9eec47b 13 Redistribution and use in source and binary forms, with or without
apluscw 187:92cbb9eec47b 14 modification, are permitted provided that the following conditions are met:
apluscw 187:92cbb9eec47b 15 - Redistributions of source code must retain the above copyright
apluscw 187:92cbb9eec47b 16 notice, this list of conditions and the following disclaimer.
apluscw 187:92cbb9eec47b 17 - Redistributions in binary form must reproduce the above copyright
apluscw 187:92cbb9eec47b 18 notice, this list of conditions and the following disclaimer in the
apluscw 187:92cbb9eec47b 19 documentation and/or other materials provided with the distribution.
apluscw 187:92cbb9eec47b 20 - Neither the name of ARM nor the names of its contributors may be used
apluscw 187:92cbb9eec47b 21 to endorse or promote products derived from this software without
apluscw 187:92cbb9eec47b 22 specific prior written permission.
apluscw 187:92cbb9eec47b 23 *
apluscw 187:92cbb9eec47b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
apluscw 187:92cbb9eec47b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
apluscw 187:92cbb9eec47b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
apluscw 187:92cbb9eec47b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
apluscw 187:92cbb9eec47b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
apluscw 187:92cbb9eec47b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
apluscw 187:92cbb9eec47b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
apluscw 187:92cbb9eec47b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
apluscw 187:92cbb9eec47b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
apluscw 187:92cbb9eec47b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
apluscw 187:92cbb9eec47b 34 POSSIBILITY OF SUCH DAMAGE.
apluscw 187:92cbb9eec47b 35 ---------------------------------------------------------------------------*/
apluscw 187:92cbb9eec47b 36
apluscw 187:92cbb9eec47b 37
apluscw 187:92cbb9eec47b 38 #if defined ( __ICCARM__ )
apluscw 187:92cbb9eec47b 39 #pragma system_include /* treat file as system include file for MISRA check */
apluscw 187:92cbb9eec47b 40 #endif
apluscw 187:92cbb9eec47b 41
apluscw 187:92cbb9eec47b 42 #ifndef __CORE_CM0_H_GENERIC
apluscw 187:92cbb9eec47b 43 #define __CORE_CM0_H_GENERIC
apluscw 187:92cbb9eec47b 44
apluscw 187:92cbb9eec47b 45 #ifdef __cplusplus
apluscw 187:92cbb9eec47b 46 extern "C" {
apluscw 187:92cbb9eec47b 47 #endif
apluscw 187:92cbb9eec47b 48
apluscw 187:92cbb9eec47b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
apluscw 187:92cbb9eec47b 50 CMSIS violates the following MISRA-C:2004 rules:
apluscw 187:92cbb9eec47b 51
apluscw 187:92cbb9eec47b 52 \li Required Rule 8.5, object/function definition in header file.<br>
apluscw 187:92cbb9eec47b 53 Function definitions in header files are used to allow 'inlining'.
apluscw 187:92cbb9eec47b 54
apluscw 187:92cbb9eec47b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
apluscw 187:92cbb9eec47b 56 Unions are used for effective representation of core registers.
apluscw 187:92cbb9eec47b 57
apluscw 187:92cbb9eec47b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
apluscw 187:92cbb9eec47b 59 Function-like macros are used to allow more efficient code.
apluscw 187:92cbb9eec47b 60 */
apluscw 187:92cbb9eec47b 61
apluscw 187:92cbb9eec47b 62
apluscw 187:92cbb9eec47b 63 /*******************************************************************************
apluscw 187:92cbb9eec47b 64 * CMSIS definitions
apluscw 187:92cbb9eec47b 65 ******************************************************************************/
apluscw 187:92cbb9eec47b 66 /** \ingroup Cortex_M0
apluscw 187:92cbb9eec47b 67 @{
apluscw 187:92cbb9eec47b 68 */
apluscw 187:92cbb9eec47b 69
apluscw 187:92cbb9eec47b 70 /* CMSIS CM0 definitions */
apluscw 187:92cbb9eec47b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
apluscw 187:92cbb9eec47b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
apluscw 187:92cbb9eec47b 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
apluscw 187:92cbb9eec47b 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
apluscw 187:92cbb9eec47b 75
apluscw 187:92cbb9eec47b 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
apluscw 187:92cbb9eec47b 77
apluscw 187:92cbb9eec47b 78
apluscw 187:92cbb9eec47b 79 #if defined ( __CC_ARM )
apluscw 187:92cbb9eec47b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
apluscw 187:92cbb9eec47b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
apluscw 187:92cbb9eec47b 82 #define __STATIC_INLINE static __inline
apluscw 187:92cbb9eec47b 83
apluscw 187:92cbb9eec47b 84 #elif defined ( __GNUC__ )
apluscw 187:92cbb9eec47b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
apluscw 187:92cbb9eec47b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
apluscw 187:92cbb9eec47b 87 #define __STATIC_INLINE static inline
apluscw 187:92cbb9eec47b 88
apluscw 187:92cbb9eec47b 89 #elif defined ( __ICCARM__ )
apluscw 187:92cbb9eec47b 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
apluscw 187:92cbb9eec47b 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
apluscw 187:92cbb9eec47b 92 #define __STATIC_INLINE static inline
apluscw 187:92cbb9eec47b 93
apluscw 187:92cbb9eec47b 94 #elif defined ( __TMS470__ )
apluscw 187:92cbb9eec47b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
apluscw 187:92cbb9eec47b 96 #define __STATIC_INLINE static inline
apluscw 187:92cbb9eec47b 97
apluscw 187:92cbb9eec47b 98 #elif defined ( __TASKING__ )
apluscw 187:92cbb9eec47b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
apluscw 187:92cbb9eec47b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
apluscw 187:92cbb9eec47b 101 #define __STATIC_INLINE static inline
apluscw 187:92cbb9eec47b 102
apluscw 187:92cbb9eec47b 103 #elif defined ( __CSMC__ )
apluscw 187:92cbb9eec47b 104 #define __packed
apluscw 187:92cbb9eec47b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
apluscw 187:92cbb9eec47b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
apluscw 187:92cbb9eec47b 107 #define __STATIC_INLINE static inline
apluscw 187:92cbb9eec47b 108
apluscw 187:92cbb9eec47b 109 #endif
apluscw 187:92cbb9eec47b 110
apluscw 187:92cbb9eec47b 111 /** __FPU_USED indicates whether an FPU is used or not.
apluscw 187:92cbb9eec47b 112 This core does not support an FPU at all
apluscw 187:92cbb9eec47b 113 */
apluscw 187:92cbb9eec47b 114 #define __FPU_USED 0
apluscw 187:92cbb9eec47b 115
apluscw 187:92cbb9eec47b 116 #if defined ( __CC_ARM )
apluscw 187:92cbb9eec47b 117 #if defined __TARGET_FPU_VFP
apluscw 187:92cbb9eec47b 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
apluscw 187:92cbb9eec47b 119 #endif
apluscw 187:92cbb9eec47b 120
apluscw 187:92cbb9eec47b 121 #elif defined ( __GNUC__ )
apluscw 187:92cbb9eec47b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
apluscw 187:92cbb9eec47b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
apluscw 187:92cbb9eec47b 124 #endif
apluscw 187:92cbb9eec47b 125
apluscw 187:92cbb9eec47b 126 #elif defined ( __ICCARM__ )
apluscw 187:92cbb9eec47b 127 #if defined __ARMVFP__
apluscw 187:92cbb9eec47b 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
apluscw 187:92cbb9eec47b 129 #endif
apluscw 187:92cbb9eec47b 130
apluscw 187:92cbb9eec47b 131 #elif defined ( __TMS470__ )
apluscw 187:92cbb9eec47b 132 #if defined __TI__VFP_SUPPORT____
apluscw 187:92cbb9eec47b 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
apluscw 187:92cbb9eec47b 134 #endif
apluscw 187:92cbb9eec47b 135
apluscw 187:92cbb9eec47b 136 #elif defined ( __TASKING__ )
apluscw 187:92cbb9eec47b 137 #if defined __FPU_VFP__
apluscw 187:92cbb9eec47b 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
apluscw 187:92cbb9eec47b 139 #endif
apluscw 187:92cbb9eec47b 140
apluscw 187:92cbb9eec47b 141 #elif defined ( __CSMC__ ) /* Cosmic */
apluscw 187:92cbb9eec47b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
apluscw 187:92cbb9eec47b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
apluscw 187:92cbb9eec47b 144 #endif
apluscw 187:92cbb9eec47b 145 #endif
apluscw 187:92cbb9eec47b 146
apluscw 187:92cbb9eec47b 147 #include <stdint.h> /* standard types definitions */
apluscw 187:92cbb9eec47b 148 #include <core_cmInstr.h> /* Core Instruction Access */
apluscw 187:92cbb9eec47b 149 #include <core_cmFunc.h> /* Core Function Access */
apluscw 187:92cbb9eec47b 150
apluscw 187:92cbb9eec47b 151 #ifdef __cplusplus
apluscw 187:92cbb9eec47b 152 }
apluscw 187:92cbb9eec47b 153 #endif
apluscw 187:92cbb9eec47b 154
apluscw 187:92cbb9eec47b 155 #endif /* __CORE_CM0_H_GENERIC */
apluscw 187:92cbb9eec47b 156
apluscw 187:92cbb9eec47b 157 #ifndef __CMSIS_GENERIC
apluscw 187:92cbb9eec47b 158
apluscw 187:92cbb9eec47b 159 #ifndef __CORE_CM0_H_DEPENDANT
apluscw 187:92cbb9eec47b 160 #define __CORE_CM0_H_DEPENDANT
apluscw 187:92cbb9eec47b 161
apluscw 187:92cbb9eec47b 162 #ifdef __cplusplus
apluscw 187:92cbb9eec47b 163 extern "C" {
apluscw 187:92cbb9eec47b 164 #endif
apluscw 187:92cbb9eec47b 165
apluscw 187:92cbb9eec47b 166 /* check device defines and use defaults */
apluscw 187:92cbb9eec47b 167 #if defined __CHECK_DEVICE_DEFINES
apluscw 187:92cbb9eec47b 168 #ifndef __CM0_REV
apluscw 187:92cbb9eec47b 169 #define __CM0_REV 0x0000
apluscw 187:92cbb9eec47b 170 #warning "__CM0_REV not defined in device header file; using default!"
apluscw 187:92cbb9eec47b 171 #endif
apluscw 187:92cbb9eec47b 172
apluscw 187:92cbb9eec47b 173 #ifndef __NVIC_PRIO_BITS
apluscw 187:92cbb9eec47b 174 #define __NVIC_PRIO_BITS 2
apluscw 187:92cbb9eec47b 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
apluscw 187:92cbb9eec47b 176 #endif
apluscw 187:92cbb9eec47b 177
apluscw 187:92cbb9eec47b 178 #ifndef __Vendor_SysTickConfig
apluscw 187:92cbb9eec47b 179 #define __Vendor_SysTickConfig 0
apluscw 187:92cbb9eec47b 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
apluscw 187:92cbb9eec47b 181 #endif
apluscw 187:92cbb9eec47b 182 #endif
apluscw 187:92cbb9eec47b 183
apluscw 187:92cbb9eec47b 184 /* IO definitions (access restrictions to peripheral registers) */
apluscw 187:92cbb9eec47b 185 /**
apluscw 187:92cbb9eec47b 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
apluscw 187:92cbb9eec47b 187
apluscw 187:92cbb9eec47b 188 <strong>IO Type Qualifiers</strong> are used
apluscw 187:92cbb9eec47b 189 \li to specify the access to peripheral variables.
apluscw 187:92cbb9eec47b 190 \li for automatic generation of peripheral register debug information.
apluscw 187:92cbb9eec47b 191 */
apluscw 187:92cbb9eec47b 192 #ifdef __cplusplus
apluscw 187:92cbb9eec47b 193 #define __I volatile /*!< Defines 'read only' permissions */
apluscw 187:92cbb9eec47b 194 #else
apluscw 187:92cbb9eec47b 195 #define __I volatile const /*!< Defines 'read only' permissions */
apluscw 187:92cbb9eec47b 196 #endif
apluscw 187:92cbb9eec47b 197 #define __O volatile /*!< Defines 'write only' permissions */
apluscw 187:92cbb9eec47b 198 #define __IO volatile /*!< Defines 'read / write' permissions */
apluscw 187:92cbb9eec47b 199
apluscw 187:92cbb9eec47b 200 /*@} end of group Cortex_M0 */
apluscw 187:92cbb9eec47b 201
apluscw 187:92cbb9eec47b 202
apluscw 187:92cbb9eec47b 203
apluscw 187:92cbb9eec47b 204 /*******************************************************************************
apluscw 187:92cbb9eec47b 205 * Register Abstraction
apluscw 187:92cbb9eec47b 206 Core Register contain:
apluscw 187:92cbb9eec47b 207 - Core Register
apluscw 187:92cbb9eec47b 208 - Core NVIC Register
apluscw 187:92cbb9eec47b 209 - Core SCB Register
apluscw 187:92cbb9eec47b 210 - Core SysTick Register
apluscw 187:92cbb9eec47b 211 ******************************************************************************/
apluscw 187:92cbb9eec47b 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
apluscw 187:92cbb9eec47b 213 \brief Type definitions and defines for Cortex-M processor based devices.
apluscw 187:92cbb9eec47b 214 */
apluscw 187:92cbb9eec47b 215
apluscw 187:92cbb9eec47b 216 /** \ingroup CMSIS_core_register
apluscw 187:92cbb9eec47b 217 \defgroup CMSIS_CORE Status and Control Registers
apluscw 187:92cbb9eec47b 218 \brief Core Register type definitions.
apluscw 187:92cbb9eec47b 219 @{
apluscw 187:92cbb9eec47b 220 */
apluscw 187:92cbb9eec47b 221
apluscw 187:92cbb9eec47b 222 /** \brief Union type to access the Application Program Status Register (APSR).
apluscw 187:92cbb9eec47b 223 */
apluscw 187:92cbb9eec47b 224 typedef union
apluscw 187:92cbb9eec47b 225 {
apluscw 187:92cbb9eec47b 226 struct
apluscw 187:92cbb9eec47b 227 {
apluscw 187:92cbb9eec47b 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
apluscw 187:92cbb9eec47b 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
apluscw 187:92cbb9eec47b 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
apluscw 187:92cbb9eec47b 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
apluscw 187:92cbb9eec47b 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
apluscw 187:92cbb9eec47b 233 } b; /*!< Structure used for bit access */
apluscw 187:92cbb9eec47b 234 uint32_t w; /*!< Type used for word access */
apluscw 187:92cbb9eec47b 235 } APSR_Type;
apluscw 187:92cbb9eec47b 236
apluscw 187:92cbb9eec47b 237 /* APSR Register Definitions */
apluscw 187:92cbb9eec47b 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
apluscw 187:92cbb9eec47b 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
apluscw 187:92cbb9eec47b 240
apluscw 187:92cbb9eec47b 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
apluscw 187:92cbb9eec47b 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
apluscw 187:92cbb9eec47b 243
apluscw 187:92cbb9eec47b 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
apluscw 187:92cbb9eec47b 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
apluscw 187:92cbb9eec47b 246
apluscw 187:92cbb9eec47b 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
apluscw 187:92cbb9eec47b 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
apluscw 187:92cbb9eec47b 249
apluscw 187:92cbb9eec47b 250
apluscw 187:92cbb9eec47b 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
apluscw 187:92cbb9eec47b 252 */
apluscw 187:92cbb9eec47b 253 typedef union
apluscw 187:92cbb9eec47b 254 {
apluscw 187:92cbb9eec47b 255 struct
apluscw 187:92cbb9eec47b 256 {
apluscw 187:92cbb9eec47b 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
apluscw 187:92cbb9eec47b 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
apluscw 187:92cbb9eec47b 259 } b; /*!< Structure used for bit access */
apluscw 187:92cbb9eec47b 260 uint32_t w; /*!< Type used for word access */
apluscw 187:92cbb9eec47b 261 } IPSR_Type;
apluscw 187:92cbb9eec47b 262
apluscw 187:92cbb9eec47b 263 /* IPSR Register Definitions */
apluscw 187:92cbb9eec47b 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
apluscw 187:92cbb9eec47b 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
apluscw 187:92cbb9eec47b 266
apluscw 187:92cbb9eec47b 267
apluscw 187:92cbb9eec47b 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
apluscw 187:92cbb9eec47b 269 */
apluscw 187:92cbb9eec47b 270 typedef union
apluscw 187:92cbb9eec47b 271 {
apluscw 187:92cbb9eec47b 272 struct
apluscw 187:92cbb9eec47b 273 {
apluscw 187:92cbb9eec47b 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
apluscw 187:92cbb9eec47b 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
apluscw 187:92cbb9eec47b 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
apluscw 187:92cbb9eec47b 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
apluscw 187:92cbb9eec47b 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
apluscw 187:92cbb9eec47b 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
apluscw 187:92cbb9eec47b 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
apluscw 187:92cbb9eec47b 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
apluscw 187:92cbb9eec47b 282 } b; /*!< Structure used for bit access */
apluscw 187:92cbb9eec47b 283 uint32_t w; /*!< Type used for word access */
apluscw 187:92cbb9eec47b 284 } xPSR_Type;
apluscw 187:92cbb9eec47b 285
apluscw 187:92cbb9eec47b 286 /* xPSR Register Definitions */
apluscw 187:92cbb9eec47b 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
apluscw 187:92cbb9eec47b 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
apluscw 187:92cbb9eec47b 289
apluscw 187:92cbb9eec47b 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
apluscw 187:92cbb9eec47b 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
apluscw 187:92cbb9eec47b 292
apluscw 187:92cbb9eec47b 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
apluscw 187:92cbb9eec47b 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
apluscw 187:92cbb9eec47b 295
apluscw 187:92cbb9eec47b 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
apluscw 187:92cbb9eec47b 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
apluscw 187:92cbb9eec47b 298
apluscw 187:92cbb9eec47b 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
apluscw 187:92cbb9eec47b 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
apluscw 187:92cbb9eec47b 301
apluscw 187:92cbb9eec47b 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
apluscw 187:92cbb9eec47b 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
apluscw 187:92cbb9eec47b 304
apluscw 187:92cbb9eec47b 305
apluscw 187:92cbb9eec47b 306 /** \brief Union type to access the Control Registers (CONTROL).
apluscw 187:92cbb9eec47b 307 */
apluscw 187:92cbb9eec47b 308 typedef union
apluscw 187:92cbb9eec47b 309 {
apluscw 187:92cbb9eec47b 310 struct
apluscw 187:92cbb9eec47b 311 {
apluscw 187:92cbb9eec47b 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
apluscw 187:92cbb9eec47b 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
apluscw 187:92cbb9eec47b 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
apluscw 187:92cbb9eec47b 315 } b; /*!< Structure used for bit access */
apluscw 187:92cbb9eec47b 316 uint32_t w; /*!< Type used for word access */
apluscw 187:92cbb9eec47b 317 } CONTROL_Type;
apluscw 187:92cbb9eec47b 318
apluscw 187:92cbb9eec47b 319 /* CONTROL Register Definitions */
apluscw 187:92cbb9eec47b 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
apluscw 187:92cbb9eec47b 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
apluscw 187:92cbb9eec47b 322
apluscw 187:92cbb9eec47b 323 /*@} end of group CMSIS_CORE */
apluscw 187:92cbb9eec47b 324
apluscw 187:92cbb9eec47b 325
apluscw 187:92cbb9eec47b 326 /** \ingroup CMSIS_core_register
apluscw 187:92cbb9eec47b 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
apluscw 187:92cbb9eec47b 328 \brief Type definitions for the NVIC Registers
apluscw 187:92cbb9eec47b 329 @{
apluscw 187:92cbb9eec47b 330 */
apluscw 187:92cbb9eec47b 331
apluscw 187:92cbb9eec47b 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
apluscw 187:92cbb9eec47b 333 */
apluscw 187:92cbb9eec47b 334 typedef struct
apluscw 187:92cbb9eec47b 335 {
apluscw 187:92cbb9eec47b 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
apluscw 187:92cbb9eec47b 337 uint32_t RESERVED0[31];
apluscw 187:92cbb9eec47b 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
apluscw 187:92cbb9eec47b 339 uint32_t RSERVED1[31];
apluscw 187:92cbb9eec47b 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
apluscw 187:92cbb9eec47b 341 uint32_t RESERVED2[31];
apluscw 187:92cbb9eec47b 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
apluscw 187:92cbb9eec47b 343 uint32_t RESERVED3[31];
apluscw 187:92cbb9eec47b 344 uint32_t RESERVED4[64];
apluscw 187:92cbb9eec47b 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
apluscw 187:92cbb9eec47b 346 } NVIC_Type;
apluscw 187:92cbb9eec47b 347
apluscw 187:92cbb9eec47b 348 /*@} end of group CMSIS_NVIC */
apluscw 187:92cbb9eec47b 349
apluscw 187:92cbb9eec47b 350
apluscw 187:92cbb9eec47b 351 /** \ingroup CMSIS_core_register
apluscw 187:92cbb9eec47b 352 \defgroup CMSIS_SCB System Control Block (SCB)
apluscw 187:92cbb9eec47b 353 \brief Type definitions for the System Control Block Registers
apluscw 187:92cbb9eec47b 354 @{
apluscw 187:92cbb9eec47b 355 */
apluscw 187:92cbb9eec47b 356
apluscw 187:92cbb9eec47b 357 /** \brief Structure type to access the System Control Block (SCB).
apluscw 187:92cbb9eec47b 358 */
apluscw 187:92cbb9eec47b 359 typedef struct
apluscw 187:92cbb9eec47b 360 {
apluscw 187:92cbb9eec47b 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
apluscw 187:92cbb9eec47b 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
apluscw 187:92cbb9eec47b 363 uint32_t RESERVED0;
apluscw 187:92cbb9eec47b 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
apluscw 187:92cbb9eec47b 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
apluscw 187:92cbb9eec47b 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
apluscw 187:92cbb9eec47b 367 uint32_t RESERVED1;
apluscw 187:92cbb9eec47b 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
apluscw 187:92cbb9eec47b 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
apluscw 187:92cbb9eec47b 370 } SCB_Type;
apluscw 187:92cbb9eec47b 371
apluscw 187:92cbb9eec47b 372 /* SCB CPUID Register Definitions */
apluscw 187:92cbb9eec47b 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
apluscw 187:92cbb9eec47b 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
apluscw 187:92cbb9eec47b 375
apluscw 187:92cbb9eec47b 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
apluscw 187:92cbb9eec47b 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
apluscw 187:92cbb9eec47b 378
apluscw 187:92cbb9eec47b 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
apluscw 187:92cbb9eec47b 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
apluscw 187:92cbb9eec47b 381
apluscw 187:92cbb9eec47b 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
apluscw 187:92cbb9eec47b 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
apluscw 187:92cbb9eec47b 384
apluscw 187:92cbb9eec47b 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
apluscw 187:92cbb9eec47b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
apluscw 187:92cbb9eec47b 387
apluscw 187:92cbb9eec47b 388 /* SCB Interrupt Control State Register Definitions */
apluscw 187:92cbb9eec47b 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
apluscw 187:92cbb9eec47b 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
apluscw 187:92cbb9eec47b 391
apluscw 187:92cbb9eec47b 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
apluscw 187:92cbb9eec47b 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
apluscw 187:92cbb9eec47b 394
apluscw 187:92cbb9eec47b 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
apluscw 187:92cbb9eec47b 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
apluscw 187:92cbb9eec47b 397
apluscw 187:92cbb9eec47b 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
apluscw 187:92cbb9eec47b 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
apluscw 187:92cbb9eec47b 400
apluscw 187:92cbb9eec47b 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
apluscw 187:92cbb9eec47b 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
apluscw 187:92cbb9eec47b 403
apluscw 187:92cbb9eec47b 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
apluscw 187:92cbb9eec47b 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
apluscw 187:92cbb9eec47b 406
apluscw 187:92cbb9eec47b 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
apluscw 187:92cbb9eec47b 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
apluscw 187:92cbb9eec47b 409
apluscw 187:92cbb9eec47b 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
apluscw 187:92cbb9eec47b 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
apluscw 187:92cbb9eec47b 412
apluscw 187:92cbb9eec47b 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
apluscw 187:92cbb9eec47b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
apluscw 187:92cbb9eec47b 415
apluscw 187:92cbb9eec47b 416 /* SCB Application Interrupt and Reset Control Register Definitions */
apluscw 187:92cbb9eec47b 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
apluscw 187:92cbb9eec47b 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
apluscw 187:92cbb9eec47b 419
apluscw 187:92cbb9eec47b 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
apluscw 187:92cbb9eec47b 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
apluscw 187:92cbb9eec47b 422
apluscw 187:92cbb9eec47b 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
apluscw 187:92cbb9eec47b 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
apluscw 187:92cbb9eec47b 425
apluscw 187:92cbb9eec47b 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
apluscw 187:92cbb9eec47b 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
apluscw 187:92cbb9eec47b 428
apluscw 187:92cbb9eec47b 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
apluscw 187:92cbb9eec47b 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
apluscw 187:92cbb9eec47b 431
apluscw 187:92cbb9eec47b 432 /* SCB System Control Register Definitions */
apluscw 187:92cbb9eec47b 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
apluscw 187:92cbb9eec47b 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
apluscw 187:92cbb9eec47b 435
apluscw 187:92cbb9eec47b 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
apluscw 187:92cbb9eec47b 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
apluscw 187:92cbb9eec47b 438
apluscw 187:92cbb9eec47b 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
apluscw 187:92cbb9eec47b 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
apluscw 187:92cbb9eec47b 441
apluscw 187:92cbb9eec47b 442 /* SCB Configuration Control Register Definitions */
apluscw 187:92cbb9eec47b 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
apluscw 187:92cbb9eec47b 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
apluscw 187:92cbb9eec47b 445
apluscw 187:92cbb9eec47b 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
apluscw 187:92cbb9eec47b 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
apluscw 187:92cbb9eec47b 448
apluscw 187:92cbb9eec47b 449 /* SCB System Handler Control and State Register Definitions */
apluscw 187:92cbb9eec47b 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
apluscw 187:92cbb9eec47b 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
apluscw 187:92cbb9eec47b 452
apluscw 187:92cbb9eec47b 453 /*@} end of group CMSIS_SCB */
apluscw 187:92cbb9eec47b 454
apluscw 187:92cbb9eec47b 455
apluscw 187:92cbb9eec47b 456 /** \ingroup CMSIS_core_register
apluscw 187:92cbb9eec47b 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
apluscw 187:92cbb9eec47b 458 \brief Type definitions for the System Timer Registers.
apluscw 187:92cbb9eec47b 459 @{
apluscw 187:92cbb9eec47b 460 */
apluscw 187:92cbb9eec47b 461
apluscw 187:92cbb9eec47b 462 /** \brief Structure type to access the System Timer (SysTick).
apluscw 187:92cbb9eec47b 463 */
apluscw 187:92cbb9eec47b 464 typedef struct
apluscw 187:92cbb9eec47b 465 {
apluscw 187:92cbb9eec47b 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
apluscw 187:92cbb9eec47b 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
apluscw 187:92cbb9eec47b 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
apluscw 187:92cbb9eec47b 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
apluscw 187:92cbb9eec47b 470 } SysTick_Type;
apluscw 187:92cbb9eec47b 471
apluscw 187:92cbb9eec47b 472 /* SysTick Control / Status Register Definitions */
apluscw 187:92cbb9eec47b 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
apluscw 187:92cbb9eec47b 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
apluscw 187:92cbb9eec47b 475
apluscw 187:92cbb9eec47b 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
apluscw 187:92cbb9eec47b 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
apluscw 187:92cbb9eec47b 478
apluscw 187:92cbb9eec47b 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
apluscw 187:92cbb9eec47b 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
apluscw 187:92cbb9eec47b 481
apluscw 187:92cbb9eec47b 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
apluscw 187:92cbb9eec47b 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
apluscw 187:92cbb9eec47b 484
apluscw 187:92cbb9eec47b 485 /* SysTick Reload Register Definitions */
apluscw 187:92cbb9eec47b 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
apluscw 187:92cbb9eec47b 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
apluscw 187:92cbb9eec47b 488
apluscw 187:92cbb9eec47b 489 /* SysTick Current Register Definitions */
apluscw 187:92cbb9eec47b 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
apluscw 187:92cbb9eec47b 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
apluscw 187:92cbb9eec47b 492
apluscw 187:92cbb9eec47b 493 /* SysTick Calibration Register Definitions */
apluscw 187:92cbb9eec47b 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
apluscw 187:92cbb9eec47b 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
apluscw 187:92cbb9eec47b 496
apluscw 187:92cbb9eec47b 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
apluscw 187:92cbb9eec47b 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
apluscw 187:92cbb9eec47b 499
apluscw 187:92cbb9eec47b 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
apluscw 187:92cbb9eec47b 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
apluscw 187:92cbb9eec47b 502
apluscw 187:92cbb9eec47b 503 /*@} end of group CMSIS_SysTick */
apluscw 187:92cbb9eec47b 504
apluscw 187:92cbb9eec47b 505
apluscw 187:92cbb9eec47b 506 /** \ingroup CMSIS_core_register
apluscw 187:92cbb9eec47b 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
apluscw 187:92cbb9eec47b 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
apluscw 187:92cbb9eec47b 509 are only accessible over DAP and not via processor. Therefore
apluscw 187:92cbb9eec47b 510 they are not covered by the Cortex-M0 header file.
apluscw 187:92cbb9eec47b 511 @{
apluscw 187:92cbb9eec47b 512 */
apluscw 187:92cbb9eec47b 513 /*@} end of group CMSIS_CoreDebug */
apluscw 187:92cbb9eec47b 514
apluscw 187:92cbb9eec47b 515
apluscw 187:92cbb9eec47b 516 /** \ingroup CMSIS_core_register
apluscw 187:92cbb9eec47b 517 \defgroup CMSIS_core_base Core Definitions
apluscw 187:92cbb9eec47b 518 \brief Definitions for base addresses, unions, and structures.
apluscw 187:92cbb9eec47b 519 @{
apluscw 187:92cbb9eec47b 520 */
apluscw 187:92cbb9eec47b 521
apluscw 187:92cbb9eec47b 522 /* Memory mapping of Cortex-M0 Hardware */
apluscw 187:92cbb9eec47b 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
apluscw 187:92cbb9eec47b 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
apluscw 187:92cbb9eec47b 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
apluscw 187:92cbb9eec47b 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
apluscw 187:92cbb9eec47b 527
apluscw 187:92cbb9eec47b 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
apluscw 187:92cbb9eec47b 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
apluscw 187:92cbb9eec47b 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
apluscw 187:92cbb9eec47b 531
apluscw 187:92cbb9eec47b 532
apluscw 187:92cbb9eec47b 533 /*@} */
apluscw 187:92cbb9eec47b 534
apluscw 187:92cbb9eec47b 535
apluscw 187:92cbb9eec47b 536
apluscw 187:92cbb9eec47b 537 /*******************************************************************************
apluscw 187:92cbb9eec47b 538 * Hardware Abstraction Layer
apluscw 187:92cbb9eec47b 539 Core Function Interface contains:
apluscw 187:92cbb9eec47b 540 - Core NVIC Functions
apluscw 187:92cbb9eec47b 541 - Core SysTick Functions
apluscw 187:92cbb9eec47b 542 - Core Register Access Functions
apluscw 187:92cbb9eec47b 543 ******************************************************************************/
apluscw 187:92cbb9eec47b 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
apluscw 187:92cbb9eec47b 545 */
apluscw 187:92cbb9eec47b 546
apluscw 187:92cbb9eec47b 547
apluscw 187:92cbb9eec47b 548
apluscw 187:92cbb9eec47b 549 /* ########################## NVIC functions #################################### */
apluscw 187:92cbb9eec47b 550 /** \ingroup CMSIS_Core_FunctionInterface
apluscw 187:92cbb9eec47b 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
apluscw 187:92cbb9eec47b 552 \brief Functions that manage interrupts and exceptions via the NVIC.
apluscw 187:92cbb9eec47b 553 @{
apluscw 187:92cbb9eec47b 554 */
apluscw 187:92cbb9eec47b 555
apluscw 187:92cbb9eec47b 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
apluscw 187:92cbb9eec47b 557 /* The following MACROS handle generation of the register offset and byte masks */
apluscw 187:92cbb9eec47b 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
apluscw 187:92cbb9eec47b 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
apluscw 187:92cbb9eec47b 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
apluscw 187:92cbb9eec47b 561
apluscw 187:92cbb9eec47b 562
apluscw 187:92cbb9eec47b 563 /** \brief Enable External Interrupt
apluscw 187:92cbb9eec47b 564
apluscw 187:92cbb9eec47b 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
apluscw 187:92cbb9eec47b 566
apluscw 187:92cbb9eec47b 567 \param [in] IRQn External interrupt number. Value cannot be negative.
apluscw 187:92cbb9eec47b 568 */
apluscw 187:92cbb9eec47b 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
apluscw 187:92cbb9eec47b 570 {
apluscw 187:92cbb9eec47b 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
apluscw 187:92cbb9eec47b 572 }
apluscw 187:92cbb9eec47b 573
apluscw 187:92cbb9eec47b 574
apluscw 187:92cbb9eec47b 575 /** \brief Disable External Interrupt
apluscw 187:92cbb9eec47b 576
apluscw 187:92cbb9eec47b 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
apluscw 187:92cbb9eec47b 578
apluscw 187:92cbb9eec47b 579 \param [in] IRQn External interrupt number. Value cannot be negative.
apluscw 187:92cbb9eec47b 580 */
apluscw 187:92cbb9eec47b 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
apluscw 187:92cbb9eec47b 582 {
apluscw 187:92cbb9eec47b 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
apluscw 187:92cbb9eec47b 584 }
apluscw 187:92cbb9eec47b 585
apluscw 187:92cbb9eec47b 586
apluscw 187:92cbb9eec47b 587 /** \brief Get Pending Interrupt
apluscw 187:92cbb9eec47b 588
apluscw 187:92cbb9eec47b 589 The function reads the pending register in the NVIC and returns the pending bit
apluscw 187:92cbb9eec47b 590 for the specified interrupt.
apluscw 187:92cbb9eec47b 591
apluscw 187:92cbb9eec47b 592 \param [in] IRQn Interrupt number.
apluscw 187:92cbb9eec47b 593
apluscw 187:92cbb9eec47b 594 \return 0 Interrupt status is not pending.
apluscw 187:92cbb9eec47b 595 \return 1 Interrupt status is pending.
apluscw 187:92cbb9eec47b 596 */
apluscw 187:92cbb9eec47b 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
apluscw 187:92cbb9eec47b 598 {
apluscw 187:92cbb9eec47b 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
apluscw 187:92cbb9eec47b 600 }
apluscw 187:92cbb9eec47b 601
apluscw 187:92cbb9eec47b 602
apluscw 187:92cbb9eec47b 603 /** \brief Set Pending Interrupt
apluscw 187:92cbb9eec47b 604
apluscw 187:92cbb9eec47b 605 The function sets the pending bit of an external interrupt.
apluscw 187:92cbb9eec47b 606
apluscw 187:92cbb9eec47b 607 \param [in] IRQn Interrupt number. Value cannot be negative.
apluscw 187:92cbb9eec47b 608 */
apluscw 187:92cbb9eec47b 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
apluscw 187:92cbb9eec47b 610 {
apluscw 187:92cbb9eec47b 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
apluscw 187:92cbb9eec47b 612 }
apluscw 187:92cbb9eec47b 613
apluscw 187:92cbb9eec47b 614
apluscw 187:92cbb9eec47b 615 /** \brief Clear Pending Interrupt
apluscw 187:92cbb9eec47b 616
apluscw 187:92cbb9eec47b 617 The function clears the pending bit of an external interrupt.
apluscw 187:92cbb9eec47b 618
apluscw 187:92cbb9eec47b 619 \param [in] IRQn External interrupt number. Value cannot be negative.
apluscw 187:92cbb9eec47b 620 */
apluscw 187:92cbb9eec47b 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
apluscw 187:92cbb9eec47b 622 {
apluscw 187:92cbb9eec47b 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
apluscw 187:92cbb9eec47b 624 }
apluscw 187:92cbb9eec47b 625
apluscw 187:92cbb9eec47b 626
apluscw 187:92cbb9eec47b 627 /** \brief Set Interrupt Priority
apluscw 187:92cbb9eec47b 628
apluscw 187:92cbb9eec47b 629 The function sets the priority of an interrupt.
apluscw 187:92cbb9eec47b 630
apluscw 187:92cbb9eec47b 631 \note The priority cannot be set for every core interrupt.
apluscw 187:92cbb9eec47b 632
apluscw 187:92cbb9eec47b 633 \param [in] IRQn Interrupt number.
apluscw 187:92cbb9eec47b 634 \param [in] priority Priority to set.
apluscw 187:92cbb9eec47b 635 */
apluscw 187:92cbb9eec47b 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
apluscw 187:92cbb9eec47b 637 {
apluscw 187:92cbb9eec47b 638 if((int32_t)(IRQn) < 0) {
apluscw 187:92cbb9eec47b 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
apluscw 187:92cbb9eec47b 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
apluscw 187:92cbb9eec47b 641 }
apluscw 187:92cbb9eec47b 642 else {
apluscw 187:92cbb9eec47b 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
apluscw 187:92cbb9eec47b 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
apluscw 187:92cbb9eec47b 645 }
apluscw 187:92cbb9eec47b 646 }
apluscw 187:92cbb9eec47b 647
apluscw 187:92cbb9eec47b 648
apluscw 187:92cbb9eec47b 649 /** \brief Get Interrupt Priority
apluscw 187:92cbb9eec47b 650
apluscw 187:92cbb9eec47b 651 The function reads the priority of an interrupt. The interrupt
apluscw 187:92cbb9eec47b 652 number can be positive to specify an external (device specific)
apluscw 187:92cbb9eec47b 653 interrupt, or negative to specify an internal (core) interrupt.
apluscw 187:92cbb9eec47b 654
apluscw 187:92cbb9eec47b 655
apluscw 187:92cbb9eec47b 656 \param [in] IRQn Interrupt number.
apluscw 187:92cbb9eec47b 657 \return Interrupt Priority. Value is aligned automatically to the implemented
apluscw 187:92cbb9eec47b 658 priority bits of the microcontroller.
apluscw 187:92cbb9eec47b 659 */
apluscw 187:92cbb9eec47b 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
apluscw 187:92cbb9eec47b 661 {
apluscw 187:92cbb9eec47b 662
apluscw 187:92cbb9eec47b 663 if((int32_t)(IRQn) < 0) {
apluscw 187:92cbb9eec47b 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
apluscw 187:92cbb9eec47b 665 }
apluscw 187:92cbb9eec47b 666 else {
apluscw 187:92cbb9eec47b 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
apluscw 187:92cbb9eec47b 668 }
apluscw 187:92cbb9eec47b 669 }
apluscw 187:92cbb9eec47b 670
apluscw 187:92cbb9eec47b 671
apluscw 187:92cbb9eec47b 672 /** \brief System Reset
apluscw 187:92cbb9eec47b 673
apluscw 187:92cbb9eec47b 674 The function initiates a system reset request to reset the MCU.
apluscw 187:92cbb9eec47b 675 */
apluscw 187:92cbb9eec47b 676 __STATIC_INLINE void NVIC_SystemReset(void)
apluscw 187:92cbb9eec47b 677 {
apluscw 187:92cbb9eec47b 678 __DSB(); /* Ensure all outstanding memory accesses included
apluscw 187:92cbb9eec47b 679 buffered write are completed before reset */
apluscw 187:92cbb9eec47b 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
apluscw 187:92cbb9eec47b 681 SCB_AIRCR_SYSRESETREQ_Msk);
apluscw 187:92cbb9eec47b 682 __DSB(); /* Ensure completion of memory access */
apluscw 187:92cbb9eec47b 683 while(1) { __NOP(); } /* wait until reset */
apluscw 187:92cbb9eec47b 684 }
apluscw 187:92cbb9eec47b 685
apluscw 187:92cbb9eec47b 686 /*@} end of CMSIS_Core_NVICFunctions */
apluscw 187:92cbb9eec47b 687
apluscw 187:92cbb9eec47b 688
apluscw 187:92cbb9eec47b 689
apluscw 187:92cbb9eec47b 690 /* ################################## SysTick function ############################################ */
apluscw 187:92cbb9eec47b 691 /** \ingroup CMSIS_Core_FunctionInterface
apluscw 187:92cbb9eec47b 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
apluscw 187:92cbb9eec47b 693 \brief Functions that configure the System.
apluscw 187:92cbb9eec47b 694 @{
apluscw 187:92cbb9eec47b 695 */
apluscw 187:92cbb9eec47b 696
apluscw 187:92cbb9eec47b 697 #if (__Vendor_SysTickConfig == 0)
apluscw 187:92cbb9eec47b 698
apluscw 187:92cbb9eec47b 699 /** \brief System Tick Configuration
apluscw 187:92cbb9eec47b 700
apluscw 187:92cbb9eec47b 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
apluscw 187:92cbb9eec47b 702 Counter is in free running mode to generate periodic interrupts.
apluscw 187:92cbb9eec47b 703
apluscw 187:92cbb9eec47b 704 \param [in] ticks Number of ticks between two interrupts.
apluscw 187:92cbb9eec47b 705
apluscw 187:92cbb9eec47b 706 \return 0 Function succeeded.
apluscw 187:92cbb9eec47b 707 \return 1 Function failed.
apluscw 187:92cbb9eec47b 708
apluscw 187:92cbb9eec47b 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
apluscw 187:92cbb9eec47b 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
apluscw 187:92cbb9eec47b 711 must contain a vendor-specific implementation of this function.
apluscw 187:92cbb9eec47b 712
apluscw 187:92cbb9eec47b 713 */
apluscw 187:92cbb9eec47b 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
apluscw 187:92cbb9eec47b 715 {
apluscw 187:92cbb9eec47b 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
apluscw 187:92cbb9eec47b 717
apluscw 187:92cbb9eec47b 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
apluscw 187:92cbb9eec47b 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
apluscw 187:92cbb9eec47b 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
apluscw 187:92cbb9eec47b 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
apluscw 187:92cbb9eec47b 722 SysTick_CTRL_TICKINT_Msk |
apluscw 187:92cbb9eec47b 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
apluscw 187:92cbb9eec47b 724 return (0UL); /* Function successful */
apluscw 187:92cbb9eec47b 725 }
apluscw 187:92cbb9eec47b 726
apluscw 187:92cbb9eec47b 727 #endif
apluscw 187:92cbb9eec47b 728
apluscw 187:92cbb9eec47b 729 /*@} end of CMSIS_Core_SysTickFunctions */
apluscw 187:92cbb9eec47b 730
apluscw 187:92cbb9eec47b 731
apluscw 187:92cbb9eec47b 732
apluscw 187:92cbb9eec47b 733
apluscw 187:92cbb9eec47b 734 #ifdef __cplusplus
apluscw 187:92cbb9eec47b 735 }
apluscw 187:92cbb9eec47b 736 #endif
apluscw 187:92cbb9eec47b 737
apluscw 187:92cbb9eec47b 738 #endif /* __CORE_CM0_H_DEPENDANT */
apluscw 187:92cbb9eec47b 739
apluscw 187:92cbb9eec47b 740 #endif /* __CMSIS_GENERIC */