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/*
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* MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
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* _Please_ see the comments in MFRC522.h - they give useful hints and background.
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* Released into the public domain.
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*/
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#include "MFRC522.h"
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8
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static const char* const _TypeNamePICC[] =
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{
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"Unknown type",
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"PICC compliant with ISO/IEC 14443-4",
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"PICC compliant with ISO/IEC 18092 (NFC)",
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"MIFARE Mini, 320 bytes",
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"MIFARE 1KB",
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"MIFARE 4KB",
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"MIFARE Ultralight or Ultralight C",
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"MIFARE Plus",
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"MIFARE TNP3XXX",
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/* not complete UID */
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"SAK indicates UID is not complete"
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};
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static const char* const _ErrorMessage[] =
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{
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"Unknown error",
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"Success",
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"Error in communication",
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"Collision detected",
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"Timeout in communication",
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"A buffer is not big enough",
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"Internal error in the code, should not happen",
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"Invalid argument",
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"The CRC_A does not match",
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"A MIFARE PICC responded with NAK"
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};
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#define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
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#define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
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/////////////////////////////////////////////////////////////////////////////////////
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// Functions for setting up the driver
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/////////////////////////////////////////////////////////////////////////////////////
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/**
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* Constructor.
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* Prepares the output pins.
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*/
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MFRC522::MFRC522(PinName mosi,
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PinName miso,
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PinName sclk,
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PinName cs,
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PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
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{
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/* Configure SPI bus */
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m_SPI.format(8, 0);
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m_SPI.frequency(8000000);
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/* Release SPI-CS pin */
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m_CS = 1;
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/* Release RESET pin */
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m_RESET = 1;
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} // End constructor
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/**
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* Destructor.
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*/
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MFRC522::~MFRC522()
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{
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}
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/////////////////////////////////////////////////////////////////////////////////////
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// Basic interface functions for communicating with the MFRC522
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/////////////////////////////////////////////////////////////////////////////////////
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80
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/**
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* Writes a byte to the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
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{
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m_CS = 0; /* Select SPI Chip MFRC522 */
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// MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
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(void) m_SPI.write(reg & 0x7E);
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(void) m_SPI.write(value);
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m_CS = 1; /* Release SPI Chip MFRC522 */
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} // End PCD_WriteRegister()
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/**
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* Writes a number of bytes to the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
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{
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m_CS = 0; /* Select SPI Chip MFRC522 */
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103
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// MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
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(void) m_SPI.write(reg & 0x7E);
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for (uint8_t index = 0; index < count; index++)
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{
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(void) m_SPI.write(values[index]);
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}
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m_CS = 1; /* Release SPI Chip MFRC522 */
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} // End PCD_WriteRegister()
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/**
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* Reads a byte from the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
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{
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uint8_t value;
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m_CS = 0; /* Select SPI Chip MFRC522 */
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122
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// MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
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(void) m_SPI.write(0x80 | reg);
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// Read the value back. Send 0 to stop reading.
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value = m_SPI.write(0);
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128
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m_CS = 1; /* Release SPI Chip MFRC522 */
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return value;
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} // End PCD_ReadRegister()
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/**
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* Reads a number of bytes from the specified register in the MFRC522 chip.
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* The interface is described in the datasheet section 8.1.2.
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*/
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void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
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{
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if (count == 0) { return; }
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uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
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uint8_t index = 0; // Index in values array.
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m_CS = 0; /* Select SPI Chip MFRC522 */
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count--; // One read is performed outside of the loop
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(void) m_SPI.write(address); // Tell MFRC522 which address we want to read
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148
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while (index < count)
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{
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151
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if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
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152
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{
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153
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// Create bit mask for bit positions rxAlign..7
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uint8_t mask = 0;
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for (uint8_t i = rxAlign; i <= 7; i++)
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{
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mask |= (1 << i);
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158
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}
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159
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// Read value and tell that we want to read the same address again.
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uint8_t value = m_SPI.write(address);
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162
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// Apply mask to both current value of values[0] and the new data in value.
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values[0] = (values[index] & ~mask) | (value & mask);
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}
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else
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{
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168
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// Read value and tell that we want to read the same address again.
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169
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values[index] = m_SPI.write(address);
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170
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}
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index++;
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}
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values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
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m_CS = 1; /* Release SPI Chip MFRC522 */
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178
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} // End PCD_ReadRegister()
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/**
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* Sets the bits given in mask in register reg.
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*/
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void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
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{
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uint8_t tmp = PCD_ReadRegister(reg);
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PCD_WriteRegister(reg, tmp | mask); // set bit mask
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} // End PCD_SetRegisterBitMask()
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/**
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* Clears the bits given in mask from register reg.
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*/
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void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
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{
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uint8_t tmp = PCD_ReadRegister(reg);
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PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
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} // End PCD_ClearRegisterBitMask()
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198
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/**
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200
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* Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
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|
201
|
*/
|
| AtomX |
0:efd786b99a72
|
202
|
uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
|
| AtomX |
0:efd786b99a72
|
203
|
{
|
| AtomX |
0:efd786b99a72
|
204
|
PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
|
| AtomX |
1:63d729186747
|
205
|
PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
|
| AtomX |
1:63d729186747
|
206
|
PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
|
| AtomX |
1:63d729186747
|
207
|
PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
|
| AtomX |
0:efd786b99a72
|
208
|
PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
|
| AtomX |
0:efd786b99a72
|
209
|
|
| AtomX |
1:63d729186747
|
210
|
// Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
|
| AtomX |
0:efd786b99a72
|
211
|
uint16_t i = 5000;
|
| AtomX |
0:efd786b99a72
|
212
|
uint8_t n;
|
| AtomX |
0:efd786b99a72
|
213
|
while (1)
|
| AtomX |
0:efd786b99a72
|
214
|
{
|
| AtomX |
0:efd786b99a72
|
215
|
n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
|
| AtomX |
0:efd786b99a72
|
216
|
if (n & 0x04)
|
| AtomX |
0:efd786b99a72
|
217
|
{
|
| AtomX |
0:efd786b99a72
|
218
|
// CRCIRq bit set - calculation done
|
| AtomX |
0:efd786b99a72
|
219
|
break;
|
| AtomX |
0:efd786b99a72
|
220
|
}
|
| AtomX |
1:63d729186747
|
221
|
|
| AtomX |
0:efd786b99a72
|
222
|
if (--i == 0)
|
| AtomX |
0:efd786b99a72
|
223
|
{
|
| AtomX |
0:efd786b99a72
|
224
|
// The emergency break. We will eventually terminate on this one after 89ms.
|
| AtomX |
0:efd786b99a72
|
225
|
// Communication with the MFRC522 might be down.
|
| AtomX |
0:efd786b99a72
|
226
|
return STATUS_TIMEOUT;
|
| AtomX |
0:efd786b99a72
|
227
|
}
|
| AtomX |
0:efd786b99a72
|
228
|
}
|
| AtomX |
0:efd786b99a72
|
229
|
|
| AtomX |
0:efd786b99a72
|
230
|
// Stop calculating CRC for new content in the FIFO.
|
| AtomX |
0:efd786b99a72
|
231
|
PCD_WriteRegister(CommandReg, PCD_Idle);
|
| AtomX |
0:efd786b99a72
|
232
|
|
| AtomX |
0:efd786b99a72
|
233
|
// Transfer the result from the registers to the result buffer
|
| AtomX |
0:efd786b99a72
|
234
|
result[0] = PCD_ReadRegister(CRCResultRegL);
|
| AtomX |
0:efd786b99a72
|
235
|
result[1] = PCD_ReadRegister(CRCResultRegH);
|
| AtomX |
0:efd786b99a72
|
236
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
237
|
} // End PCD_CalculateCRC()
|
| AtomX |
0:efd786b99a72
|
238
|
|
| AtomX |
0:efd786b99a72
|
239
|
|
| AtomX |
0:efd786b99a72
|
240
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
241
|
// Functions for manipulating the MFRC522
|
| AtomX |
0:efd786b99a72
|
242
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
243
|
|
| AtomX |
0:efd786b99a72
|
244
|
/**
|
| AtomX |
0:efd786b99a72
|
245
|
* Initializes the MFRC522 chip.
|
| AtomX |
0:efd786b99a72
|
246
|
*/
|
| AtomX |
0:efd786b99a72
|
247
|
void MFRC522::PCD_Init()
|
| AtomX |
0:efd786b99a72
|
248
|
{
|
| AtomX |
0:efd786b99a72
|
249
|
/* Reset MFRC522 */
|
| AtomX |
0:efd786b99a72
|
250
|
m_RESET = 0;
|
| AtomX |
0:efd786b99a72
|
251
|
wait_ms(10);
|
| AtomX |
0:efd786b99a72
|
252
|
m_RESET = 1;
|
| AtomX |
1:63d729186747
|
253
|
|
| AtomX |
1:63d729186747
|
254
|
// Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
|
| AtomX |
0:efd786b99a72
|
255
|
wait_ms(50);
|
| AtomX |
0:efd786b99a72
|
256
|
|
| AtomX |
0:efd786b99a72
|
257
|
// When communicating with a PICC we need a timeout if something goes wrong.
|
| AtomX |
0:efd786b99a72
|
258
|
// f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
|
| AtomX |
0:efd786b99a72
|
259
|
// TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
|
| AtomX |
0:efd786b99a72
|
260
|
PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
|
| AtomX |
1:63d729186747
|
261
|
PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
|
| AtomX |
0:efd786b99a72
|
262
|
PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
|
| AtomX |
0:efd786b99a72
|
263
|
PCD_WriteRegister(TReloadRegL, 0xE8);
|
| AtomX |
0:efd786b99a72
|
264
|
|
| AtomX |
0:efd786b99a72
|
265
|
PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
|
| AtomX |
0:efd786b99a72
|
266
|
PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
|
| AtomX |
0:efd786b99a72
|
267
|
|
| AtomX |
0:efd786b99a72
|
268
|
PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
|
| AtomX |
0:efd786b99a72
|
269
|
|
| AtomX |
0:efd786b99a72
|
270
|
PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
|
| AtomX |
0:efd786b99a72
|
271
|
} // End PCD_Init()
|
| AtomX |
0:efd786b99a72
|
272
|
|
| AtomX |
0:efd786b99a72
|
273
|
/**
|
| AtomX |
0:efd786b99a72
|
274
|
* Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
|
| AtomX |
0:efd786b99a72
|
275
|
*/
|
| AtomX |
0:efd786b99a72
|
276
|
void MFRC522::PCD_Reset()
|
| AtomX |
0:efd786b99a72
|
277
|
{
|
| AtomX |
0:efd786b99a72
|
278
|
PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
|
| AtomX |
0:efd786b99a72
|
279
|
// The datasheet does not mention how long the SoftRest command takes to complete.
|
| AtomX |
0:efd786b99a72
|
280
|
// But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
|
| AtomX |
1:63d729186747
|
281
|
// Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
|
| AtomX |
0:efd786b99a72
|
282
|
wait_ms(50);
|
| AtomX |
0:efd786b99a72
|
283
|
|
| AtomX |
0:efd786b99a72
|
284
|
// Wait for the PowerDown bit in CommandReg to be cleared
|
| AtomX |
0:efd786b99a72
|
285
|
while (PCD_ReadRegister(CommandReg) & (1<<4))
|
| AtomX |
0:efd786b99a72
|
286
|
{
|
| AtomX |
0:efd786b99a72
|
287
|
// PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
|
| AtomX |
0:efd786b99a72
|
288
|
}
|
| AtomX |
0:efd786b99a72
|
289
|
} // End PCD_Reset()
|
| AtomX |
0:efd786b99a72
|
290
|
|
| AtomX |
0:efd786b99a72
|
291
|
/**
|
| AtomX |
0:efd786b99a72
|
292
|
* Turns the antenna on by enabling pins TX1 and TX2.
|
| AtomX |
0:efd786b99a72
|
293
|
* After a reset these pins disabled.
|
| AtomX |
0:efd786b99a72
|
294
|
*/
|
| AtomX |
0:efd786b99a72
|
295
|
void MFRC522::PCD_AntennaOn()
|
| AtomX |
0:efd786b99a72
|
296
|
{
|
| AtomX |
0:efd786b99a72
|
297
|
uint8_t value = PCD_ReadRegister(TxControlReg);
|
| AtomX |
0:efd786b99a72
|
298
|
if ((value & 0x03) != 0x03)
|
| AtomX |
0:efd786b99a72
|
299
|
{
|
| AtomX |
0:efd786b99a72
|
300
|
PCD_WriteRegister(TxControlReg, value | 0x03);
|
| AtomX |
0:efd786b99a72
|
301
|
}
|
| AtomX |
0:efd786b99a72
|
302
|
} // End PCD_AntennaOn()
|
| AtomX |
0:efd786b99a72
|
303
|
|
| AtomX |
0:efd786b99a72
|
304
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
305
|
// Functions for communicating with PICCs
|
| AtomX |
0:efd786b99a72
|
306
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
307
|
|
| AtomX |
0:efd786b99a72
|
308
|
/**
|
| AtomX |
0:efd786b99a72
|
309
|
* Executes the Transceive command.
|
| AtomX |
0:efd786b99a72
|
310
|
* CRC validation can only be done if backData and backLen are specified.
|
| AtomX |
0:efd786b99a72
|
311
|
*/
|
| AtomX |
1:63d729186747
|
312
|
uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
|
| AtomX |
1:63d729186747
|
313
|
uint8_t sendLen,
|
| AtomX |
1:63d729186747
|
314
|
uint8_t *backData,
|
| AtomX |
1:63d729186747
|
315
|
uint8_t *backLen,
|
| AtomX |
1:63d729186747
|
316
|
uint8_t *validBits,
|
| AtomX |
1:63d729186747
|
317
|
uint8_t rxAlign,
|
| AtomX |
1:63d729186747
|
318
|
bool checkCRC)
|
| AtomX |
0:efd786b99a72
|
319
|
{
|
| AtomX |
0:efd786b99a72
|
320
|
uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
|
| AtomX |
0:efd786b99a72
|
321
|
return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
|
| AtomX |
0:efd786b99a72
|
322
|
} // End PCD_TransceiveData()
|
| AtomX |
0:efd786b99a72
|
323
|
|
| AtomX |
0:efd786b99a72
|
324
|
/**
|
| AtomX |
0:efd786b99a72
|
325
|
* Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
|
| AtomX |
0:efd786b99a72
|
326
|
* CRC validation can only be done if backData and backLen are specified.
|
| AtomX |
0:efd786b99a72
|
327
|
*/
|
| AtomX |
1:63d729186747
|
328
|
uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
|
| AtomX |
1:63d729186747
|
329
|
uint8_t waitIRq,
|
| AtomX |
1:63d729186747
|
330
|
uint8_t *sendData,
|
| AtomX |
1:63d729186747
|
331
|
uint8_t sendLen,
|
| AtomX |
1:63d729186747
|
332
|
uint8_t *backData,
|
| AtomX |
1:63d729186747
|
333
|
uint8_t *backLen,
|
| AtomX |
1:63d729186747
|
334
|
uint8_t *validBits,
|
| AtomX |
1:63d729186747
|
335
|
uint8_t rxAlign,
|
| AtomX |
1:63d729186747
|
336
|
bool checkCRC)
|
| AtomX |
0:efd786b99a72
|
337
|
{
|
| AtomX |
0:efd786b99a72
|
338
|
uint8_t n, _validBits = 0;
|
| AtomX |
0:efd786b99a72
|
339
|
uint32_t i;
|
| AtomX |
0:efd786b99a72
|
340
|
|
| AtomX |
0:efd786b99a72
|
341
|
// Prepare values for BitFramingReg
|
| AtomX |
0:efd786b99a72
|
342
|
uint8_t txLastBits = validBits ? *validBits : 0;
|
| AtomX |
0:efd786b99a72
|
343
|
uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
|
| AtomX |
0:efd786b99a72
|
344
|
|
| AtomX |
0:efd786b99a72
|
345
|
PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
|
| AtomX |
0:efd786b99a72
|
346
|
PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
|
| AtomX |
0:efd786b99a72
|
347
|
PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
|
| AtomX |
0:efd786b99a72
|
348
|
PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
|
| AtomX |
0:efd786b99a72
|
349
|
PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
|
| AtomX |
0:efd786b99a72
|
350
|
PCD_WriteRegister(CommandReg, command); // Execute the command
|
| AtomX |
0:efd786b99a72
|
351
|
if (command == PCD_Transceive)
|
| AtomX |
0:efd786b99a72
|
352
|
{
|
| AtomX |
0:efd786b99a72
|
353
|
PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
|
| AtomX |
0:efd786b99a72
|
354
|
}
|
| AtomX |
0:efd786b99a72
|
355
|
|
| AtomX |
0:efd786b99a72
|
356
|
// Wait for the command to complete.
|
| AtomX |
0:efd786b99a72
|
357
|
// In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
|
| AtomX |
1:63d729186747
|
358
|
// Each iteration of the do-while-loop takes 17.86us.
|
| AtomX |
0:efd786b99a72
|
359
|
i = 2000;
|
| AtomX |
0:efd786b99a72
|
360
|
while (1)
|
| AtomX |
0:efd786b99a72
|
361
|
{
|
| AtomX |
0:efd786b99a72
|
362
|
n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
|
| AtomX |
0:efd786b99a72
|
363
|
if (n & waitIRq)
|
| AtomX |
0:efd786b99a72
|
364
|
{ // One of the interrupts that signal success has been set.
|
| AtomX |
0:efd786b99a72
|
365
|
break;
|
| AtomX |
0:efd786b99a72
|
366
|
}
|
| AtomX |
0:efd786b99a72
|
367
|
|
| AtomX |
0:efd786b99a72
|
368
|
if (n & 0x01)
|
| AtomX |
0:efd786b99a72
|
369
|
{ // Timer interrupt - nothing received in 25ms
|
| AtomX |
0:efd786b99a72
|
370
|
return STATUS_TIMEOUT;
|
| AtomX |
0:efd786b99a72
|
371
|
}
|
| AtomX |
0:efd786b99a72
|
372
|
|
| AtomX |
0:efd786b99a72
|
373
|
if (--i == 0)
|
| AtomX |
0:efd786b99a72
|
374
|
{ // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
|
| AtomX |
0:efd786b99a72
|
375
|
return STATUS_TIMEOUT;
|
| AtomX |
0:efd786b99a72
|
376
|
}
|
| AtomX |
0:efd786b99a72
|
377
|
}
|
| AtomX |
0:efd786b99a72
|
378
|
|
| AtomX |
0:efd786b99a72
|
379
|
// Stop now if any errors except collisions were detected.
|
| AtomX |
0:efd786b99a72
|
380
|
uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
|
| AtomX |
0:efd786b99a72
|
381
|
if (errorRegValue & 0x13)
|
| AtomX |
0:efd786b99a72
|
382
|
{ // BufferOvfl ParityErr ProtocolErr
|
| AtomX |
0:efd786b99a72
|
383
|
return STATUS_ERROR;
|
| AtomX |
0:efd786b99a72
|
384
|
}
|
| AtomX |
0:efd786b99a72
|
385
|
|
| AtomX |
0:efd786b99a72
|
386
|
// If the caller wants data back, get it from the MFRC522.
|
| AtomX |
0:efd786b99a72
|
387
|
if (backData && backLen)
|
| AtomX |
0:efd786b99a72
|
388
|
{
|
| AtomX |
0:efd786b99a72
|
389
|
n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
|
| AtomX |
0:efd786b99a72
|
390
|
if (n > *backLen)
|
| AtomX |
0:efd786b99a72
|
391
|
{
|
| AtomX |
0:efd786b99a72
|
392
|
return STATUS_NO_ROOM;
|
| AtomX |
0:efd786b99a72
|
393
|
}
|
| AtomX |
0:efd786b99a72
|
394
|
|
| AtomX |
0:efd786b99a72
|
395
|
*backLen = n; // Number of bytes returned
|
| AtomX |
0:efd786b99a72
|
396
|
PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
|
| AtomX |
0:efd786b99a72
|
397
|
_validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
|
| AtomX |
0:efd786b99a72
|
398
|
if (validBits)
|
| AtomX |
0:efd786b99a72
|
399
|
{
|
| AtomX |
0:efd786b99a72
|
400
|
*validBits = _validBits;
|
| AtomX |
0:efd786b99a72
|
401
|
}
|
| AtomX |
0:efd786b99a72
|
402
|
}
|
| AtomX |
0:efd786b99a72
|
403
|
|
| AtomX |
0:efd786b99a72
|
404
|
// Tell about collisions
|
| AtomX |
0:efd786b99a72
|
405
|
if (errorRegValue & 0x08)
|
| AtomX |
0:efd786b99a72
|
406
|
{ // CollErr
|
| AtomX |
0:efd786b99a72
|
407
|
return STATUS_COLLISION;
|
| AtomX |
0:efd786b99a72
|
408
|
}
|
| AtomX |
0:efd786b99a72
|
409
|
|
| AtomX |
0:efd786b99a72
|
410
|
// Perform CRC_A validation if requested.
|
| AtomX |
0:efd786b99a72
|
411
|
if (backData && backLen && checkCRC)
|
| AtomX |
0:efd786b99a72
|
412
|
{
|
| AtomX |
0:efd786b99a72
|
413
|
// In this case a MIFARE Classic NAK is not OK.
|
| AtomX |
0:efd786b99a72
|
414
|
if ((*backLen == 1) && (_validBits == 4))
|
| AtomX |
0:efd786b99a72
|
415
|
{
|
| AtomX |
0:efd786b99a72
|
416
|
return STATUS_MIFARE_NACK;
|
| AtomX |
0:efd786b99a72
|
417
|
}
|
| AtomX |
0:efd786b99a72
|
418
|
|
| AtomX |
0:efd786b99a72
|
419
|
// We need at least the CRC_A value and all 8 bits of the last byte must be received.
|
| AtomX |
0:efd786b99a72
|
420
|
if ((*backLen < 2) || (_validBits != 0))
|
| AtomX |
0:efd786b99a72
|
421
|
{
|
| AtomX |
0:efd786b99a72
|
422
|
return STATUS_CRC_WRONG;
|
| AtomX |
0:efd786b99a72
|
423
|
}
|
| AtomX |
0:efd786b99a72
|
424
|
|
| AtomX |
0:efd786b99a72
|
425
|
// Verify CRC_A - do our own calculation and store the control in controlBuffer.
|
| AtomX |
0:efd786b99a72
|
426
|
uint8_t controlBuffer[2];
|
| AtomX |
0:efd786b99a72
|
427
|
n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
|
| AtomX |
0:efd786b99a72
|
428
|
if (n != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
429
|
{
|
| AtomX |
0:efd786b99a72
|
430
|
return n;
|
| AtomX |
0:efd786b99a72
|
431
|
}
|
| AtomX |
0:efd786b99a72
|
432
|
|
| AtomX |
0:efd786b99a72
|
433
|
if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
|
| AtomX |
0:efd786b99a72
|
434
|
{
|
| AtomX |
0:efd786b99a72
|
435
|
return STATUS_CRC_WRONG;
|
| AtomX |
0:efd786b99a72
|
436
|
}
|
| AtomX |
0:efd786b99a72
|
437
|
}
|
| AtomX |
0:efd786b99a72
|
438
|
|
| AtomX |
0:efd786b99a72
|
439
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
440
|
} // End PCD_CommunicateWithPICC()
|
| AtomX |
0:efd786b99a72
|
441
|
|
| AtomX |
1:63d729186747
|
442
|
/*
|
| AtomX |
0:efd786b99a72
|
443
|
* Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
|
| AtomX |
0:efd786b99a72
|
444
|
* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
|
| AtomX |
0:efd786b99a72
|
445
|
*/
|
| AtomX |
0:efd786b99a72
|
446
|
uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
|
| AtomX |
0:efd786b99a72
|
447
|
{
|
| AtomX |
0:efd786b99a72
|
448
|
return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
|
| AtomX |
0:efd786b99a72
|
449
|
} // End PICC_RequestA()
|
| AtomX |
0:efd786b99a72
|
450
|
|
| AtomX |
0:efd786b99a72
|
451
|
/**
|
| AtomX |
0:efd786b99a72
|
452
|
* Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
|
| AtomX |
0:efd786b99a72
|
453
|
* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
|
| AtomX |
0:efd786b99a72
|
454
|
*/
|
| AtomX |
0:efd786b99a72
|
455
|
uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
|
| AtomX |
0:efd786b99a72
|
456
|
{
|
| AtomX |
0:efd786b99a72
|
457
|
return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
|
| AtomX |
0:efd786b99a72
|
458
|
} // End PICC_WakeupA()
|
| AtomX |
0:efd786b99a72
|
459
|
|
| AtomX |
1:63d729186747
|
460
|
/*
|
| AtomX |
0:efd786b99a72
|
461
|
* Transmits REQA or WUPA commands.
|
| AtomX |
0:efd786b99a72
|
462
|
* Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
|
| AtomX |
0:efd786b99a72
|
463
|
*/
|
| AtomX |
0:efd786b99a72
|
464
|
uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
|
| AtomX |
0:efd786b99a72
|
465
|
{
|
| AtomX |
0:efd786b99a72
|
466
|
uint8_t validBits;
|
| AtomX |
0:efd786b99a72
|
467
|
uint8_t status;
|
| AtomX |
0:efd786b99a72
|
468
|
|
| AtomX |
0:efd786b99a72
|
469
|
if (bufferATQA == NULL || *bufferSize < 2)
|
| AtomX |
0:efd786b99a72
|
470
|
{ // The ATQA response is 2 bytes long.
|
| AtomX |
0:efd786b99a72
|
471
|
return STATUS_NO_ROOM;
|
| AtomX |
0:efd786b99a72
|
472
|
}
|
| AtomX |
0:efd786b99a72
|
473
|
|
| AtomX |
0:efd786b99a72
|
474
|
// ValuesAfterColl=1 => Bits received after collision are cleared.
|
| AtomX |
0:efd786b99a72
|
475
|
PCD_ClrRegisterBits(CollReg, 0x80);
|
| AtomX |
0:efd786b99a72
|
476
|
|
| AtomX |
0:efd786b99a72
|
477
|
// For REQA and WUPA we need the short frame format
|
| AtomX |
0:efd786b99a72
|
478
|
// - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
|
| AtomX |
0:efd786b99a72
|
479
|
validBits = 7;
|
| AtomX |
0:efd786b99a72
|
480
|
|
| AtomX |
0:efd786b99a72
|
481
|
status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
|
| AtomX |
0:efd786b99a72
|
482
|
if (status != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
483
|
{
|
| AtomX |
0:efd786b99a72
|
484
|
return status;
|
| AtomX |
0:efd786b99a72
|
485
|
}
|
| AtomX |
0:efd786b99a72
|
486
|
|
| AtomX |
0:efd786b99a72
|
487
|
if ((*bufferSize != 2) || (validBits != 0))
|
| AtomX |
0:efd786b99a72
|
488
|
{ // ATQA must be exactly 16 bits.
|
| AtomX |
0:efd786b99a72
|
489
|
return STATUS_ERROR;
|
| AtomX |
0:efd786b99a72
|
490
|
}
|
| AtomX |
0:efd786b99a72
|
491
|
|
| AtomX |
0:efd786b99a72
|
492
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
493
|
} // End PICC_REQA_or_WUPA()
|
| AtomX |
0:efd786b99a72
|
494
|
|
| AtomX |
1:63d729186747
|
495
|
/*
|
| AtomX |
0:efd786b99a72
|
496
|
* Transmits SELECT/ANTICOLLISION commands to select a single PICC.
|
| AtomX |
0:efd786b99a72
|
497
|
*/
|
| AtomX |
0:efd786b99a72
|
498
|
uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
|
| AtomX |
0:efd786b99a72
|
499
|
{
|
| AtomX |
0:efd786b99a72
|
500
|
bool uidComplete;
|
| AtomX |
0:efd786b99a72
|
501
|
bool selectDone;
|
| AtomX |
0:efd786b99a72
|
502
|
bool useCascadeTag;
|
| AtomX |
0:efd786b99a72
|
503
|
uint8_t cascadeLevel = 1;
|
| AtomX |
0:efd786b99a72
|
504
|
uint8_t result;
|
| AtomX |
0:efd786b99a72
|
505
|
uint8_t count;
|
| AtomX |
0:efd786b99a72
|
506
|
uint8_t index;
|
| AtomX |
0:efd786b99a72
|
507
|
uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
|
| AtomX |
0:efd786b99a72
|
508
|
uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
|
| AtomX |
0:efd786b99a72
|
509
|
uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
|
| AtomX |
0:efd786b99a72
|
510
|
uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
|
| AtomX |
0:efd786b99a72
|
511
|
uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
|
| AtomX |
0:efd786b99a72
|
512
|
uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
|
| AtomX |
0:efd786b99a72
|
513
|
uint8_t *responseBuffer;
|
| AtomX |
0:efd786b99a72
|
514
|
uint8_t responseLength;
|
| AtomX |
0:efd786b99a72
|
515
|
|
| AtomX |
0:efd786b99a72
|
516
|
// Description of buffer structure:
|
| AtomX |
0:efd786b99a72
|
517
|
// Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
|
| AtomX |
0:efd786b99a72
|
518
|
// Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
|
| AtomX |
0:efd786b99a72
|
519
|
// Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
|
| AtomX |
0:efd786b99a72
|
520
|
// Byte 3: UID-data
|
| AtomX |
0:efd786b99a72
|
521
|
// Byte 4: UID-data
|
| AtomX |
0:efd786b99a72
|
522
|
// Byte 5: UID-data
|
| AtomX |
0:efd786b99a72
|
523
|
// Byte 6: BCC Block Check Character - XOR of bytes 2-5
|
| AtomX |
0:efd786b99a72
|
524
|
// Byte 7: CRC_A
|
| AtomX |
0:efd786b99a72
|
525
|
// Byte 8: CRC_A
|
| AtomX |
0:efd786b99a72
|
526
|
// The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
|
| AtomX |
0:efd786b99a72
|
527
|
//
|
| AtomX |
0:efd786b99a72
|
528
|
// Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
|
| AtomX |
0:efd786b99a72
|
529
|
// UID size Cascade level Byte2 Byte3 Byte4 Byte5
|
| AtomX |
0:efd786b99a72
|
530
|
// ======== ============= ===== ===== ===== =====
|
| AtomX |
0:efd786b99a72
|
531
|
// 4 bytes 1 uid0 uid1 uid2 uid3
|
| AtomX |
0:efd786b99a72
|
532
|
// 7 bytes 1 CT uid0 uid1 uid2
|
| AtomX |
0:efd786b99a72
|
533
|
// 2 uid3 uid4 uid5 uid6
|
| AtomX |
0:efd786b99a72
|
534
|
// 10 bytes 1 CT uid0 uid1 uid2
|
| AtomX |
0:efd786b99a72
|
535
|
// 2 CT uid3 uid4 uid5
|
| AtomX |
0:efd786b99a72
|
536
|
// 3 uid6 uid7 uid8 uid9
|
| AtomX |
0:efd786b99a72
|
537
|
|
| AtomX |
0:efd786b99a72
|
538
|
// Sanity checks
|
| AtomX |
0:efd786b99a72
|
539
|
if (validBits > 80)
|
| AtomX |
0:efd786b99a72
|
540
|
{
|
| AtomX |
0:efd786b99a72
|
541
|
return STATUS_INVALID;
|
| AtomX |
0:efd786b99a72
|
542
|
}
|
| AtomX |
0:efd786b99a72
|
543
|
|
| AtomX |
0:efd786b99a72
|
544
|
// Prepare MFRC522
|
| AtomX |
0:efd786b99a72
|
545
|
// ValuesAfterColl=1 => Bits received after collision are cleared.
|
| AtomX |
0:efd786b99a72
|
546
|
PCD_ClrRegisterBits(CollReg, 0x80);
|
| AtomX |
0:efd786b99a72
|
547
|
|
| AtomX |
0:efd786b99a72
|
548
|
// Repeat Cascade Level loop until we have a complete UID.
|
| AtomX |
0:efd786b99a72
|
549
|
uidComplete = false;
|
| AtomX |
0:efd786b99a72
|
550
|
while ( ! uidComplete)
|
| AtomX |
0:efd786b99a72
|
551
|
{
|
| AtomX |
0:efd786b99a72
|
552
|
// Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
|
| AtomX |
0:efd786b99a72
|
553
|
switch (cascadeLevel)
|
| AtomX |
0:efd786b99a72
|
554
|
{
|
| AtomX |
0:efd786b99a72
|
555
|
case 1:
|
| AtomX |
0:efd786b99a72
|
556
|
buffer[0] = PICC_CMD_SEL_CL1;
|
| AtomX |
0:efd786b99a72
|
557
|
uidIndex = 0;
|
| AtomX |
0:efd786b99a72
|
558
|
useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
|
| AtomX |
0:efd786b99a72
|
559
|
break;
|
| AtomX |
0:efd786b99a72
|
560
|
|
| AtomX |
0:efd786b99a72
|
561
|
case 2:
|
| AtomX |
0:efd786b99a72
|
562
|
buffer[0] = PICC_CMD_SEL_CL2;
|
| AtomX |
0:efd786b99a72
|
563
|
uidIndex = 3;
|
| AtomX |
0:efd786b99a72
|
564
|
useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
|
| AtomX |
0:efd786b99a72
|
565
|
break;
|
| AtomX |
0:efd786b99a72
|
566
|
|
| AtomX |
0:efd786b99a72
|
567
|
case 3:
|
| AtomX |
0:efd786b99a72
|
568
|
buffer[0] = PICC_CMD_SEL_CL3;
|
| AtomX |
0:efd786b99a72
|
569
|
uidIndex = 6;
|
| AtomX |
0:efd786b99a72
|
570
|
useCascadeTag = false; // Never used in CL3.
|
| AtomX |
0:efd786b99a72
|
571
|
break;
|
| AtomX |
0:efd786b99a72
|
572
|
|
| AtomX |
0:efd786b99a72
|
573
|
default:
|
| AtomX |
0:efd786b99a72
|
574
|
return STATUS_INTERNAL_ERROR;
|
| AtomX |
0:efd786b99a72
|
575
|
//break;
|
| AtomX |
0:efd786b99a72
|
576
|
}
|
| AtomX |
0:efd786b99a72
|
577
|
|
| AtomX |
0:efd786b99a72
|
578
|
// How many UID bits are known in this Cascade Level?
|
| AtomX |
0:efd786b99a72
|
579
|
if(validBits > (8 * uidIndex))
|
| AtomX |
0:efd786b99a72
|
580
|
{
|
| AtomX |
0:efd786b99a72
|
581
|
currentLevelKnownBits = validBits - (8 * uidIndex);
|
| AtomX |
0:efd786b99a72
|
582
|
}
|
| AtomX |
0:efd786b99a72
|
583
|
else
|
| AtomX |
0:efd786b99a72
|
584
|
{
|
| AtomX |
0:efd786b99a72
|
585
|
currentLevelKnownBits = 0;
|
| AtomX |
0:efd786b99a72
|
586
|
}
|
| AtomX |
0:efd786b99a72
|
587
|
|
| AtomX |
0:efd786b99a72
|
588
|
// Copy the known bits from uid->uidByte[] to buffer[]
|
| AtomX |
0:efd786b99a72
|
589
|
index = 2; // destination index in buffer[]
|
| AtomX |
0:efd786b99a72
|
590
|
if (useCascadeTag)
|
| AtomX |
0:efd786b99a72
|
591
|
{
|
| AtomX |
0:efd786b99a72
|
592
|
buffer[index++] = PICC_CMD_CT;
|
| AtomX |
0:efd786b99a72
|
593
|
}
|
| AtomX |
0:efd786b99a72
|
594
|
|
| AtomX |
0:efd786b99a72
|
595
|
uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
|
| AtomX |
0:efd786b99a72
|
596
|
if (bytesToCopy)
|
| AtomX |
0:efd786b99a72
|
597
|
{
|
| AtomX |
0:efd786b99a72
|
598
|
// Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
|
| AtomX |
0:efd786b99a72
|
599
|
uint8_t maxBytes = useCascadeTag ? 3 : 4;
|
| AtomX |
0:efd786b99a72
|
600
|
if (bytesToCopy > maxBytes)
|
| AtomX |
0:efd786b99a72
|
601
|
{
|
| AtomX |
0:efd786b99a72
|
602
|
bytesToCopy = maxBytes;
|
| AtomX |
0:efd786b99a72
|
603
|
}
|
| AtomX |
0:efd786b99a72
|
604
|
|
| AtomX |
0:efd786b99a72
|
605
|
for (count = 0; count < bytesToCopy; count++)
|
| AtomX |
0:efd786b99a72
|
606
|
{
|
| AtomX |
0:efd786b99a72
|
607
|
buffer[index++] = uid->uidByte[uidIndex + count];
|
| AtomX |
0:efd786b99a72
|
608
|
}
|
| AtomX |
0:efd786b99a72
|
609
|
}
|
| AtomX |
0:efd786b99a72
|
610
|
|
| AtomX |
0:efd786b99a72
|
611
|
// Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
|
| AtomX |
0:efd786b99a72
|
612
|
if (useCascadeTag)
|
| AtomX |
0:efd786b99a72
|
613
|
{
|
| AtomX |
0:efd786b99a72
|
614
|
currentLevelKnownBits += 8;
|
| AtomX |
0:efd786b99a72
|
615
|
}
|
| AtomX |
0:efd786b99a72
|
616
|
|
| AtomX |
0:efd786b99a72
|
617
|
// Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
|
| AtomX |
0:efd786b99a72
|
618
|
selectDone = false;
|
| AtomX |
0:efd786b99a72
|
619
|
while ( ! selectDone)
|
| AtomX |
0:efd786b99a72
|
620
|
{
|
| AtomX |
0:efd786b99a72
|
621
|
// Find out how many bits and bytes to send and receive.
|
| AtomX |
0:efd786b99a72
|
622
|
if (currentLevelKnownBits >= 32)
|
| AtomX |
0:efd786b99a72
|
623
|
{ // All UID bits in this Cascade Level are known. This is a SELECT.
|
| AtomX |
0:efd786b99a72
|
624
|
//Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
|
| AtomX |
0:efd786b99a72
|
625
|
buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
|
| AtomX |
0:efd786b99a72
|
626
|
|
| AtomX |
0:efd786b99a72
|
627
|
// Calulate BCC - Block Check Character
|
| AtomX |
0:efd786b99a72
|
628
|
buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
|
| AtomX |
0:efd786b99a72
|
629
|
|
| AtomX |
0:efd786b99a72
|
630
|
// Calculate CRC_A
|
| AtomX |
0:efd786b99a72
|
631
|
result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
|
| AtomX |
0:efd786b99a72
|
632
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
633
|
{
|
| AtomX |
0:efd786b99a72
|
634
|
return result;
|
| AtomX |
0:efd786b99a72
|
635
|
}
|
| AtomX |
0:efd786b99a72
|
636
|
|
| AtomX |
0:efd786b99a72
|
637
|
txLastBits = 0; // 0 => All 8 bits are valid.
|
| AtomX |
0:efd786b99a72
|
638
|
bufferUsed = 9;
|
| AtomX |
0:efd786b99a72
|
639
|
|
| AtomX |
0:efd786b99a72
|
640
|
// Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
|
| AtomX |
0:efd786b99a72
|
641
|
responseBuffer = &buffer[6];
|
| AtomX |
0:efd786b99a72
|
642
|
responseLength = 3;
|
| AtomX |
0:efd786b99a72
|
643
|
}
|
| AtomX |
0:efd786b99a72
|
644
|
else
|
| AtomX |
0:efd786b99a72
|
645
|
{ // This is an ANTICOLLISION.
|
| AtomX |
0:efd786b99a72
|
646
|
//Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
|
| AtomX |
0:efd786b99a72
|
647
|
txLastBits = currentLevelKnownBits % 8;
|
| AtomX |
0:efd786b99a72
|
648
|
count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
|
| AtomX |
0:efd786b99a72
|
649
|
index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
|
| AtomX |
0:efd786b99a72
|
650
|
buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
|
| AtomX |
0:efd786b99a72
|
651
|
bufferUsed = index + (txLastBits ? 1 : 0);
|
| AtomX |
0:efd786b99a72
|
652
|
|
| AtomX |
0:efd786b99a72
|
653
|
// Store response in the unused part of buffer
|
| AtomX |
0:efd786b99a72
|
654
|
responseBuffer = &buffer[index];
|
| AtomX |
0:efd786b99a72
|
655
|
responseLength = sizeof(buffer) - index;
|
| AtomX |
0:efd786b99a72
|
656
|
}
|
| AtomX |
0:efd786b99a72
|
657
|
|
| AtomX |
0:efd786b99a72
|
658
|
// Set bit adjustments
|
| AtomX |
0:efd786b99a72
|
659
|
rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
|
| AtomX |
0:efd786b99a72
|
660
|
PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
|
| AtomX |
0:efd786b99a72
|
661
|
|
| AtomX |
0:efd786b99a72
|
662
|
// Transmit the buffer and receive the response.
|
| AtomX |
0:efd786b99a72
|
663
|
result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
|
| AtomX |
0:efd786b99a72
|
664
|
if (result == STATUS_COLLISION)
|
| AtomX |
0:efd786b99a72
|
665
|
{ // More than one PICC in the field => collision.
|
| AtomX |
0:efd786b99a72
|
666
|
result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
|
| AtomX |
0:efd786b99a72
|
667
|
if (result & 0x20)
|
| AtomX |
0:efd786b99a72
|
668
|
{ // CollPosNotValid
|
| AtomX |
0:efd786b99a72
|
669
|
return STATUS_COLLISION; // Without a valid collision position we cannot continue
|
| AtomX |
0:efd786b99a72
|
670
|
}
|
| AtomX |
0:efd786b99a72
|
671
|
|
| AtomX |
0:efd786b99a72
|
672
|
uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
|
| AtomX |
0:efd786b99a72
|
673
|
if (collisionPos == 0)
|
| AtomX |
0:efd786b99a72
|
674
|
{
|
| AtomX |
0:efd786b99a72
|
675
|
collisionPos = 32;
|
| AtomX |
0:efd786b99a72
|
676
|
}
|
| AtomX |
0:efd786b99a72
|
677
|
|
| AtomX |
0:efd786b99a72
|
678
|
if (collisionPos <= currentLevelKnownBits)
|
| AtomX |
0:efd786b99a72
|
679
|
{ // No progress - should not happen
|
| AtomX |
0:efd786b99a72
|
680
|
return STATUS_INTERNAL_ERROR;
|
| AtomX |
0:efd786b99a72
|
681
|
}
|
| AtomX |
0:efd786b99a72
|
682
|
|
| AtomX |
0:efd786b99a72
|
683
|
// Choose the PICC with the bit set.
|
| AtomX |
0:efd786b99a72
|
684
|
currentLevelKnownBits = collisionPos;
|
| AtomX |
0:efd786b99a72
|
685
|
count = (currentLevelKnownBits - 1) % 8; // The bit to modify
|
| AtomX |
0:efd786b99a72
|
686
|
index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
|
| AtomX |
0:efd786b99a72
|
687
|
buffer[index] |= (1 << count);
|
| AtomX |
0:efd786b99a72
|
688
|
}
|
| AtomX |
0:efd786b99a72
|
689
|
else if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
690
|
{
|
| AtomX |
0:efd786b99a72
|
691
|
return result;
|
| AtomX |
0:efd786b99a72
|
692
|
}
|
| AtomX |
0:efd786b99a72
|
693
|
else
|
| AtomX |
0:efd786b99a72
|
694
|
{ // STATUS_OK
|
| AtomX |
0:efd786b99a72
|
695
|
if (currentLevelKnownBits >= 32)
|
| AtomX |
0:efd786b99a72
|
696
|
{ // This was a SELECT.
|
| AtomX |
0:efd786b99a72
|
697
|
selectDone = true; // No more anticollision
|
| AtomX |
0:efd786b99a72
|
698
|
// We continue below outside the while.
|
| AtomX |
0:efd786b99a72
|
699
|
}
|
| AtomX |
0:efd786b99a72
|
700
|
else
|
| AtomX |
0:efd786b99a72
|
701
|
{ // This was an ANTICOLLISION.
|
| AtomX |
0:efd786b99a72
|
702
|
// We now have all 32 bits of the UID in this Cascade Level
|
| AtomX |
0:efd786b99a72
|
703
|
currentLevelKnownBits = 32;
|
| AtomX |
0:efd786b99a72
|
704
|
// Run loop again to do the SELECT.
|
| AtomX |
0:efd786b99a72
|
705
|
}
|
| AtomX |
0:efd786b99a72
|
706
|
}
|
| AtomX |
0:efd786b99a72
|
707
|
} // End of while ( ! selectDone)
|
| AtomX |
0:efd786b99a72
|
708
|
|
| AtomX |
0:efd786b99a72
|
709
|
// We do not check the CBB - it was constructed by us above.
|
| AtomX |
0:efd786b99a72
|
710
|
|
| AtomX |
0:efd786b99a72
|
711
|
// Copy the found UID bytes from buffer[] to uid->uidByte[]
|
| AtomX |
0:efd786b99a72
|
712
|
index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
|
| AtomX |
0:efd786b99a72
|
713
|
bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
|
| AtomX |
0:efd786b99a72
|
714
|
for (count = 0; count < bytesToCopy; count++)
|
| AtomX |
0:efd786b99a72
|
715
|
{
|
| AtomX |
0:efd786b99a72
|
716
|
uid->uidByte[uidIndex + count] = buffer[index++];
|
| AtomX |
0:efd786b99a72
|
717
|
}
|
| AtomX |
0:efd786b99a72
|
718
|
|
| AtomX |
0:efd786b99a72
|
719
|
// Check response SAK (Select Acknowledge)
|
| AtomX |
0:efd786b99a72
|
720
|
if (responseLength != 3 || txLastBits != 0)
|
| AtomX |
0:efd786b99a72
|
721
|
{ // SAK must be exactly 24 bits (1 byte + CRC_A).
|
| AtomX |
0:efd786b99a72
|
722
|
return STATUS_ERROR;
|
| AtomX |
0:efd786b99a72
|
723
|
}
|
| AtomX |
0:efd786b99a72
|
724
|
|
| AtomX |
0:efd786b99a72
|
725
|
// Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
|
| AtomX |
0:efd786b99a72
|
726
|
result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
|
| AtomX |
0:efd786b99a72
|
727
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
728
|
{
|
| AtomX |
0:efd786b99a72
|
729
|
return result;
|
| AtomX |
0:efd786b99a72
|
730
|
}
|
| AtomX |
0:efd786b99a72
|
731
|
|
| AtomX |
0:efd786b99a72
|
732
|
if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
|
| AtomX |
0:efd786b99a72
|
733
|
{
|
| AtomX |
0:efd786b99a72
|
734
|
return STATUS_CRC_WRONG;
|
| AtomX |
0:efd786b99a72
|
735
|
}
|
| AtomX |
0:efd786b99a72
|
736
|
|
| AtomX |
0:efd786b99a72
|
737
|
if (responseBuffer[0] & 0x04)
|
| AtomX |
0:efd786b99a72
|
738
|
{ // Cascade bit set - UID not complete yes
|
| AtomX |
0:efd786b99a72
|
739
|
cascadeLevel++;
|
| AtomX |
0:efd786b99a72
|
740
|
}
|
| AtomX |
0:efd786b99a72
|
741
|
else
|
| AtomX |
0:efd786b99a72
|
742
|
{
|
| AtomX |
0:efd786b99a72
|
743
|
uidComplete = true;
|
| AtomX |
0:efd786b99a72
|
744
|
uid->sak = responseBuffer[0];
|
| AtomX |
0:efd786b99a72
|
745
|
}
|
| AtomX |
0:efd786b99a72
|
746
|
} // End of while ( ! uidComplete)
|
| AtomX |
0:efd786b99a72
|
747
|
|
| AtomX |
0:efd786b99a72
|
748
|
// Set correct uid->size
|
| AtomX |
0:efd786b99a72
|
749
|
uid->size = 3 * cascadeLevel + 1;
|
| AtomX |
0:efd786b99a72
|
750
|
|
| AtomX |
0:efd786b99a72
|
751
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
752
|
} // End PICC_Select()
|
| AtomX |
0:efd786b99a72
|
753
|
|
| AtomX |
1:63d729186747
|
754
|
/*
|
| AtomX |
0:efd786b99a72
|
755
|
* Instructs a PICC in state ACTIVE(*) to go to state HALT.
|
| AtomX |
0:efd786b99a72
|
756
|
*/
|
| AtomX |
0:efd786b99a72
|
757
|
uint8_t MFRC522::PICC_HaltA()
|
| AtomX |
0:efd786b99a72
|
758
|
{
|
| AtomX |
0:efd786b99a72
|
759
|
uint8_t result;
|
| AtomX |
0:efd786b99a72
|
760
|
uint8_t buffer[4];
|
| AtomX |
0:efd786b99a72
|
761
|
|
| AtomX |
0:efd786b99a72
|
762
|
// Build command buffer
|
| AtomX |
0:efd786b99a72
|
763
|
buffer[0] = PICC_CMD_HLTA;
|
| AtomX |
0:efd786b99a72
|
764
|
buffer[1] = 0;
|
| AtomX |
0:efd786b99a72
|
765
|
|
| AtomX |
0:efd786b99a72
|
766
|
// Calculate CRC_A
|
| AtomX |
0:efd786b99a72
|
767
|
result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
|
| AtomX |
0:efd786b99a72
|
768
|
if (result == STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
769
|
{
|
| AtomX |
0:efd786b99a72
|
770
|
// Send the command.
|
| AtomX |
0:efd786b99a72
|
771
|
// The standard says:
|
| AtomX |
0:efd786b99a72
|
772
|
// If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
|
| AtomX |
0:efd786b99a72
|
773
|
// HLTA command, this response shall be interpreted as 'not acknowledge'.
|
| AtomX |
0:efd786b99a72
|
774
|
// We interpret that this way: Only STATUS_TIMEOUT is an success.
|
| AtomX |
0:efd786b99a72
|
775
|
result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
|
| AtomX |
0:efd786b99a72
|
776
|
if (result == STATUS_TIMEOUT)
|
| AtomX |
0:efd786b99a72
|
777
|
{
|
| AtomX |
0:efd786b99a72
|
778
|
result = STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
779
|
}
|
| AtomX |
0:efd786b99a72
|
780
|
else if (result == STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
781
|
{ // That is ironically NOT ok in this case ;-)
|
| AtomX |
0:efd786b99a72
|
782
|
result = STATUS_ERROR;
|
| AtomX |
0:efd786b99a72
|
783
|
}
|
| AtomX |
0:efd786b99a72
|
784
|
}
|
| AtomX |
0:efd786b99a72
|
785
|
|
| AtomX |
0:efd786b99a72
|
786
|
return result;
|
| AtomX |
0:efd786b99a72
|
787
|
} // End PICC_HaltA()
|
| AtomX |
0:efd786b99a72
|
788
|
|
| AtomX |
0:efd786b99a72
|
789
|
|
| AtomX |
0:efd786b99a72
|
790
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
791
|
// Functions for communicating with MIFARE PICCs
|
| AtomX |
0:efd786b99a72
|
792
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
793
|
|
| AtomX |
1:63d729186747
|
794
|
/*
|
| AtomX |
0:efd786b99a72
|
795
|
* Executes the MFRC522 MFAuthent command.
|
| AtomX |
0:efd786b99a72
|
796
|
*/
|
| AtomX |
0:efd786b99a72
|
797
|
uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
|
| AtomX |
0:efd786b99a72
|
798
|
{
|
| AtomX |
0:efd786b99a72
|
799
|
uint8_t i, waitIRq = 0x10; // IdleIRq
|
| AtomX |
0:efd786b99a72
|
800
|
|
| AtomX |
0:efd786b99a72
|
801
|
// Build command buffer
|
| AtomX |
0:efd786b99a72
|
802
|
uint8_t sendData[12];
|
| AtomX |
0:efd786b99a72
|
803
|
sendData[0] = command;
|
| AtomX |
0:efd786b99a72
|
804
|
sendData[1] = blockAddr;
|
| AtomX |
0:efd786b99a72
|
805
|
|
| AtomX |
0:efd786b99a72
|
806
|
for (i = 0; i < MF_KEY_SIZE; i++)
|
| AtomX |
0:efd786b99a72
|
807
|
{ // 6 key bytes
|
| AtomX |
0:efd786b99a72
|
808
|
sendData[2+i] = key->keyByte[i];
|
| AtomX |
0:efd786b99a72
|
809
|
}
|
| AtomX |
0:efd786b99a72
|
810
|
|
| AtomX |
0:efd786b99a72
|
811
|
for (i = 0; i < 4; i++)
|
| AtomX |
0:efd786b99a72
|
812
|
{ // The first 4 bytes of the UID
|
| AtomX |
0:efd786b99a72
|
813
|
sendData[8+i] = uid->uidByte[i];
|
| AtomX |
0:efd786b99a72
|
814
|
}
|
| AtomX |
0:efd786b99a72
|
815
|
|
| AtomX |
0:efd786b99a72
|
816
|
// Start the authentication.
|
| AtomX |
0:efd786b99a72
|
817
|
return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
|
| AtomX |
0:efd786b99a72
|
818
|
} // End PCD_Authenticate()
|
| AtomX |
0:efd786b99a72
|
819
|
|
| AtomX |
1:63d729186747
|
820
|
/*
|
| AtomX |
0:efd786b99a72
|
821
|
* Used to exit the PCD from its authenticated state.
|
| AtomX |
0:efd786b99a72
|
822
|
* Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
|
| AtomX |
0:efd786b99a72
|
823
|
*/
|
| AtomX |
0:efd786b99a72
|
824
|
void MFRC522::PCD_StopCrypto1()
|
| AtomX |
0:efd786b99a72
|
825
|
{
|
| AtomX |
0:efd786b99a72
|
826
|
// Clear MFCrypto1On bit
|
| AtomX |
0:efd786b99a72
|
827
|
PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
|
| AtomX |
0:efd786b99a72
|
828
|
} // End PCD_StopCrypto1()
|
| AtomX |
0:efd786b99a72
|
829
|
|
| AtomX |
1:63d729186747
|
830
|
/*
|
| AtomX |
0:efd786b99a72
|
831
|
* Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
|
| AtomX |
0:efd786b99a72
|
832
|
*/
|
| AtomX |
0:efd786b99a72
|
833
|
uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
|
| AtomX |
0:efd786b99a72
|
834
|
{
|
| AtomX |
0:efd786b99a72
|
835
|
uint8_t result = STATUS_NO_ROOM;
|
| AtomX |
0:efd786b99a72
|
836
|
|
| AtomX |
0:efd786b99a72
|
837
|
// Sanity check
|
| AtomX |
0:efd786b99a72
|
838
|
if ((buffer == NULL) || (*bufferSize < 18))
|
| AtomX |
0:efd786b99a72
|
839
|
{
|
| AtomX |
0:efd786b99a72
|
840
|
return result;
|
| AtomX |
0:efd786b99a72
|
841
|
}
|
| AtomX |
0:efd786b99a72
|
842
|
|
| AtomX |
0:efd786b99a72
|
843
|
// Build command buffer
|
| AtomX |
0:efd786b99a72
|
844
|
buffer[0] = PICC_CMD_MF_READ;
|
| AtomX |
0:efd786b99a72
|
845
|
buffer[1] = blockAddr;
|
| AtomX |
0:efd786b99a72
|
846
|
|
| AtomX |
0:efd786b99a72
|
847
|
// Calculate CRC_A
|
| AtomX |
0:efd786b99a72
|
848
|
result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
|
| AtomX |
0:efd786b99a72
|
849
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
850
|
{
|
| AtomX |
0:efd786b99a72
|
851
|
return result;
|
| AtomX |
0:efd786b99a72
|
852
|
}
|
| AtomX |
0:efd786b99a72
|
853
|
|
| AtomX |
0:efd786b99a72
|
854
|
// Transmit the buffer and receive the response, validate CRC_A.
|
| AtomX |
0:efd786b99a72
|
855
|
return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
|
| AtomX |
0:efd786b99a72
|
856
|
} // End MIFARE_Read()
|
| AtomX |
0:efd786b99a72
|
857
|
|
| AtomX |
1:63d729186747
|
858
|
/*
|
| AtomX |
0:efd786b99a72
|
859
|
* Writes 16 bytes to the active PICC.
|
| AtomX |
0:efd786b99a72
|
860
|
*/
|
| AtomX |
0:efd786b99a72
|
861
|
uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
|
| AtomX |
0:efd786b99a72
|
862
|
{
|
| AtomX |
0:efd786b99a72
|
863
|
uint8_t result;
|
| AtomX |
0:efd786b99a72
|
864
|
|
| AtomX |
0:efd786b99a72
|
865
|
// Sanity check
|
| AtomX |
0:efd786b99a72
|
866
|
if (buffer == NULL || bufferSize < 16)
|
| AtomX |
0:efd786b99a72
|
867
|
{
|
| AtomX |
0:efd786b99a72
|
868
|
return STATUS_INVALID;
|
| AtomX |
0:efd786b99a72
|
869
|
}
|
| AtomX |
0:efd786b99a72
|
870
|
|
| AtomX |
0:efd786b99a72
|
871
|
// Mifare Classic protocol requires two communications to perform a write.
|
| AtomX |
0:efd786b99a72
|
872
|
// Step 1: Tell the PICC we want to write to block blockAddr.
|
| AtomX |
0:efd786b99a72
|
873
|
uint8_t cmdBuffer[2];
|
| AtomX |
0:efd786b99a72
|
874
|
cmdBuffer[0] = PICC_CMD_MF_WRITE;
|
| AtomX |
0:efd786b99a72
|
875
|
cmdBuffer[1] = blockAddr;
|
| AtomX |
0:efd786b99a72
|
876
|
// Adds CRC_A and checks that the response is MF_ACK.
|
| AtomX |
0:efd786b99a72
|
877
|
result = PCD_MIFARE_Transceive(cmdBuffer, 2);
|
| AtomX |
0:efd786b99a72
|
878
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
879
|
{
|
| AtomX |
0:efd786b99a72
|
880
|
return result;
|
| AtomX |
0:efd786b99a72
|
881
|
}
|
| AtomX |
0:efd786b99a72
|
882
|
|
| AtomX |
0:efd786b99a72
|
883
|
// Step 2: Transfer the data
|
| AtomX |
0:efd786b99a72
|
884
|
// Adds CRC_A and checks that the response is MF_ACK.
|
| AtomX |
0:efd786b99a72
|
885
|
result = PCD_MIFARE_Transceive(buffer, bufferSize);
|
| AtomX |
0:efd786b99a72
|
886
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
887
|
{
|
| AtomX |
0:efd786b99a72
|
888
|
return result;
|
| AtomX |
0:efd786b99a72
|
889
|
}
|
| AtomX |
0:efd786b99a72
|
890
|
|
| AtomX |
0:efd786b99a72
|
891
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
892
|
} // End MIFARE_Write()
|
| AtomX |
0:efd786b99a72
|
893
|
|
| AtomX |
1:63d729186747
|
894
|
/*
|
| AtomX |
0:efd786b99a72
|
895
|
* Writes a 4 byte page to the active MIFARE Ultralight PICC.
|
| AtomX |
0:efd786b99a72
|
896
|
*/
|
| AtomX |
0:efd786b99a72
|
897
|
uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
|
| AtomX |
0:efd786b99a72
|
898
|
{
|
| AtomX |
0:efd786b99a72
|
899
|
uint8_t result;
|
| AtomX |
0:efd786b99a72
|
900
|
|
| AtomX |
0:efd786b99a72
|
901
|
// Sanity check
|
| AtomX |
0:efd786b99a72
|
902
|
if (buffer == NULL || bufferSize < 4)
|
| AtomX |
0:efd786b99a72
|
903
|
{
|
| AtomX |
0:efd786b99a72
|
904
|
return STATUS_INVALID;
|
| AtomX |
0:efd786b99a72
|
905
|
}
|
| AtomX |
0:efd786b99a72
|
906
|
|
| AtomX |
0:efd786b99a72
|
907
|
// Build commmand buffer
|
| AtomX |
0:efd786b99a72
|
908
|
uint8_t cmdBuffer[6];
|
| AtomX |
0:efd786b99a72
|
909
|
cmdBuffer[0] = PICC_CMD_UL_WRITE;
|
| AtomX |
0:efd786b99a72
|
910
|
cmdBuffer[1] = page;
|
| AtomX |
0:efd786b99a72
|
911
|
memcpy(&cmdBuffer[2], buffer, 4);
|
| AtomX |
0:efd786b99a72
|
912
|
|
| AtomX |
0:efd786b99a72
|
913
|
// Perform the write
|
| AtomX |
0:efd786b99a72
|
914
|
result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
|
| AtomX |
0:efd786b99a72
|
915
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
916
|
{
|
| AtomX |
0:efd786b99a72
|
917
|
return result;
|
| AtomX |
0:efd786b99a72
|
918
|
}
|
| AtomX |
0:efd786b99a72
|
919
|
|
| AtomX |
0:efd786b99a72
|
920
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
921
|
} // End MIFARE_Ultralight_Write()
|
| AtomX |
0:efd786b99a72
|
922
|
|
| AtomX |
1:63d729186747
|
923
|
/*
|
| AtomX |
0:efd786b99a72
|
924
|
* MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
|
| AtomX |
0:efd786b99a72
|
925
|
*/
|
| AtomX |
0:efd786b99a72
|
926
|
uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
|
| AtomX |
0:efd786b99a72
|
927
|
{
|
| AtomX |
0:efd786b99a72
|
928
|
return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
|
| AtomX |
0:efd786b99a72
|
929
|
} // End MIFARE_Decrement()
|
| AtomX |
0:efd786b99a72
|
930
|
|
| AtomX |
1:63d729186747
|
931
|
/*
|
| AtomX |
0:efd786b99a72
|
932
|
* MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
|
| AtomX |
0:efd786b99a72
|
933
|
*/
|
| AtomX |
0:efd786b99a72
|
934
|
uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
|
| AtomX |
0:efd786b99a72
|
935
|
{
|
| AtomX |
0:efd786b99a72
|
936
|
return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
|
| AtomX |
0:efd786b99a72
|
937
|
} // End MIFARE_Increment()
|
| AtomX |
0:efd786b99a72
|
938
|
|
| AtomX |
0:efd786b99a72
|
939
|
/**
|
| AtomX |
0:efd786b99a72
|
940
|
* MIFARE Restore copies the value of the addressed block into a volatile memory.
|
| AtomX |
0:efd786b99a72
|
941
|
*/
|
| AtomX |
0:efd786b99a72
|
942
|
uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
|
| AtomX |
0:efd786b99a72
|
943
|
{
|
| AtomX |
0:efd786b99a72
|
944
|
// The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
|
| AtomX |
0:efd786b99a72
|
945
|
// Doing only a single step does not work, so I chose to transfer 0L in step two.
|
| AtomX |
0:efd786b99a72
|
946
|
return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
|
| AtomX |
0:efd786b99a72
|
947
|
} // End MIFARE_Restore()
|
| AtomX |
0:efd786b99a72
|
948
|
|
| AtomX |
1:63d729186747
|
949
|
/*
|
| AtomX |
0:efd786b99a72
|
950
|
* Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
|
| AtomX |
0:efd786b99a72
|
951
|
*/
|
| AtomX |
0:efd786b99a72
|
952
|
uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
|
| AtomX |
0:efd786b99a72
|
953
|
{
|
| AtomX |
0:efd786b99a72
|
954
|
uint8_t result;
|
| AtomX |
0:efd786b99a72
|
955
|
uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
|
| AtomX |
0:efd786b99a72
|
956
|
|
| AtomX |
0:efd786b99a72
|
957
|
// Step 1: Tell the PICC the command and block address
|
| AtomX |
0:efd786b99a72
|
958
|
cmdBuffer[0] = command;
|
| AtomX |
0:efd786b99a72
|
959
|
cmdBuffer[1] = blockAddr;
|
| AtomX |
0:efd786b99a72
|
960
|
|
| AtomX |
0:efd786b99a72
|
961
|
// Adds CRC_A and checks that the response is MF_ACK.
|
| AtomX |
0:efd786b99a72
|
962
|
result = PCD_MIFARE_Transceive(cmdBuffer, 2);
|
| AtomX |
0:efd786b99a72
|
963
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
964
|
{
|
| AtomX |
0:efd786b99a72
|
965
|
return result;
|
| AtomX |
0:efd786b99a72
|
966
|
}
|
| AtomX |
0:efd786b99a72
|
967
|
|
| AtomX |
0:efd786b99a72
|
968
|
// Step 2: Transfer the data
|
| AtomX |
0:efd786b99a72
|
969
|
// Adds CRC_A and accept timeout as success.
|
| AtomX |
0:efd786b99a72
|
970
|
result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
|
| AtomX |
0:efd786b99a72
|
971
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
972
|
{
|
| AtomX |
0:efd786b99a72
|
973
|
return result;
|
| AtomX |
0:efd786b99a72
|
974
|
}
|
| AtomX |
0:efd786b99a72
|
975
|
|
| AtomX |
0:efd786b99a72
|
976
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
977
|
} // End MIFARE_TwoStepHelper()
|
| AtomX |
0:efd786b99a72
|
978
|
|
| AtomX |
1:63d729186747
|
979
|
/*
|
| AtomX |
0:efd786b99a72
|
980
|
* MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
|
| AtomX |
0:efd786b99a72
|
981
|
*/
|
| AtomX |
0:efd786b99a72
|
982
|
uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
|
| AtomX |
0:efd786b99a72
|
983
|
{
|
| AtomX |
0:efd786b99a72
|
984
|
uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
|
| AtomX |
0:efd786b99a72
|
985
|
|
| AtomX |
0:efd786b99a72
|
986
|
// Tell the PICC we want to transfer the result into block blockAddr.
|
| AtomX |
0:efd786b99a72
|
987
|
cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
|
| AtomX |
0:efd786b99a72
|
988
|
cmdBuffer[1] = blockAddr;
|
| AtomX |
0:efd786b99a72
|
989
|
|
| AtomX |
0:efd786b99a72
|
990
|
// Adds CRC_A and checks that the response is MF_ACK.
|
| AtomX |
0:efd786b99a72
|
991
|
return PCD_MIFARE_Transceive(cmdBuffer, 2);
|
| AtomX |
0:efd786b99a72
|
992
|
} // End MIFARE_Transfer()
|
| AtomX |
0:efd786b99a72
|
993
|
|
| AtomX |
0:efd786b99a72
|
994
|
|
| AtomX |
0:efd786b99a72
|
995
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
996
|
// Support functions
|
| AtomX |
0:efd786b99a72
|
997
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
998
|
|
| AtomX |
1:63d729186747
|
999
|
/*
|
| AtomX |
0:efd786b99a72
|
1000
|
* Wrapper for MIFARE protocol communication.
|
| AtomX |
0:efd786b99a72
|
1001
|
* Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
|
| AtomX |
0:efd786b99a72
|
1002
|
*/
|
| AtomX |
0:efd786b99a72
|
1003
|
uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
|
| AtomX |
0:efd786b99a72
|
1004
|
{
|
| AtomX |
0:efd786b99a72
|
1005
|
uint8_t result;
|
| AtomX |
0:efd786b99a72
|
1006
|
uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
|
| AtomX |
0:efd786b99a72
|
1007
|
|
| AtomX |
0:efd786b99a72
|
1008
|
// Sanity check
|
| AtomX |
0:efd786b99a72
|
1009
|
if (sendData == NULL || sendLen > 16)
|
| AtomX |
0:efd786b99a72
|
1010
|
{
|
| AtomX |
0:efd786b99a72
|
1011
|
return STATUS_INVALID;
|
| AtomX |
0:efd786b99a72
|
1012
|
}
|
| AtomX |
0:efd786b99a72
|
1013
|
|
| AtomX |
0:efd786b99a72
|
1014
|
// Copy sendData[] to cmdBuffer[] and add CRC_A
|
| AtomX |
0:efd786b99a72
|
1015
|
memcpy(cmdBuffer, sendData, sendLen);
|
| AtomX |
0:efd786b99a72
|
1016
|
result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
|
| AtomX |
0:efd786b99a72
|
1017
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
1018
|
{
|
| AtomX |
0:efd786b99a72
|
1019
|
return result;
|
| AtomX |
0:efd786b99a72
|
1020
|
}
|
| AtomX |
0:efd786b99a72
|
1021
|
|
| AtomX |
0:efd786b99a72
|
1022
|
sendLen += 2;
|
| AtomX |
0:efd786b99a72
|
1023
|
|
| AtomX |
0:efd786b99a72
|
1024
|
// Transceive the data, store the reply in cmdBuffer[]
|
| AtomX |
0:efd786b99a72
|
1025
|
uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
|
| AtomX |
0:efd786b99a72
|
1026
|
uint8_t cmdBufferSize = sizeof(cmdBuffer);
|
| AtomX |
0:efd786b99a72
|
1027
|
uint8_t validBits = 0;
|
| AtomX |
0:efd786b99a72
|
1028
|
result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
|
| AtomX |
0:efd786b99a72
|
1029
|
if (acceptTimeout && result == STATUS_TIMEOUT)
|
| AtomX |
0:efd786b99a72
|
1030
|
{
|
| AtomX |
0:efd786b99a72
|
1031
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
1032
|
}
|
| AtomX |
0:efd786b99a72
|
1033
|
|
| AtomX |
0:efd786b99a72
|
1034
|
if (result != STATUS_OK)
|
| AtomX |
0:efd786b99a72
|
1035
|
{
|
| AtomX |
0:efd786b99a72
|
1036
|
return result;
|
| AtomX |
0:efd786b99a72
|
1037
|
}
|
| AtomX |
0:efd786b99a72
|
1038
|
|
| AtomX |
0:efd786b99a72
|
1039
|
// The PICC must reply with a 4 bit ACK
|
| AtomX |
0:efd786b99a72
|
1040
|
if (cmdBufferSize != 1 || validBits != 4)
|
| AtomX |
0:efd786b99a72
|
1041
|
{
|
| AtomX |
0:efd786b99a72
|
1042
|
return STATUS_ERROR;
|
| AtomX |
0:efd786b99a72
|
1043
|
}
|
| AtomX |
0:efd786b99a72
|
1044
|
|
| AtomX |
0:efd786b99a72
|
1045
|
if (cmdBuffer[0] != MF_ACK)
|
| AtomX |
0:efd786b99a72
|
1046
|
{
|
| AtomX |
0:efd786b99a72
|
1047
|
return STATUS_MIFARE_NACK;
|
| AtomX |
0:efd786b99a72
|
1048
|
}
|
| AtomX |
0:efd786b99a72
|
1049
|
|
| AtomX |
0:efd786b99a72
|
1050
|
return STATUS_OK;
|
| AtomX |
0:efd786b99a72
|
1051
|
} // End PCD_MIFARE_Transceive()
|
| AtomX |
0:efd786b99a72
|
1052
|
|
| AtomX |
0:efd786b99a72
|
1053
|
|
| AtomX |
1:63d729186747
|
1054
|
/*
|
| AtomX |
0:efd786b99a72
|
1055
|
* Translates the SAK (Select Acknowledge) to a PICC type.
|
| AtomX |
0:efd786b99a72
|
1056
|
*/
|
| AtomX |
0:efd786b99a72
|
1057
|
uint8_t MFRC522::PICC_GetType(uint8_t sak)
|
| AtomX |
0:efd786b99a72
|
1058
|
{
|
| AtomX |
0:efd786b99a72
|
1059
|
uint8_t retType = PICC_TYPE_UNKNOWN;
|
| AtomX |
0:efd786b99a72
|
1060
|
|
| AtomX |
0:efd786b99a72
|
1061
|
if (sak & 0x04)
|
| AtomX |
0:efd786b99a72
|
1062
|
{ // UID not complete
|
| AtomX |
0:efd786b99a72
|
1063
|
retType = PICC_TYPE_NOT_COMPLETE;
|
| AtomX |
0:efd786b99a72
|
1064
|
}
|
| AtomX |
0:efd786b99a72
|
1065
|
else
|
| AtomX |
0:efd786b99a72
|
1066
|
{
|
| AtomX |
0:efd786b99a72
|
1067
|
switch (sak)
|
| AtomX |
0:efd786b99a72
|
1068
|
{
|
| AtomX |
0:efd786b99a72
|
1069
|
case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
|
| AtomX |
0:efd786b99a72
|
1070
|
case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
|
| AtomX |
0:efd786b99a72
|
1071
|
case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
|
| AtomX |
0:efd786b99a72
|
1072
|
case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
|
| AtomX |
0:efd786b99a72
|
1073
|
case 0x10:
|
| AtomX |
0:efd786b99a72
|
1074
|
case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
|
| AtomX |
0:efd786b99a72
|
1075
|
case 0x01: retType = PICC_TYPE_TNP3XXX; break;
|
| AtomX |
0:efd786b99a72
|
1076
|
default:
|
| AtomX |
0:efd786b99a72
|
1077
|
if (sak & 0x20)
|
| AtomX |
0:efd786b99a72
|
1078
|
{
|
| AtomX |
0:efd786b99a72
|
1079
|
retType = PICC_TYPE_ISO_14443_4;
|
| AtomX |
0:efd786b99a72
|
1080
|
}
|
| AtomX |
0:efd786b99a72
|
1081
|
else if (sak & 0x40)
|
| AtomX |
0:efd786b99a72
|
1082
|
{
|
| AtomX |
0:efd786b99a72
|
1083
|
retType = PICC_TYPE_ISO_18092;
|
| AtomX |
0:efd786b99a72
|
1084
|
}
|
| AtomX |
0:efd786b99a72
|
1085
|
break;
|
| AtomX |
0:efd786b99a72
|
1086
|
}
|
| AtomX |
0:efd786b99a72
|
1087
|
}
|
| AtomX |
0:efd786b99a72
|
1088
|
|
| AtomX |
0:efd786b99a72
|
1089
|
return (retType);
|
| AtomX |
0:efd786b99a72
|
1090
|
} // End PICC_GetType()
|
| AtomX |
0:efd786b99a72
|
1091
|
|
| AtomX |
1:63d729186747
|
1092
|
/*
|
| AtomX |
0:efd786b99a72
|
1093
|
* Returns a string pointer to the PICC type name.
|
| AtomX |
0:efd786b99a72
|
1094
|
*/
|
| AtomX |
0:efd786b99a72
|
1095
|
char* MFRC522::PICC_GetTypeName(uint8_t piccType)
|
| AtomX |
0:efd786b99a72
|
1096
|
{
|
| AtomX |
0:efd786b99a72
|
1097
|
if(piccType == PICC_TYPE_NOT_COMPLETE)
|
| AtomX |
0:efd786b99a72
|
1098
|
{
|
| AtomX |
0:efd786b99a72
|
1099
|
piccType = MFRC522_MaxPICCs - 1;
|
| AtomX |
0:efd786b99a72
|
1100
|
}
|
| AtomX |
0:efd786b99a72
|
1101
|
|
| AtomX |
0:efd786b99a72
|
1102
|
return((char *) _TypeNamePICC[piccType]);
|
| AtomX |
0:efd786b99a72
|
1103
|
} // End PICC_GetTypeName()
|
| AtomX |
0:efd786b99a72
|
1104
|
|
| AtomX |
1:63d729186747
|
1105
|
/*
|
| AtomX |
0:efd786b99a72
|
1106
|
* Returns a string pointer to a status code name.
|
| AtomX |
0:efd786b99a72
|
1107
|
*/
|
| AtomX |
0:efd786b99a72
|
1108
|
char* MFRC522::GetStatusCodeName(uint8_t code)
|
| AtomX |
0:efd786b99a72
|
1109
|
{
|
| AtomX |
0:efd786b99a72
|
1110
|
return((char *) _ErrorMessage[code]);
|
| AtomX |
0:efd786b99a72
|
1111
|
} // End GetStatusCodeName()
|
| AtomX |
0:efd786b99a72
|
1112
|
|
| AtomX |
1:63d729186747
|
1113
|
/*
|
| AtomX |
0:efd786b99a72
|
1114
|
* Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
|
| AtomX |
0:efd786b99a72
|
1115
|
*/
|
| AtomX |
1:63d729186747
|
1116
|
void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
|
| AtomX |
1:63d729186747
|
1117
|
uint8_t g0,
|
| AtomX |
1:63d729186747
|
1118
|
uint8_t g1,
|
| AtomX |
1:63d729186747
|
1119
|
uint8_t g2,
|
| AtomX |
1:63d729186747
|
1120
|
uint8_t g3)
|
| AtomX |
0:efd786b99a72
|
1121
|
{
|
| AtomX |
0:efd786b99a72
|
1122
|
uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
|
| AtomX |
0:efd786b99a72
|
1123
|
uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
|
| AtomX |
0:efd786b99a72
|
1124
|
uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
|
| AtomX |
0:efd786b99a72
|
1125
|
|
| AtomX |
0:efd786b99a72
|
1126
|
accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
|
| AtomX |
0:efd786b99a72
|
1127
|
accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
|
| AtomX |
0:efd786b99a72
|
1128
|
accessBitBuffer[2] = c3 << 4 | c2;
|
| AtomX |
0:efd786b99a72
|
1129
|
} // End MIFARE_SetAccessBits()
|
| AtomX |
0:efd786b99a72
|
1130
|
|
| AtomX |
0:efd786b99a72
|
1131
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
1132
|
// Convenience functions - does not add extra functionality
|
| AtomX |
0:efd786b99a72
|
1133
|
/////////////////////////////////////////////////////////////////////////////////////
|
| AtomX |
0:efd786b99a72
|
1134
|
|
| AtomX |
1:63d729186747
|
1135
|
/*
|
| AtomX |
0:efd786b99a72
|
1136
|
* Returns true if a PICC responds to PICC_CMD_REQA.
|
| AtomX |
0:efd786b99a72
|
1137
|
* Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
|
| AtomX |
0:efd786b99a72
|
1138
|
*/
|
| AtomX |
0:efd786b99a72
|
1139
|
bool MFRC522::PICC_IsNewCardPresent(void)
|
| AtomX |
0:efd786b99a72
|
1140
|
{
|
| AtomX |
0:efd786b99a72
|
1141
|
uint8_t bufferATQA[2];
|
| AtomX |
0:efd786b99a72
|
1142
|
uint8_t bufferSize = sizeof(bufferATQA);
|
| AtomX |
0:efd786b99a72
|
1143
|
uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
|
| AtomX |
0:efd786b99a72
|
1144
|
return ((result == STATUS_OK) || (result == STATUS_COLLISION));
|
| AtomX |
0:efd786b99a72
|
1145
|
} // End PICC_IsNewCardPresent()
|
| AtomX |
0:efd786b99a72
|
1146
|
|
| AtomX |
1:63d729186747
|
1147
|
/*
|
| AtomX |
0:efd786b99a72
|
1148
|
* Simple wrapper around PICC_Select.
|
| AtomX |
0:efd786b99a72
|
1149
|
*/
|
| AtomX |
0:efd786b99a72
|
1150
|
bool MFRC522::PICC_ReadCardSerial(void)
|
| AtomX |
0:efd786b99a72
|
1151
|
{
|
| AtomX |
0:efd786b99a72
|
1152
|
uint8_t result = PICC_Select(&uid);
|
| AtomX |
0:efd786b99a72
|
1153
|
return (result == STATUS_OK);
|
| AtomX |
0:efd786b99a72
|
1154
|
} // End PICC_ReadCardSerial()
|