Andrew Boyson
A stack which works with or without an Mbed os library. Provides IPv4 or IPv6 with a full 1500 byte buffer.
Dependents: oldheating gps motorhome heating
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nicdefs.h
00001 00002 struct RX_DESC_TypeDef 00003 { 00004 unsigned int Packet; 00005 unsigned int Ctrl; 00006 }; 00007 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; 00008 00009 00010 struct RX_STAT_TypeDef 00011 { 00012 unsigned int Info; 00013 unsigned int HashCRC; 00014 }; 00015 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; 00016 00017 00018 struct TX_DESC_TypeDef 00019 { 00020 unsigned int Packet; 00021 unsigned int Ctrl; 00022 }; 00023 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; 00024 00025 00026 struct TX_STAT_TypeDef 00027 { 00028 unsigned int Info; 00029 }; 00030 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; 00031 00032 00033 //Registers 00034 #define MAC1 (*((volatile unsigned *) 0x50000000)) 00035 #define MAC2 (*((volatile unsigned *) 0x50000004)) 00036 #define IPGT (*((volatile unsigned *) 0x50000008)) 00037 #define IPGR (*((volatile unsigned *) 0x5000000C)) 00038 #define CLRT (*((volatile unsigned *) 0x50000010)) 00039 #define MAXF (*((volatile unsigned *) 0x50000014)) 00040 #define SUPP (*((volatile unsigned *) 0x50000018)) 00041 #define MCFG (*((volatile unsigned *) 0x50000020)) 00042 #define MCMD (*((volatile unsigned *) 0x50000024)) 00043 #define MADR (*((volatile unsigned *) 0x50000028)) 00044 #define MWTD (*((volatile unsigned *) 0x5000002C)) 00045 #define MRDD (*((volatile unsigned *) 0x50000030)) 00046 #define MIND (*((volatile unsigned *) 0x50000034)) 00047 #define SA0 (*((volatile unsigned *) 0x50000040)) 00048 #define SA1 (*((volatile unsigned *) 0x50000044)) 00049 #define SA2 (*((volatile unsigned *) 0x50000048)) 00050 00051 #define COMMAND (*((volatile unsigned *) 0x50000100)) 00052 #define STATUS (*((volatile unsigned *) 0x50000104)) 00053 00054 #define RX_DESCRIPTOR (*((volatile unsigned *) 0x50000108)) 00055 #define RX_STATUS (*((volatile unsigned *) 0x5000010C)) 00056 #define RX_DESCRIPTOR_NUMBER (*((volatile unsigned *) 0x50000110)) 00057 #define RX_PRODUCE_INDEX (*((volatile unsigned *) 0x50000114)) 00058 #define RX_CONSUME_INDEX (*((volatile unsigned *) 0x50000118)) 00059 00060 #define TX_DESCRIPTOR (*((volatile unsigned *) 0x5000011C)) 00061 #define TX_STATUS (*((volatile unsigned *) 0x50000120)) 00062 #define TX_DESCRIPTOR_NUMBER (*((volatile unsigned *) 0x50000124)) 00063 #define TX_PRODUCE_INDEX (*((volatile unsigned *) 0x50000128)) 00064 #define TX_CONSUME_INDEX (*((volatile unsigned *) 0x5000012C)) 00065 00066 #define RX_FILTER_CTRL (*((volatile unsigned *) 0x50000200)) 00067 #define INT_ENABLE (*((volatile unsigned *) 0x50000FE4)) 00068 #define INT_CLEAR (*((volatile unsigned *) 0x50000FE8)) 00069 00070 /* MAC Configuration Register 1 */ 00071 #define MAC1_REC_EN 0x00000001 /* Receive Enable */ 00072 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ 00073 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ 00074 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ 00075 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ 00076 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ 00077 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ 00078 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ 00079 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ 00080 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ 00081 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ 00082 00083 /* MAC Configuration Register 2 */ 00084 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ 00085 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ 00086 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ 00087 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ 00088 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ 00089 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ 00090 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ 00091 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ 00092 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ 00093 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ 00094 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ 00095 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ 00096 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ 00097 00098 /* Back-to-Back Inter-Packet-Gap Register */ 00099 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ 00100 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ 00101 00102 /* Non Back-to-Back Inter-Packet-Gap Register */ 00103 #define IPGR_DEF 0x00000012 /* Recommended value */ 00104 00105 /* Collision Window/Retry Register */ 00106 #define CLRT_DEF 0x0000370F /* Default value */ 00107 00108 /* PHY Support Register */ 00109 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ 00110 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ 00111 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */ 00112 00113 /* Test Register */ 00114 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ 00115 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */ 00116 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ 00117 00118 /* MII Management Configuration Register */ 00119 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ 00120 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ 00121 #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ 00122 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ 00123 00124 /* MII Management Command Register */ 00125 #define MCMD_READ 0x00000001 /* MII Read */ 00126 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */ 00127 00128 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ 00129 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ 00130 00131 /* MII Management Address Register */ 00132 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ 00133 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ 00134 00135 /* MII Management Indicators Register */ 00136 #define MIND_BUSY 0x00000001 /* MII is Busy */ 00137 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ 00138 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ 00139 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ 00140 00141 /* Command Register */ 00142 #define CR_RX_EN 0x00000001 /* Enable Receive */ 00143 #define CR_TX_EN 0x00000002 /* Enable Transmit */ 00144 #define CR_REG_RES 0x00000008 /* Reset Host Registers */ 00145 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ 00146 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ 00147 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ 00148 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ 00149 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ 00150 #define CR_RMII 0x00000200 /* Reduced MII Interface */ 00151 #define CR_FULL_DUP 0x00000400 /* Full Duplex */ 00152 00153 /* Status Register */ 00154 #define SR_RX_EN 0x00000001 /* Enable Receive */ 00155 #define SR_TX_EN 0x00000002 /* Enable Transmit */ 00156 00157 /* Transmit Status Vector 0 Register */ 00158 #define TSV0_CRC_ERR 0x00000001 /* CRC error */ 00159 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ 00160 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ 00161 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */ 00162 #define TSV0_MCAST 0x00000010 /* Multicast Destination */ 00163 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ 00164 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ 00165 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ 00166 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ 00167 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ 00168 #define TSV0_GIANT 0x00000400 /* Giant Frame */ 00169 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ 00170 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ 00171 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ 00172 #define TSV0_PAUSE 0x20000000 /* Pause Frame */ 00173 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ 00174 #define TSV0_VLAN 0x80000000 /* VLAN Frame */ 00175 00176 /* Transmit Status Vector 1 Register */ 00177 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ 00178 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ 00179 00180 /* Receive Status Vector Register */ 00181 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ 00182 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ 00183 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ 00184 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ 00185 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ 00186 #define RSV_CRC_ERR 0x00100000 /* CRC Error */ 00187 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ 00188 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ 00189 #define RSV_REC_OK 0x00800000 /* Frame Received OK */ 00190 #define RSV_MCAST 0x01000000 /* Multicast Frame */ 00191 #define RSV_BCAST 0x02000000 /* Broadcast Frame */ 00192 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ 00193 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ 00194 #define RSV_PAUSE 0x10000000 /* Pause Frame */ 00195 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ 00196 #define RSV_VLAN 0x40000000 /* VLAN Frame */ 00197 00198 /* Flow Control Counter Register */ 00199 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ 00200 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ 00201 00202 /* Flow Control Status Register */ 00203 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ 00204 00205 /* Receive Filter Control Register */ 00206 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ 00207 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ 00208 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ 00209 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ 00210 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ 00211 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ 00212 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ 00213 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ 00214 00215 /* Receive Filter WoL Status/Clear Registers */ 00216 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ 00217 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ 00218 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ 00219 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ 00220 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ 00221 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ 00222 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ 00223 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ 00224 00225 /* Interrupt Status/Enable/Clear/Set Registers */ 00226 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ 00227 #define INT_RX_ERR 0x00000002 /* Receive Error */ 00228 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ 00229 #define INT_RX_DONE 0x00000008 /* Receive Done */ 00230 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ 00231 #define INT_TX_ERR 0x00000020 /* Transmit Error */ 00232 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ 00233 #define INT_TX_DONE 0x00000080 /* Transmit Done */ 00234 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ 00235 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ 00236 00237 /* Power Down Register */ 00238 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ 00239 00240 /* RX Descriptor Control Word */ 00241 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */ 00242 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ 00243 00244 /* RX Status Hash CRC Word */ 00245 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ 00246 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ 00247 00248 /* RX Status Information Word */ 00249 #define RINFO_SIZE 0x000007FF /* Data size in bytes */ 00250 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ 00251 #define RINFO_VLAN 0x00080000 /* VLAN Frame */ 00252 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ 00253 #define RINFO_MCAST 0x00200000 /* Multicast Frame */ 00254 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */ 00255 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ 00256 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ 00257 #define RINFO_LEN_ERR 0x02000000 /* Length Error */ 00258 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ 00259 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ 00260 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ 00261 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ 00262 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ 00263 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ 00264 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) 00265 00266 /* TX Descriptor Control Word */ 00267 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ 00268 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ 00269 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ 00270 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ 00271 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ 00272 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ 00273 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ 00274 00275 /* TX Status Information Word */ 00276 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */ 00277 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ 00278 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ 00279 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ 00280 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ 00281 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ 00282 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ 00283 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ 00284 00285 /* ENET Device Revision ID */ 00286 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ 00287 00288 /* DP83848C PHY Registers */ 00289 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ 00290 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ 00291 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ 00292 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ 00293 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ 00294 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ 00295 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ 00296 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ 00297 00298 /* PHY Extended Registers */ 00299 #define PHY_REG_STS 0x10 /* Status Register */ 00300 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ 00301 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ 00302 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ 00303 #define PHY_REG_RECR 0x15 /* Receive Error Counter */ 00304 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ 00305 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ 00306 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ 00307 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */ 00308 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ 00309 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ 00310 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ 00311 00312 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */ 00313 00314 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ 00315 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ 00316 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ 00317 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ 00318 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ 00319 00320 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ 00321 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */ 00322 00323 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */ 00324 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */ 00325 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */ 00326 00327 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */ 00328 00329 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */ 00330 00331 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */ 00332 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
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