A GPS disciplined clock
Dependencies: net lpc1768 crypto clock web log
gps/uart1.c
- Committer:
- andrewboyson
- Date:
- 2018-02-04
- Revision:
- 3:36ee2aa7945a
- Child:
- 4:108157115360
File content as of revision 3:36ee2aa7945a:
#include "defs.h" #define DL_115200 52 //115200 #define DL_9600 625 //9600 #define DIV_VAL 0 //0 == do not use #define MUL_VAL 1 //Cannot be zero int Uart1GetC() // Returns a negative number if no character to read or if there was an error. 0 to 255 otherwise. { if ((LPC_UART1->LSR & 0x01) == 0) return -1; //RDR (bit 0) is 1 if RBR has data; 0 if it is empty. return LPC_UART1->RBR; //Receive Buffer Register - oldest character in the RX FIFO } int Uart1PutC(char c) // Returns zero on success or -1 if the buffer was full or not ready { //THRE is set immediately upon detection of an empty THR and is cleared on a THR write. if ((LPC_UART1->LSR & 0x20) == 0) return -1; //THRE (bit 5) is 1 if THR is empty; 0 if it is full. LPC_UART1->THR = c; //Transmit Holding Register - newest character in the TX FIFO return 0; } void Uart1Init(int baud) { //Enable fifos LPC_UART1->FCR = 1; //Bit 0 is FIFO Enable //Disable irqs LPC_UART1->IER = 0; //Enable writing to divider registers LPC_UART1->LCR = 0x80; //set LCR[DLAB] //Set divider values int dl = 0; switch (baud) { case 115200: dl = DL_115200; break; case 9600: default : dl = DL_9600; break; } LPC_UART1->DLM = dl >> 8; LPC_UART1->DLL = dl & 0xFF; LPC_UART1->FDR = DIV_VAL | MUL_VAL << 4; // 8 bit, 1 stop, no parity, disable writing to divisors; reset DLAB LPC_UART1->LCR = 0x03; //Select the function of the tx and rx pins: P0.15 and P0.16 LPC_PINCON->PINSEL0 &= ~(3UL << 30); LPC_PINCON->PINSEL0 |= 1UL << 30; // table 80. 31:30 = 0b01; tx = P0_15; LPC_PINCON->PINMODE0 &= ~(3UL << 30); LPC_PINCON->PINSEL1 &= ~ 3UL; LPC_PINCON->PINSEL1 |= 1UL; // table 80. 01:00 = 0b01 rx = P0_16; LPC_PINCON->PINMODE1 &= ~ 3UL; }