Andrew Boyson / gps

A GPS disciplined clock

Dependencies:   net lpc1768 crypto clock web log

gps/uart1.c@14:1bce51823be0, 2018-12-04 (annotated)

Committer:
andrewboyson
Date:
Tue Dec 04 14:39:47 2018 +0000
Revision:
14:1bce51823be0
Child:
34:d9586fc921dc
Updated clock

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrewboyson 14:1bce51823be0 1 #include "bitband.h"
andrewboyson 14:1bce51823be0 2
andrewboyson 14:1bce51823be0 3 #define DL_115200 52 //115200
andrewboyson 14:1bce51823be0 4 #define DL_9600 625 //9600
andrewboyson 14:1bce51823be0 5 #define DIV_VAL 0 //0 == do not use
andrewboyson 14:1bce51823be0 6 #define MUL_VAL 1 //Cannot be zero
andrewboyson 14:1bce51823be0 7
andrewboyson 14:1bce51823be0 8 #define U1RBR_ADDR 0x40010000 //Receiver Buffer Register (DLAB = 0 RO common RBR THR DLL)
andrewboyson 14:1bce51823be0 9 #define U1THR_ADDR 0x40010000 //Transmit Holding Register (DLAB = 0 WO common RBR THR DLL)
andrewboyson 14:1bce51823be0 10 #define U1DLL_ADDR 0x40010000 //Divisor Latch LSB register (DLAB = 1 RW common RBR THR DLL)
andrewboyson 14:1bce51823be0 11 #define U1DLM_ADDR 0x40010004 //Divisor Latch MSB register (DLAB = 1 RW common IER DLM)
andrewboyson 14:1bce51823be0 12 #define U1IER_ADDR 0x40010004 //Divisor Latch MSB register (DLAB = 0 RW common IER DLM)
andrewboyson 14:1bce51823be0 13 #define U1FCR_ADDR 0x40010008 //FIFO Control Register
andrewboyson 14:1bce51823be0 14 #define U1LCR_ADDR 0x4001000C //Line Control Register
andrewboyson 14:1bce51823be0 15 #define U1LSR_ADDR 0x40010014 //Line Status Register
andrewboyson 14:1bce51823be0 16 #define U1FDR_ADDR 0x40010028 //Fractional Divider Register
andrewboyson 14:1bce51823be0 17
andrewboyson 14:1bce51823be0 18 #define RECEIVE_BUFFER_REGISTER *((volatile unsigned *) U1RBR_ADDR)
andrewboyson 14:1bce51823be0 19 #define TRANSMIT_HOLDING_REGISTER *((volatile unsigned *) U1THR_ADDR)
andrewboyson 14:1bce51823be0 20 #define LINE_CONTROL_REGISTER *((volatile unsigned *) U1LCR_ADDR)
andrewboyson 14:1bce51823be0 21 #define DIVISOR_LSB *((volatile unsigned *) U1DLL_ADDR)
andrewboyson 14:1bce51823be0 22 #define DIVISOR_MSB *((volatile unsigned *) U1DLM_ADDR)
andrewboyson 14:1bce51823be0 23 #define FRACTIONAL_DIVIDER_REGISTER *((volatile unsigned *) U1FDR_ADDR)
andrewboyson 14:1bce51823be0 24
andrewboyson 14:1bce51823be0 25 #define FIFO_ENABLE BIT_BAND4(U1FCR_ADDR, 0)
andrewboyson 14:1bce51823be0 26 #define DIVISOR_ACCESS_BIT BIT_BAND4(U1LCR_ADDR, 7) //Divisor Latch Access Bit
andrewboyson 14:1bce51823be0 27 #define RECEIVER_DATA_READY BIT_BAND4(U1LSR_ADDR, 0) //Receiver Data Ready
andrewboyson 14:1bce51823be0 28 #define TRANSMIT_HOLDING_REGISTER_EMPTY BIT_BAND4(U1LSR_ADDR, 5) //Transmitter Holding Register Empty
andrewboyson 14:1bce51823be0 29
andrewboyson 14:1bce51823be0 30 int Uart1GetC() // Returns a negative number if no character to read or if there was an error. 0 to 255 otherwise.
andrewboyson 14:1bce51823be0 31 {
andrewboyson 14:1bce51823be0 32 if (!RECEIVER_DATA_READY) return -1;
andrewboyson 14:1bce51823be0 33 return RECEIVE_BUFFER_REGISTER; //oldest character in the RX FIFO
andrewboyson 14:1bce51823be0 34 }
andrewboyson 14:1bce51823be0 35 int Uart1PutC(char c) // Returns zero on success or -1 if the buffer was full or not ready
andrewboyson 14:1bce51823be0 36 {
andrewboyson 14:1bce51823be0 37 if (!TRANSMIT_HOLDING_REGISTER_EMPTY) return -1; //set immediately upon detection of an empty THR and is cleared on a THR write.
andrewboyson 14:1bce51823be0 38 TRANSMIT_HOLDING_REGISTER = c; //newest character in the TX FIFO
andrewboyson 14:1bce51823be0 39 return 0;
andrewboyson 14:1bce51823be0 40 }
andrewboyson 14:1bce51823be0 41
andrewboyson 14:1bce51823be0 42 static void setBaud(int baud)
andrewboyson 14:1bce51823be0 43 {
andrewboyson 14:1bce51823be0 44 DIVISOR_ACCESS_BIT = 1;
andrewboyson 14:1bce51823be0 45 int dl = 0;
andrewboyson 14:1bce51823be0 46 switch (baud)
andrewboyson 14:1bce51823be0 47 {
andrewboyson 14:1bce51823be0 48 case 115200: dl = DL_115200; break;
andrewboyson 14:1bce51823be0 49 case 9600:
andrewboyson 14:1bce51823be0 50 default : dl = DL_9600; break;
andrewboyson 14:1bce51823be0 51 }
andrewboyson 14:1bce51823be0 52 DIVISOR_MSB = dl >> 8;
andrewboyson 14:1bce51823be0 53 DIVISOR_LSB = dl & 0xFF;
andrewboyson 14:1bce51823be0 54 FRACTIONAL_DIVIDER_REGISTER = DIV_VAL | MUL_VAL << 4;
andrewboyson 14:1bce51823be0 55
andrewboyson 14:1bce51823be0 56 DIVISOR_ACCESS_BIT = 0;
andrewboyson 14:1bce51823be0 57 }
andrewboyson 14:1bce51823be0 58 void Uart1Init(int baud)
andrewboyson 14:1bce51823be0 59 {
andrewboyson 14:1bce51823be0 60 FIFO_ENABLE = 1;
andrewboyson 14:1bce51823be0 61
andrewboyson 14:1bce51823be0 62 setBaud(baud);
andrewboyson 14:1bce51823be0 63
andrewboyson 14:1bce51823be0 64 LINE_CONTROL_REGISTER |= 0x03; // 8 bit, 1 stop, no parity
andrewboyson 14:1bce51823be0 65 }