André Lopes / Mbed 2 deprecated testes

VERSAO FINAL

Dependencies:   4DGL-uLCD-SE C12832 LM75B MMA7660 mbed-rtos mbed

Fork of main by André Ambrósio

PowerControl/PowerControl.h@1:39b4c6a60595, 2016-05-20 (annotated)

Committer:
andrelopes31
Date:
Fri May 20 17:34:35 2016 +0000
Revision:
1:39b4c6a60595
FINAL

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrelopes31 1:39b4c6a60595 1 /* mbed PowerControl Library
andrelopes31 1:39b4c6a60595 2 * Copyright (c) 2010 Michael Wei
andrelopes31 1:39b4c6a60595 3 */
andrelopes31 1:39b4c6a60595 4
andrelopes31 1:39b4c6a60595 5 #ifndef MBED_POWERCONTROL_H
andrelopes31 1:39b4c6a60595 6 #define MBED_POWERCONTROL_H
andrelopes31 1:39b4c6a60595 7
andrelopes31 1:39b4c6a60595 8 //shouldn't have to include, but fixes weird problems with defines
andrelopes31 1:39b4c6a60595 9 //#include "LPC1768/LPC17xx.h"
andrelopes31 1:39b4c6a60595 10
andrelopes31 1:39b4c6a60595 11 //System Control Register
andrelopes31 1:39b4c6a60595 12 // bit 0: Reserved
andrelopes31 1:39b4c6a60595 13 // bit 1: Sleep on Exit
andrelopes31 1:39b4c6a60595 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
andrelopes31 1:39b4c6a60595 15 // bit 2: Deep Sleep
andrelopes31 1:39b4c6a60595 16 #define LPC1768_SCR_SLEEPDEEP 0x4
andrelopes31 1:39b4c6a60595 17 // bit 3: Resereved
andrelopes31 1:39b4c6a60595 18 // bit 4: Send on Pending
andrelopes31 1:39b4c6a60595 19 #define LPC1768_SCR_SEVONPEND 0x10
andrelopes31 1:39b4c6a60595 20 // bit 5-31: Reserved
andrelopes31 1:39b4c6a60595 21
andrelopes31 1:39b4c6a60595 22 //Power Control Register
andrelopes31 1:39b4c6a60595 23 // bit 0: Power mode control bit 0 (power-down mode)
andrelopes31 1:39b4c6a60595 24 #define LPC1768_PCON_PM0 0x1
andrelopes31 1:39b4c6a60595 25 // bit 1: Power mode control bit 1 (deep power-down mode)
andrelopes31 1:39b4c6a60595 26 #define LPC1768_PCON_PM1 0x2
andrelopes31 1:39b4c6a60595 27 // bit 2: Brown-out reduced power mode
andrelopes31 1:39b4c6a60595 28 #define LPC1768_PCON_BODRPM 0x4
andrelopes31 1:39b4c6a60595 29 // bit 3: Brown-out global disable
andrelopes31 1:39b4c6a60595 30 #define LPC1768_PCON_BOGD 0x8
andrelopes31 1:39b4c6a60595 31 // bit 4: Brown-out reset disable
andrelopes31 1:39b4c6a60595 32 #define LPC1768_PCON_BORD 0x10
andrelopes31 1:39b4c6a60595 33 // bit 5-7 : Reserved
andrelopes31 1:39b4c6a60595 34 // bit 8: Sleep Mode Entry Flag
andrelopes31 1:39b4c6a60595 35 #define LPC1768_PCON_SMFLAG 0x100
andrelopes31 1:39b4c6a60595 36 // bit 9: Deep Sleep Entry Flag
andrelopes31 1:39b4c6a60595 37 #define LPC1768_PCON_DSFLAG 0x200
andrelopes31 1:39b4c6a60595 38 // bit 10: Power Down Entry Flag
andrelopes31 1:39b4c6a60595 39 #define LPC1768_PCON_PDFLAG 0x400
andrelopes31 1:39b4c6a60595 40 // bit 11: Deep Power Down Entry Flag
andrelopes31 1:39b4c6a60595 41 #define LPC1768_PCON_DPDFLAG 0x800
andrelopes31 1:39b4c6a60595 42 // bit 12-31: Reserved
andrelopes31 1:39b4c6a60595 43
andrelopes31 1:39b4c6a60595 44 //"Sleep Mode" (WFI).
andrelopes31 1:39b4c6a60595 45 inline void Sleep(void)
andrelopes31 1:39b4c6a60595 46 {
andrelopes31 1:39b4c6a60595 47 __WFI();
andrelopes31 1:39b4c6a60595 48 }
andrelopes31 1:39b4c6a60595 49
andrelopes31 1:39b4c6a60595 50 //"Deep Sleep" Mode
andrelopes31 1:39b4c6a60595 51 inline void DeepSleep(void)
andrelopes31 1:39b4c6a60595 52 {
andrelopes31 1:39b4c6a60595 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
andrelopes31 1:39b4c6a60595 54 __WFI();
andrelopes31 1:39b4c6a60595 55 }
andrelopes31 1:39b4c6a60595 56
andrelopes31 1:39b4c6a60595 57 //"Power-Down" Mode
andrelopes31 1:39b4c6a60595 58 inline void PowerDown(void)
andrelopes31 1:39b4c6a60595 59 {
andrelopes31 1:39b4c6a60595 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
andrelopes31 1:39b4c6a60595 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
andrelopes31 1:39b4c6a60595 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
andrelopes31 1:39b4c6a60595 63 __WFI();
andrelopes31 1:39b4c6a60595 64 //reset back to normal
andrelopes31 1:39b4c6a60595 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
andrelopes31 1:39b4c6a60595 66 }
andrelopes31 1:39b4c6a60595 67
andrelopes31 1:39b4c6a60595 68 //"Deep Power-Down" Mode
andrelopes31 1:39b4c6a60595 69 inline void DeepPowerDown(void)
andrelopes31 1:39b4c6a60595 70 {
andrelopes31 1:39b4c6a60595 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
andrelopes31 1:39b4c6a60595 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
andrelopes31 1:39b4c6a60595 73 __WFI();
andrelopes31 1:39b4c6a60595 74 //reset back to normal
andrelopes31 1:39b4c6a60595 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
andrelopes31 1:39b4c6a60595 76 }
andrelopes31 1:39b4c6a60595 77
andrelopes31 1:39b4c6a60595 78 //shut down BOD during power-down/deep sleep
andrelopes31 1:39b4c6a60595 79 inline void BrownOut_ReducedPowerMode_Enable(void)
andrelopes31 1:39b4c6a60595 80 {
andrelopes31 1:39b4c6a60595 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
andrelopes31 1:39b4c6a60595 82 }
andrelopes31 1:39b4c6a60595 83
andrelopes31 1:39b4c6a60595 84 //turn on BOD during power-down/deep sleep
andrelopes31 1:39b4c6a60595 85 inline void BrownOut_ReducedPowerMode_Disable(void)
andrelopes31 1:39b4c6a60595 86 {
andrelopes31 1:39b4c6a60595 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
andrelopes31 1:39b4c6a60595 88 }
andrelopes31 1:39b4c6a60595 89
andrelopes31 1:39b4c6a60595 90 //turn off brown out circutry
andrelopes31 1:39b4c6a60595 91 inline void BrownOut_Global_Disable(void)
andrelopes31 1:39b4c6a60595 92 {
andrelopes31 1:39b4c6a60595 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
andrelopes31 1:39b4c6a60595 94 }
andrelopes31 1:39b4c6a60595 95
andrelopes31 1:39b4c6a60595 96 //turn on brown out circutry
andrelopes31 1:39b4c6a60595 97 inline void BrownOut_Global_Enable(void)
andrelopes31 1:39b4c6a60595 98 {
andrelopes31 1:39b4c6a60595 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
andrelopes31 1:39b4c6a60595 100 }
andrelopes31 1:39b4c6a60595 101
andrelopes31 1:39b4c6a60595 102 //turn off brown out reset circutry
andrelopes31 1:39b4c6a60595 103 inline void BrownOut_Reset_Disable(void)
andrelopes31 1:39b4c6a60595 104 {
andrelopes31 1:39b4c6a60595 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
andrelopes31 1:39b4c6a60595 106 }
andrelopes31 1:39b4c6a60595 107
andrelopes31 1:39b4c6a60595 108 //turn on brown outreset circutry
andrelopes31 1:39b4c6a60595 109 inline void BrownOut_Reset_Enable(void)
andrelopes31 1:39b4c6a60595 110 {
andrelopes31 1:39b4c6a60595 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
andrelopes31 1:39b4c6a60595 112 }
andrelopes31 1:39b4c6a60595 113 //Peripheral Control Register
andrelopes31 1:39b4c6a60595 114 // bit 0: Reserved
andrelopes31 1:39b4c6a60595 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
andrelopes31 1:39b4c6a60595 116 #define LPC1768_PCONP_PCTIM0 0x2
andrelopes31 1:39b4c6a60595 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
andrelopes31 1:39b4c6a60595 118 #define LPC1768_PCONP_PCTIM1 0x4
andrelopes31 1:39b4c6a60595 119 // bit 3: PCUART0: UART 0 power/clock enable
andrelopes31 1:39b4c6a60595 120 #define LPC1768_PCONP_PCUART0 0x8
andrelopes31 1:39b4c6a60595 121 // bit 4: PCUART1: UART 1 power/clock enable
andrelopes31 1:39b4c6a60595 122 #define LPC1768_PCONP_PCUART1 0x10
andrelopes31 1:39b4c6a60595 123 // bit 5: Reserved
andrelopes31 1:39b4c6a60595 124 // bit 6: PCPWM1: PWM 1 power/clock enable
andrelopes31 1:39b4c6a60595 125 #define LPC1768_PCONP_PCPWM1 0x40
andrelopes31 1:39b4c6a60595 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
andrelopes31 1:39b4c6a60595 127 #define LPC1768_PCONP_PCI2C0 0x80
andrelopes31 1:39b4c6a60595 128 // bit 8: PCSPI: SPI interface power/clock enable
andrelopes31 1:39b4c6a60595 129 #define LPC1768_PCONP_PCSPI 0x100
andrelopes31 1:39b4c6a60595 130 // bit 9: PCRTC: RTC power/clock enable
andrelopes31 1:39b4c6a60595 131 #define LPC1768_PCONP_PCRTC 0x200
andrelopes31 1:39b4c6a60595 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
andrelopes31 1:39b4c6a60595 133 #define LPC1768_PCONP_PCSSP1 0x400
andrelopes31 1:39b4c6a60595 134 // bit 11: Reserved
andrelopes31 1:39b4c6a60595 135 // bit 12: PCADC: A/D converter power/clock enable
andrelopes31 1:39b4c6a60595 136 #define LPC1768_PCONP_PCADC 0x1000
andrelopes31 1:39b4c6a60595 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
andrelopes31 1:39b4c6a60595 138 #define LPC1768_PCONP_PCCAN1 0x2000
andrelopes31 1:39b4c6a60595 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
andrelopes31 1:39b4c6a60595 140 #define LPC1768_PCONP_PCCAN2 0x4000
andrelopes31 1:39b4c6a60595 141 // bit 15: PCGPIO: GPIOs power/clock enable
andrelopes31 1:39b4c6a60595 142 #define LPC1768_PCONP_PCGPIO 0x8000
andrelopes31 1:39b4c6a60595 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
andrelopes31 1:39b4c6a60595 144 #define LPC1768_PCONP_PCRIT 0x10000
andrelopes31 1:39b4c6a60595 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
andrelopes31 1:39b4c6a60595 146 #define LPC1768_PCONP_PCMCPWM 0x20000
andrelopes31 1:39b4c6a60595 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
andrelopes31 1:39b4c6a60595 148 #define LPC1768_PCONP_PCQEI 0x40000
andrelopes31 1:39b4c6a60595 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
andrelopes31 1:39b4c6a60595 150 #define LPC1768_PCONP_PCI2C1 0x80000
andrelopes31 1:39b4c6a60595 151 // bit 20: Reserved
andrelopes31 1:39b4c6a60595 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
andrelopes31 1:39b4c6a60595 153 #define LPC1768_PCONP_PCSSP0 0x200000
andrelopes31 1:39b4c6a60595 154 // bit 22: PCTIM2: Timer 2 power/clock enable
andrelopes31 1:39b4c6a60595 155 #define LPC1768_PCONP_PCTIM2 0x400000
andrelopes31 1:39b4c6a60595 156 // bit 23: PCTIM3: Timer 3 power/clock enable
andrelopes31 1:39b4c6a60595 157 #define LPC1768_PCONP_PCQTIM3 0x800000
andrelopes31 1:39b4c6a60595 158 // bit 24: PCUART2: UART 2 power/clock enable
andrelopes31 1:39b4c6a60595 159 #define LPC1768_PCONP_PCUART2 0x1000000
andrelopes31 1:39b4c6a60595 160 // bit 25: PCUART3: UART 3 power/clock enable
andrelopes31 1:39b4c6a60595 161 #define LPC1768_PCONP_PCUART3 0x2000000
andrelopes31 1:39b4c6a60595 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
andrelopes31 1:39b4c6a60595 163 #define LPC1768_PCONP_PCI2C2 0x4000000
andrelopes31 1:39b4c6a60595 164 // bit 27: PCI2S: I2S interface power/clock enable
andrelopes31 1:39b4c6a60595 165 #define LPC1768_PCONP_PCI2S 0x8000000
andrelopes31 1:39b4c6a60595 166 // bit 28: Reserved
andrelopes31 1:39b4c6a60595 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
andrelopes31 1:39b4c6a60595 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
andrelopes31 1:39b4c6a60595 169 // bit 30: PCENET: Ethernet block power/clock enable
andrelopes31 1:39b4c6a60595 170 #define LPC1768_PCONP_PCENET 0x40000000
andrelopes31 1:39b4c6a60595 171 // bit 31: PCUSB: USB interface power/clock enable
andrelopes31 1:39b4c6a60595 172 #define LPC1768_PCONP_PCUSB 0x80000000
andrelopes31 1:39b4c6a60595 173
andrelopes31 1:39b4c6a60595 174 //Powers Up specified Peripheral(s)
andrelopes31 1:39b4c6a60595 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
andrelopes31 1:39b4c6a60595 176 {
andrelopes31 1:39b4c6a60595 177 return LPC_SC->PCONP |= bitMask;
andrelopes31 1:39b4c6a60595 178 }
andrelopes31 1:39b4c6a60595 179
andrelopes31 1:39b4c6a60595 180 //Powers Down specified Peripheral(s)
andrelopes31 1:39b4c6a60595 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
andrelopes31 1:39b4c6a60595 182 {
andrelopes31 1:39b4c6a60595 183 return LPC_SC->PCONP &= ~bitMask;
andrelopes31 1:39b4c6a60595 184 }
andrelopes31 1:39b4c6a60595 185
andrelopes31 1:39b4c6a60595 186 //returns if the peripheral is on or off
andrelopes31 1:39b4c6a60595 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
andrelopes31 1:39b4c6a60595 188 {
andrelopes31 1:39b4c6a60595 189 return (LPC_SC->PCONP & peripheral) ? true : false;
andrelopes31 1:39b4c6a60595 190 }
andrelopes31 1:39b4c6a60595 191
andrelopes31 1:39b4c6a60595 192 #endif