André Lopes / Mbed 2 deprecated testes

VERSAO FINAL

Dependencies:   4DGL-uLCD-SE C12832 LM75B MMA7660 mbed-rtos mbed

Fork of main by André Ambrósio

PowerControl/EthernetPowerControl.cpp@1:39b4c6a60595, 2016-05-20 (annotated)

Committer:
andrelopes31
Date:
Fri May 20 17:34:35 2016 +0000
Revision:
1:39b4c6a60595
FINAL

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrelopes31 1:39b4c6a60595 1 #include "EthernetPowerControl.h"
andrelopes31 1:39b4c6a60595 2
andrelopes31 1:39b4c6a60595 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
andrelopes31 1:39b4c6a60595 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
andrelopes31 1:39b4c6a60595 5 unsigned int tout;
andrelopes31 1:39b4c6a60595 6 /* Hardware MII Management for LPC176x devices. */
andrelopes31 1:39b4c6a60595 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
andrelopes31 1:39b4c6a60595 8 LPC_EMAC->MWTD = Value;
andrelopes31 1:39b4c6a60595 9
andrelopes31 1:39b4c6a60595 10 /* Wait utill operation completed */
andrelopes31 1:39b4c6a60595 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
andrelopes31 1:39b4c6a60595 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
andrelopes31 1:39b4c6a60595 13 break;
andrelopes31 1:39b4c6a60595 14 }
andrelopes31 1:39b4c6a60595 15 }
andrelopes31 1:39b4c6a60595 16 }
andrelopes31 1:39b4c6a60595 17
andrelopes31 1:39b4c6a60595 18 static unsigned short read_PHY (unsigned int PhyReg) {
andrelopes31 1:39b4c6a60595 19 /* Read a PHY register 'PhyReg'. */
andrelopes31 1:39b4c6a60595 20 unsigned int tout, val;
andrelopes31 1:39b4c6a60595 21
andrelopes31 1:39b4c6a60595 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
andrelopes31 1:39b4c6a60595 23 LPC_EMAC->MCMD = MCMD_READ;
andrelopes31 1:39b4c6a60595 24
andrelopes31 1:39b4c6a60595 25 /* Wait until operation completed */
andrelopes31 1:39b4c6a60595 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
andrelopes31 1:39b4c6a60595 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
andrelopes31 1:39b4c6a60595 28 break;
andrelopes31 1:39b4c6a60595 29 }
andrelopes31 1:39b4c6a60595 30 }
andrelopes31 1:39b4c6a60595 31 LPC_EMAC->MCMD = 0;
andrelopes31 1:39b4c6a60595 32 val = LPC_EMAC->MRDD;
andrelopes31 1:39b4c6a60595 33
andrelopes31 1:39b4c6a60595 34 return (val);
andrelopes31 1:39b4c6a60595 35 }
andrelopes31 1:39b4c6a60595 36
andrelopes31 1:39b4c6a60595 37 void EMAC_Init()
andrelopes31 1:39b4c6a60595 38 {
andrelopes31 1:39b4c6a60595 39 unsigned int tout,regv;
andrelopes31 1:39b4c6a60595 40 /* Power Up the EMAC controller. */
andrelopes31 1:39b4c6a60595 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
andrelopes31 1:39b4c6a60595 42
andrelopes31 1:39b4c6a60595 43 LPC_PINCON->PINSEL2 = 0x50150105;
andrelopes31 1:39b4c6a60595 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
andrelopes31 1:39b4c6a60595 45 LPC_PINCON->PINSEL3 |= 0x00000005;
andrelopes31 1:39b4c6a60595 46
andrelopes31 1:39b4c6a60595 47 /* Reset all EMAC internal modules. */
andrelopes31 1:39b4c6a60595 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
andrelopes31 1:39b4c6a60595 49 MAC1_SIM_RES | MAC1_SOFT_RES;
andrelopes31 1:39b4c6a60595 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
andrelopes31 1:39b4c6a60595 51
andrelopes31 1:39b4c6a60595 52 /* A short delay after reset. */
andrelopes31 1:39b4c6a60595 53 for (tout = 100; tout; tout--);
andrelopes31 1:39b4c6a60595 54
andrelopes31 1:39b4c6a60595 55 /* Initialize MAC control registers. */
andrelopes31 1:39b4c6a60595 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
andrelopes31 1:39b4c6a60595 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
andrelopes31 1:39b4c6a60595 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
andrelopes31 1:39b4c6a60595 59 LPC_EMAC->CLRT = CLRT_DEF;
andrelopes31 1:39b4c6a60595 60 LPC_EMAC->IPGR = IPGR_DEF;
andrelopes31 1:39b4c6a60595 61
andrelopes31 1:39b4c6a60595 62 /* Enable Reduced MII interface. */
andrelopes31 1:39b4c6a60595 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
andrelopes31 1:39b4c6a60595 64
andrelopes31 1:39b4c6a60595 65 /* Reset Reduced MII Logic. */
andrelopes31 1:39b4c6a60595 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
andrelopes31 1:39b4c6a60595 67 for (tout = 100; tout; tout--);
andrelopes31 1:39b4c6a60595 68 LPC_EMAC->SUPP = 0;
andrelopes31 1:39b4c6a60595 69
andrelopes31 1:39b4c6a60595 70 /* Put the DP83848C in reset mode */
andrelopes31 1:39b4c6a60595 71 write_PHY (PHY_REG_BMCR, 0x8000);
andrelopes31 1:39b4c6a60595 72
andrelopes31 1:39b4c6a60595 73 /* Wait for hardware reset to end. */
andrelopes31 1:39b4c6a60595 74 for (tout = 0; tout < 0x100000; tout++) {
andrelopes31 1:39b4c6a60595 75 regv = read_PHY (PHY_REG_BMCR);
andrelopes31 1:39b4c6a60595 76 if (!(regv & 0x8000)) {
andrelopes31 1:39b4c6a60595 77 /* Reset complete */
andrelopes31 1:39b4c6a60595 78 break;
andrelopes31 1:39b4c6a60595 79 }
andrelopes31 1:39b4c6a60595 80 }
andrelopes31 1:39b4c6a60595 81 }
andrelopes31 1:39b4c6a60595 82
andrelopes31 1:39b4c6a60595 83
andrelopes31 1:39b4c6a60595 84 void PHY_PowerDown()
andrelopes31 1:39b4c6a60595 85 {
andrelopes31 1:39b4c6a60595 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
andrelopes31 1:39b4c6a60595 87 EMAC_Init(); //init EMAC if it is not already init'd
andrelopes31 1:39b4c6a60595 88
andrelopes31 1:39b4c6a60595 89 unsigned int regv;
andrelopes31 1:39b4c6a60595 90 regv = read_PHY(PHY_REG_BMCR);
andrelopes31 1:39b4c6a60595 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
andrelopes31 1:39b4c6a60595 92 regv = read_PHY(PHY_REG_BMCR);
andrelopes31 1:39b4c6a60595 93
andrelopes31 1:39b4c6a60595 94 //shouldn't need the EMAC now.
andrelopes31 1:39b4c6a60595 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
andrelopes31 1:39b4c6a60595 96
andrelopes31 1:39b4c6a60595 97 //and turn off the PHY OSC
andrelopes31 1:39b4c6a60595 98 LPC_GPIO1->FIODIR |= 0x8000000;
andrelopes31 1:39b4c6a60595 99 LPC_GPIO1->FIOCLR = 0x8000000;
andrelopes31 1:39b4c6a60595 100 }
andrelopes31 1:39b4c6a60595 101
andrelopes31 1:39b4c6a60595 102 void PHY_PowerUp()
andrelopes31 1:39b4c6a60595 103 {
andrelopes31 1:39b4c6a60595 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
andrelopes31 1:39b4c6a60595 105 EMAC_Init(); //init EMAC if it is not already init'd
andrelopes31 1:39b4c6a60595 106
andrelopes31 1:39b4c6a60595 107 LPC_GPIO1->FIODIR |= 0x8000000;
andrelopes31 1:39b4c6a60595 108 LPC_GPIO1->FIOSET = 0x8000000;
andrelopes31 1:39b4c6a60595 109
andrelopes31 1:39b4c6a60595 110 //wait for osc to be stable
andrelopes31 1:39b4c6a60595 111 wait_ms(200);
andrelopes31 1:39b4c6a60595 112
andrelopes31 1:39b4c6a60595 113 unsigned int regv;
andrelopes31 1:39b4c6a60595 114 regv = read_PHY(PHY_REG_BMCR);
andrelopes31 1:39b4c6a60595 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
andrelopes31 1:39b4c6a60595 116 regv = read_PHY(PHY_REG_BMCR);
andrelopes31 1:39b4c6a60595 117 }
andrelopes31 1:39b4c6a60595 118
andrelopes31 1:39b4c6a60595 119 void PHY_EnergyDetect_Enable()
andrelopes31 1:39b4c6a60595 120 {
andrelopes31 1:39b4c6a60595 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
andrelopes31 1:39b4c6a60595 122 EMAC_Init(); //init EMAC if it is not already init'd
andrelopes31 1:39b4c6a60595 123
andrelopes31 1:39b4c6a60595 124 unsigned int regv;
andrelopes31 1:39b4c6a60595 125 regv = read_PHY(PHY_REG_EDCR);
andrelopes31 1:39b4c6a60595 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
andrelopes31 1:39b4c6a60595 127 regv = read_PHY(PHY_REG_EDCR);
andrelopes31 1:39b4c6a60595 128 }
andrelopes31 1:39b4c6a60595 129
andrelopes31 1:39b4c6a60595 130 void PHY_EnergyDetect_Disable()
andrelopes31 1:39b4c6a60595 131 {
andrelopes31 1:39b4c6a60595 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
andrelopes31 1:39b4c6a60595 133 EMAC_Init(); //init EMAC if it is not already init'd
andrelopes31 1:39b4c6a60595 134 unsigned int regv;
andrelopes31 1:39b4c6a60595 135 regv = read_PHY(PHY_REG_EDCR);
andrelopes31 1:39b4c6a60595 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
andrelopes31 1:39b4c6a60595 137 regv = read_PHY(PHY_REG_EDCR);
andrelopes31 1:39b4c6a60595 138 }