Andrea Stradella / Mbed 2 deprecated SILICATUSA-ISO15693

SILICA TUSA NXP CLRC66301HN1 RFID READER DEMO BOARD

Dependencies:   mbed

main.cpp@0:bda68ad195a7, 2012-04-24 (annotated)

Committer:
andreastradella
Date:
Tue Apr 24 09:47:18 2012 +0000
Revision:
0:bda68ad195a7
Working code for Silica TUSA RFID demo board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreastradella 0:bda68ad195a7 1 #include "mbed.h"
andreastradella 0:bda68ad195a7 2
andreastradella 0:bda68ad195a7 3 SPI spi(p11, p12, p13); // mosi, miso, sclk
andreastradella 0:bda68ad195a7 4 DigitalOut cs(p28); // chip select
andreastradella 0:bda68ad195a7 5 DigitalOut ifsel1(p26); // interface select pin for CLRC6630
andreastradella 0:bda68ad195a7 6 DigitalOut pdres(p27); // CLRC6630 RESET pin - H = RESET
andreastradella 0:bda68ad195a7 7 DigitalOut led[] = {(LED1) , (LED2) , (LED3) , (LED4)}; // onboard LEDs
andreastradella 0:bda68ad195a7 8 Serial pc(USBTX, USBRX); // tx, rx
andreastradella 0:bda68ad195a7 9
andreastradella 0:bda68ad195a7 10 char r;
andreastradella 0:bda68ad195a7 11 int w = 0;
andreastradella 0:bda68ad195a7 12 char UID0 , UID1 , UID2 , UID3 , UID4, UID5 , UID6 , UID7 , UID8 , UID9, UID10;
andreastradella 0:bda68ad195a7 13
andreastradella 0:bda68ad195a7 14
andreastradella 0:bda68ad195a7 15 //write SPI registers
andreastradella 0:bda68ad195a7 16 void write_reg(char n, char o)
andreastradella 0:bda68ad195a7 17 {
andreastradella 0:bda68ad195a7 18
andreastradella 0:bda68ad195a7 19 cs=0; // device select
andreastradella 0:bda68ad195a7 20
andreastradella 0:bda68ad195a7 21 spi.write (n<<1);
andreastradella 0:bda68ad195a7 22 spi.write (o);
andreastradella 0:bda68ad195a7 23
andreastradella 0:bda68ad195a7 24 cs=1; // device deselect
andreastradella 0:bda68ad195a7 25 }
andreastradella 0:bda68ad195a7 26
andreastradella 0:bda68ad195a7 27
andreastradella 0:bda68ad195a7 28 // read SPI registers
andreastradella 0:bda68ad195a7 29 char read_reg(char n)
andreastradella 0:bda68ad195a7 30 {
andreastradella 0:bda68ad195a7 31 char t;
andreastradella 0:bda68ad195a7 32 cs=0; // device select
andreastradella 0:bda68ad195a7 33
andreastradella 0:bda68ad195a7 34
andreastradella 0:bda68ad195a7 35 spi.write ((n<<1)|0x01);
andreastradella 0:bda68ad195a7 36 t=spi.write (0);
andreastradella 0:bda68ad195a7 37
andreastradella 0:bda68ad195a7 38 cs=1; // device deselect
andreastradella 0:bda68ad195a7 39
andreastradella 0:bda68ad195a7 40 return t;
andreastradella 0:bda68ad195a7 41 }
andreastradella 0:bda68ad195a7 42
andreastradella 0:bda68ad195a7 43
andreastradella 0:bda68ad195a7 44 //> Terminate any running command. Flush_FiFo
andreastradella 0:bda68ad195a7 45 void terminate_and_flush_FiFo()
andreastradella 0:bda68ad195a7 46 {
andreastradella 0:bda68ad195a7 47 write_reg( 0x00, 0x00 );
andreastradella 0:bda68ad195a7 48 write_reg( 0x02, 0xB0 );
andreastradella 0:bda68ad195a7 49 }
andreastradella 0:bda68ad195a7 50
andreastradella 0:bda68ad195a7 51
andreastradella 0:bda68ad195a7 52 // Clear all IRQ 0,1 flags
andreastradella 0:bda68ad195a7 53 void clear_IRQ()
andreastradella 0:bda68ad195a7 54 {
andreastradella 0:bda68ad195a7 55 write_reg( 0x06, 0x7F );
andreastradella 0:bda68ad195a7 56 write_reg( 0x07, 0x7F );
andreastradella 0:bda68ad195a7 57 }
andreastradella 0:bda68ad195a7 58
andreastradella 0:bda68ad195a7 59
andreastradella 0:bda68ad195a7 60 // Disable Irq 0,1 sources
andreastradella 0:bda68ad195a7 61 void disable_IRQ()
andreastradella 0:bda68ad195a7 62 {
andreastradella 0:bda68ad195a7 63 write_reg( 0x08, 0x00 );
andreastradella 0:bda68ad195a7 64 write_reg( 0x09, 0x00 );
andreastradella 0:bda68ad195a7 65 }
andreastradella 0:bda68ad195a7 66
andreastradella 0:bda68ad195a7 67
andreastradella 0:bda68ad195a7 68 //> Wait until the command is finished. Enable IRQ sources.
andreastradella 0:bda68ad195a7 69 void wait_command_and_enable_IRQ()
andreastradella 0:bda68ad195a7 70 {
andreastradella 0:bda68ad195a7 71 write_reg( 0x08, 0x18 ); // Enable Irqs 0,1
andreastradella 0:bda68ad195a7 72 write_reg( 0x09, 0x42 ); // Enable the global IRQ to be propagated to the IRQ pin
andreastradella 0:bda68ad195a7 73
andreastradella 0:bda68ad195a7 74 while( (read_reg( 0x07 ) & 0x40)==0);
andreastradella 0:bda68ad195a7 75 }
andreastradella 0:bda68ad195a7 76
andreastradella 0:bda68ad195a7 77
andreastradella 0:bda68ad195a7 78 // Read IRQ 0,1 Status register
andreastradella 0:bda68ad195a7 79 void read_IRQ_status()
andreastradella 0:bda68ad195a7 80 {
andreastradella 0:bda68ad195a7 81 r = read_reg( 0x06 );
andreastradella 0:bda68ad195a7 82 r = read_reg( 0x07 );
andreastradella 0:bda68ad195a7 83 }
andreastradella 0:bda68ad195a7 84
andreastradella 0:bda68ad195a7 85
andreastradella 0:bda68ad195a7 86 // Start tranceive command
andreastradella 0:bda68ad195a7 87 void start_tranceive()
andreastradella 0:bda68ad195a7 88 {
andreastradella 0:bda68ad195a7 89 write_reg( 0x00, 0x07 );
andreastradella 0:bda68ad195a7 90 wait(0.01);
andreastradella 0:bda68ad195a7 91 }
andreastradella 0:bda68ad195a7 92
andreastradella 0:bda68ad195a7 93
andreastradella 0:bda68ad195a7 94 int main() {
andreastradella 0:bda68ad195a7 95
andreastradella 0:bda68ad195a7 96 while (1) {
andreastradella 0:bda68ad195a7 97
andreastradella 0:bda68ad195a7 98 // start activity LED;
andreastradella 0:bda68ad195a7 99 led[3] = 0;
andreastradella 0:bda68ad195a7 100 led[2] = 0;
andreastradella 0:bda68ad195a7 101 led[1] = 0;
andreastradella 0:bda68ad195a7 102 led[0] = 1;
andreastradella 0:bda68ad195a7 103
andreastradella 0:bda68ad195a7 104 // set the comunication method
andreastradella 0:bda68ad195a7 105 //ifsel1 = 0; // usare questa istruzione per le schede revisione prototipo
andreastradella 0:bda68ad195a7 106 ifsel1 = 1; // usare questa istruzione per le schede revisione B
andreastradella 0:bda68ad195a7 107 wait(0.001);
andreastradella 0:bda68ad195a7 108
andreastradella 0:bda68ad195a7 109 // SPI comunication settings
andreastradella 0:bda68ad195a7 110 spi.format(8,0);
andreastradella 0:bda68ad195a7 111 spi.frequency(1000000);
andreastradella 0:bda68ad195a7 112
andreastradella 0:bda68ad195a7 113 do {
andreastradella 0:bda68ad195a7 114
andreastradella 0:bda68ad195a7 115 w = 0;
andreastradella 0:bda68ad195a7 116
andreastradella 0:bda68ad195a7 117 do {
andreastradella 0:bda68ad195a7 118
andreastradella 0:bda68ad195a7 119 //RESET the device
andreastradella 0:bda68ad195a7 120 pdres = 1;
andreastradella 0:bda68ad195a7 121 wait(0.001);
andreastradella 0:bda68ad195a7 122 pdres = 0;
andreastradella 0:bda68ad195a7 123
andreastradella 0:bda68ad195a7 124 wait(0.005);
andreastradella 0:bda68ad195a7 125
andreastradella 0:bda68ad195a7 126
andreastradella 0:bda68ad195a7 127 //> --------------------------------
andreastradella 0:bda68ad195a7 128 //write_reg( 0x37, 0xFF );
andreastradella 0:bda68ad195a7 129
andreastradella 0:bda68ad195a7 130 //> =============================================
andreastradella 0:bda68ad195a7 131 //> Load Protocol (ISO15693)
andreastradella 0:bda68ad195a7 132 //> =============================================
andreastradella 0:bda68ad195a7 133
andreastradella 0:bda68ad195a7 134 write_reg( 0x0F, 0x98 ); // Configure T0
andreastradella 0:bda68ad195a7 135 write_reg( 0x14, 0x92 ); // Configure T1 and cascade it with T0
andreastradella 0:bda68ad195a7 136 write_reg( 0x19, 0x20 ); // Configure T2 for LFO AutoTrimm
andreastradella 0:bda68ad195a7 137 write_reg( 0x1A, 0x03 ); // T2 reload value for LFO AutoTrimm
andreastradella 0:bda68ad195a7 138 write_reg( 0x1B, 0xFF );
andreastradella 0:bda68ad195a7 139 write_reg( 0x1E, 0x00 ); // Configure T3 (for LPCD/ AutoTrimm)
andreastradella 0:bda68ad195a7 140 write_reg( 0x02, 0x90 ); // Set FiFo-Size and Waterlevel
andreastradella 0:bda68ad195a7 141 write_reg( 0x03, 0xFE );
andreastradella 0:bda68ad195a7 142 write_reg( 0x0C, 0x80 ); // Init. RxBitCtrl register
andreastradella 0:bda68ad195a7 143 write_reg( 0x28, 0x80 );
andreastradella 0:bda68ad195a7 144 write_reg( 0x29, 0x00 ); // Init. TxAmp register
andreastradella 0:bda68ad195a7 145 write_reg( 0x2A, 0x01 ); // Init. DrvCon register
andreastradella 0:bda68ad195a7 146 write_reg( 0x2B, 0x05 ); // Init. TxI register
andreastradella 0:bda68ad195a7 147 write_reg( 0x34, 0x00 ); // Init RxSOFD register
andreastradella 0:bda68ad195a7 148 write_reg( 0x38, 0x12 ); // Init. RCV register
andreastradella 0:bda68ad195a7 149
andreastradella 0:bda68ad195a7 150 //> Terminate any running command. Flush_FiFo
andreastradella 0:bda68ad195a7 151 terminate_and_flush_FiFo();
andreastradella 0:bda68ad195a7 152
andreastradella 0:bda68ad195a7 153 // Clear all IRQ 0,1 flags
andreastradella 0:bda68ad195a7 154 clear_IRQ();
andreastradella 0:bda68ad195a7 155
andreastradella 0:bda68ad195a7 156 // Write in FIFO "Load protocol" params(TxProtocol=Iso15693(0a), 0xRxProtocol=Iso15693(0a),
andreastradella 0:bda68ad195a7 157 write_reg( 0x05, 0x0A );
andreastradella 0:bda68ad195a7 158 write_reg( 0x05, 0x0A );
andreastradella 0:bda68ad195a7 159
andreastradella 0:bda68ad195a7 160 // Idle interrupt(Command terminated), RC663_BIT_IDLEIRQ=0x10
andreastradella 0:bda68ad195a7 161 r = read_reg( 0x08 );
andreastradella 0:bda68ad195a7 162 write_reg( 0x08, 0x10 ); // Enable IRQ0, 0xIRQ1 interrupt sources
andreastradella 0:bda68ad195a7 163
andreastradella 0:bda68ad195a7 164 // Enable Global IRQ propagation.
andreastradella 0:bda68ad195a7 165 r = read_reg( 0x09 );
andreastradella 0:bda68ad195a7 166 write_reg( 0x09, 0x40 );
andreastradella 0:bda68ad195a7 167 wait(0.001);
andreastradella 0:bda68ad195a7 168 r = read_reg( 0x09 );
andreastradella 0:bda68ad195a7 169
andreastradella 0:bda68ad195a7 170 //> Start RC663 command "Load Protocol"=0x0d
andreastradella 0:bda68ad195a7 171 write_reg( 0x00, 0x0D ); // Execute Rc663 command: "Load protocol"
andreastradella 0:bda68ad195a7 172
andreastradella 0:bda68ad195a7 173 //SLP 100
andreastradella 0:bda68ad195a7 174 wait(0.1);
andreastradella 0:bda68ad195a7 175
andreastradella 0:bda68ad195a7 176 // Disable Irq 0,1 sources
andreastradella 0:bda68ad195a7 177 disable_IRQ();
andreastradella 0:bda68ad195a7 178
andreastradella 0:bda68ad195a7 179 write_reg( 0x02, 0xB0 ); // Flush FIFO
andreastradella 0:bda68ad195a7 180
andreastradella 0:bda68ad195a7 181 //> Apply RegisterSet
andreastradella 0:bda68ad195a7 182 write_reg( 0x2C, 0x7B );
andreastradella 0:bda68ad195a7 183 write_reg( 0x2D, 0x7B );
andreastradella 0:bda68ad195a7 184 write_reg( 0x2E, 0x08 );
andreastradella 0:bda68ad195a7 185 write_reg( 0x2F, 0x00 );
andreastradella 0:bda68ad195a7 186 write_reg( 0x30, 0x00 );
andreastradella 0:bda68ad195a7 187 write_reg( 0x31, 0x00 );
andreastradella 0:bda68ad195a7 188 write_reg( 0x33, 0x0F );
andreastradella 0:bda68ad195a7 189 write_reg( 0x35, 0x02 );
andreastradella 0:bda68ad195a7 190 write_reg( 0x37, 0x4E );
andreastradella 0:bda68ad195a7 191 write_reg( 0x39, 0x04 );
andreastradella 0:bda68ad195a7 192 write_reg( 0x36, 0x8C ); // Set the RxWait register
andreastradella 0:bda68ad195a7 193 write_reg( 0x31, 0xC0 );
andreastradella 0:bda68ad195a7 194 write_reg( 0x32, 0x00 );
andreastradella 0:bda68ad195a7 195
andreastradella 0:bda68ad195a7 196 // Write Timer-0, 0xTimer-1 reload values(high,low)
andreastradella 0:bda68ad195a7 197 write_reg( 0x10, 0x18 );
andreastradella 0:bda68ad195a7 198 write_reg( 0x11, 0x86 );
andreastradella 0:bda68ad195a7 199 write_reg( 0x15, 0x00 );
andreastradella 0:bda68ad195a7 200 write_reg( 0x16, 0x00 );
andreastradella 0:bda68ad195a7 201 write_reg( 0x29, 0x0A );
andreastradella 0:bda68ad195a7 202 write_reg( 0x28, 0x81 );
andreastradella 0:bda68ad195a7 203 write_reg( 0x0B, 0x00 ); // Disable MIFARE Crypto1
andreastradella 0:bda68ad195a7 204
andreastradella 0:bda68ad195a7 205 //> =============================================
andreastradella 0:bda68ad195a7 206 //> FieldOn
andreastradella 0:bda68ad195a7 207 //> =============================================
andreastradella 0:bda68ad195a7 208 write_reg( 0x28, 0x89 );
andreastradella 0:bda68ad195a7 209 wait(0.1);
andreastradella 0:bda68ad195a7 210
andreastradella 0:bda68ad195a7 211 //> =============================================
andreastradella 0:bda68ad195a7 212 //> ActivateCard
andreastradella 0:bda68ad195a7 213 //> =============================================
andreastradella 0:bda68ad195a7 214
andreastradella 0:bda68ad195a7 215 // Set short timeout. Timer-0,Timer-1 reload values(hi,lo)
andreastradella 0:bda68ad195a7 216 write_reg( 0x10, 0x24 );
andreastradella 0:bda68ad195a7 217 write_reg( 0x11, 0xEB );
andreastradella 0:bda68ad195a7 218 write_reg( 0x15, 0x00 );
andreastradella 0:bda68ad195a7 219 write_reg( 0x16, 0x00 );
andreastradella 0:bda68ad195a7 220
andreastradella 0:bda68ad195a7 221 //> Terminate any running command. Flush_FiFo
andreastradella 0:bda68ad195a7 222 terminate_and_flush_FiFo();
andreastradella 0:bda68ad195a7 223
andreastradella 0:bda68ad195a7 224 // Clear all IRQ 0,1 flags
andreastradella 0:bda68ad195a7 225 clear_IRQ();
andreastradella 0:bda68ad195a7 226
andreastradella 0:bda68ad195a7 227 // Write: "Flags" and "Inventory" cmd in FIFO
andreastradella 0:bda68ad195a7 228 write_reg( 0x05, 0x36 );
andreastradella 0:bda68ad195a7 229 write_reg( 0x05, 0x01 );
andreastradella 0:bda68ad195a7 230 write_reg( 0x05, 0x00 );
andreastradella 0:bda68ad195a7 231 write_reg( 0x05, 0x00 );
andreastradella 0:bda68ad195a7 232
andreastradella 0:bda68ad195a7 233 // Start tranceive command
andreastradella 0:bda68ad195a7 234 start_tranceive();
andreastradella 0:bda68ad195a7 235
andreastradella 0:bda68ad195a7 236 //> Wait until the command is finished. Enable IRQ sources.
andreastradella 0:bda68ad195a7 237 wait_command_and_enable_IRQ();
andreastradella 0:bda68ad195a7 238
andreastradella 0:bda68ad195a7 239 while (w == 0){
andreastradella 0:bda68ad195a7 240 pc.printf("\nNO CARD DETECTED...\n");
andreastradella 0:bda68ad195a7 241 pc.printf("WAITING FOR A CARD...\n");
andreastradella 0:bda68ad195a7 242
andreastradella 0:bda68ad195a7 243 led[3] = 0;
andreastradella 0:bda68ad195a7 244 led[2] = 0;
andreastradella 0:bda68ad195a7 245 led[0] = 0;
andreastradella 0:bda68ad195a7 246 led[1] = 1;
andreastradella 0:bda68ad195a7 247
andreastradella 0:bda68ad195a7 248 w++;
andreastradella 0:bda68ad195a7 249 }
andreastradella 0:bda68ad195a7 250
andreastradella 0:bda68ad195a7 251 } while ( read_reg( 0x40 == 0 ) );
andreastradella 0:bda68ad195a7 252
andreastradella 0:bda68ad195a7 253 // Disable IRQ0,IRQ1 interrupt sources
andreastradella 0:bda68ad195a7 254 disable_IRQ();
andreastradella 0:bda68ad195a7 255
andreastradella 0:bda68ad195a7 256 // Read IRQ 0,1 Status register
andreastradella 0:bda68ad195a7 257 read_IRQ_status();
andreastradella 0:bda68ad195a7 258
andreastradella 0:bda68ad195a7 259 //> Read FIFO, 0xUID
andreastradella 0:bda68ad195a7 260 r = read_reg( 0x04 );
andreastradella 0:bda68ad195a7 261
andreastradella 0:bda68ad195a7 262 pc.printf("\nUID = %02X ", UID1 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 263
andreastradella 0:bda68ad195a7 264 pc.printf("%02X ", UID2 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 265
andreastradella 0:bda68ad195a7 266 pc.printf("%02X ", UID3 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 267
andreastradella 0:bda68ad195a7 268 pc.printf("%02X ", UID4 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 269
andreastradella 0:bda68ad195a7 270 pc.printf("%02X ", UID5 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 271
andreastradella 0:bda68ad195a7 272 pc.printf("%02X ", UID6 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 273
andreastradella 0:bda68ad195a7 274 pc.printf("%02X ", UID7 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 275
andreastradella 0:bda68ad195a7 276 pc.printf("%02X ", UID8 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 277
andreastradella 0:bda68ad195a7 278 pc.printf("%02X ", UID9 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 279
andreastradella 0:bda68ad195a7 280 pc.printf("%02X\n ", UID10 = read_reg( 0x05 ));
andreastradella 0:bda68ad195a7 281
andreastradella 0:bda68ad195a7 282 // Read IRQ 0,1 Status register
andreastradella 0:bda68ad195a7 283 read_IRQ_status();
andreastradella 0:bda68ad195a7 284
andreastradella 0:bda68ad195a7 285 // Read Error status register
andreastradella 0:bda68ad195a7 286 r = read_reg( 0x0A ); // Response: 00
andreastradella 0:bda68ad195a7 287
andreastradella 0:bda68ad195a7 288 r = read_reg( 0x2E ); // Response: 08
andreastradella 0:bda68ad195a7 289 write_reg( 0x2E, 0x08 );
andreastradella 0:bda68ad195a7 290 r = read_reg( 0x0C ); // Response: 80
andreastradella 0:bda68ad195a7 291 r = read_reg( 0x2E ); // Response: 08
andreastradella 0:bda68ad195a7 292 write_reg( 0x2E, 0x08 );
andreastradella 0:bda68ad195a7 293
andreastradella 0:bda68ad195a7 294 led[3] = 0;
andreastradella 0:bda68ad195a7 295 led[1] = 0;
andreastradella 0:bda68ad195a7 296 led[0] = 0;
andreastradella 0:bda68ad195a7 297 led[2] = 1;
andreastradella 0:bda68ad195a7 298
andreastradella 0:bda68ad195a7 299 } while( (read_reg( 0x05 ) & 0x04) == 0 );
andreastradella 0:bda68ad195a7 300
andreastradella 0:bda68ad195a7 301
andreastradella 0:bda68ad195a7 302 //> =============================================
andreastradella 0:bda68ad195a7 303 //> Apply Waiting time
andreastradella 0:bda68ad195a7 304 //> =============================================
andreastradella 0:bda68ad195a7 305
andreastradella 0:bda68ad195a7 306 write_reg( 0x10, 0x20 );
andreastradella 0:bda68ad195a7 307 write_reg( 0x11, 0xFF );
andreastradella 0:bda68ad195a7 308 write_reg( 0x15, 0x00 );
andreastradella 0:bda68ad195a7 309 write_reg( 0x16, 0x00 );
andreastradella 0:bda68ad195a7 310
andreastradella 0:bda68ad195a7 311 r = read_reg( 0x0E ); // Response: 00
andreastradella 0:bda68ad195a7 312
andreastradella 0:bda68ad195a7 313 // Clear all IRQ1 flags
andreastradella 0:bda68ad195a7 314 write_reg( 0x07, 0x7F );
andreastradella 0:bda68ad195a7 315
andreastradella 0:bda68ad195a7 316 led[3] = 0;
andreastradella 0:bda68ad195a7 317 led[0] = 0;
andreastradella 0:bda68ad195a7 318 led[1] = 0;
andreastradella 0:bda68ad195a7 319 led[2] = 1;
andreastradella 0:bda68ad195a7 320
andreastradella 0:bda68ad195a7 321 }
andreastradella 0:bda68ad195a7 322 }