Andrea Stradella / Mbed 2 deprecated SILICATUSA-ISO14443B

SILICA TUSA NXP CLRC66301HN1 RFID READER DEMO BOARD

Dependencies:   mbed

main.cpp@0:24d5bc0093ad, 2012-04-24 (annotated)

Committer:
andreastradella
Date:
Tue Apr 24 09:44:29 2012 +0000
Revision:
0:24d5bc0093ad
Working code for Silica TUSA RFID demo board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreastradella 0:24d5bc0093ad 1 #include "mbed.h"
andreastradella 0:24d5bc0093ad 2
andreastradella 0:24d5bc0093ad 3 SPI spi(p11, p12, p13); // mosi, miso, sclk
andreastradella 0:24d5bc0093ad 4 DigitalOut cs(p28); // chip select
andreastradella 0:24d5bc0093ad 5 DigitalOut ifsel1(p26); // interface select pin for CLRC6630
andreastradella 0:24d5bc0093ad 6 DigitalOut pdres(p27); // CLRC6630 RESET pin - H = RESET
andreastradella 0:24d5bc0093ad 7 DigitalOut led[] = {(LED1) , (LED2) , (LED3) , (LED4)}; // onboard LEDs
andreastradella 0:24d5bc0093ad 8 Serial pc(USBTX, USBRX); // tx, rx
andreastradella 0:24d5bc0093ad 9
andreastradella 0:24d5bc0093ad 10 char r;
andreastradella 0:24d5bc0093ad 11 int w = 0;
andreastradella 0:24d5bc0093ad 12 //char ATQB0 , ATQB1 , ATQB2 , ATQB3 , ATQB4, ATQB5 , ATQB6 , ATQB7 , ATQB8 , ATQB9, ATQB10 , ATQB11 , ATQB12 , ATQB13 , ATQB14, ATQB15 , ATQB16 , ATQB17 , ATQB18;
andreastradella 0:24d5bc0093ad 13
andreastradella 0:24d5bc0093ad 14
andreastradella 0:24d5bc0093ad 15 //write SPI registers
andreastradella 0:24d5bc0093ad 16 void write_reg(char n, char o)
andreastradella 0:24d5bc0093ad 17 {
andreastradella 0:24d5bc0093ad 18
andreastradella 0:24d5bc0093ad 19 cs=0; // device select
andreastradella 0:24d5bc0093ad 20
andreastradella 0:24d5bc0093ad 21 spi.write (n<<1);
andreastradella 0:24d5bc0093ad 22 spi.write (o);
andreastradella 0:24d5bc0093ad 23
andreastradella 0:24d5bc0093ad 24 cs=1; // device deselect
andreastradella 0:24d5bc0093ad 25 }
andreastradella 0:24d5bc0093ad 26
andreastradella 0:24d5bc0093ad 27
andreastradella 0:24d5bc0093ad 28 // read SPI registers
andreastradella 0:24d5bc0093ad 29 char read_reg(char n)
andreastradella 0:24d5bc0093ad 30 {
andreastradella 0:24d5bc0093ad 31 char t;
andreastradella 0:24d5bc0093ad 32 cs=0; // device select
andreastradella 0:24d5bc0093ad 33
andreastradella 0:24d5bc0093ad 34
andreastradella 0:24d5bc0093ad 35 spi.write ((n<<1)|0x01);
andreastradella 0:24d5bc0093ad 36 t=spi.write (0);
andreastradella 0:24d5bc0093ad 37
andreastradella 0:24d5bc0093ad 38 cs=1; // device deselect
andreastradella 0:24d5bc0093ad 39
andreastradella 0:24d5bc0093ad 40 return t;
andreastradella 0:24d5bc0093ad 41 }
andreastradella 0:24d5bc0093ad 42
andreastradella 0:24d5bc0093ad 43
andreastradella 0:24d5bc0093ad 44 //> Terminate any running command. Flush_FiFo
andreastradella 0:24d5bc0093ad 45 void terminate_and_flush_FiFo()
andreastradella 0:24d5bc0093ad 46 {
andreastradella 0:24d5bc0093ad 47 write_reg( 0x00, 0x00 );
andreastradella 0:24d5bc0093ad 48 write_reg( 0x02, 0xB0 );
andreastradella 0:24d5bc0093ad 49 }
andreastradella 0:24d5bc0093ad 50
andreastradella 0:24d5bc0093ad 51
andreastradella 0:24d5bc0093ad 52 // Clear all IRQ 0,1 flags
andreastradella 0:24d5bc0093ad 53 void clear_IRQ()
andreastradella 0:24d5bc0093ad 54 {
andreastradella 0:24d5bc0093ad 55 write_reg( 0x06, 0x7F );
andreastradella 0:24d5bc0093ad 56 write_reg( 0x07, 0x7F );
andreastradella 0:24d5bc0093ad 57 }
andreastradella 0:24d5bc0093ad 58
andreastradella 0:24d5bc0093ad 59
andreastradella 0:24d5bc0093ad 60 // Disable Irq 0,1 sources
andreastradella 0:24d5bc0093ad 61 void disable_IRQ()
andreastradella 0:24d5bc0093ad 62 {
andreastradella 0:24d5bc0093ad 63 write_reg( 0x08, 0x00 );
andreastradella 0:24d5bc0093ad 64 write_reg( 0x09, 0x00 );
andreastradella 0:24d5bc0093ad 65 }
andreastradella 0:24d5bc0093ad 66
andreastradella 0:24d5bc0093ad 67
andreastradella 0:24d5bc0093ad 68 //> Wait until the command is finished. Enable IRQ sources.
andreastradella 0:24d5bc0093ad 69 void wait_command_and_enable_IRQ()
andreastradella 0:24d5bc0093ad 70 {
andreastradella 0:24d5bc0093ad 71 write_reg( 0x08, 0x18 ); // Enable Irqs 0,1
andreastradella 0:24d5bc0093ad 72 write_reg( 0x09, 0x42 ); // Enable the global IRQ to be propagated to the IRQ pin
andreastradella 0:24d5bc0093ad 73
andreastradella 0:24d5bc0093ad 74 while( (read_reg( 0x07 ) & 0x40)==0);
andreastradella 0:24d5bc0093ad 75 }
andreastradella 0:24d5bc0093ad 76
andreastradella 0:24d5bc0093ad 77
andreastradella 0:24d5bc0093ad 78 // Read IRQ 0,1 Status register
andreastradella 0:24d5bc0093ad 79 void read_IRQ_status()
andreastradella 0:24d5bc0093ad 80 {
andreastradella 0:24d5bc0093ad 81 r = read_reg( 0x06 );
andreastradella 0:24d5bc0093ad 82 r = read_reg( 0x07 );
andreastradella 0:24d5bc0093ad 83 }
andreastradella 0:24d5bc0093ad 84
andreastradella 0:24d5bc0093ad 85
andreastradella 0:24d5bc0093ad 86 // Start tranceive command
andreastradella 0:24d5bc0093ad 87 void start_tranceive()
andreastradella 0:24d5bc0093ad 88 {
andreastradella 0:24d5bc0093ad 89 write_reg( 0x00, 0x07 );
andreastradella 0:24d5bc0093ad 90 wait(0.001);
andreastradella 0:24d5bc0093ad 91 }
andreastradella 0:24d5bc0093ad 92
andreastradella 0:24d5bc0093ad 93
andreastradella 0:24d5bc0093ad 94 int main() {
andreastradella 0:24d5bc0093ad 95
andreastradella 0:24d5bc0093ad 96 // start activity LED;
andreastradella 0:24d5bc0093ad 97 led[3] = 0;
andreastradella 0:24d5bc0093ad 98 led[2] = 0;
andreastradella 0:24d5bc0093ad 99 led[1] = 0;
andreastradella 0:24d5bc0093ad 100 led[0] = 1;
andreastradella 0:24d5bc0093ad 101
andreastradella 0:24d5bc0093ad 102 // set the comunication method
andreastradella 0:24d5bc0093ad 103 //ifsel1 = 0; // usare questa istruzione per le schede revisione prototipo
andreastradella 0:24d5bc0093ad 104 ifsel1 = 1; // usare questa istruzione per le schede revisione B
andreastradella 0:24d5bc0093ad 105 wait(0.001);
andreastradella 0:24d5bc0093ad 106
andreastradella 0:24d5bc0093ad 107 // SPI comunication settings
andreastradella 0:24d5bc0093ad 108 spi.format(8,0);
andreastradella 0:24d5bc0093ad 109 spi.frequency(1000000);
andreastradella 0:24d5bc0093ad 110 do {
andreastradella 0:24d5bc0093ad 111 //RESET the device
andreastradella 0:24d5bc0093ad 112 pdres = 1;
andreastradella 0:24d5bc0093ad 113 wait(0.001);
andreastradella 0:24d5bc0093ad 114 pdres = 0;
andreastradella 0:24d5bc0093ad 115
andreastradella 0:24d5bc0093ad 116 wait(0.005);
andreastradella 0:24d5bc0093ad 117
andreastradella 0:24d5bc0093ad 118 //> Load Protocol
andreastradella 0:24d5bc0093ad 119 write_reg( 0x0F, 0x98 ); // Timer0 Timer starts at the end of transmission
andreastradella 0:24d5bc0093ad 120 write_reg( 0x37, 0xFF );
andreastradella 0:24d5bc0093ad 121 write_reg( 0x14, 0x92 ); //Timer1 Timer starts at the end of transmission
andreastradella 0:24d5bc0093ad 122 write_reg( 0x19, 0x20 ); //Timer2
andreastradella 0:24d5bc0093ad 123 write_reg( 0x1A, 0x03 ); //TReload Hi
andreastradella 0:24d5bc0093ad 124 write_reg( 0x1B, 0xFF ); //TReload Lo
andreastradella 0:24d5bc0093ad 125 write_reg( 0x1E, 0x00 ); //Timer3
andreastradella 0:24d5bc0093ad 126 write_reg( 0x02, 0x90 ); //FIFO control register ->sets FIFO size to 255bytes
andreastradella 0:24d5bc0093ad 127 write_reg( 0x03, 0xFE ); //Waterlevel settings
andreastradella 0:24d5bc0093ad 128 write_reg( 0x0C, 0x80 ); //RXBitCtrl (Values AfterColl)
andreastradella 0:24d5bc0093ad 129 write_reg( 0x28, 0x87 ); //DrvMode_Reg both driver pins enable, invert one driver
andreastradella 0:24d5bc0093ad 130 write_reg( 0x29, 0xCC ); //00 TXAmp_Reg: set continous wave amplitude, set residual carrier
andreastradella 0:24d5bc0093ad 131 write_reg( 0x2A, 0x01 ); //DrvCon_Reg: sets driver config to TXEnvelope
andreastradella 0:24d5bc0093ad 132 write_reg( 0x2B, 0x05 ); //Txl_Reg: sets iiLoad, was auch immer das ist
andreastradella 0:24d5bc0093ad 133 write_reg( 0x34, 0x00 ); //RxSofD_Reg: Subcarrier and SOF detection off
andreastradella 0:24d5bc0093ad 134 write_reg( 0x38, 0x12 ); //Rcv_Reg: defines input for signal processing and defines collision level
andreastradella 0:24d5bc0093ad 135
andreastradella 0:24d5bc0093ad 136 write_reg( 0x00, 0x00 ); //Idle commmand
andreastradella 0:24d5bc0093ad 137 wait(0.02);
andreastradella 0:24d5bc0093ad 138
andreastradella 0:24d5bc0093ad 139 write_reg( 0x02, 0xB0 ); //FIFO Control
andreastradella 0:24d5bc0093ad 140
andreastradella 0:24d5bc0093ad 141 write_reg( 0x06, 0x7F ); //IRQ0_Reg:
andreastradella 0:24d5bc0093ad 142 write_reg( 0x07, 0x7F ); //IRQ1_Reg:
andreastradella 0:24d5bc0093ad 143 write_reg( 0x05, 0x04 ); // write Tx and RX protocol numbers (04 for ISO14443B)
andreastradella 0:24d5bc0093ad 144 write_reg( 0x05, 0x04 ); // write Tx and RX protocol numbers (04 for ISO14443B)
andreastradella 0:24d5bc0093ad 145 write_reg( 0x08, 0x10 ); //IRQ0En_Reg: IdleIrq is enable propagated to GlobalIRQ
andreastradella 0:24d5bc0093ad 146 write_reg( 0x09, 0x40 ); //IRQ1En_Reg: GlobalIrq propagated to the interrupt pin
andreastradella 0:24d5bc0093ad 147 write_reg( 0x00, 0x0D ); //LoadProtocol
andreastradella 0:24d5bc0093ad 148 wait(0.02);
andreastradella 0:24d5bc0093ad 149
andreastradella 0:24d5bc0093ad 150 write_reg( 0x08, 0x00 ); //Reset IRQ0
andreastradella 0:24d5bc0093ad 151 write_reg( 0x09, 0x00 ); //Reset IRQ1
andreastradella 0:24d5bc0093ad 152 write_reg( 0x02, 0xB0 ); //FIFO Control
andreastradella 0:24d5bc0093ad 153
andreastradella 0:24d5bc0093ad 154 // Init registers.
andreastradella 0:24d5bc0093ad 155 write_reg( 0x2C, 0x7B );
andreastradella 0:24d5bc0093ad 156 write_reg( 0x2D, 0x7B );
andreastradella 0:24d5bc0093ad 157 write_reg( 0x2E, 0x08 );
andreastradella 0:24d5bc0093ad 158 write_reg( 0x2F, 0x0A ); //00
andreastradella 0:24d5bc0093ad 159 write_reg( 0x30, 0x00 );
andreastradella 0:24d5bc0093ad 160 write_reg( 0x31, 0x01 );
andreastradella 0:24d5bc0093ad 161 write_reg( 0x33, 0x05 ); //05
andreastradella 0:24d5bc0093ad 162 write_reg( 0x34, 0xB2 );
andreastradella 0:24d5bc0093ad 163 write_reg( 0x35, 0x34 );
andreastradella 0:24d5bc0093ad 164 write_reg( 0x37, 0x3F ); //3F
andreastradella 0:24d5bc0093ad 165 write_reg( 0x38, 0x12 ); // 12
andreastradella 0:24d5bc0093ad 166 write_reg( 0x39, 0x0A ); //0A
andreastradella 0:24d5bc0093ad 167 // End of load protocol
andreastradella 0:24d5bc0093ad 168
andreastradella 0:24d5bc0093ad 169 // start activity LED;
andreastradella 0:24d5bc0093ad 170 led[3] = 0;
andreastradella 0:24d5bc0093ad 171 led[2] = 0;
andreastradella 0:24d5bc0093ad 172 led[1] = 1;
andreastradella 0:24d5bc0093ad 173 led[0] = 0;
andreastradella 0:24d5bc0093ad 174
andreastradella 0:24d5bc0093ad 175 //> ==============================================
andreastradella 0:24d5bc0093ad 176 //> Field Reset
andreastradella 0:24d5bc0093ad 177 //> ==============================================
andreastradella 0:24d5bc0093ad 178
andreastradella 0:24d5bc0093ad 179 // Field off: Read out DrvMod register. Disable Drivers
andreastradella 0:24d5bc0093ad 180 r = read_reg( 0x28 ); // Response: 87
andreastradella 0:24d5bc0093ad 181
andreastradella 0:24d5bc0093ad 182 write_reg( 0x47, 0x04 ); // DEBUG
andreastradella 0:24d5bc0093ad 183 //> phhalHw_FieldOn
andreastradella 0:24d5bc0093ad 184 write_reg( 0x28, 0x8F );
andreastradella 0:24d5bc0093ad 185 //SLP 100
andreastradella 0:24d5bc0093ad 186 wait(0.02);
andreastradella 0:24d5bc0093ad 187
andreastradella 0:24d5bc0093ad 188 //> Send REQB command
andreastradella 0:24d5bc0093ad 189 write_reg( 0x31, 0xC1 );
andreastradella 0:24d5bc0093ad 190 write_reg( 0x32, 0x0B );
andreastradella 0:24d5bc0093ad 191 write_reg( 0x00, 0x00 );
andreastradella 0:24d5bc0093ad 192 write_reg( 0x02, 0xB0 );
andreastradella 0:24d5bc0093ad 193 write_reg( 0x06, 0x7F );
andreastradella 0:24d5bc0093ad 194 write_reg( 0x07, 0x7F );
andreastradella 0:24d5bc0093ad 195
andreastradella 0:24d5bc0093ad 196 write_reg( 0x05, 0x06 ); // SR176
andreastradella 0:24d5bc0093ad 197 write_reg( 0x05, 0x00 );
andreastradella 0:24d5bc0093ad 198
andreastradella 0:24d5bc0093ad 199 /*write_reg( 0x05, 0x00 ); // GMTL
andreastradella 0:24d5bc0093ad 200 write_reg( 0x05, 0x0B );
andreastradella 0:24d5bc0093ad 201 write_reg( 0x05, 0x3F );
andreastradella 0:24d5bc0093ad 202 write_reg( 0x05, 0x80 ); */
andreastradella 0:24d5bc0093ad 203
andreastradella 0:24d5bc0093ad 204 /*write_reg( 0x05, 0x05 ); //ISO14443B
andreastradella 0:24d5bc0093ad 205 write_reg( 0x05, 0x00 );
andreastradella 0:24d5bc0093ad 206 write_reg( 0x05, 0x00 );*/
andreastradella 0:24d5bc0093ad 207
andreastradella 0:24d5bc0093ad 208 write_reg( 0x00, 0x07 ); // Response: 00
andreastradella 0:24d5bc0093ad 209
andreastradella 0:24d5bc0093ad 210 //SLP 100
andreastradella 0:24d5bc0093ad 211 wait(0.02);
andreastradella 0:24d5bc0093ad 212
andreastradella 0:24d5bc0093ad 213 //RE 04 0C // Read FIFOLevel (12 bytes)
andreastradella 0:24d5bc0093ad 214 r = read_reg( 0x04 );
andreastradella 0:24d5bc0093ad 215 //if (r != 0x1B) return;
andreastradella 0:24d5bc0093ad 216
andreastradella 0:24d5bc0093ad 217 if( r != 0 )
andreastradella 0:24d5bc0093ad 218 {
andreastradella 0:24d5bc0093ad 219 // start activity LED;
andreastradella 0:24d5bc0093ad 220 led[3] = 1;
andreastradella 0:24d5bc0093ad 221 led[2] = 0;
andreastradella 0:24d5bc0093ad 222 led[1] = 0;
andreastradella 0:24d5bc0093ad 223 led[0] = 0;
andreastradella 0:24d5bc0093ad 224 pc.printf("received = 0x%02X bytes: ", r);
andreastradella 0:24d5bc0093ad 225 while( read_reg( 0x04 ) )
andreastradella 0:24d5bc0093ad 226 {
andreastradella 0:24d5bc0093ad 227 pc.printf("%02X ", r = read_reg( 0x05 ));
andreastradella 0:24d5bc0093ad 228 }
andreastradella 0:24d5bc0093ad 229 pc.printf("\r\n", r);
andreastradella 0:24d5bc0093ad 230 }
andreastradella 0:24d5bc0093ad 231 else
andreastradella 0:24d5bc0093ad 232 pc.printf("NO CARD\r\n");
andreastradella 0:24d5bc0093ad 233
andreastradella 0:24d5bc0093ad 234 } while( -1 );
andreastradella 0:24d5bc0093ad 235 }