Andrea Stradella / Mbed 2 deprecated SILICATUSA-ISO14443A

SILICA TUSA NXP CLRC66301HN1 RFID READER DEMO BOARD

Dependencies:   mbed

main.cpp@0:d0a023131133, 2012-04-24 (annotated)

Committer:
andreastradella
Date:
Tue Apr 24 09:40:29 2012 +0000
Revision:
0:d0a023131133
Working code for Silica TUSA RFID demo board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreastradella 0:d0a023131133 1 #include "mbed.h"
andreastradella 0:d0a023131133 2
andreastradella 0:d0a023131133 3 SPI spi(p11, p12, p13); // mosi, miso, sclk
andreastradella 0:d0a023131133 4 DigitalOut cs(p28); // chip select
andreastradella 0:d0a023131133 5 DigitalOut ifsel1(p26); // interface select pin for CLRC6630
andreastradella 0:d0a023131133 6 DigitalOut pdres(p27); // CLRC6630 RESET pin - H = RESET
andreastradella 0:d0a023131133 7 DigitalOut led[] = {(LED1) , (LED2) , (LED3) , (LED4)}; // onboard LEDs
andreastradella 0:d0a023131133 8 Serial pc(USBTX, USBRX); // tx, rx
andreastradella 0:d0a023131133 9
andreastradella 0:d0a023131133 10 char r;
andreastradella 0:d0a023131133 11 int w = 0;
andreastradella 0:d0a023131133 12 char UID0 , UID1 , UID2 , UID3 , UID4;
andreastradella 0:d0a023131133 13
andreastradella 0:d0a023131133 14
andreastradella 0:d0a023131133 15 //write SPI registers
andreastradella 0:d0a023131133 16 void write_reg(char n, char o)
andreastradella 0:d0a023131133 17 {
andreastradella 0:d0a023131133 18
andreastradella 0:d0a023131133 19 cs=0; // device select
andreastradella 0:d0a023131133 20
andreastradella 0:d0a023131133 21 spi.write (n<<1);
andreastradella 0:d0a023131133 22 spi.write (o);
andreastradella 0:d0a023131133 23
andreastradella 0:d0a023131133 24 cs=1; // device deselect
andreastradella 0:d0a023131133 25 }
andreastradella 0:d0a023131133 26
andreastradella 0:d0a023131133 27
andreastradella 0:d0a023131133 28 // read SPI registers
andreastradella 0:d0a023131133 29 char read_reg(char n)
andreastradella 0:d0a023131133 30 {
andreastradella 0:d0a023131133 31 char t;
andreastradella 0:d0a023131133 32 cs=0; // device select
andreastradella 0:d0a023131133 33
andreastradella 0:d0a023131133 34
andreastradella 0:d0a023131133 35 spi.write ((n<<1)|0x01);
andreastradella 0:d0a023131133 36 t=spi.write (0);
andreastradella 0:d0a023131133 37
andreastradella 0:d0a023131133 38 cs=1; // device deselect
andreastradella 0:d0a023131133 39
andreastradella 0:d0a023131133 40 return t;
andreastradella 0:d0a023131133 41 }
andreastradella 0:d0a023131133 42
andreastradella 0:d0a023131133 43
andreastradella 0:d0a023131133 44 //> Terminate any running command. Flush_FiFo
andreastradella 0:d0a023131133 45 void terminate_and_flush_FiFo()
andreastradella 0:d0a023131133 46 {
andreastradella 0:d0a023131133 47 write_reg( 0x00, 0x00 );
andreastradella 0:d0a023131133 48 write_reg( 0x02, 0xb0 );
andreastradella 0:d0a023131133 49 }
andreastradella 0:d0a023131133 50
andreastradella 0:d0a023131133 51
andreastradella 0:d0a023131133 52 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 53 void clear_IRQ()
andreastradella 0:d0a023131133 54 {
andreastradella 0:d0a023131133 55 write_reg( 0x06, 0x7f );
andreastradella 0:d0a023131133 56 write_reg( 0x07, 0x7f );
andreastradella 0:d0a023131133 57 }
andreastradella 0:d0a023131133 58
andreastradella 0:d0a023131133 59
andreastradella 0:d0a023131133 60 // Disable Irq 0,1 sources
andreastradella 0:d0a023131133 61 void disable_IRQ()
andreastradella 0:d0a023131133 62 {
andreastradella 0:d0a023131133 63 write_reg( 0x08, 0x00 );
andreastradella 0:d0a023131133 64 write_reg( 0x09, 0x00 );
andreastradella 0:d0a023131133 65 }
andreastradella 0:d0a023131133 66
andreastradella 0:d0a023131133 67
andreastradella 0:d0a023131133 68 //> Wait until the command is finished. Enable IRQ sources.
andreastradella 0:d0a023131133 69 void wait_command_and_enable_IRQ()
andreastradella 0:d0a023131133 70 {
andreastradella 0:d0a023131133 71 write_reg( 0x08, 0x18 ); // Enable Irqs 0,1
andreastradella 0:d0a023131133 72 write_reg( 0x09, 0x42 ); // Enable the global IRQ to be propagated to the IRQ pin
andreastradella 0:d0a023131133 73
andreastradella 0:d0a023131133 74 while( (read_reg( 0x07 ) & 0x40)==0);
andreastradella 0:d0a023131133 75 }
andreastradella 0:d0a023131133 76
andreastradella 0:d0a023131133 77
andreastradella 0:d0a023131133 78 // Read IRQ 0,1 Status register
andreastradella 0:d0a023131133 79 void read_IRQ_status()
andreastradella 0:d0a023131133 80 {
andreastradella 0:d0a023131133 81 r = read_reg( 0x06 );
andreastradella 0:d0a023131133 82 r = read_reg( 0x07 );
andreastradella 0:d0a023131133 83 }
andreastradella 0:d0a023131133 84
andreastradella 0:d0a023131133 85
andreastradella 0:d0a023131133 86 // Start tranceive command
andreastradella 0:d0a023131133 87 void start_tranceive()
andreastradella 0:d0a023131133 88 {
andreastradella 0:d0a023131133 89 write_reg( 0x00, 0x07 );
andreastradella 0:d0a023131133 90 wait(0.001);
andreastradella 0:d0a023131133 91 }
andreastradella 0:d0a023131133 92
andreastradella 0:d0a023131133 93
andreastradella 0:d0a023131133 94 int main() {
andreastradella 0:d0a023131133 95
andreastradella 0:d0a023131133 96 while (1) {
andreastradella 0:d0a023131133 97
andreastradella 0:d0a023131133 98 // start activity LED;
andreastradella 0:d0a023131133 99 led[3] = 0;
andreastradella 0:d0a023131133 100 led[2] = 0;
andreastradella 0:d0a023131133 101 led[1] = 0;
andreastradella 0:d0a023131133 102 led[0] = 1;
andreastradella 0:d0a023131133 103
andreastradella 0:d0a023131133 104 // set the comunication method
andreastradella 0:d0a023131133 105 //ifsel1 = 0; // usare questa istruzione per le schede revisione prototipo
andreastradella 0:d0a023131133 106 ifsel1 = 1; // usare questa istruzione per le schede revisione B
andreastradella 0:d0a023131133 107 wait(0.001);
andreastradella 0:d0a023131133 108
andreastradella 0:d0a023131133 109 // SPI comunication settings
andreastradella 0:d0a023131133 110 spi.format(8,0);
andreastradella 0:d0a023131133 111 spi.frequency(1000000);
andreastradella 0:d0a023131133 112
andreastradella 0:d0a023131133 113 do {
andreastradella 0:d0a023131133 114
andreastradella 0:d0a023131133 115 w = 0;
andreastradella 0:d0a023131133 116
andreastradella 0:d0a023131133 117 do {
andreastradella 0:d0a023131133 118
andreastradella 0:d0a023131133 119 wait(0.1);
andreastradella 0:d0a023131133 120
andreastradella 0:d0a023131133 121 //RESET the device
andreastradella 0:d0a023131133 122 pdres = 1;
andreastradella 0:d0a023131133 123 wait(0.001);
andreastradella 0:d0a023131133 124 pdres = 0;
andreastradella 0:d0a023131133 125
andreastradella 0:d0a023131133 126 wait(0.005);
andreastradella 0:d0a023131133 127
andreastradella 0:d0a023131133 128 //> =============================================
andreastradella 0:d0a023131133 129 //> RC663 Script for (Iso14443-3A protocol):
andreastradella 0:d0a023131133 130 //> * ReqA
andreastradella 0:d0a023131133 131 //> * Get UID (Select: Casade level 1)
andreastradella 0:d0a023131133 132 //> * HaltA
andreastradella 0:d0a023131133 133 //>
andreastradella 0:d0a023131133 134 //> Note: Only one PICC shall be in HF
andreastradella 0:d0a023131133 135 //> =============================================
andreastradella 0:d0a023131133 136
andreastradella 0:d0a023131133 137 //> =============================================
andreastradella 0:d0a023131133 138 //> RC663 ApplyProtocolSettings: ISO14443A=01
andreastradella 0:d0a023131133 139 //> =============================================
andreastradella 0:d0a023131133 140 //
andreastradella 0:d0a023131133 141 //> Configure Timers
andreastradella 0:d0a023131133 142 //
andreastradella 0:d0a023131133 143 // Set Timer-0, T0Control_Reg:
andreastradella 0:d0a023131133 144 // Starts at the end of Tx. Stops after Rx of first data. Auto-reloaded. 13.56 MHz input clock.
andreastradella 0:d0a023131133 145 write_reg( 0x0F, 0x98 );
andreastradella 0:d0a023131133 146
andreastradella 0:d0a023131133 147 // Set Timer-1, T1Control_Reg:
andreastradella 0:d0a023131133 148 // Starts at the end of Tx. Stops after Rx of first data. Input clock - cascaded with Timer-0.
andreastradella 0:d0a023131133 149 write_reg( 0x14, 0x92 );
andreastradella 0:d0a023131133 150
andreastradella 0:d0a023131133 151 // Set Timer-2, T2Control_Reg: Timer used for LFO trimming
andreastradella 0:d0a023131133 152 write_reg( 0x19, 0x20 );
andreastradella 0:d0a023131133 153
andreastradella 0:d0a023131133 154 // Set Timer-2 reload value (T2ReloadHi_Reg and T2ReloadLo_Reg)
andreastradella 0:d0a023131133 155 write_reg( 0x1A, 0x03 );
andreastradella 0:d0a023131133 156 write_reg( 0x1B, 0xFF );
andreastradella 0:d0a023131133 157
andreastradella 0:d0a023131133 158 // Set Timer-3, T3Control_Reg:
andreastradella 0:d0a023131133 159 // Not started automatically. Not reloaded. Input clock 13.56 MHz
andreastradella 0:d0a023131133 160 write_reg( 0x1E, 0x00 );
andreastradella 0:d0a023131133 161
andreastradella 0:d0a023131133 162 //> Configure FIFO Size=255 and Water-level
andreastradella 0:d0a023131133 163 // Set FifoControl_Reg, Fifo size=255 bytes. Flush FIFO
andreastradella 0:d0a023131133 164 write_reg( 0x02, 0x90 );
andreastradella 0:d0a023131133 165
andreastradella 0:d0a023131133 166 // Set WaterLevel =(FIFO length -1)
andreastradella 0:d0a023131133 167 write_reg( 0x03, 0xFE );
andreastradella 0:d0a023131133 168
andreastradella 0:d0a023131133 169 // RxBitCtrl_Reg(0x0c) Received bit after collision are replaced with 1.
andreastradella 0:d0a023131133 170 write_reg( 0x0C, 0x80 );
andreastradella 0:d0a023131133 171
andreastradella 0:d0a023131133 172 // DrvMod reg(0x28), Tx2Inv=1
andreastradella 0:d0a023131133 173 r = read_reg( 0x28 );
andreastradella 0:d0a023131133 174 write_reg( 0x28, 0x80 );
andreastradella 0:d0a023131133 175
andreastradella 0:d0a023131133 176 // TxAmp_Reg(0x29)
andreastradella 0:d0a023131133 177 write_reg( 0x29, 0x00 );
andreastradella 0:d0a023131133 178
andreastradella 0:d0a023131133 179 // DrvCon_Reg(0x2A)
andreastradella 0:d0a023131133 180 write_reg( 0x2A, 0x01 );
andreastradella 0:d0a023131133 181
andreastradella 0:d0a023131133 182 // TxI_Reg(0x05),(0x05)
andreastradella 0:d0a023131133 183 write_reg( 0x2B, 0x05 );
andreastradella 0:d0a023131133 184
andreastradella 0:d0a023131133 185 // RxSOFD_Reg(0x34),(0x00),
andreastradella 0:d0a023131133 186 write_reg( 0x34, 0x00 );
andreastradella 0:d0a023131133 187
andreastradella 0:d0a023131133 188 // Rcv_Reg(0x38),(0x12)
andreastradella 0:d0a023131133 189 write_reg( 0x38, 0x12 );
andreastradella 0:d0a023131133 190 //
andreastradella 0:d0a023131133 191 //> =============================================
andreastradella 0:d0a023131133 192 //> 2. LoadProtocol( bTxProtocol=0, bRxProtocol=0)
andreastradella 0:d0a023131133 193 //> =============================================
andreastradella 0:d0a023131133 194
andreastradella 0:d0a023131133 195 //> Terminate any running command. Flush_FiFo
andreastradella 0:d0a023131133 196 terminate_and_flush_FiFo();
andreastradella 0:d0a023131133 197
andreastradella 0:d0a023131133 198 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 199 clear_IRQ();
andreastradella 0:d0a023131133 200
andreastradella 0:d0a023131133 201 //> Write in Fifo: Tx and Rx protocol numbers(0,0)
andreastradella 0:d0a023131133 202 r = read_reg( 0x04 );
andreastradella 0:d0a023131133 203 write_reg( 0x05, 0x00 ); // Rx protocol=0
andreastradella 0:d0a023131133 204 write_reg( 0x05, 0x00 ); // Tx prot=0
andreastradella 0:d0a023131133 205
andreastradella 0:d0a023131133 206 // Enable IRQ0 interrupt sources
andreastradella 0:d0a023131133 207 //
andreastradella 0:d0a023131133 208 // Idle interrupt(Command terminated), RC663_BIT_IDLEIRQ=0x10
andreastradella 0:d0a023131133 209 r = read_reg( 0x08 );
andreastradella 0:d0a023131133 210 write_reg( 0x08, 0x10 );
andreastradella 0:d0a023131133 211
andreastradella 0:d0a023131133 212 // Enable Global IRQ propagation.
andreastradella 0:d0a023131133 213 r = read_reg( 0x09 );
andreastradella 0:d0a023131133 214 write_reg( 0x09, 0x40 );
andreastradella 0:d0a023131133 215 wait(0.001);
andreastradella 0:d0a023131133 216 r = read_reg( 0x09 );
andreastradella 0:d0a023131133 217
andreastradella 0:d0a023131133 218 //> Start RC663 command "Load Protocol"=0x0d
andreastradella 0:d0a023131133 219 write_reg( 0x00, 0x0D );
andreastradella 0:d0a023131133 220
andreastradella 0:d0a023131133 221 //L_LoadProtocol
andreastradella 0:d0a023131133 222
andreastradella 0:d0a023131133 223 while( (read_reg( 0x07 ) & 0x40)==0);
andreastradella 0:d0a023131133 224
andreastradella 0:d0a023131133 225 // Disable Irq 0,1 sources
andreastradella 0:d0a023131133 226 disable_IRQ();
andreastradella 0:d0a023131133 227
andreastradella 0:d0a023131133 228 //> Flush Fifo. Read Error Reg
andreastradella 0:d0a023131133 229 write_reg( 0x02, 0xB0 );
andreastradella 0:d0a023131133 230 r = read_reg( 0x0A );
andreastradella 0:d0a023131133 231
andreastradella 0:d0a023131133 232 // Apply RegisterSet
andreastradella 0:d0a023131133 233 //
andreastradella 0:d0a023131133 234 //> Configure CRC-16 calculation, preset value(0x6363) for Tx&Rx
andreastradella 0:d0a023131133 235 write_reg( 0x2C, 0x18 );
andreastradella 0:d0a023131133 236 write_reg( 0x2D, 0x18 );
andreastradella 0:d0a023131133 237 write_reg( 0x2E, 0x08 );
andreastradella 0:d0a023131133 238
andreastradella 0:d0a023131133 239 // Length of the pulse modulation in carrier clks+1
andreastradella 0:d0a023131133 240 write_reg( 0x2F, 0x20 );
andreastradella 0:d0a023131133 241
andreastradella 0:d0a023131133 242 // Symbol 1 and 0 burst lengths = 8 bits.
andreastradella 0:d0a023131133 243 write_reg( 0x30, 0x00 );
andreastradella 0:d0a023131133 244
andreastradella 0:d0a023131133 245 // Start symbol=Symbol2, Stop symbol=Symbol3
andreastradella 0:d0a023131133 246 write_reg( 0x33, 0xCF );
andreastradella 0:d0a023131133 247
andreastradella 0:d0a023131133 248 // Set Rx Baudrate 106 kBaud
andreastradella 0:d0a023131133 249 write_reg( 0x35, 0x04 );
andreastradella 0:d0a023131133 250
andreastradella 0:d0a023131133 251 // Set min-levels for Rx and phase shift
andreastradella 0:d0a023131133 252 write_reg( 0x37, 0x32 );
andreastradella 0:d0a023131133 253 write_reg( 0x39, 0x00 );
andreastradella 0:d0a023131133 254
andreastradella 0:d0a023131133 255 // Set Rx waiting time
andreastradella 0:d0a023131133 256 write_reg( 0x36, 0x90 );
andreastradella 0:d0a023131133 257 write_reg( 0x31, 0xC0 );
andreastradella 0:d0a023131133 258 write_reg( 0x32, 0x0B );
andreastradella 0:d0a023131133 259
andreastradella 0:d0a023131133 260 // Set Timeout. Write T0,T1 reload values(hi,Low)
andreastradella 0:d0a023131133 261 write_reg( 0x10, 0x08 );
andreastradella 0:d0a023131133 262 write_reg( 0x11, 0xD8 );
andreastradella 0:d0a023131133 263 write_reg( 0x15, 0x00 );
andreastradella 0:d0a023131133 264 write_reg( 0x16, 0x00 );
andreastradella 0:d0a023131133 265
andreastradella 0:d0a023131133 266 // Write DrvMod register
andreastradella 0:d0a023131133 267 write_reg( 0x28, 0x81 );
andreastradella 0:d0a023131133 268
andreastradella 0:d0a023131133 269 //> MIFARE Crypto1 state is further disabled.
andreastradella 0:d0a023131133 270 write_reg( 0x0B, 0x00 );
andreastradella 0:d0a023131133 271
andreastradella 0:d0a023131133 272 //> FieldOn
andreastradella 0:d0a023131133 273 write_reg( 0x28, 0x89 );
andreastradella 0:d0a023131133 274
andreastradella 0:d0a023131133 275 wait(0.005);
andreastradella 0:d0a023131133 276
andreastradella 0:d0a023131133 277 //> =============================================
andreastradella 0:d0a023131133 278 //> I14443p3a_Sw_RequestA
andreastradella 0:d0a023131133 279 //> =============================================
andreastradella 0:d0a023131133 280
andreastradella 0:d0a023131133 281 // TxWaitStart at the end of Rx data
andreastradella 0:d0a023131133 282 write_reg( 0x31, 0xC0 );
andreastradella 0:d0a023131133 283
andreastradella 0:d0a023131133 284 // Set min.time between Rx and Tx or between two Tx
andreastradella 0:d0a023131133 285 write_reg( 0x32, 0x0B );
andreastradella 0:d0a023131133 286
andreastradella 0:d0a023131133 287 //> Set timeout for this command cmd. Init reload values for timers-0,1
andreastradella 0:d0a023131133 288 write_reg( 0x10, 0x08 );
andreastradella 0:d0a023131133 289 write_reg( 0x11, 0x94 );
andreastradella 0:d0a023131133 290 write_reg( 0x15, 0x00 );
andreastradella 0:d0a023131133 291 write_reg( 0x16, 0x00 );
andreastradella 0:d0a023131133 292 write_reg( 0x06, 0x08 );
andreastradella 0:d0a023131133 293 write_reg( 0x36, 0x90 );
andreastradella 0:d0a023131133 294 write_reg( 0x2E, 0x0F );
andreastradella 0:d0a023131133 295
andreastradella 0:d0a023131133 296 //> ---------------------
andreastradella 0:d0a023131133 297 //> Send the ReqA command
andreastradella 0:d0a023131133 298 //> ---------------------
andreastradella 0:d0a023131133 299
andreastradella 0:d0a023131133 300 //> Terminate any running command. FlushFifo
andreastradella 0:d0a023131133 301 terminate_and_flush_FiFo();
andreastradella 0:d0a023131133 302
andreastradella 0:d0a023131133 303 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 304 clear_IRQ();
andreastradella 0:d0a023131133 305
andreastradella 0:d0a023131133 306 //> Write ReqA=26 into FIFO
andreastradella 0:d0a023131133 307 write_reg( 0x05, 0x26 );
andreastradella 0:d0a023131133 308
andreastradella 0:d0a023131133 309 //> Start RC663 command "Transcieve"=0x07. Activate Rx after Tx finishes.
andreastradella 0:d0a023131133 310 write_reg( 0x00, 0x07 );
andreastradella 0:d0a023131133 311
andreastradella 0:d0a023131133 312 //> Wait until the command is finished. Enable IRQ sources.
andreastradella 0:d0a023131133 313 wait_command_and_enable_IRQ();
andreastradella 0:d0a023131133 314
andreastradella 0:d0a023131133 315 // Disable Irq 0,1 sources
andreastradella 0:d0a023131133 316 disable_IRQ();
andreastradella 0:d0a023131133 317
andreastradella 0:d0a023131133 318 // Return Irq0 status
andreastradella 0:d0a023131133 319 r = read_reg( 0x06 );
andreastradella 0:d0a023131133 320
andreastradella 0:d0a023131133 321 //> Wait until reception
andreastradella 0:d0a023131133 322 write_reg( 0x08, 0x54 );
andreastradella 0:d0a023131133 323 write_reg( 0x09, 0x42 );
andreastradella 0:d0a023131133 324 wait(0.001);
andreastradella 0:d0a023131133 325
andreastradella 0:d0a023131133 326 while( (read_reg( 0x07 ) & 0x40)==0);
andreastradella 0:d0a023131133 327
andreastradella 0:d0a023131133 328 while (w == 0){
andreastradella 0:d0a023131133 329 pc.printf("\nNO CARD DETECTED...\n");
andreastradella 0:d0a023131133 330 pc.printf("WAITING FOR A CARD...\n");
andreastradella 0:d0a023131133 331 w++;
andreastradella 0:d0a023131133 332 }
andreastradella 0:d0a023131133 333
andreastradella 0:d0a023131133 334 } while ( read_reg( 0x40 == 0 ) );
andreastradella 0:d0a023131133 335
andreastradella 0:d0a023131133 336 write_reg( 0x08, 0x00 );
andreastradella 0:d0a023131133 337 write_reg( 0x09, 0x00 );
andreastradella 0:d0a023131133 338
andreastradella 0:d0a023131133 339 r = read_reg( 0x05 );
andreastradella 0:d0a023131133 340 r = read_reg( 0x05 );
andreastradella 0:d0a023131133 341
andreastradella 0:d0a023131133 342 // Read the error register
andreastradella 0:d0a023131133 343 r = read_reg( 0x0a );
andreastradella 0:d0a023131133 344
andreastradella 0:d0a023131133 345 // Reset TxLastBits_Reg
andreastradella 0:d0a023131133 346 write_reg( 0x2E, 0x08 );
andreastradella 0:d0a023131133 347
andreastradella 0:d0a023131133 348 //> ------------------------------
andreastradella 0:d0a023131133 349 //> Get UID cascade level-1
andreastradella 0:d0a023131133 350 //> ------------------------------
andreastradella 0:d0a023131133 351 write_reg( 0x2E, 0x08 );
andreastradella 0:d0a023131133 352 write_reg( 0x0C, 0x00 );
andreastradella 0:d0a023131133 353
andreastradella 0:d0a023131133 354 // Terminate any running command, FlushFifo
andreastradella 0:d0a023131133 355 terminate_and_flush_FiFo();
andreastradella 0:d0a023131133 356
andreastradella 0:d0a023131133 357 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 358 clear_IRQ();
andreastradella 0:d0a023131133 359
andreastradella 0:d0a023131133 360 //> Write "Antcollision CL 1" cmd into FIFO (SEL=93, NVB=20)
andreastradella 0:d0a023131133 361 write_reg( 0x05, 0x93 );
andreastradella 0:d0a023131133 362 write_reg( 0x05, 0x20 );
andreastradella 0:d0a023131133 363
andreastradella 0:d0a023131133 364 // Start tranceive command
andreastradella 0:d0a023131133 365 start_tranceive();
andreastradella 0:d0a023131133 366
andreastradella 0:d0a023131133 367 // Wait until the command is finished
andreastradella 0:d0a023131133 368 wait_command_and_enable_IRQ();
andreastradella 0:d0a023131133 369
andreastradella 0:d0a023131133 370 // Disable IRQ0 interrupt sources
andreastradella 0:d0a023131133 371 disable_IRQ();
andreastradella 0:d0a023131133 372
andreastradella 0:d0a023131133 373 // Read IRQ 0,1 Status register
andreastradella 0:d0a023131133 374 read_IRQ_status();
andreastradella 0:d0a023131133 375
andreastradella 0:d0a023131133 376 //> Read FIFO, Expected - Complete UID (one PICC in HF)
andreastradella 0:d0a023131133 377 r = read_reg( 0x04 ); // FIFO length
andreastradella 0:d0a023131133 378
andreastradella 0:d0a023131133 379 // Cascade Tag (UID0)
andreastradella 0:d0a023131133 380 pc.printf("\nUID = 0x%02X", UID0 = read_reg( 0x05 ));
andreastradella 0:d0a023131133 381
andreastradella 0:d0a023131133 382 // UID1
andreastradella 0:d0a023131133 383 pc.printf("%02X", UID1 = read_reg( 0x05 ));
andreastradella 0:d0a023131133 384
andreastradella 0:d0a023131133 385 // UID2
andreastradella 0:d0a023131133 386 pc.printf("%02X", UID2 =read_reg( 0x05 ));
andreastradella 0:d0a023131133 387
andreastradella 0:d0a023131133 388 // UID3
andreastradella 0:d0a023131133 389 pc.printf("%02X\n", UID3 =read_reg( 0x05 ));
andreastradella 0:d0a023131133 390
andreastradella 0:d0a023131133 391 // BCC
andreastradella 0:d0a023131133 392 pc.printf("BCC = 0x%02X\n", UID4 =read_reg( 0x05 ));
andreastradella 0:d0a023131133 393
andreastradella 0:d0a023131133 394 led[1] = 1;
andreastradella 0:d0a023131133 395
andreastradella 0:d0a023131133 396 w = 1;
andreastradella 0:d0a023131133 397
andreastradella 0:d0a023131133 398 //> Read Error register
andreastradella 0:d0a023131133 399 r = read_reg( 0x0A );
andreastradella 0:d0a023131133 400
andreastradella 0:d0a023131133 401 //> ------------------------------
andreastradella 0:d0a023131133 402 //> Select cascade level-1
andreastradella 0:d0a023131133 403 //> ------------------------------
andreastradella 0:d0a023131133 404 // Terminate any running command, FlushFifo
andreastradella 0:d0a023131133 405 terminate_and_flush_FiFo();
andreastradella 0:d0a023131133 406
andreastradella 0:d0a023131133 407 write_reg( 0x2C, 0x19 ); // Enable RX and TX CRC
andreastradella 0:d0a023131133 408 write_reg( 0x2D, 0x19 );
andreastradella 0:d0a023131133 409 write_reg( 0x0C, 0x00 );
andreastradella 0:d0a023131133 410
andreastradella 0:d0a023131133 411
andreastradella 0:d0a023131133 412 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 413 clear_IRQ();
andreastradella 0:d0a023131133 414
andreastradella 0:d0a023131133 415 //> Write "Select CL 1" cmd into FIFO (SEL=93, NVB=70)
andreastradella 0:d0a023131133 416 write_reg( 0x05, 0x93 );
andreastradella 0:d0a023131133 417 write_reg( 0x05, 0x70 );
andreastradella 0:d0a023131133 418 write_reg( 0x05, UID0 ); // UID bytes ...
andreastradella 0:d0a023131133 419 write_reg( 0x05, UID1 );
andreastradella 0:d0a023131133 420 write_reg( 0x05, UID2 );
andreastradella 0:d0a023131133 421 write_reg( 0x05, UID3 );
andreastradella 0:d0a023131133 422 write_reg( 0x05, UID4 );
andreastradella 0:d0a023131133 423
andreastradella 0:d0a023131133 424 // Start tranceive command
andreastradella 0:d0a023131133 425 start_tranceive();
andreastradella 0:d0a023131133 426
andreastradella 0:d0a023131133 427 // Wait until the command is finished
andreastradella 0:d0a023131133 428 wait_command_and_enable_IRQ();
andreastradella 0:d0a023131133 429
andreastradella 0:d0a023131133 430 // Disable IRQ0 interrupt sources
andreastradella 0:d0a023131133 431 disable_IRQ();
andreastradella 0:d0a023131133 432
andreastradella 0:d0a023131133 433 // Read IRQ 0,1 Status register
andreastradella 0:d0a023131133 434 read_IRQ_status();
andreastradella 0:d0a023131133 435
andreastradella 0:d0a023131133 436 //> Read FIFO, Expected - Complete UID (one PICC in HF)
andreastradella 0:d0a023131133 437 r = read_reg( 0x04 ); // FIFO length
andreastradella 0:d0a023131133 438
andreastradella 0:d0a023131133 439 } while( (read_reg( 0x05 ) & 0x04) == 0 );
andreastradella 0:d0a023131133 440
andreastradella 0:d0a023131133 441 pc.printf("7 BYTE CARD DETECTED\n");
andreastradella 0:d0a023131133 442
andreastradella 0:d0a023131133 443 led[2] = 1;
andreastradella 0:d0a023131133 444
andreastradella 0:d0a023131133 445 //----------------------------------------------------------------------------------------
andreastradella 0:d0a023131133 446 //----------------------------------------------------------------------------------------
andreastradella 0:d0a023131133 447 //> ------------------------------
andreastradella 0:d0a023131133 448 //> Get UID cascade level-2
andreastradella 0:d0a023131133 449 //> ------------------------------
andreastradella 0:d0a023131133 450 write_reg( 0x2E, 0x08 );
andreastradella 0:d0a023131133 451 write_reg( 0x0C, 0x00 );
andreastradella 0:d0a023131133 452 write_reg( 0x2C, 0x18 ); // TX, RX CRC off
andreastradella 0:d0a023131133 453 write_reg( 0x2D, 0x18 );
andreastradella 0:d0a023131133 454
andreastradella 0:d0a023131133 455 // Terminate any running command, FlushFifo
andreastradella 0:d0a023131133 456 terminate_and_flush_FiFo();
andreastradella 0:d0a023131133 457
andreastradella 0:d0a023131133 458 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 459 clear_IRQ();
andreastradella 0:d0a023131133 460
andreastradella 0:d0a023131133 461 //> Write "Antcollision CL 2" cmd into FIFO (SEL=95, NVB=20)
andreastradella 0:d0a023131133 462 write_reg( 0x05, 0x95 );
andreastradella 0:d0a023131133 463 write_reg( 0x05, 0x20 );
andreastradella 0:d0a023131133 464
andreastradella 0:d0a023131133 465 // Start tranceive command
andreastradella 0:d0a023131133 466 start_tranceive();
andreastradella 0:d0a023131133 467
andreastradella 0:d0a023131133 468 // Wait until the command is finished
andreastradella 0:d0a023131133 469 wait_command_and_enable_IRQ();
andreastradella 0:d0a023131133 470
andreastradella 0:d0a023131133 471 // Disable IRQ0 interrupt sources
andreastradella 0:d0a023131133 472 disable_IRQ();
andreastradella 0:d0a023131133 473
andreastradella 0:d0a023131133 474 // Read IRQ 0,1 Status register
andreastradella 0:d0a023131133 475 read_IRQ_status();
andreastradella 0:d0a023131133 476
andreastradella 0:d0a023131133 477 //> Read FIFO
andreastradella 0:d0a023131133 478 r = read_reg( 0x04 ); // FIFO length
andreastradella 0:d0a023131133 479
andreastradella 0:d0a023131133 480 // Cascade Tag (UID0)
andreastradella 0:d0a023131133 481 pc.printf("UID = 0x%02X", UID0 = read_reg( 0x05 ));
andreastradella 0:d0a023131133 482
andreastradella 0:d0a023131133 483 // UID1
andreastradella 0:d0a023131133 484 pc.printf("%02X", UID1 = read_reg( 0x05 ));
andreastradella 0:d0a023131133 485
andreastradella 0:d0a023131133 486 // UID2
andreastradella 0:d0a023131133 487 pc.printf("%02X", UID2 =read_reg( 0x05 ));
andreastradella 0:d0a023131133 488
andreastradella 0:d0a023131133 489 // UID
andreastradella 0:d0a023131133 490 pc.printf("%02X\n", UID3 =read_reg( 0x05 ));
andreastradella 0:d0a023131133 491
andreastradella 0:d0a023131133 492 // BCC
andreastradella 0:d0a023131133 493 pc.printf("BCC = 0x%02X\n", UID4 =read_reg( 0x05 ));
andreastradella 0:d0a023131133 494
andreastradella 0:d0a023131133 495 led[3] = 1;
andreastradella 0:d0a023131133 496
andreastradella 0:d0a023131133 497 //> Read Error register
andreastradella 0:d0a023131133 498 r = read_reg( 0x0A );
andreastradella 0:d0a023131133 499
andreastradella 0:d0a023131133 500 //> ------------------------------
andreastradella 0:d0a023131133 501 //> Select cascade level-2
andreastradella 0:d0a023131133 502 //> ------------------------------
andreastradella 0:d0a023131133 503 // Terminate any running command, FlushFifo
andreastradella 0:d0a023131133 504 terminate_and_flush_FiFo();
andreastradella 0:d0a023131133 505
andreastradella 0:d0a023131133 506 write_reg( 0x2C, 0x19 ); // Enable RX and TX CRC
andreastradella 0:d0a023131133 507 write_reg( 0x2D, 0x19 );
andreastradella 0:d0a023131133 508 write_reg( 0x0C, 0x00 );
andreastradella 0:d0a023131133 509
andreastradella 0:d0a023131133 510 // Clear all IRQ 0,1 flags
andreastradella 0:d0a023131133 511 clear_IRQ();
andreastradella 0:d0a023131133 512
andreastradella 0:d0a023131133 513 //> Write "Select CL 2" cmd into FIFO (SEL=95, NVB=70)
andreastradella 0:d0a023131133 514 write_reg( 0x05, 0x95 );
andreastradella 0:d0a023131133 515 write_reg( 0x05, 0x70 );
andreastradella 0:d0a023131133 516 write_reg( 0x05, UID0 ); // UID bytes ...
andreastradella 0:d0a023131133 517 write_reg( 0x05, UID1 );
andreastradella 0:d0a023131133 518 write_reg( 0x05, UID2 );
andreastradella 0:d0a023131133 519 write_reg( 0x05, UID3 );
andreastradella 0:d0a023131133 520 write_reg( 0x05, UID4 );
andreastradella 0:d0a023131133 521
andreastradella 0:d0a023131133 522 // Start tranceive command
andreastradella 0:d0a023131133 523 start_tranceive();
andreastradella 0:d0a023131133 524
andreastradella 0:d0a023131133 525 // Wait until the command is finished
andreastradella 0:d0a023131133 526 wait_command_and_enable_IRQ();
andreastradella 0:d0a023131133 527
andreastradella 0:d0a023131133 528 // Disable IRQ0 interrupt sources
andreastradella 0:d0a023131133 529 disable_IRQ();
andreastradella 0:d0a023131133 530
andreastradella 0:d0a023131133 531 // Read IRQ 0,1 Status register
andreastradella 0:d0a023131133 532 read_IRQ_status();
andreastradella 0:d0a023131133 533
andreastradella 0:d0a023131133 534 //> Read FIFO
andreastradella 0:d0a023131133 535 r = read_reg( 0x04 ); // FIFO length
andreastradella 0:d0a023131133 536
andreastradella 0:d0a023131133 537 r = read_reg( 0x05 ); // Response
andreastradella 0:d0a023131133 538
andreastradella 0:d0a023131133 539 led[3] = 1 ;
andreastradella 0:d0a023131133 540
andreastradella 0:d0a023131133 541 }
andreastradella 0:d0a023131133 542 }