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Comitter:
theotherjimmy
Date:
Tue Sep 25 13:43:09 2018 -0500
Parent:
42:2cf3f29fece1
Child:
44:bad0b339f97d
Commit message:
Release 5.10.0

Changed in this revision

arm_pack_manager/__init__.py Show annotated file Show diff for this revision Revisions of this file
arm_pack_manager/aliases.json Show annotated file Show diff for this revision Revisions of this file
arm_pack_manager/index.json Show annotated file Show diff for this revision Revisions of this file
arm_pack_manager/pack_manager.py Show annotated file Show diff for this revision Revisions of this file
bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin Show annotated file Show diff for this revision Revisions of this file
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device_management.py Show annotated file Show diff for this revision Revisions of this file
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options.py Show annotated file Show diff for this revision Revisions of this file
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targets/REALTEK_RTL8195AM.py Show annotated file Show diff for this revision Revisions of this file
targets/STM32_gen_PeripheralPins.py Show annotated file Show diff for this revision Revisions of this file
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test_configs/6lowpanInterface_host.json Show annotated file Show diff for this revision Revisions of this file
test_configs/6lowpanInterface_router.json Show annotated file Show diff for this revision Revisions of this file
test_configs/ESP8266Interface.json Show annotated file Show diff for this revision Revisions of this file
test_configs/EthernetInterface.json Show annotated file Show diff for this revision Revisions of this file
test_configs/HeapBlockDevice.json Show annotated file Show diff for this revision Revisions of this file
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test_configs/HeapBlockDeviceAndWifiInterface.json Show annotated file Show diff for this revision Revisions of this file
test_configs/ISM43362Interface.json Show annotated file Show diff for this revision Revisions of this file
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tests.py Show annotated file Show diff for this revision Revisions of this file
toolchains/__init__.py Show annotated file Show diff for this revision Revisions of this file
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utils.py Show annotated file Show diff for this revision Revisions of this file
--- a/arm_pack_manager/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/arm_pack_manager/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,10 +1,16 @@
-from urllib2 import urlopen, URLError
+try:
+    from urllib2 import urlopen, URLError
+except ImportError:
+    from urllib.request import urlopen, URLError
 from bs4 import BeautifulSoup
 from os.path import join, dirname, basename
 from os import makedirs
 from errno import EEXIST
 from threading import Thread
-from Queue import Queue
+try:
+    from Queue import Queue
+except ImportError:
+    from queue import Queue
 from re import compile, sub
 from sys import stderr, stdout
 from itertools import takewhile
@@ -15,6 +21,8 @@
 import warnings
 from distutils.version import LooseVersion
 
+from tools.flash_algo import PackFlashAlgo
+
 warnings.filterwarnings("ignore")
 
 from fuzzywuzzy import process
@@ -145,12 +153,41 @@
                          for pdsc in root_data.find_all("pdsc")]
         return self.urls
 
+    def _get_sectors(self, device):
+        """Extract sector sizes from device FLM algorithm
+
+        Will return None if there is no algorithm, pdsc URL formatted in correctly
+
+        :return: A list tuples of sector start and size
+        :rtype: [list]
+        """
+        try:
+            pack = self.pack_from_cache(device)
+            ret = []
+            for filename in device['algorithm'].keys():
+                try:
+                    flm = pack.open(filename)
+                    flash_alg = PackFlashAlgo(flm.read())
+                    sectors = [(flash_alg.flash_start + offset, size)
+                               for offset, size in flash_alg.sector_sizes]
+                    ret.extend(sectors)
+                except Exception:
+                    pass
+            ret.sort(key=lambda sector: sector[0])
+            return ret
+        except Exception:
+            return None
+
     def _extract_dict(self, device, filename, pack) :
         to_ret = dict(pdsc_file=filename, pack_file=pack)
         try : to_ret["memory"] = dict([(m["id"], dict(start=m["start"],
                                                       size=m["size"]))
                                        for m in device("memory")])
-        except (KeyError, TypeError, IndexError) as e : pass
+        except (KeyError, TypeError, IndexError) as e:
+            try : to_ret["memory"] = dict([(m["name"], dict(start=m["start"],
+                                                          size=m["size"]))
+                                           for m in device("memory")])
+            except (KeyError, TypeError, IndexError) as e : pass
         try: algorithms = device("algorithm")
         except:
             try: algorithms = device.parent("algorithm")
@@ -219,6 +256,7 @@
             del to_ret["compile"]
 
         to_ret['debug-interface'] = []
+        to_ret['sectors'] = self._get_sectors(to_ret)
 
         return to_ret
 
@@ -445,4 +483,3 @@
         """
         self.cache_file(url)
         return self.pdsc_from_cache(url)
-
--- a/arm_pack_manager/aliases.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/arm_pack_manager/aliases.json	Tue Sep 25 13:43:09 2018 -0500
@@ -1,1 +1,1 @@
-{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "Apollo1 EVB": "APOLLO512-KBR", "NuTiny-SDK-M451": "M453VG6AE", "NuTiny-SDK-M0518": "M0518SD2AE", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "Z32F0640100KITG": "Z32F06410AES", "SAMD51-XPRO": "ATSAMD51P20A", "NuTiny-SDK-NANO112": "NANO112VC2AN", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "STM32H743I-EVAL": "STM32H743XI", "NUCLEO-L152RE": "STM32L152RE", "TWR-KV10Z32": "MKV10Z32xxx7", "XMC4800 Automation Board": "XMC4800-E196x2048", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-K70F120M": "MK70FN1M0xxx12", "STM32F769I-Discovery": "STM32F769NIHx", "TWR-KE18F": "MKE18F512xxx16", "MCBSTM32F400": "STM32F407IG", "SAML21-XPRO": "ATSAML21J18A", "STM32F030-Discovery": "STM32F030R8", "SAMA5D2-XULT": "ATSAMA5D27", "Apollo EVK": "APOLLO512-KBR", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "MCB1700": "LPC1758", "V2M-MPS2": "CMSDK_CM7", "MCB54110": "LPC54114J256BD64", "LPC1788-32 Developers Kit": "LPC1788", "Z32F1280100KITG": "Z32F12811ARS", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "Colibri-VF50": "MVF50NN15xxxx40", "MCBSTM32F200": "STM32F207IG", "EVAL-ADuCM322EBZ": "ADuCM322", "FRDM-KL25Z": "MKL25Z128xxx4", "SN32F707B Starter Kit Rev1_0": "SN32F70*B", "NUCLEO-F446RE": "STM32F446RE", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "MCB11C14": "LPC11C14FBD48/301", "FRDM-KL02Z": "MKL02Z32xxx4", "Colibri-iMX7": "MCIMX7D7", "NuTiny-SDK-Mini55": "Mini54XZAE", "NuTiny-SDK-Mini57": "Mini57TDE", "SAM3S-EK": "ATSAM3S4C", "SF2_DEV_KIT": "M2S050", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "uVision Simulator": "ARMCM0", "FRDM-K28F": "MK28FN2M0xxx15", "TRK-KEA64": "SKEAZN64xxx2", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "EVAL-ADuCM320EBZ": "ADuCM320", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "NOVPEK-iMX7": "MCIMX7D7", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SAMG55-XPRO": "ATSAMG55J19", "Fixed Virtual Platform": "ARMCA5", "SAMHA1G16A-XPRO": "ATSAMHA1G16A", "FRDM-KE06Z": "MKE06Z128xxx4", "NUCLEO-F072RB": "STM32F072RB", "NuTiny-SDK-NUC100": "NUC100VE3DN", "MCBTMPM360": "TMPM362F10FG", "NuTiny-SDK-NUC121": "NUC121SC2AE", "NuTiny-SDK-NUC029AE": "NUC029FAE", "NuTiny-SDK-M0564": "M0564VG4AE", "V2M-MPS2 (IoT)": "IOTKit_ARMv8MML", "ADuCM4050 EZ-KIT": "ADuCM4050", "FRDM-K20D50M": "MK20DX128xxx5", "STM32756G-EVAL": "STM32F756NGHx", "SAM4L-XPRO": "ATSAM4LC4C", "FRDM-KL43Z": "MKL43Z256xxx4", "nRF52 PCA10036": "nRF52832_xxAA", "TWR-KV11Z75M": "MKV11Z128xxx7", "NuTiny-SDK-NUC029AN": "NUC029TAN", "TWR-VF65GS10": "MVF61NS15xxxx50", "TWR-KM34Z50": "MKM34Z128xxx5", "STM32L-Discovery": "STM32L152RB", "AC30M1464 MINI B/D": "AC30M1464", "IMX7-PHYBOARD-ZETA": "MCIMX7D7", "XMC1100 Boot Kit": "XMC1100-T038x0064", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", "EFM32WG-STK3800": "EFM32WG990F256", "MCB1313": "LPC1313FBD48", "NuTiny-SDK-M480": "M487JIDAE", "TWR-K65F180M": "MK65FN2M0xxx18", "EB_TMPM369FDFG": "TMPM369FDFG", "TS-R-IN32M3-EC": "R-IN32M3-EC", "XMC4300 Relax Kit": "XMC4300-F100x256", "LPCXpresso54114": "LPC54114J256BD64", "STM32F429I-Discovery": "STM32F429ZI", "Colibri-VF61": "MVF61NN15xxxx50", "NUCLEO-F091RC": "STM32F091RC", "SAMV71-XULTRA": "ATSAMV71Q21", "FRDM-KW41Z": "MKW41Z512xxx4", "TWR-KL43Z48M": "MKL43Z256xxx4", "STM32373C-EVAL": "STM32F373VC", "QN908XDK": "QN9080A", "STM32F746G-Discovery": "STM32F746NGHx", "TWR-K24F120M": "MK24FN256xxx12", "nRF52 PCA10040": "nRF52832_xxAA", "MCBSTM32C": "STM32F107VC", "FRDM-KL03Z": "MKL03Z32xxx4", "MCBSTM32E": "STM32F103ZG", "NUCLEO-F401RE": "STM32F401RE", "SF2_EVAL_KIT": "M2S025", "STM32303C-EVAL": "STM32F303VC", "AC33MA384A MINI B/D": "AC33MA384A", "SAML22-XPRO": "ATSAML22N18A", "XMC4800 Relax EtherCAT Kit": "XMC4800-F144x2048", "iMX7-Dual-COM": "MCIMX7D7", "TRK-KEA128": "SKEAZ128xxx4", "SAM4S-EK": "SAM4S16C", "TWR-K20D50M": "MK20DX128xxx5", "STM32F3-Discovery": "STM32F303VC", "LPCXpresso1125": "LPC1125JBD48/303", "STM32F4-Discovery": "STM32F407VG", "CMSIS_RTOS_Tutorial": "STM32F103RB", "SAM3X-EK": "ATSAM3X8H", "SF2_ADV_DEV_KIT": "M2S150", "SN32F760 Starter Kit Rev1_1": "SN32F76*", "Core103R_Board": "MM32x103", "NuTiny-SDK-Mini51": "Mini54LDE", "Apollo2 EVB": "AMAPH1KK-KBR", "FRDM-KE04Z": "MKE04Z8xxx4", "NuTiny-SDK-NUC123": "NUC123SD4AN0", "TWR-KL28Z72M": "MKL28Z512xxx7", "Apollo2 EVK": "AMAPH1KK-KBR", "LPC4330-Xplorer": "LPC4330", "NuTiny-SDK-NUC126": "NUC126VG4AE", "MCBTMPM330": "TMPM330FDFG", "NUCLEO-L476RG": "STM32L476RG", "STM32F334-Discovery": "STM32F334C8", "MCB1800": "LPC1850", "EFM32GG-STK3700": "EFM32GG990F1024", "GD32150C-START": "GD32F150C8", "AC33GA256 MINI B/D": "AC33GA256", "TS-R-IN32M3-CL": "R-IN32M3-CL", "TS-R-IN32M3-CEC": "R-IN32M3-EC", "EVAL-ADuCM320iQSPZ": "ADuCM320i", "AC33M8128/6128 MINI B/D": "AC33M8128", "SAM4S-XPRO": "ATSAM4SD32C", "STM32L053-Discovery": "STM32L053C8", "TWR-KM34Z50MV3": "MKM34Z128Axxx5", "PAC52XX EVK": "PAC52XX", "XMC4500 CPU Board - General Purpose (CPU_45A)": "XMC4500-F144x1024", "NuTiny-SDK-NUC122": "NUC122SD2AN", "Z32F3840100KITG": "Z32F38412ALS", "LPCXpresso54608": "LPC54608J512BD208", "MCIMX7ULP-EVK": "MCIMX7U5", "LPC824 LPCXpresso": "LPC824M201JHI33", "STM32439I-EVAL": "STM32F439NI", "EFM32TG-STK3300": "EFM32TG840F32", "AC33M4064/3064 MINI B/D": "AC33M4064", "NUCLEO-F030R8": "STM32F030R8", "NuTiny-SDK-NUC131": "NUC131SD2AE", "DK-TM4C129x": "TM4C129XNCZAD", "STM32F769I-EVAL": "STM32F769NIHx", "SF2_STARTER_KIT": "M2S010", "nRF51 PCA20006": "nRF51822_xxaa", "TS-R-IN32M4-CL2": "R-IN32M4-CL2", "MCIMX6SX-SABRE": "MCIMX6X1", "EVAL-ADICUP3029": "ADuCM3029", "SAM4C-EK": "ATSAM4C16C", "MCB1500": "LPC1549JBD100", "TWR-KW21D256": "MKW21D256xxx5", "STM32L476G-EVAL": "STM32L476ZG", "MCIMX7D-SABRE": "MCIMX7D7", "STM32F051-Discovery": "STM32F051R8", "NUCLEO-L053R8": "STM32L053R8", "FRDM-K64F": "MK64FN1M0VLL12", "TLE9869 EvalKit": "TLE9869QXA20", "NuTiny-SDK-NUC240": "NUC240VE3AE", "LPC84x LPCXpresso": "LPC845M301JBD64", "S32K144-EVB": "S32K144UAT0xxxx", "SAMD20-XPRO": "ATSAMD20J18", "SN32F770 Starter Kit Rev1_0": "SN32F70*B", "SAM4E-EK": "SAM4E16C", "MCB1343": "LPC1343FBD48", "LinkIt 7687 development board": "MT7687F", "XMC4500 CPU Board - General Purpose (CPU_45B)": "XMC4500-E144x1024", "SAM3N-EK": "ATSAM3N4C", "LinkIt 2523 development board": "MT2523x", "SAM3U-EK": "ATSAM3U4E", "ADSP-CM419F EZ-BOARD M0": "ADSP-CM419F-BCZ_M0", "ADuCM3029 EZ-KIT": "ADuCM3029", "NuTiny-SDK-NUC200": "NUC220VE3AN", "FRDM-KL82Z": "MKL81Z128xxx7", "XMC1300 Boot Kit": "XMC1302-T038x0200", "Bulb Board": "S6E1A12B0A", "MCBTMPM395": "TMPM395FWAXBG", "STM32F072-Discovery": "STM32F072RB", "BMSKTOPASM369": "TMPM369FDFG", "LPCXpresso54102": "LPC54102J512BD64", "NuTiny-SDK-NANO100AN": "NANO100VD3AN", "TWR-K60D100M": "MK60DN512xxx10", "TWR-K20D72M": "MK20DX256xxx7", "nRF51 PCA10031": "nRF51422_xxAC", "EK-TM4C1294XL": "TM4C1294NCPDT", "SK-FM3-176PMC-ETHERNET": "MB9BFD18T", "LPC4088-32 Developers Kit": "LPC4088FET208", "FRDM-KW36": "MKW36A512xxx4", "TLE984x Eval.Board": "TLE9844QX", "XMC4500 Relax Lite Kit": "XMC4500-F100x1024", "iMX6-SoloX-COM": "MCIMX6X4", "SAME70-XPLD": "ATSAME70Q21", "LPCXpresso11U68": "LPC11U68JBD100", "XMC4400 CPU Board - General Purpose  (CPU_44A)": "XMC4400-F100x512", "NUCLEO-F103RB": "STM32F103RB", "EFM32ZG-STK3200": "EFM32ZG222F32", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "MCBTWRK60": "MK60DN512xxx10", "MCB9B500": "MB9BF506R", "Z32F0642100KITG": "Z32F06423AKE", "ADSP-CM419F EZ-BOARD": "ADSP-CM419F", "LPC812 LPCXpresso": "LPC812M101JDH20", "TWR-KL82Z72M": "MKL82Z128xxx7", "SN32F100 Starter Kit": "SN32F10*", "NuTiny-SDK-M0519": "M0519VE3AE", "TWR-K64F120M": "MK64FN1M0xxx12", "MCB4300": "LPC4350", "XMC4200 CPU Board - Actuator  (CPU_42A)": "XMC4200-F64x256", "EVAL-ADuCM360MKZ": "ADuCM360"}
\ No newline at end of file
+{"nRF51 PCA10028": "nRF51422_xxAC", "SAM4L-EK": "ATSAM4LC4C", "HVP-KV31F120M": "MKV31F512xxx12", "Apollo1 EVB": "APOLLO512-KBR", "STM32F429I-Discovery": "STM32F429ZI", "MAPS-KS22": "MKS22FN256xxx12", "SAMD21-XPRO": "ATSAMD21J18A", "EVKB-IMXRT1050": "MIMXRT1052xxxxB", "STM32L073Z-EVAL": "STM32L073VZ", "TLE9879 EvalKit": "TLE9879QXA40", "STM32F401C-Discovery": "STM32F401VC", "NuTiny-SDK-M051": "M0516LDE", "TWR-K21D50M": "MK21DN512Axxx5", "MCB11C14": "LPC11C14FBD48/301", "TWR-K21F120M": "MK21FN1M0Axxx12", "NuTiny-SDK-NANO112": "NANO112VC2AN", "XMC4500 Relax Kit": "XMC4500-F100x1024", "TWR-K22F120M": "MK22FN512xxx12", "MCB1200": "LPC1227FBD64/301", "DB-MAX71637": "MAX71637", "XMC 2Go": "XMC1100-Q024x0064", "STM32H743I-EVAL": "STM32H743XI", "V2M-MPS3 (IoT)": "IOTKit_CM33_MPS3", "NUCLEO-L152RE": "STM32L152RE", "Colibri-VF61": "MVF61NN15xxxx50", "EV-COG-AD4050LZ": "ADuCM4x50", "FRDM-KW40Z": "MKW40Z160xxx4", "NuTiny-SDK-NM1200": "NM1200LBAE", "TWR-KV10Z32": "MKV10Z32xxx7", "TWR-K70F120M": "MK70FN1M0xxx12", "STM32F769I-Discovery": "STM32F769NIHx", "TWR-KE18F": "MKE18F512xxx16", "S32K148-EVB": "S32K148UAxxxLQx", "MAX32660_EVKIT": "MAX32660", "MCBSTM32F400": "STM32F407IG", "FRDM-KL25Z": "MKL25Z128xxx4", "LPCXpresso54608": "LPC54608J512", "AC33M4064/3064 MINI B/D": "AC33M4064", "STM32756G-EVAL": "STM32F756NGHx", "SAMA5D2-XULT": "ATSAMA5D27", "Apollo EVK": "APOLLO512-KBR", "NuTiny-SDK-NUC505": "NUC505YO13Y", "NuTiny-SDK-M058S": "M058SSAN", "TRK-KEA8": "SKEAZN8xxx4", "EVK-MIMX8MQ": "MIMX8MQ6xxxJZ", "TWR-VF65GS10": "MVF61NS15xxxx50", "NUCLEO-F446RE": "STM32F446RE", "Z32F0642100KITG": "Z32F06423AKE", "MCB54110": "LPC54114J256BD64", "STM32L496G-Discovery": "STM32L496AGIx", "LPC1788-32 Developers Kit": "LPC1788", "Z32F1280100KITG": "Z32F12811ARS", "MAX32625_EVKIT": "MAX32625", "NuTiny-SDK-NUC472": "NUC472HI8AE", "EFM32GG-DK3750": "EFM32GG990F1024", "TWR-KV11Z75M": "MKV11Z128xxx7", "SAME54-XPRO": "ATSAME54P20A", "Colibri-VF50": "MVF50NN15xxxx40", "MCBSTM32F200": "STM32F207IG", "FRDM-KL82Z": "MKL82Z128xxx7", "FRDM-KL46Z": "MKL46Z256xxx4", "HVP-KE18F": "MKE18F512xxx16", "HVP-KV58F": "MKV58F1M0xxx24", "HVP-KV46F150M": "MKV46F256xxx16", "FRDM-K22F": "MK22FN512xxx12", "EVAL-ADuCM322EBZ": "ADuCM322", "MCBTMPM360": "TMPM362F10FG", "A31G112 MINI B/D": "A31G11x", "STM32F072-Discovery": "STM32F072RB", "NuTiny-SDK-NANO103": "NANO103SD3AE", "MCBNUC1xx": "NUC140VE3AN", "Z32F0640100KITG": "Z32F06410AES", "FRDM-KL81Z": "MKL81Z128xxx7", "LPCXpresso54114": "LPC54114J256", "Colibri-iMX7": "MCIMX7D7", "MAX32650_EVKIT": "MAX32650", "NuTiny-SDK-Mini55": "Mini54XZAE", "NuTiny-SDK-Mini57": "Mini57TDE", "SAM3S-EK": "ATSAM3S4C", "SF2_DEV_KIT": "M2S050", "FRDM-KL43Z": "MKL43Z256xxx4", "FRDM-KL27Z": "MKL27Z64xxx4", "NuTiny-SDK-NANO100BN": "NANO130KE3BN", "NuTiny-SDK-Mini58": "Mini58LDE", "XMC1400 Boot Kit": "XMC1402-Q040x0128", "FRDM-K28F": "MK28FN2M0xxx15", "TRK-KEA64": "SKEAZN64xxx2", "SAM3N-EK": "ATSAM3N4C", "XMC1200 Boot Kit": "XMC1201-T038x0200", "N5 Starter Kit": "nRF51422_xxAA", "Core031C_Board": "MM32x031", "EFM32HG-SLSTK3400A": "EFM32HG322F64", "EVAL-ADuCM320EBZ": "ADuCM320", "ADSP-CM419F EZ-BOARD M4": "ADSP-CM419F-BCZ_M4", "ADSP-CM419F EZ-BOARD M0": "ADSP-CM419F-BCZ_M0", "Fixed Virtual Platform": "ARMCA5", "FRDM-KE06Z": "MKE06Z128xxx4", "NUCLEO-F072RB": "STM32F072RB", "NuTiny-SDK-NUC100": "NUC100VE3DN", "MCB1700": "LPC1758", "MCBTWRK60": "MK60DN512xxx10", "FRDM-K32W042": "K32W042S1M2xxx", "NuTiny-SDK-NUC121": "NUC121SC2AE", "NuTiny-SDK-NUC029AE": "NUC029FAE", "NuTiny-SDK-M0564": "M0564VG4AE", "XMC4800 Automation Board": "XMC4800-E196x2048", "FRDM-K20D50M": "MK20DX128xxx5", "TS-R-IN32M3-CEC": "R-IN32M3-EC", "SAM4L-XPRO": "ATSAM4LC4C", "EVAL-ADuCM360MKZ": "ADuCM360", "nRF52 PCA10036": "nRF52832_xxAA", "STM32303C-EVAL": "STM32F303VC", "LPCXpresso54102": "LPC54102J512", "SF2_STARTER_KIT": "M2S010", "STM32L-Discovery": "STM32L152RB", "IMX7-PHYBOARD-ZETA": "MCIMX7D7", "nRF51 PCA20006": "nRF51822_xxaa", "TWR-KV46F150M": "MKV46F256xxx16", "Koala EVM": "STM32F429II", "LPC54018-IoT-Module": "LPC54018", "V2M-MPS2-SSE-200": "SMM-SSE-200", "EFM32WG-STK3800": "EFM32WG990F256", "MCIMX7D-SABRE": "MCIMX7D7", "MCB1313": "LPC1313FBD48", "STM32F7-SOM": "STM32F746NGHx", "TWR-K65F180M": "MK65FN2M0xxx18", "EB_TMPM369FDFG": "TMPM369FDFG", "SAM4C-EK": "ATSAM4C16C", "LPCXpresso845-MAX": "LPC845M301JBD64", "TS-R-IN32M3-EC": "R-IN32M3-EC", "TWR-KM34Z50MV3": "MKM34Z128Axxx5", "RS14100": "RS14100_1MB", "NUCLEO-F091RC": "STM32F091RC", "SAMV71-XULTRA": "ATSAMV71Q21", "FRDM-KW41Z": "MKW41Z512xxx4", "TWR-KL43Z48M": "MKL43Z256xxx4", "STM32373C-EVAL": "STM32F373VC", "QN908XDK": "QN9080A", "NuTiny-SDK-M480": "M487JIDAE", "SH32F2xxEVB": "SH32F205", "RC10001_DB": "RC10001", "LinkIt 2523 development board": "MT2523x", "MCIMX7ULP-EVK": "MCIMX7U5", "nRF52 PCA10040": "nRF52832_xxAA", "MCBSTM32C": "STM32F107VC", "FRDM-KL03Z": "MKL03Z32xxx4", "AC30M1464 MINI B/D": "AC30M1464", "NUCLEO-F401RE": "STM32F401RE", "SF2_EVAL_KIT": "M2S025", "AC33MA384A MINI B/D": "AC33MA384A", "SAML22-XPRO": "ATSAML22N18A", "XMC4800 Relax EtherCAT Kit": "XMC4800-F144x2048", "iMX7-Dual-COM": "MCIMX7D7", "TRK-KEA128": "SKEAZ128xxx4", "SAM4S-EK": "SAM4S16C", "TWR-K20D50M": "MK20DX128xxx5", "STM32F3-Discovery": "STM32F303VC", "LPC812 LPCXpresso": "LPC812M101JDH20", "LPCXpresso1125": "LPC1125JBD48/303", "STM32F4-Discovery": "STM32F407VG", "CMSIS_RTOS_Tutorial": "STM32F103RB", "SAM3X-EK": "ATSAM3X8H", "SF2_ADV_DEV_KIT": "M2S150", "RTK772100-GENMAI": "R7S72100", "SN32F760 Starter Kit Rev1_1": "SN32F76*", "Core103R_Board": "MM32x103", "NuTiny-SDK-Mini51": "Mini54LDE", "EK-TM4C1294XL": "TM4C1294NCPDT", "Apollo2 EVB": "AMAPH1KK-KBR", "TWR-KV58F220M": "MKV58F1M0xxx24", "FRDM-K82F": "MK82FN256xxx15", "FRDM-KE04Z": "MKE04Z8xxx4", "NuTiny-SDK-NUC123": "NUC123SD4AN0", "TLE984x Eval.Board Rev1.4": "TLE9844QX", "Apollo2 EVK": "AMAPH1KK-KBR", "LPC4330-Xplorer": "LPC4330", "TWR-K24F120M": "MK24FN256xxx12", "MCBTMPM330": "TMPM330FDFG", "NUCLEO-L476RG": "STM32L476RG", "LPCXpresso54628": "LPC54628J512", "TWR-KL81Z72M": "MKL81Z128xxx7", "STM32F334-Discovery": "STM32F334C8", "MCB1800": "LPC1850", "EFM32GG-STK3700": "EFM32GG990F1024", "FRDM-K28FA": "MK28FN2M0Axxx15", "MAX32630_EVKIT": "MAX32630", "FRDM-KL02Z": "MKL02Z32xxx4", "GD32150C-START": "GD32F150C8", "AC33GA256 MINI B/D": "AC33GA256", "TS-R-IN32M3-CL": "R-IN32M3-CL", "FRDM-KE15Z": "MKE15Z256xxx7", "STM32072B-EVAL": "STM32F072VB", "STM32091C-EVAL": "STM32F091VC", "EVAL-ADuCM320iQSPZ": "ADuCM320i", "STM32L4R9I-EVAL": "STM32L4R9AIIx", "AC33M8128/6128 MINI B/D": "AC33M8128", "SAM4S-XPRO": "ATSAM4SD32C", "HEXIWEAR": "MK64FN1M0xxx12", "STM32L053-Discovery": "STM32L053C8", "A31G123 MINI B/D": "A31G12x", "STM32303E-EVAL": "STM32F303VE", "PAC52XX EVK": "PAC52XX", "XMC4500 CPU Board - General Purpose (CPU_45A)": "XMC4500-F144x1024", "NuTiny-SDK-NUC122": "NUC122SD2AN", "Musca": "Musca", "Z32F3840100KITG": "Z32F38412ALS", "SAML21-XPRO": "ATSAML21J18A", "A33G527/526 MINI B/D": "A33G52x", "EFM32TG-STK3300": "EFM32TG840F32", "STM32F030-Discovery": "STM32F030R8", "NUCLEO-F030R8": "STM32F030R8", "NuTiny-SDK-NUC131": "NUC131SD2AE", "NuTiny-SDK-M2351": "M2351KIAAE", "32F469IDISCOVERY": "STM32F469NI", "STM32F769I-EVAL": "STM32F769NIHx", "TWR-KM34Z50": "MKM34Z128xxx5", "XMC1100 Boot Kit": "XMC1100-T038x0064", "TS-R-IN32M4-CL2": "R-IN32M4-CL2", "V2M-MPS2 (IoT)": "IOTKit_ARMv8MML", "FRDM-KL28Z": "MKL28Z512xxx7", "MCIMX6SX-SABRE": "MCIMX6X1", "EVAL-ADICUP3029": "ADuCM3029", "iMXRT1052 Developers Kit": "MIMXRT1052", "FRDM-KV11Z": "MKV11Z128xxx7", "TWR-KV31F120M": "MKV31F512xxx12", "MCB1500": "LPC1549JBD100", "TWR-K80F150M": "MK80FN256xxx15", "TWR-KW21D256": "MKW21D256xxx5", "STM32L476G-EVAL": "STM32L476ZG", "NuTiny-SDK-NUC029AN": "NUC029TAN", "STM32F051-Discovery": "STM32F051R8", "NUCLEO-L053R8": "STM32L053R8", "FRDM-K64F": "MK64FN1M0xxx12", "MCBSTM32E": "STM32F103ZG", "TLE9869 EvalKit": "TLE9869QXA20", "NuTiny-SDK-NUC240": "NUC240VE3AE", "DK-TM4C129x": "TM4C129XNCZAD", "S32K144-EVB": "S32K144UAT0xxxx", "LPCXpresso824-MAX": "LPC824M201JHI33", "SAMD20-XPRO": "ATSAMD20J18", "TWR-KL28Z72M": "MKL28Z512xxx7", "SN32F770 Starter Kit Rev1_0": "SN32F70*B", "SAM4E-EK": "SAM4E16C", "MCB1343": "LPC1343FBD48", "LinkIt 7687 development board": "MT7687F", "XMC4500 CPU Board - General Purpose (CPU_45B)": "XMC4500-E144x1024", "LPCXpresso51U68": "LPC51U68", "LPCXpresso54018": "LPC54018", "ADuCM4050 EZ-KIT": "ADuCM4050", "LPCXpresso54618": "LPC54618J512", "NuTiny-SDK-M0518": "M0518SD2AE", "SAM3U-EK": "ATSAM3U4E", "SAMG55-XPRO": "ATSAMG55J19", "ADuCM3029 EZ-KIT": "ADuCM3029", "EVK-MIMXRT1020": "MIMXRT1021xxxxx", "FRDM-KV31F": "MKV31F512xxx12", "NuTiny-SDK-NUC200": "NUC220VE3AN", "NuTiny-SDK-NUC126": "NUC126VG4AE", "XMC1300 Boot Kit": "XMC1302-T038x0200", "Bulb Board": "S6E1A12B0A", "MAX32620_EVKIT": "MAX32620", "NuTiny-SDK-NUC2201": "NUC2201LE3AE", "MCBTMPM395": "TMPM395FWAXBG", "SN32F707B Starter Kit Rev1_0": "SN32F70*B", "BMSKTOPASM369": "TMPM369FDFG", "uVision Simulator": "ARMCM0", "NuTiny-SDK-NANO100AN": "NANO100VD3AN", "TWR-K60D100M": "MK60DN512xxx10", "TWR-K20D72M": "MK20DX256xxx7", "EV-COG-AD3029LZ": "ADuCM3029", "V2M-MPS3-SSE-200": "SSE-200-MPS3", "nRF51 PCA10031": "nRF51422_xxAC", "XMC4700 Relax Kit": "XMC4700-F144x2048", "SK-FM3-176PMC-ETHERNET": "MB9BFD18T", "LPC4088-32 Developers Kit": "LPC4088FET208", "FRDM-KW36": "MKW36A512xxx4", "FRDM-K66F": "MK66FN2M0xxx18", "XMC4500 Relax Lite Kit": "XMC4500-F100x1024", "TWR-K81F150M": "MK81FN256xxx15", "iMX6-SoloX-COM": "MCIMX6X4", "SAME70-XPLD": "ATSAME70Q21", "LPCXpresso11U68": "LPC11U68JBD100", "XMC4400 CPU Board - General Purpose  (CPU_44A)": "XMC4400-F100x512", "HVP-KV11Z75M": "MKV11Z128xxx7", "NUCLEO-F103RB": "STM32F103RB", "SAMC21N-XPRO": "ATSAMC21N18A", "FRDM-KE02Z40M": "MKE02Z64xxx4", "EFM32ZG-STK3200": "EFM32ZG222F32", "MCB9B500": "MB9BF506R", "V2M-MPS2": "CMSDK_CM7", "Arduino-Quattro": "ATSAMG55J19", "ADSP-CM419F EZ-BOARD": "ADSP-CM419F", "XMC4300 Relax Kit": "XMC4300-F100x256", "TWR-KL82Z72M": "MKL82Z128xxx7", "SN32F100 Starter Kit": "SN32F10*", "NuTiny-SDK-M0519": "M0519VE3AE", "TWR-K64F120M": "MK64FN1M0xxx12", "MCB4300": "LPC4350", "iMX7-Meerkat-96Boards": "MCIMX7D7", "XMC4200 CPU Board - Actuator  (CPU_42A)": "XMC4200-F64x256", "NuTiny-SDK-M451": "M453VG6AE", "STM32F746G-Discovery": "STM32F746NGHx"}
\ No newline at end of file
--- a/arm_pack_manager/index.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/arm_pack_manager/index.json	Tue Sep 25 13:43:09 2018 -0500
@@ -1,1 +1,1 @@
-{"S6E2H16E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H16G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKE16F512xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKE16F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1290NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC029LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC120LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMA5D26": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D26.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D27": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D27.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D24": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D24.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2H16F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMA5D22": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D22.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D23": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D23.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F417IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMA5D21": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D21.svd", "processor": {"fpu": "DP_FPU"}}, "MB9BF317S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG390F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG390F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF317T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MK24FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK24F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "AMAPH1KK-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F423RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MK60DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "N572P072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF106R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF415N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF106N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F722RC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC21J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4300-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4300_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4300c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4300_series/Include/XMC4300.h", "define": "XMC4300_F100x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x0FFC0"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4300.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "AC30M1364": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG230F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG230F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F109F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM383FWEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F411RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LM3S6422": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6422.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S6420": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6420.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC100RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S600": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s600.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD09C13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD09_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD09\\ATSAMD09C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK22FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM066FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M066.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F412VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO100ND2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "XMC1201-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini57EDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F105RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF328S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF328T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK26FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK26F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11U24FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TLE9879QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MKV11Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV11Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M452LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L451CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK02FN64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK02F12810.h", "define": "MK02FN64xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK02F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC1301-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKS20FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKS20F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF529T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "Z32F06410AES": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF166R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF529S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "GD32F150G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG232F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG232F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK63FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK63F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC230VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F150G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMA5D28": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D28.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F071RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LPC11U35FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMv8MML_DSP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL46Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL46Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M4TKRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32LG295F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG295F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC18S50": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "TLE9844QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xF000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAML21E18B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21E18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF128S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM395FWAXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM395_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BF128T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK22DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S308": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s308.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "nRF51422_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "ATSAM3A8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3A8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "nRF51422_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F722IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F722IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TM4C1237H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM061FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M061.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F756NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32HG220F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1202-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK52DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK52D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG220F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7661BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ARMSC000": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMSC000/Include/ARMSC000.h", "define": "ARMSC000"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC000.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM462F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK82FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK82F25615.h", "define": "MK82FN256xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK82F25615.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MKE04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": "0x400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE04Z1284.h", "define": "MKE04Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKE04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129DNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32L475RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F766J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "S6E2CC8J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TM4C1230C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1230C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F121E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F121E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32L031C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5G36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F410CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAML22G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1292NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ISD9160": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "EZR32WG230F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L486VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32WG230F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK22F25612.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1102LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1115JET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV30F64xxx10": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV30F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK20DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F302CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F446ZC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG990F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG990F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKE14Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE14Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKE16F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE16F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F303VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F777BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG295F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG295F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1236D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1236D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32WG230F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1102UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG330F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG330F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL05Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM376FDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MAX71617": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71616": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "NANO120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32TG230F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG230F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1100-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AFB42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Z32F06423EKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TLE9873QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9873.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100AFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0xAFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM342FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM342_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00009000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM380FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TLE9845QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9845.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xB000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG942F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG942F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK64FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO130SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9BF429S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "GD32F407IE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TLE9867QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "M452VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM4F122H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC200SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32LG330F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG330F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1778": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F122H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F411RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1774": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1777": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1776": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F411CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L100R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC240SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2C29H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG390F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG390F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5752": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5752.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M4TKVG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NM1120XB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "Mini54ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "MT2523x": {"core": "Cortex-M4", "vendor": "MediaTek:129", "algorithm": {"tools/keil/mt2523/2523_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x04008000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.5.0.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt2523/Include/mt2523.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x00400000"}, "IRAM2": {"start": "0x04008000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00400000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "208000000"}}, "S6E2DH5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC11A12FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "ATSAMD21G16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F378VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1J14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1J14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM4F111E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F111E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J14B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1J14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TMPM373FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M373.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M058LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F469BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1346FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2412": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2412.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "MK30DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ARMv8MML_DSP_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM067FWQG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M067.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC220LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG822F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG822F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C129XNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129XNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMR21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F108F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C58J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S050": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "S6E2C3AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L486JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32G880F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G880F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G880F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F407VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX7D2": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D2_A7.svd", "processor": {"fpu": "SP_FPU"}}, "MCIMX7D5": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D5_A7.svd", "processor": {"fpu": "SP_FPU"}}, "MCIMX7D7": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D7_A7.svd", "processor": {"fpu": "SP_FPU"}}, "NANO112LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32LG895F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG895F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG990F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG990F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG980F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG980F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAME70J21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TLE9842QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9842.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x8000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC1317FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC131LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F479AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC4088FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC130LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F100RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1120TB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAML22G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F479ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M452RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMA5D35": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D35.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAM3U1C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "TM4C1231H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D36": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F450VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S2911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F038C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG895F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG895F1024"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG895F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EZR32WG330F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11U12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F412RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M052ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F469ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC442KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EFM32G290F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G290F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G290F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1232D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1232D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "Mini55TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC844M201JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NM1200ZBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F423VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L433CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK22FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M052ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F190T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV71N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV71N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32LG990F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG990F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L432KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L432KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK11DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK11D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L051K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L081CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL28Z512xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_KL28.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MKL28Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF112R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM368FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C22FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKS22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKS22F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO102SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "NUC472VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "S6E2C38H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NM1120FC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "XMC1302-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4104-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF314R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMC20G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG942F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG942F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK50DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMD21E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAM4SD32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD32B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L443RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG900F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG900F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F706J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F112E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG942F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG942F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DH5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF105N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451MRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAMD09D14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD09_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD09\\ATSAMD09D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F150R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L476ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F228F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L476ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "GD32F150R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5D56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5791": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5791.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1937": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1937.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F121H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F121H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG890F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG890F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG980F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG980F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "TM4C123FH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123FH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F210E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F210E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC11E67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4315": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4317": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4310": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAM3S2C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM4F232H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4313": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAMD21J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2B93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2b93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S1968": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1968.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF528T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF528S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32G880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G880F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1823EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK22FN512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F51212.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151UC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M451MRD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L462VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF341L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF341M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF341N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF465K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1224FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LPC11E11FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC126VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MVF62NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF62NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF406R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F102CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF406N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1225FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S5P36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5P31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C18H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NANO120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EFM32G842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G842F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F413RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32JG12B500F512GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F512GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC120RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "S6E2C19L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAME54P19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKL02Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "Generic_NUC400_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TM4C1294KCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1294KCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1402-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F401RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32GG840F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG840F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFR32BG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F707BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4700-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9BN2": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2HE4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L431KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L431KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9BN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "Generic_NUC200_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F051T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1120EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMDA0E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MBL/Include/ARMv8MBL.h", "define": "ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "Mini52TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "XMC1301-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G200F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32G/EFM32G200F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO120SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "SN32F765J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51J19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKW21D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5P3B": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1768": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1769": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM366FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1763": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "Mini52FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F101C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1766": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1767": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG380F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG380F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1765": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S5747": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5747.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_CM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L475JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC220SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11U35FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F378CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF467M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1785": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1786": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1787": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U2C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x000020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x000004000"}, "IRAM2": {"start": "0x20080000", "size": "0x000004000"}, "IROM1": {"start": "0x00080000", "size": "0x000020000"}}, "debug": "SVD/SAM3U/ATSAM3U2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32L063R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1788": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC4200-Q48x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMHA1G14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00010000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.0.0.pack", "compile": {"header": "Device/SAMHA1/Include/samha1.h", "define": "__SAMHA1G16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000200"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SAMHA1/ATSAMHA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "N572F072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MCIMX7U5": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U5_A7.svd", "processor": {"fpu": "SP_FPU"}}, "NUC121ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MCIMX7U3": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U3_A7.svd", "processor": {"fpu": "SP_FPU"}}, "STM32L071RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F121C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F121C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG940F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG940F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F131H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F131H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM376FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32H743VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L471RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L471RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC240SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F091CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "LPC11U34FHN33/311": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC220LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9AFB41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F412CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32LG980F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG980F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123BE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM367FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG360F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG360F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L071V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG350F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG350F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F215VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S1F11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK65FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK65F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4LS8A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC812M101JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "M452VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F479ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF315R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9AF312K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG321F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG321F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11E14FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG12B500F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK20FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451MLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F778AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMC21J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini51LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC11A14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1G21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1g21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMR21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S37": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "S6E2D55GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L053C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S30": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1231H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32W108CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F756IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TM4C1231H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK10FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F413CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F207VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV71N21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMV71N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMV71N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV71N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ARMCM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM372FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG890F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG890F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F231E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F231E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM3N1C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9879QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM368FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F301C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK21DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK21DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F301C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "S6E1A11B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAM4LC8A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3748": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3748.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF321K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM037FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M037.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKL26Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2GK6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F437ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV42F128xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV42F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F437ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1517JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "NUC120LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2H14F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1403-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32TG110F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1237E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMC21E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6X4": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC1112FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6X1": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X3": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "S6E2D35GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32G232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G232F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1200TBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1401-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C5AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F103ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC20N18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20N/ATSAMC20N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF512R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S3634": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C123AE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123AE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L051T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2GM6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini51LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F103V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF512N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S1850": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1850.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG280F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG280F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20N17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20N/ATSAMC20N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4320": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4323": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4322": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4325": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F302CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1654": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1655": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1656": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO110SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EFM32GG940F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG940F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51422_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F1653": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5K31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD51J18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F777VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "Mini57TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG880F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG880F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ADSP-CM419F-BCZ_M4": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "0", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M4/CM41x_M4_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.pdsc", "memory": {"IROM2": {"start": "0x11001000", "size": "0x000FF000"}, "IRAM1": {"start": "0x10000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20010000", "size": "0x00018000"}, "IROM1": {"start": "0x11000000", "size": "0x00001000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S5G56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1404-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADSP-CM419F-BCZ_M0": {"core": "Cortex-M0", "vendor": "Analog Devices:1", "algorithm": {}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x200F0000", "size": "0x00008000"}}, "debug": "SVD/CM41x_M0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F446VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F227F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM367FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC200SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F245J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3A4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3A4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMD11C13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F229F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG895F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG895F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Z32F12811ARS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F417ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC4072FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11E36FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "NUC120RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG232F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG232F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C59H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F1251": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1252": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F1253": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x7C00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG225F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG225F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF465L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "Mini51TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAM4CMP32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMP32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F302C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32PG1B200F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1402-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5C31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C129LNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129LNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM462F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1301-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM370FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG395F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG395F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M485KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TLE9867QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F131E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F131E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO112VC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "NM1820EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C123GE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C29J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4LC2C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG895F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG895F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L433RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG880F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK40DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SKEAZN16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO110KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9AF311K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG840F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG840F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M451MRC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "Mini58LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L071C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M052LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M052LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M0519SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC131SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD10D13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL04Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G280F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F773S": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F773T": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G210F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G210F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G210F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MAX71637": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71636": {"core": "Cortex-M3", "vendor": "Maxim:23", "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "STM32F030CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG840F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG840F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM440_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "LM4F111B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F111B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD11D14AM": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE18F512xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKE18F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD11D14AS": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21N18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21N/ATSAMC21N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0519VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C1294NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A04UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAME51J18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C129CNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1403-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F122E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F122E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S9L71": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l71.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Z32F12811ATS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG380F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG380F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMS70J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC11U35FET48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "AC33MA384A": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33MA384A/Flashloader/AC33Mx384A_384.flm": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33MA384A\\Core\\include\\AC33Mx384A.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33MA384A\\SVD\\AC33Mx384A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "M0564LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32HG308F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG308F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1549JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M052ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L151RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3X4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC11E67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG890F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M481LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD21G18AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F732VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL16Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G230F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F078CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3826": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s3826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKE02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L471QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC43S20": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32LG980F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG980F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F405ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B95": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b95.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F405ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32G230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G230F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK21DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L051R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4108-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L051R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F048G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM33Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF114R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "PAC5250": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H46F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2D35J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG895F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG895F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG880F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG880F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM461_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L452VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG222F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAME70Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70Q21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L452VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9GN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9gn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1231C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1231C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG825F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG825F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F303R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M0516LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF312R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230RC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F469NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1224FBD64/121": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC4104-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1302-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F722ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMDA0J14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD64/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F746VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M451MSD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "GD32F130K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM365FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M365.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5G31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM0plus": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM0plus/Include/CMSDK_CM0plus.h", "define": "CMSDK_CM0plus"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0plus.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "GD32F130K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1510LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC54S616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F302R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L073VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F302R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C129DNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F246J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6Y1": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y0": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32L073VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F779NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F427IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF524K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF524L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF524M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF466N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMR21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5B91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5b91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DL13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "NM1820ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF466R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG995F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG995F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EZR32WG330F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK21FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG995F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG995F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG842F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG842F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "ATSAME53N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C123GH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF164K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F072C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123ZD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32GG232F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG232F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD10C13A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF116T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4SA16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SA16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG290F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG290F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F030K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF568M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC845M301JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MB9BF404R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C4AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF404N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4800-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9DN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11E12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2G36J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2G36H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKM14Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F758F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1958": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1958.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "M4LEDLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG842F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG842F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51802_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32L475ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKV10Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV10Z1287.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "DS_CM3": {"core": "Cortex-M3", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.1.0.0.pack", "compile": {"header": "Device/DS_CM3/Include/DS_CM3.h", "define": "DS_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.pdsc", "memory": {}, "debug": "SVD/DS_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF428T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LPC4330": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "SN32F774T": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F774S": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ARMv8MML_DSP_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051R4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F415OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F051R6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV46F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV46F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F358VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32G200F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G200F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1225FBD64/321": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S8738": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8738.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "nRF51824_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "MKV10Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV10Z1287.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "STM32F038K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S8733": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8733.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L152C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF366R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AFA44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M452LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32TG840F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG840F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4800-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "NANO100SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S8933": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8933.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NM1823ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S8930": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8930.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG232F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG232F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC123SD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TM4C129ENCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1345FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MCIMX7S5": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S5_A7.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F205VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG232F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG232F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MCIMX7S3": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S3_A7.svd", "processor": {"fpu": "SP_FPU"}}, "ATSAM3U4E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M052ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1112FHI33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM4050": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADuCM4x50.FLM": {"default": "1", "ramsize": null, "size": "0x7F000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.1.0.0.pack", "compile": {"header": "Include/ADuCM4050.h", "define": "__ADUCM4050__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x7F000"}}, "debug": "SVD/ADuCM4050.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "52000000"}}, "LPC54607J256BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EZR32HG220F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1100FBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32HG220F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1850": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F236J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32HG320F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM4": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EZR32HG220F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM0": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM0/Include/CMSDK_CM0.h", "define": "CMSDK_CM0"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TLE9861QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9861.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "CMSDK_CM3": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM3/Include/CMSDK_CM3.h", "define": "CMSDK_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF416T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "GD32F450IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32PG1B100F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F450IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M058LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F450II": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG900F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG900F256"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG900F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF121J": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B120J_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xJ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG290F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG290F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKV31F128xxx10": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV31F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NUC140RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1401-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK10FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF416R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM4F130C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F130C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3N00B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N00A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "S6E2G38H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2G38J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54S618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NM1820LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC4108-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5762": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5762.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKW41Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70J21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NANO100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "M481SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32ZG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG942F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG942F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG290F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG290F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK24FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK24F25612.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1225FBD48/321": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "ATSAME54N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKL15Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M2S005": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LPC11U34FBD48/311": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM374FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M374.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E1A12B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG230F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG230F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1403-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S57": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC43S50": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F429BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC140LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9AF141M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC4500-F144x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1202-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F413MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L485JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L485xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F413MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM3S1B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L443CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32WG330F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG330F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F303C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME51J19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EZR32WG330F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14F512xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKE14F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG390F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG390F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F091RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV71Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV71Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F102RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G890F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G890F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G890F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2276": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2276.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2678": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2678.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1233C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1233C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM475FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54S616J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "TLE9844-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844_2.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xF000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ADuCM320i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320i.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0516ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC1517JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32TG232F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG232F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F072RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F150C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33M6128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LPC1343FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2GK8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A12FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32JG1B200F256GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F150C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F415RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32LG895F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG895F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F071VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF565K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC120LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100NE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9AF344N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1120DC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "nRF51822_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F410T8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TLE9877QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF322L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF322M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ISD9360": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "M4TKLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKL46Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL46Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L062K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L062xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L062x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32HG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MKL24Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S3654": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U14FET48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S3651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M485SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "HT32F1251B": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF115R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME70Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F103T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5U91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5u91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F437VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "S6E2DH5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F101R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LM3S1651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F437VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A02UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54S608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC122ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "NUC131LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM384FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M384.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9AFA41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11C12FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C2AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MK53DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1104UK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F225J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L073CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011G3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114LVFHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NUC130RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32GG995F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG995F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9792": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9792.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG880F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM366FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4SP32A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4SP_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4SP/sam4sp.h", "define": "__SAM4SP32A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4SP/ATSAM4SP32A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG980F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG980F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK12DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK12D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F415ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9AF156R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1316FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK60FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11U14FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F247F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827YB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L162RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32HG310F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG310F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMR21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF467R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C123GH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9AF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM068FWXBG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M068.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Z32F06410AKS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM330FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "AC33M8128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32H753ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32WG360F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG360F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F768F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK80FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK82F25615.h", "define": "MK82FN256xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K80_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK80F25615.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NANO100SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TM4C1297NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1297NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F745IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "IOTKit_ARMv8MBL": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MBL/Include/IOTKit_ARMv8MBL.h", "define": "IOTKit_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC200SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK20DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC824M201JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG12P431F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO100SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "M451YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F777ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM343FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM343_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S815": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s815.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L475VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMG51N18": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51N18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3N26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s3n26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG890F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG890F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG942F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG942F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129CNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32L151RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF405R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F107RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M4TKVE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L082KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F107RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF156N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SKEAZN32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "SN32F759F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF405N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L082KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1115FET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F358CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFA31N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM362F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M362.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG842F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG842F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG280F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG280F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM4S16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMG54J19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "NUC472HG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EFR32BG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32HG220F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF429T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "M052LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F378RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L152R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M481SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC100LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKV58F1M0xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x2F000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00100000"}}, "debug": "SVD/MKV58F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "HT32F52220": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "AC33GA256": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33GA256/Flashloader/AC33GA256_CDFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33GA256\\Core\\include\\AC33GA256.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33GA256\\SVD\\AC33GA256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32JG12B500F1024IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11A11FHN33/001": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1435": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005C00"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1435.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TMPM341FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM341_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "S6E2C2AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG360F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG360F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL33Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL33Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG350F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG350F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini54TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "TM4C123AH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123AH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C39H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NM1320LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1320_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1320_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1320_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NM1320AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO103SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1202-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4800-E196x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM364F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M364.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ARMCM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC812M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F413RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F038G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC120VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK20DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C3AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L053R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1549JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M0564RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F450ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F091CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450ZI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F405OE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MKL43Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00010000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.0.0.pack", "compile": {"header": "Device/SAMHA1/Include/samha1.h", "define": "__SAMHA1G16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMHA1/ATSAMHA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG222F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F450ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S010": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "XMC1302-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "nRF51801_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "NUC240VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L475QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK70FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG295F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG295F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G26J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L072RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF321M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF321L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM4F110C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F110C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L475QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK20DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO120LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MKE02Z64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1236H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1236H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1112FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F767VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1112FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F301R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC824M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F301R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L072RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME51N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF116S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC54101J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E1A12C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32MG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG332F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG332F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32L152RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "NUC240SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC54114J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG295F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG295F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM333FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32LG330F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF218S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF218T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H743BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MB9AF131N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F423CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NUC126LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG825F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG825F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE02Z32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L152R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M0519LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F706BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG995F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG995F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1232C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1232C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MVF50NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMC20J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D55GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3X4E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC4078FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M0518LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F031K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32HG108F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG108F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ARMCM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "NANO112SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "AC30M1332": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S2A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "NANO120KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TMPM37AFSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M37A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF118S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF118T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC4078FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F058C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F746VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F031E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6633": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6633.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32GG380F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG380F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF121M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKE18F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE18F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG990F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG990F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C38L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG995F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG995F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F170R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF141N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F469NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF141L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3S1A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC54606J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAM3S1C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKL26Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "N572F065": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\N572F065_v3.svd", "processor": {"clock": "48000000"}}, "LPC844M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "S6E2H44F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F105V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4A6ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H44E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54113J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MT7687F": {"core": "Cortex-M4", "vendor": "MediaTek:129", "algorithm": {"tools/keil/mt7687/7687_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.5.0.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt7687/Include/mt7687.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x00100000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00200000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "192000000"}}, "MKW35Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO103LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG395F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG395F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1200LBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11E36FHN33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO120KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32L031F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "BlueNRG-1": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STBlueNRG1.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x28000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.1.1.1.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x28000"}}, "debug": "SVD/BlueNRG1.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MCIMX7D3": {"core": "Cortex-A7", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.6.1.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D3_A7.svd", "processor": {"fpu": "SP_FPU"}}, "NANO120SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9BF564L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9BF564K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9AFA31M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF156M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "R-IN32M3-EC": {"core": "Cortex-M3", "vendor": "Renesas:117", "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_EC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "AC33M4064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C123BH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F398VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4800-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKL14Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B200F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC122LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "STM32H753II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TM4C1299KCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1299KCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F756J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF312L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO130SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "HT32F1755": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini54XFHC": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKW20Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW20Z4.h", "define": "MKW20Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW20Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L052T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1224FBD48/121": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TM4C1233E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4350": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F767BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4353": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO102LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "LPC4357": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32LG940F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG940F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKV42F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV42F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC54101J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4502-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1100FAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM343F10XBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM343_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV42F64xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV42F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MKM14Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54616J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F423MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKL34Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL34Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6G1": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G0": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G3": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC4327": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF366K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC505YLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "S6E2C58L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKS20FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKS20F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F120H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F120H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1138": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1138.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK60FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK60FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "EZR32LG230F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1133": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1133.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "APOLLO512-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32G842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G842F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK50DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F030F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMCM23": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "QN9083A": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "QN9083C": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAMC20G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG842F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG842F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKV56F512xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00080000"}}, "debug": "SVD/MKV56F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "NANO120LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "LM4F211E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F211E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U35FHI33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F745VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32JG1B200F128GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F217ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2533": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2533.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F733IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32LG395F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG395F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL26Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F110E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F110E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L471VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "LM3S1R21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21J16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG942F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG942F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK28FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x1FFC0000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK28F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "LPC11U34FBD48/421": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MCIMX6Y2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32BG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG322F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG322F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M452LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32ZG210F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC220VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1100-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC4402-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini51FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAMC20E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G232F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1F16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4402-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C4AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMG51G18": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51G18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L083VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G280F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G280F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G280F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F231H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F231H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM073FSDUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M073.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32ZG210F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32HG308F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG308F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG940F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG940F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "AU9110LF3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/AU9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}, "Flash/AU9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/AU9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM4LS4A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4LS4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS4B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1547JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "STM32F469AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L083VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG230F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG230F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "NANO103ZD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1225FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TMPM332FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G230F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54607J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "MKL24Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L152C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083B": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "Mini58ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG390F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG390F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF421L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C1299NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1299NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M453VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4N8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM4N8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L162QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG12B500F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1313FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11A14FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG840F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG840F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54S606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC4500-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1764": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2D55J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S8938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F207ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "PAC5220": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D31": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "NUC029FAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC029_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC029AE\\Include\\NUC029FAE.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NUC029AE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "PAC5223": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120EC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1202-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKV10Z16xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P16_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MKW21Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32G280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G280F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9AF131M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF131L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F427VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3U1E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1313FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF131K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BFD17S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "XMC1404-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S800": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4078FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BFD17T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO102LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MKW22D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC4A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF567R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4LC4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK64FN1M0VLL12": {"core": "Cortex-M4", "vendor": "Freescale:78", "algorithm": {"addon_cmsis/Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.2.2.0.pack", "compile": {"header": "platform/devices/fsl_device_registers.h", "define": "CPU_MK64FN1M0VLL12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "platform\\devices\\MK64F12\\MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F446MC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC4078FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M4LEDRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKL25Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC43S70": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF567N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF567M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NM1330LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKM33Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "M058SZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "M482LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F215ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "M484SIDAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11U23FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG995F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG995F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F215ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FDH20/002": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G290F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA0G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FBD48/01": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L452CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF117S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M453YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L152C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM4F110H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F110H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114FHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK22FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9D90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF617S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF617T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H753XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMC20J17AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1301-Q040x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini57FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC11U37FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F101T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32WG895F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG895F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VE3DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAME53J20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NUC100VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L431VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG309F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG309F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F070F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M451VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L031E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM13Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM13Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG280F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG280F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "QN9080A": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "QN9080C": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9080B": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54102J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U13FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKL43Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1512": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF518T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11U36FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF155N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF518S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32GG895F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG895F1024"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG895F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L031K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM34Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "MKV58F512xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00080000"}}, "debug": "SVD/MKV58F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S6952": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6952.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4CP16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF155R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMG55G19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL27Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL27Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMR21E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF521M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6V7": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32GG880F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG880F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6V2": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "M453LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF521K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF142N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM072FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M072.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1520RD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC4367": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "ARMCM33_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32WG330F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG330F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM372FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC8H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1R26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG330F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG330F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL36Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G222F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U35FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFB44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E1A11C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1112FHN24/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1751": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1114FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCM33": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ADuCM361": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD\\ADuCM361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "MKL17Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL17Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG990F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG990F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F212E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F212E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM390FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM39x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG290F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG290F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG280F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG280F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "N571P032": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/N571E000.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\N571P032_v3.svd", "processor": {"clock": "23000000"}}, "TMPM367FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "M483SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L152QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5956": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5956.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F757F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MVF51NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NN151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S5951": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5951.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF315M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G890F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MCIMX6Y7": {"core": "Cortex-A9", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.4.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "XMC1404-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC125ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM4E8E": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG230F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK02FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK02F12810.h", "define": "MK02FN64xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K00_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK02F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F112C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F112C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U24FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF124M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMCA9": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCA9/Include/ARMCA9.h", "define": "ARMCA9"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32TG842F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG842F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG332F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG332F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG1B200F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F102C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME53J19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32GG900F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG900F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini55LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M481LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1201-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F415VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "Z32F06423AKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF305N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TM4C1230H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1230H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK20DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC822M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NUC130VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S5737": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5737.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV31F512xxx12": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKV31F51212.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4N16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1111FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG840F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG840F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG230F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG230F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK66F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123ZC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM4F122C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F122C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMCA7": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCA7/Include/ARMCA7.h", "define": "ARMCA7"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM361F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MVF50NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LPC11U34FHN33/421": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKE15Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE15Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "S6E2C18J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1115JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9843QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9843.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xB000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EFM32ZG222F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F413VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAML21J17B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG230F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S9B92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF116M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC220LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO110RE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MK12DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK12D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F779AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F756BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E14FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F098CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM36BFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "PAC5210": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC126RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFR32MG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MKW24D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW24D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV71Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMV71Q21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMV71Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EZR32WG230F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF616S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK70FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF616T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "nRF52832_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32WG230F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG230F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF618T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC120RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L452RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1342FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF618S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME51N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC11E68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG995F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG995F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32JG1B100F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M452RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4E16E": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAM4E16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1547JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G800F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G800F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G800F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S67": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1232H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1232H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F105RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9AF154M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF154N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO102ZB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "ATSAM4S4B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S4A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "TM4C129ENCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG110F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG110F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "AC30M1464": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1530VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L081KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F031G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF154R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11C14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6ZXR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZXR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C32E": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32E_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4C32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW40Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW40Z4.h", "define": "MKW40Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW40Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L021D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "version": "0.1.0", "STM32L073RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG980F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG980F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BFD18S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1114FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG295F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG295F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD18T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL33Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL33Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110RD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAMD20J14": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J15": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD16T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S2D93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s2d93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F131C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F131C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1332": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini51XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BFD16S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMD20J17": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK11DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK11D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21J16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1520RC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD21J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF506N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF506R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E17B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21J18AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MB9BF566L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG230F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG230F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MKE04Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE04Z1284.h", "define": "MKE04Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE04Z1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L476RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ARMCM0P": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus.h", "define": "ARMCM0P"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MB9BF329T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F429NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4C4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C49J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1751": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1751.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK60DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF314M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK11DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK11DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4504-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L431CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG390F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG390F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4337": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32L151CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF428S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "XMC1404-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11A13FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F232E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M452LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L475ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "Mini54XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F239F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4370": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32TG210F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM320": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L041K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO130KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9BF105R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF568R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1100-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1233H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F268F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1112LVFHI33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF568N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F358RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F217VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MKL13Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL13Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMSC300": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMSC300/Include/ARMSC300.h", "define": "ARMSC300"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F765BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "M451RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TMPM380FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC4076FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1404-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA1G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C129EKCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129EKCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L486QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469AE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC442JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TMPM367FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L011K3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC100LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L011K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1439": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1439.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DF5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MK20FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L011D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG940F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG940F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00010000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.0.0.pack", "compile": {"header": "Device/SAMHA1/Include/samha1.h", "define": "__SAMHA1G16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMHA1/ATSAMHA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51822_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F412ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32WG230F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKL82Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL82Z7.h", "define": "MKL82Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFA000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL82Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S10": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32PG1B200F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F205RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1810": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "NUC505DS13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "LPC1812": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1813": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1815": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1817": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L162RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L475VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD10D14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2U93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s2u93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NM1120TC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM036FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M036.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NM1520LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAML22J18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1231D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4088FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F707F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F439NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F439NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC20J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC130LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM4F121B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F121B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F111C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F111C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NM1120XC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC029TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "Mini54FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC1124JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x08000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C5AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK53DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L471JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MVF50NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S9C97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9c97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F098RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM440_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "STM32F767NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO110RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TMPM462F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC4504-F144x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3S8B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F101VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM074FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M074.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1302-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK20DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Mini58TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F101VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EZR32WG230F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG360F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG360F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32LG280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF368R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF368M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF368N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M2S025": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "Mini57XDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32TG840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF304N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ADuCM3027": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.2.0.0.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "ATSAMC21N17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21N/ATSAMC21N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC240LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32GG390F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG390F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M4TKRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM3S1635": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1635.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM3029": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.2.0.0.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "STM32F100VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MKW21Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F130H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F130H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "SN32F7651BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F439BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "Mini54TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LM3S8730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F110B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F110B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9G97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9g97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C123BH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D34": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D34.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32ZG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC130RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO130KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "S6E2C5AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1201-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG330F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG330F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini51TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "EFM32ZG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F373C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG330F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG330F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GM8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAML21E16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "MB9BF505R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "nRF52832_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3X8E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "STM32L433VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4CMS8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9877QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD20J18": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF115M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMC20G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMD20J16": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "Mini55ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F072V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL04Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M058SSAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F413VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M487SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF168N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF168M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F405VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF168R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAME70N21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32HG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F407VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "TMPM475FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EZR32WG230F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4N8A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG332F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG332F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32H753VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EZR32WG230F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM383FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F301K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1960": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1960.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F301K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F769BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF412R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMA5D33": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D33.svd", "processor": {"fpu": "DP_FPU"}}, "NUC123ZC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "XMC4200-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG110F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF412N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAML22N18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL16Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F769BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9AFA32L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F423ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW01Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW01Z4.h", "define": "MKW01Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKW01Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F120B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F120B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M484SGAAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S817": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s817.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "M453VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "HT32F1765": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC812M101JTB16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L151R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM366FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF122K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3S4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S4B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S4A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3N1B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMG54G19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F334C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF144M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF144L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F107VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334C4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5K36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG890F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG890F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L462CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO100NC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S1N11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "R-IN32M4-CL2": {"core": "Cortex-M4", "vendor": "Renesas:117", "algorithm": {"Flash/R-IN32M4_MX25L6433F.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M4_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.1.0.1.pack", "compile": {"header": "Device/Include/RIN32M4.h", "define": "RIN32M4_CL2"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M4_CL2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F429NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC240LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F302K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M058LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2C39L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S301": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s301.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S300": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s300.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F439AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG320F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2HE4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKV44F128xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV44F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "TM4C1236E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1236E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1316FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FBD48/323": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NM1120ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMD51N20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M452VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC123ZD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MK60DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC505DSA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "MKM38Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM38Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472HI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TMPM369FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKV30F128xxx10": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV30F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4800-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG395F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG395F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4312": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NUC505YO13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "MKM33Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1825": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F755J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54628J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54628.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LPC1820": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1823": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1822": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F205VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK51DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9781": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9781.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL16Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1B21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1b21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S617": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s617.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F212H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1100-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32HG322F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG322F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F132C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F132C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC121SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAM3U4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF367M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF367N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F411CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NUC123LD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32G840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G840F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L041F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F042G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LPC1857": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO112SB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "ARMCM4": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM7": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM0": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM0/Include/ARMCM0.h", "define": "ARMCM0"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM3": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM3/Include/ARMCM3.h", "define": "ARMCM3"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC1853": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32G840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G840F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1N16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F723VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "CMSDK_CM7": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L151R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF505N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG380F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG380F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2CCAH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L071KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "S6E2GH8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ADSP-CM419F": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.1.2.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x11080000", "size": "0x00080000"}, "IRAM1": {"start": "0x200F0000", "size": "0x00008000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x11000000", "size": "0x00080000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L071KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC18S57": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKL36Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EZR32LG230F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6537": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6537.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9997": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9997.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32LG230F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746NE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S2110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF114L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L072VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NANO100KC3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAM3N1A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1E14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F103C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL26Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F211H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F211H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG840F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKV11Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV11Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G890F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L083CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM4F230E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F230E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54101J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L083CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F769F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "XMC1402-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54113J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F373RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F101V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC54618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "S6E2DH5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1125JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL27Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL27Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C18L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1626": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1626.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG222F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF144N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC200LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F479VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L072V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFR32FG12P231F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMG55J19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9D96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC20J18AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B100F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "NUC472JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "MK22FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C1231E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC131SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC4104-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21E15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2D35GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MVF50NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F130C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "GD32F130C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53G19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E13FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG108F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F190R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3Z26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s3z26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F190R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD51G18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51G18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "GD32F450VI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG108F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3N0B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF522M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3N0A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF522K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TLE9867QXW20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L4A6VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "M451SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "EFM32WG230F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG230F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF132L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32HG309F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG309F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF132K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL13Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL13Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG110F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M0519SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC4400-F64x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4500-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC442RI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "M0564RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF504R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM470FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F405RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F768AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M0564VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF504N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MKV46F128xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKV46F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NUC120VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F405RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2C38J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F405RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG900F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG900F256"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG900F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L451VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1301-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32HG310F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG310F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S5R36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F777II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC20E18A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF316M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL05Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53N19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "M052LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32GG395F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG395F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F765VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL17Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL17Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG940F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG940F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32G222F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G222F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1232E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1232E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD51J20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM4F120E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F120E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32PG12B500F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F302ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC4074FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F235J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1403-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S310": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s310.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK20DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S316": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s316.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S317": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s317.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11E37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S315": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s315.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK22DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF415R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMDA1G14B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1G14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "NM1827UB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMDA1G14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG842F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG842F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1114FBD48/333": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F207IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "M452SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32L011E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM341FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM341_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "NUC121LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TLE9842-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9842_2.FLM": {"default": "1", "ramsize": null, "size": "0xA000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x9000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1226FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "EFM32TG822F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG822F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2HE4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD21E16BU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG842F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG842F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F030C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1833": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1830": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF316R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1837": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11D14FBD100/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11D14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC18S30": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW36Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM461_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S37": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MK51DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK11DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK11DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "XMC1402-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L100RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL14Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF117T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F437IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "nRF52840_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\nrf52840.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F745ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1200-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32JG12B500F1024GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "AMAPH1KK-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F446ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32LG940F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG940F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW41Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F412VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO110SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F410R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4700-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM370FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L041G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442RG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "NANO102ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "LM3S818": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s818.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F101ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "ATSAMG54N19": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F042F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MM32x031": {"core": "Cortex-M0", "vendor": "MindMotion:132", "algorithm": {"Flash/MM32x031_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.1.0.0.pack", "compile": {"header": "Device/Include/MM32x031.h", "define": "MM32x031"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/MM32x031.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F405OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32BG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S2671": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2671.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1315FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC4333": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F429ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M451MSC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M0519LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L083RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK11DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK11DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC120VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MK65FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK65F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Generic_Mini51_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F042T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042T4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1342FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKM32Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM32Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L083RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NANO112RB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "TMPM46BF10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM46B_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}, "IRAM2": {"start": "0x20080000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M46B.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F479BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S5Y36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s5y36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9790": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9790.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMS70Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L052C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F411VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM470FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L021G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1302-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L052C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC11U14FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1317FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKM33Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1202-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M483KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S828": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s828.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G880F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME53N19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "HT32F52352": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FE00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF366N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF500N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF366L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF366M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG330F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG330F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MVF60NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF306N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F107F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F766BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC832M101FDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F078VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF306R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4_FP.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S1C26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4700-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L051C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK60FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "XMC4500-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9879QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F101T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9AF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L476MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1112JHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9BN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE06Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE06Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE06Z4.h", "define": "MKE06Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE06Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "MB9BF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NM1120DB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM462F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S5D91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "EFM32LG360F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG360F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F417VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "M4LEDLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "AC30M1432": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.0.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C48H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD21E17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1827": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.7.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF324L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1100-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG1B100F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF324K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC220SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG890F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG890F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1230E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1230E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2DF5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4CMS32C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMS32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMDA1E15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1E15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAME53J18A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME53_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME53J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32LG390F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG390F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG12B500F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2H44G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1202-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M487JIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32JG12B500F1024IL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG390F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG390F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LPC54113J128BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKW36A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114LVFHN24/103": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1100DBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1302-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M058SFAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1518JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LPC54605J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "Mini54LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32L431RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L431RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG332F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG332F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M058ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32JG1B200F256IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF414R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L451RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x1_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF414N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMS70Q19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "SN32F226J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F220_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F220"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x3FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TLE9877QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "M452YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M451MLC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC120LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "TMPM333FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1301-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL43Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL46Z4.h", "define": "MKL46Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM333FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG295F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG295F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1100XBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG942F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG942F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F030RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD51G19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51G19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKE15Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE15Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32HG321F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG321F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF124L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4A6AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF124K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF514N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF514R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4N16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SN32F767BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKV44F64xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKV44F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "M0564LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKL03Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL03Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKS22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MKS22F12.h", "define": "MKS22FN256xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KSxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKS22F12.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NM1200TAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NM1530VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L063C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKE14F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE18F16.h", "define": "MKE18F512xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKE14F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC123LD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TM4C123BH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F328C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "Mini58FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F745ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F212H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MK21DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK21DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG295F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG295F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK30DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S1165": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1165.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F030R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1162": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1162.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2HE6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO112RC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "SN32F768BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S9U92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G222F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G222F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G222F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MKL17Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL17Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5662": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5662.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L011D3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MVF61NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NN151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32L476QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L476QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML22J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA1G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F100ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMDA1G15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F429IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L052R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F401CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC811M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00002000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L162ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG225F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG225F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3S8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L052R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F777NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7652BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32H753BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32PG1B200F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4078FBD100": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3J26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3j26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3U2E": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U2E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F765II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S8630": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8630.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Generic_Nano100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "NUC505DLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "clock": "100000000"}}, "LPC1110FD20": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x1000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0400"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4CMS4C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F765IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7741J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52331": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71J19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV71J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "S6E2C39J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "SKEAZN64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1237D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ISD9130": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF365L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF365K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG880F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG880F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9871QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9871.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF155M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "Mini52ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "EFM32WG840F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG840F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M058SLAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S102": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s102.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S101": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "S6E2D55G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL27Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL27Z644.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M0516ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC54114J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK40DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x0008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC122SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "M453VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "NUC100LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2CC8L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4CMP16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "Mini51ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC1227FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "M451LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F401RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F207IC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5D51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F207IF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F401RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32WG395F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG395F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108HB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9869QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9869.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1302-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F439ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC220LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L152ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD21E16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM369FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF112L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC844M201JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM4CP16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16B_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M2S090": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LM3S812": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52342": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52341": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFE00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG980F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG980F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC140RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MVF60NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC1302-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NANO120LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "NUC120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M4TKLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "M054LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NM1520LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMV70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "MB9BF165K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMDA1E16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF165L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3H6FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.0.0.pack", "compile": {"header": "Device/Include/TMPM3H6.h", "define": "TMPM3H6FWFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1E16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C1237H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG108F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32WG360F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG360F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G17B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAML21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG990F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG990F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG990F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "R-IN32M3-CL": {"core": "Cortex-M3", "vendor": "Renesas:117", "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_CL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54101J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F031C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F12365": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451MLD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "S6E2CCAJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12366": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F52231": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52230": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x7C00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1Z16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s1z16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4S8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1226FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "NM1200LAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NANO100SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "STM32F413ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32JG1B200F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F417ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF521L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L152ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54S608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ARMCM33_DSP_FP_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F334R4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4100-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S8B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32PG12B500F512GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F512GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C59J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD51P20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32GG332F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG332F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00002000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL03Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32JG12B500F1024GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F512GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F070CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2939": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2939.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51P19A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M0516ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF515N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF515R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG330F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G842F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M482LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M451LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM3S5P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG380F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG380F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5632": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L443VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKL02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL02Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F150C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM411F20XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM41xA_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM41xB_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM411_unitB.h", "define": "TMPM411F20XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20008000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54102J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK20DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "TMPM330FDWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG395F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG395F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M483SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F746BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746BE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "S6E2GK8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4800-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L476VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L476VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD20E18": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E17": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4076FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD20E15": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E14": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "LM3S3W26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s3w26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF468M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF468N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAML21J18B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C29L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F733VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM330FYWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF565L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F469ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC810M021FN8": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x00001000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "Mini52XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC140RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32LG842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5T36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s5t36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC9H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TM4C1290NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKV10Z32xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P32_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV11Z7.h", "define": "MKV11Z128xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "STM32F756ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20010000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC122SC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "ATSAM3N2A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F237F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1621": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1621.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1150": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1150.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1625": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1625.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF417S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1315FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S8530": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8530.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF417T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S8538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG842F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG842F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M487KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "SN32F248F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKV44F256xxx16": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV46F16.h", "define": "MKV46F256xxx16"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV44F16.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L462RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x2_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF166L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L011G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U24FET48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32HG320F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF322K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1E14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1E14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F765ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M0516ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC4072FET80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32LG332F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG332F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0516LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F767ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F767ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "clock": "32000000"}}, "EFM32ZG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG380F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG380F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F105VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ISD9361": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9300_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9300_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9300_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "S6E2D55JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1D21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD20G17": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M482SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S1D26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ATSAMD20G16": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F212H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMV71J21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMV71J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMV71J20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV71/include/sam.h", "define": "__SAMV71Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV71J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F446RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1302-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML22N17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G840F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV56F1M0xxx24": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV58F24.h", "define": "MKV58F1M0xxx24"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x2F000000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00100000"}}, "debug": "SVD/MKV56F24.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "STM32F769II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "IOTKit_ARMv8MML": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MML/Include/IOTKit_ARMv8MML.h", "define": "IOTKit_ARMv8MML"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1J16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1J11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC122LC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "EFM32HG210F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG210F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S2616": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2616.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1823LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC812M101JD20": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F439BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32LG330F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4500-E144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG330F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL03Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL27Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL27Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21G16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M2S150": {"core": "Cortex-M3", "vendor": "Microsemi:112", "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.61.pack", "compile": {"header": "CMSIS\\m2sxxx.h"}, "pdsc_file": "http://www.actel-ip.com/cwps/CMSIS-Core/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "STM32L071VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9843-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/TLE9843_2.FLM": {"default": "1", "ramsize": null, "size": "0xD000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\TLE984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1101LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L051K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC126LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MKW35A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK11DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK11D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DH5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "NUC123LC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ATSAM4LS2C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F098VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C49L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32H743ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMDA0J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.0.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S328": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s328.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11U37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini51XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG230F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NUC472KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "EZR32LG230F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG380F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG380F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S801": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s801.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32ZG110F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S808": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s808.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F22366": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x3FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC11U14FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM360": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD\\ADuCM360.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F303K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F072R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F230H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F230H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1237E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF364K": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF364L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F215RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM369FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F723IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M452RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "nRF52810_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.14.1.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf52810.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "APOLLO256-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F723IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF114M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54S618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F469II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC120LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F150K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5P56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H14G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2H14E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F469IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKL33Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL33Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F469IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG232F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG232F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAMA5D44": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D44.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2C49H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D41": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D41.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D42": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D42.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D43": {"core": "Cortex-A5", "vendor": "Atmel:3", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.0.0.pack", "compile": {"define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D43.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32GG290F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG290F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M0516LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "HT32F52243": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52241": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L072KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705J": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11U24FHI33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4LC2B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC2A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC472VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "GD32F190C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "TM4C123BH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21E15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK64FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1114JHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G290F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130F4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EFM32LG942F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG942F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M481ZIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TMPM36BF10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040800"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S9971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG825F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG825F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF111K": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MK12DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK12D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "XMC1201-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AC33M3064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.1.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S2948": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2948.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9D81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F407ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO110RC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F407ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32WG330F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM470FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164L": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32W108C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F103R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1816": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1816.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MVF61NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NS151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F107VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM343FEXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM343_768.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC240LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMV70Q20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EZR32WG230F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32WG/Include/em_device.h", "define": "EZR32WG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG295F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG295F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32L041C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD10C14A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1549JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M054LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "TM4C129XKCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129XKCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF416S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1112FD20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF468R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AF342M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SN32F249F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F410TB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG108F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG330F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E16": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF416N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EZR32LG330F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG108F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32ZGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q466": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "algorithm": {"Flash/ML630Q466.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/ML630Q466.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q464": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "algorithm": {"Flash/ML630Q464.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/ML630Q464.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F051K8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F051K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4074FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F051K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1330LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1330_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF217T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF217S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC122ZC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "clock": "60000000"}}, "LM4F232H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MKW31Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S6965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000B800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF516N": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L151V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF516T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF516S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF516R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F103RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1518JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "XMC1201-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1548JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LM4F210H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F210H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-T038x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF418S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2C28L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM4F111H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F111H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M451VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF418T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S32K144": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"addon_cmsis/Flash/S32K144_P512_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.0.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K144HFT0VLLT"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "platform/devices/S32K144/S32K144.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "ATSAML22N16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.0.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22N16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "S6E2G26H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM4F112H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54605J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LM3S1637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Z32F38412ALS": {"core": "Cortex-M3", "vendor": "Zilog:89", "algorithm": {"Flash/Z32F3841.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F3841.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F3841.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK10DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F429VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini52TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "LPC1112LVFHN24/003": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG395F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG395F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG232F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG232F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL36Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108CZ": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32W108_192.FLM": {"default": "1", "ramsize": null, "size": "0x30000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x08000000", "size": "0x30000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1202-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Generic_NUC100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC845M301JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC84x.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC84x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFM32LG890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKMP256_2KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34Z7.h", "define": "MKM34Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKM34Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32WG280F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG280F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F779II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32PG1B200F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32HGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK21FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21FA12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L073CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG990F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG990F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG225F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG225F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL15Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG330F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG330F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK66F18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F413CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2C2AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC20J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AFA41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL25Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL25Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL28Z7.h", "define": "MKL28Z512xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1W16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s1w16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F733ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "GD32F170C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5656": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5656.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F238F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.3.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114LVFHN24/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "GD32F170C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F779BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1202-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2793": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2793.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1401-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "CMSDK_ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MBL/Include/CMSDK_ARMv8MBL.h", "define": "CMSDK_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F469VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C58H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "clock": "84000000"}}, "S6E2C3AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S628": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s628.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70N19": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "APOLLO512-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1201-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1403-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G200F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G200F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1752": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "APOLLO256-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1756": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1754": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L152RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011F3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1759": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1758": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.3.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L011F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F207VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ARMCM23_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LM3S5739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE06Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE06Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE06Z4.h", "define": "MKE06Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE06Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5732": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5732.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCA5": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCA5/Include/ARMCA5.h", "define": "ARMCA5"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M0518LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F078RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK22FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F132E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F132E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SKEAZN8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/SKEAZN84.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S8962": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8962.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4LEDRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "STM32F413ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO100KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "STM32F469AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F407VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F723ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "S6E2D35JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E37FBD48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5G51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J16B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J16A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM3S2730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S2739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK21DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21DA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF329S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F318K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1227FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S6618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M054ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "M054ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "NUC126RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF167R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F373V8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U36FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F2755": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM366FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2139": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2139.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "TM4C1230D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1230D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG330F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF167N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF167M": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S6100": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "S6E2GH6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2GH6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG108F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG108F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC834M101FHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM3X8H": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8H.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "MKL15Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DF5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "IOTKit_CM23": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_CM23/Include/IOTKit_CM23.h", "define": "IOTKit_CM23"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F101VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "ATSAM3X8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1292NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12345": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0xFC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M0516LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6753": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6753.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F373VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKL17Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL17Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FDH20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M054ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F407IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F52253": {"core": "Cortex-M3", "vendor": "Holtek:106", "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x1FC00", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.8.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F407IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x04", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC1115FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK22F12810.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG320F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF318S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF318T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL05Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG332F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SD16C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD16B": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "ATSAMD21E15BU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21E15BU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GH8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF216T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11C14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF216S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MK10DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK50DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MM32x103": {"core": "Cortex-M3", "vendor": "MindMotion:132", "algorithm": {"Flash/MM32x103_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MM32x103.h", "define": "MM32x103_MD"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/MM32x103.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF129S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1821FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "MB9BF129T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S2950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S613": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s613.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S612": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s612.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF517S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF517T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9D92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S615": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s615.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x10000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F479NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK27FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x1FFC0000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MK27F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "STM32F103VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "LM3S1627": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1627.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3SD8B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3SD8C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAMC21J17AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M451MRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "ARMCM33_DSP_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.1.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "S6E2CCAL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG332F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG332F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C1AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF316S": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKW21D256xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF316T": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9L97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL33Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL36Z4.h", "define": "MKL36Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL33Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1401-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF500R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M481ZGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.1.1.0.pack", "compile": {"header": "Device/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F128GM32"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722VC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1824FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32F722VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "GD32F405VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMS70Q21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TMPM475FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L052T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF305R": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "GD32F405VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC21J17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.3.0.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}, "Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.1.5.0.pack", "compile": {"header": "Device/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M482SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM4F120C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F120C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG290F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG290F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11E14FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1294NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5R31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C59L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S5C56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG980F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG980F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32G/Include/em_device.h", "define": "EFM32G232F128"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32Gxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK21FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG380F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32WG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.1.4.0.pack", "compile": {"header": "Device/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32WGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG380F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK21FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.5.2.pack", "compile": {"header": "Device/Include/MK28F15.h", "define": "MK28FN2M0xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4CMP8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM361FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC11U12FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV31F256xxx12": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKV31F51212.h", "define": "MKV31F512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKV31F25612.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L496QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G17AU": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE15Z7.h", "define": "MKE15Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE14Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1302-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2GK6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF467N": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3N4B": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x06000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3N/ATSAM3N4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4A": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123GH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1607": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1607.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK50DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FN28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MWPR1516xxx": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKPR1516_P16KB.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MWPR1516.h", "define": "MWPR1516xxx"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MWPR1516.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F302VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F769NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x200000", "ramstart": "0x20020000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1402-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M058ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1548JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.0.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "M453RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "clock": "72000000"}}, "MB9BF367R": {"core": "Cortex-M4", "vendor": "Spansion:100", "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD21G17A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33_FP": {"core": "ARMV8MBL", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.3.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC120RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32HG320F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4400-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54S606J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC54S618.h", "define": "LPC54S618"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54S606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32LG940F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG940F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G18": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "SVD/STM32L4x6_v1r1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK10DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK10DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.2.1.pack", "compile": {"header": "Device/Include/MK12D5.h", "define": "MK12DX256xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini51ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "ATSAMD20G15": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G14": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21E19A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.0.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E19A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21G15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF522L": {"core": "Cortex-M3", "vendor": "Spansion:100", "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1100-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "ATSAMD21G15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.2.0.pack", "compile": {"header": "Device\\SAMD21\\Include\\samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD21\\ATSAMD21G15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM375FSDMG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M375.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3N0C": {"core": "Cortex-M3", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.0.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1J15B": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J15A": {"core": "Cortex-M0+", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.0.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LPC11E66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG12B500F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.1.0.0.pack", "compile": {"header": "Device/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F512GM48"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F765NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x20020000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM4E8C": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.0.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1202-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG822F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG822F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L041C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE04Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKE04Z1284.h", "define": "MKE04Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKE04Z1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32HG320F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.1.1.0.pack", "compile": {"header": "Device/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini52XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ATSAMS70N21": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.0.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100ND3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "42000000"}}, "SN32F767F": {"core": "Cortex-M0", "vendor": "SONiX:110", "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.2.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F732ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F130E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F130E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1345FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM363F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M363.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S5651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F732IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5652": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5652.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "CMSDK_ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.6.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1404-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.6.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.1.0.0.pack", "compile": {"header": "Device/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F1024GL125"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG110F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.1.3.0.pack", "compile": {"header": "Device/EFM32TG/Include/em_device.h", "define": "EFM32TG110F4"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32TGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM369FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF51NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NS151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S8971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8970": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8970.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKW30Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW30Z4.h", "define": "MKW30Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW30Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120ZC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1317FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F205ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MKW31Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x10", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.7.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "NM1100XAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "EZR32LG230F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.1.2.0.pack", "compile": {"header": "Device/EZR32LG/Include/em_device.h", "define": "EZR32LG230F256R69"}, "pdsc_file": "http://www.keil.com/pack/Keil.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.1.0.1.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "LPC1113FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC822M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.5.0.pack", "compile": {"header": "Device/Include/LPC8xx.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC82x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F479NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x2000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x50000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F439VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG995F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32LG.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.1.5.0.pack", "compile": {"header": "Device/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32LGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG995F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LPC1343FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F439VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32GG280F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "algorithm": {"Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.2.4.0.pack", "compile": {"header": "Device/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "http://www.keil.com/pack/Keil.EFM32GGxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG280F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x0210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x08", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.11.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ISD9341": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "MKL16Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.13.0.pack", "compile": {"header": "Device/Include/MKL17Z4.h", "define": "MKL17Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "ISD9340": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "Generic_M051_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "STM32L083V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.1.6.0.pack", "compile": {"header": "Device/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123FE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123FE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F190RB": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "algorithm": {"Flash/GD32F1x0_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.0.2.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F732RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "algorithm": {"CMSIS/Flash/STM32F7x_512_TCM.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x80000", "ramstart": "0x20010000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S6938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini52ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "clock": "24000000"}}, "STM32F318C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "algorithm": {"Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.1.4.0.pack", "compile": {"header": "Device/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME54P20A": {"core": "Cortex-M4", "vendor": "Atmel:3", "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.0.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM3S1H11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1H16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMV70N20": {"core": "Cortex-M7", "vendor": "Atmel:3", "algorithm": {"flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.3.0.pack", "compile": {"header": "SAMV70/include/sam.h", "define": "__SAMV70N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMV70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC1347FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2410": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2410.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.1.0.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}}
\ No newline at end of file
+{"S6E2H16E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H16G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF166N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1290NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG11B120F128IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC029LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG13P733F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P733F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P733F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMA5D26": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D26.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D27": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D27.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D24": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D24.svd", "processor": {"fpu": "DP_FPU"}}, "S6E2H16F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H16X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMA5D22": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D22.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D23": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D23.svd", "processor": {"fpu": "DP_FPU"}}, "HT32F12345_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "IOTKit_CM33_FP_MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.1.0.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF317S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG390F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG390F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG290F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG290F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF317T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFR32BG14P632F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "AMAPH1KK-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 8192]], "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NANO130SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F423RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1237H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "N572P072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "TMPM3HNFYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF106R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F1655_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF415N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF106N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722RC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "HT32F1755_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F429ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4400-F64x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM383FSEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "AC30M1364": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG230F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG230F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F109F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG890F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG890F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LM3S2601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P133F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P133F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P133F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6422": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6422.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S6420": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6420.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S2965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG13P733F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P733F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P733F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MQ5xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ5DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ5.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "LM3S600": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s600.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK22FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F105R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK22FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM066FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M066.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F412VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B140F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NM1120ZC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "IOTKit_CM33_MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.1.0.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS3_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9BF328S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF328T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFR32BG1P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG942F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG942F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG13P632F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TLE9879QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MKV11Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV11Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKV11Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "HT32F52344_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D21": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D21.svd", "processor": {"fpu": "DP_FPU"}}, "STM32L451CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK02FN64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "arm/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK02FN64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MK02F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "XMC1301-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKS20FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS20FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS20F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B510F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF529T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "Z32F06410AES": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF166R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF529S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "HT32F50231_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "GD32F150G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC2201LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC2201\\Include\\NUC2201.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG232F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG232F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK63FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK63FN1M0VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK63F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC230VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TMPM3H6FUDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F150G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F2755_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMA5D28": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D28"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D28.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F071RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK24FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK24FN1M0VLQ12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK24F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F2755_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO130KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "SN32F707F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMv8MML_DSP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M2351SIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "TMPM3H4FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMHA1G14AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "samha1ab/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1ab/svd/ATSAMHA1G14AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG11B320F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M4TKRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32LG295F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG295F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9844QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285274112, 4096]], "algorithm": {"Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9844.FLM": {"default": "1", "ramsize": null, "size": "0xF000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE9844_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100F000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0x10000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM3H4FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG225F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG225F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF128S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM395FWAXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM395_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFR32BG1P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF128T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK22DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S308": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s308.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "nRF51422_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51422_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51422_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F50241": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "HC32F146J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32F146JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK60DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM061FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M061.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F52253_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG900F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG900F256"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG900F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG220F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52352_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1202-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK52DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK52D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG220F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F767II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7661BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L496RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMSC000": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMSC000/Include/ARMSC000.h", "define": "ARMSC000"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC000.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM462F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK82FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK82F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK82FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK82F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK82F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "MKE04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": "0x400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z8VWJ4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffff00", "size": "0x0400"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKE04Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P532F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P532F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P532F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C129DNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG330F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG390F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG390F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAML22N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F766J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MIMX8MQ7xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "M453YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2CC8J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52253": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKV56F1M0xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV56F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "SRAM_OC": {"start": "0x2f000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x100000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV56F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "TM4C1230C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1230C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F121E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F121E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32L031C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L031C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5G36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F410CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG1B232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5G31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1292NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ISD9160": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "EZR32WG230F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F267J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B200F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN256VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1102LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M0519VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52344_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4327": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F446ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F302CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F446ZC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1301-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1654": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MKE14Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM": {"start": "0x1fffe000", "size": "0x8000"}}, "debug": "MKE14Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MKE16F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE16F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE16F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F303VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F777BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5R31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG320F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1236D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1236D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B420F2048IL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG230F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1102UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG330F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG330F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL05Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM376FDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MAX71617": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71616": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "EFR32MG1P232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG230F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG230F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F1653": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFB42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Z32F06423EKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TLE9873QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 45056]], "algorithm": {"Flash/TLE9873.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100AFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0xAFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM3HNFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM380FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TLE9845QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285257728, 4096]], "algorithm": {"Flash/TLE9845.FLM": {"default": "1", "ramsize": null, "size": "0xB000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9845_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100B000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG942F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG942F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32HG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32FG13P231F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F407IE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG11B120F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9867QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B140F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11C12FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC200SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG220F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1778": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F122H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F411RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1774": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1777": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1776": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F411CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM3H3FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC240SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2C29H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52341_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG390F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG390F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5752": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5752.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F427II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M4TKVG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NM1120XB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Mini54ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMD21G16L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21G16L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52231_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MT2523x": {"core": "Cortex-M4", "vendor": "MediaTek:129", "sectors": [[134217728, 4096]], "algorithm": {"tools/keil/mt2523/2523_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x04008000", "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.6.1.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt2523/Include/mt2523.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x00400000"}, "IRAM2": {"start": "0x04008000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00400000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "208000000"}}, "STM32F410C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC11A12FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMD21G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F50241_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F378VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA1J14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1J14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFR32MG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMDA1J14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1J14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "XMC1402-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "M058LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F446RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32LG330F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2412": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2412.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EZR32LG330F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MML_DSP_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM067FWQG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M067.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32TG822F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG822F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C129XNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129XNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMR21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F108F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H3FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C58J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M2S050": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "S6E2C3AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG395F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG395F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32G880F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G880F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F407VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX7D2": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D2_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "MCIMX7D5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "EFM32TG11B320F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX7D7": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D7_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NANO112LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG895F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG895F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG990F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG990F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1201-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32WG980F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG980F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC472HI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "ATSAME70J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "TLE9842QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285245440, 4096]], "algorithm": {"Flash/TLE9842_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x11008000"}, "Flash/TLE9842.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0x9000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "EFM32GG11B840F1024GL192": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL192.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H4FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52243_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F479AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F407VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HC32L156K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L156KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4088FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC130LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F100RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1120TB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ADSP-CM419F-BCZ_M0": {"core": "Cortex-M0", "vendor": "Analog Devices:1", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x200F0000", "size": "0x00008000"}}, "debug": "SVD/CM41x_M0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "M453LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC1100-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F479ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32TG11B320F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HC32L156KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L156KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1101LVUK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D35": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D35.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMA5D34": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D34.svd", "processor": {"fpu": "DP_FPU"}}, "TM4C1231H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D36": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "GD32F450VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S2911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F038C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG895F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG895F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG895F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450VE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HC32L150KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32FG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B420F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B820F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F423CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC11U12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG11B340F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M052ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC126LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM384FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM38x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M384.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F469ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F479II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32GG11B110F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F479IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC442KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EFM32G290F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G290F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1232D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1232D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM4G8F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC844M201JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F767BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1200ZBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F423VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32G222F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMD09C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD09_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD09\\ATSAMD09C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4CMS16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F038K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M052ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG900F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG900F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMV71N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32LG990F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG990F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0519SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L432KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK11DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK11DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L081CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL28Z512xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512_KL28.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL28Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL28Z512VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL28Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fff8000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}}, "debug": "MKL28Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S2651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF112R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM368FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG13P732F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F1755_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11C22FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M453SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKS22FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS22FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS22F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32LG230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B520F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO102SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "HT32F52220_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B100F128IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F128IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC472VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "GD32F330K4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "GD32F330K6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "TMPM3H2FSDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMV70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "XMC1302-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL36Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4104-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF314R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L152C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG942F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG942F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG295F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG295F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21E18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC802M011JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "STM32L152V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAM4SD32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD32B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4SD32B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L443RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L100C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F217IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F706J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG14P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P632F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F112E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F112E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK26FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK26F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK26FN2M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK26F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK26F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F52241_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1765_48QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2DH5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC811M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00002000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/LPC811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFM32LG840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF105N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M451MRD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG1P131F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD09D14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD09_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMD09\\Include\\samd09.h", "define": "__SAMD09D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD09_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD09\\ATSAMD09D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM367FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F150R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F150R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1313FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L476ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG13P632F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F150R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM4S4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5D56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F52220_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF464K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4S4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F121H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F121H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF464L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG890F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG890F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG980F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG980F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G6FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG1P131F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F210E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F210E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F22366_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "XMC1202-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C1AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B820F2048IL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC8N04FHI24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8N04_30.FLM": {"default": "1", "ramsize": null, "size": "0x00007800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC8N04.h", "define": "LPC8N04FHI24"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00007800"}}, "debug": "SVD/LPC8N04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "8000000"}}, "LPC1114FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151C6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F232H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4317": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4310": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC1114FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4313": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "ATSAMD21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21J18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52341": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2B93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2b93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MIMX8MD6xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MB9BF528T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF528S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF52xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "NUC123ZD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32G880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NM1823EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1P132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L151UC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC140VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F50230_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L462VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1B232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9AF341L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54113J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF341N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1251": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1224FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LPC11E11FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF516S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F1253": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32BG12P232F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF62NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF62NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF406R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC472KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "STM32F101CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF406N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M0518SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1225FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S5P36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3H1FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C18H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF516R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32G842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52230_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S800": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s800.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827UB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC120RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MK22FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK22F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S801": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s801.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2C19L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32TG11B520F128IM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54P19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MKL02Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffff00", "size": "0x0400"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "Generic_NUC400_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TM4C1294KCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1294KCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1402-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F401RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32GG840F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG840F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M451MLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LPC804M111JDH24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFR32BG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F12365_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "SN32F707BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4700-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9BN2": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U14FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L431KB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9BN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG14P732F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC100VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Generic_NUC200_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC123SD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F051T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NM1120EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMDA0E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MBL/Include/ARMv8MBL.h", "define": "ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32L152RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G200F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32G/EFM32G200F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1755_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "SN32F765J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG290F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG290F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKW21D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P133F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "Mini51XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S5P3B": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1768": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1769": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM366FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1763": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "Mini52FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F101C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1766": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKE16F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE16F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE16F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE16F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32GG380F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG380F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1765": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S5747": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5747.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L475JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG14P532F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P532F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P532F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L475JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NM1200LBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11U35FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P231F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM3HPFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F378CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1785": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1786": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1787": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x000020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x000004000"}, "IRAM2": {"start": "0x20080000", "size": "0x000004000"}, "IROM1": {"start": "0x00080000", "size": "0x000020000"}}, "debug": "SVD/SAM3U/ATSAM3U2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAM4LS2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L063R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1788": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC177x_8x.h", "define": "LPC177x_8x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC178x7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG1B132F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4200-Q48x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F439ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "N572F072": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\N572F072_v3.svd", "processor": {"clock": "48000000"}}, "MCIMX7U5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NUC121ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MCIMX7U3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/MCIMX7U5_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7U3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "STM32L071RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG980F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG980F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG940F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG940F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F131H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F131H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4LS2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32H743VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32WG990F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG990F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L471RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B840F1024IL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L471RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC240SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F450ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442KI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "NUC2201SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC2201\\Include\\NUC2201.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F723ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11U34FHN33/311": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC220LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9AFB41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F412CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F412CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1114FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L052K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B231F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B231F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BFD18S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAML21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG822F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG822F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM367FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11C24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG14P231F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L100C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG280F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG280F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM369FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TM4C123BE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123BE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG350F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG350F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F215VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F215VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM3H2FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F756IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S1F11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK65FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "arm/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "NUC122ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "ATSAM4LS8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKS20FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS20FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS20F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS20F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C49L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC812M101JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F767ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M452VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9BF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F479ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF315R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9AF312K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32HG321F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG321F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM3H2FUDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11E14FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F413VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32PG12B500F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini54XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1233H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1302-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F778AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2CC9J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "Mini51LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LPC11A14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F232H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1G21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1g21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1115JET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC220LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P332F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L053C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMR21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21G18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108CZ": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [134481920, 16]], "algorithm": {"Flash/STM32W108_192.FLM": {"default": "1", "ramsize": null, "size": "0x30000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x08000000", "size": "0x30000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2D55GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L053C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC122ZC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "XMC1201-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S30": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1231H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32W108CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [134481920, 16]], "algorithm": {"Flash/STM32W108_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32W108CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F437II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114LVFHN24/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F264S/X": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1231H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK10FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54102J512": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54102J512UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54102_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F413CG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32LG230F64R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1302-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1V131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F350K8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "ATSAMV71N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ARMCM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "TMPM372FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3H0FMDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_8.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/M3H0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG890F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG890F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM380FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M0519SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S1332": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F231E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F231E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM3N1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9879QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L021K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM368FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M368.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TLE9867QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "NM1520LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F301C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK21DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E1A11B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAM4LC8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3748": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3748.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4LC8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LC8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO102LB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "MB9BF321K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM037FWUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M037.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKL26Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GK6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NM1820EB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2GK6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F437ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV42F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F437ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1517JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F12366_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NUC120LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F150K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21E18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B420F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54606J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAMD21J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M0518SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW31Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6X4": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC1112FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6X1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "MCIMX6X3": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6SX_A9.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "S6E2D35GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32G232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG13P632F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1200TBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1401-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C5AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F103ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L4R5VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B320F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B320F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B320F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20N/ATSAMC20N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF512R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L100RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S3634": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123AE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123AE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2GM6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1112FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2GM6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini51LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F103V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F50241_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "M054ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF512N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S1850": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1850.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG280F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG280F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52354": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20N/ATSAMC20N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4320": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4323": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4322": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4325": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32F302CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG990F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HC32F146F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32F146FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG295F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG295F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32GG940F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG940F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3A8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3A8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TMPM3H1FPUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 16384], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_48.FLM": {"default": "1", "ramsize": null, "size": "0x0000C000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x0000C000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK64FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK64FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK64F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5K31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG1V131F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKE18F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE18F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE18F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD51J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F777VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM3U1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "Mini57TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32WG880F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG880F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG14P732F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P732F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P732F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L486JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ADSP-CM419F-BCZ_M4": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[285212672, 4096], [285736960, 4096]], "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "0", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.1.0.0.pack", "compile": {"header": "Device/inc/M4/CM41x_M4_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM41x_M4_DFP.pdsc", "memory": {"IROM2": {"start": "0x11001000", "size": "0x000FF000"}, "IRAM1": {"start": "0x10000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20010000", "size": "0x00018000"}, "IROM1": {"start": "0x11000000", "size": "0x00001000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S5G56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1404-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV10Z32xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKV_P32_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKV10Z1287.h", "define": "MKV10Z64xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LM3S1911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B420F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F446VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F12366_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F446VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F412RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F722IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM367FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG1B132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F245J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAM3A4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3A8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3A4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMD11C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD11_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HC32L110C6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC804M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFM32WG895F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG895F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "Z32F12811ARS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F469IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C28J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12345_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1114FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11E36FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3S2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S2B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "NUC120RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG232F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG232F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C59H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF465K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F1252": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF465L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL81Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKL_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL81Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL81Z128VMP7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL81Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fffa000", "size": "0x018000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL81Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAMV70Q19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [4194304, 8192], [4194304, 8192], [4194304, 8192], [536870896, 16], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70Q19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "Mini51TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAM4CMP32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMP32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3H5FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S5C31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F302C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG1P132F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F705J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 512], [536813568, 512]], "algorithm": {"Flash/SN32F700_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F700_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0200", "ramstart": null, "start": "0x1fff2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700.h", "define": "SN32F700"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG220F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4400-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4400c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4400_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F767IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "S6E2DF5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L4R5QI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM370FYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG395F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG395F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L071CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F64R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F64R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M485KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "XMC1301-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F131E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F131E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F64R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO112VC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMV71N19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71N19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TM4C123GE6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123GE6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C29J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L162ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM4LC2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG895F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG895F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC20E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1302-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG14P231F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG880F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG880F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK40DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SKEAZN16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO110KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF311K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768], [537657344, 8192]], "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF311N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM366FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG840F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG840F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG220F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451MRC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC120LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Mini58LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ARMCM0P": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h", "define": "ARMCM0P_MPU"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LM3S2776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L071C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M052LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B510F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC131SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG13P732F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD10D13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4088FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL04Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2G28J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "SN32F773T": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G210F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G210F128"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G210F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MAX71637": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MAX71636": {"core": "Cortex-M3", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX716xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\max716xx.h", "define": "MAX71637"}, "pdsc_file": "http://www.keil.com/pack/Keil.ZEUS_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x00400000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "108000000"}}, "MK21DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG840F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG840F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG840F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 8192], [32768, 16384], [65536, 32768], [131072, 65536], [524288, 8192], [557056, 16384], [589824, 32768], [655360, 65536]], "algorithm": {"Flash/TMPM440_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "LM4F111B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F111B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F0008_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "TMPM3H5FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11D14AM": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE18F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE18F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE18F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE18F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD11D14AS": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11D14AS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMC21N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21N/ATSAMC21N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1294NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A04UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini52TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32GG11B840F1024IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAME51J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME51J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "TM4C129CNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1403-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F122E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F122E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK64FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK64FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK64F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MK64F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207IE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9L71": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l71.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG14V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14V/Include/em_device.h", "define": "EFR32FG14V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14V/EFR32FG14V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F415OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32LG380F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG380F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1302-T028x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMS70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC11U35FET48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC240VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F1656_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33MA384A": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 256]], "algorithm": {"AC33MA384A/Flashloader/AC33Mx384A_384.flm": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33MA384A\\Core\\include\\AC33Mx384A.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33MA384A\\SVD\\AC33Mx384A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B820F2048GL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P431F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HC32L110B6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110B.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32FG1V131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG308F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG308F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1549JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG942F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG942F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024GL152": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL152.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF341M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3X4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "LPC11E67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG890F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G6FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC123SC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M481LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "ATSAMD21G18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21G18AU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F773S": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F732VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M2351ZIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "XMC1302-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F078CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3826": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s3826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L471QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12366_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC43S20": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG980F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG980F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F405ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S9B95": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b95.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1114LVFHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9B96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32G230F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G230F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52331_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L051R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1B132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM3HQFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4108-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L051R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1520RD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L083RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F303RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK11DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F303RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMG54J19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAMDA0G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1V131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L152VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG12P232F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKM33Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF114R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F50220_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "PAC5250": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H46F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC11U24FET48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D35J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG895F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG895F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG880F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG880F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM461_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B110F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L452VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG222F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG222F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54616J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "ATSAME70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L452VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S9GN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9gn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1231C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1231C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F256GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG14P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG825F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG825F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG11B820F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P732F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F303R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M0516LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF312R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F303R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC230RC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F469NE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32LG890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1224FBD64/121": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC4104-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LPC51U68": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC51U68_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC51U68_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC51U68JBD64"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC51U68_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC51U68.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B540F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMDA0J14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F2641J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD64/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "MK20DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F330F6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "GD32F130K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F407ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F407ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B420F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM365FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M365.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM0plus": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM0plus/Include/CMSDK_CM0plus.h", "define": "CMSDK_CM0plus"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0plus.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "GD32F130K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3H3FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H3.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F130K4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1510LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG11B520F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6Y7": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F302R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C129DNCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129DNCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "R7S72100": {"core": "Cortex-A9", "vendor": "Renesas:117", "sectors": [[0, 4096]], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.RZ_DFP.1.1.0.pack", "compile": {"header": "Device/Include/RZ_A1H.h", "define": "RZ_A1H"}, "pdsc_file": "http://www.keil.com/pack/Keil.RZ_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x18000000", "size": "0x800000"}}, "processor": {"fpu": "DP_FPU"}}, "MCIMX6Y2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6Y0": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6Y0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32L073VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F12366_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "SMM-SSE-200": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.V2M-MPS2_SSE_200_BSP.1.0.3.pack", "compile": {"header": "Device/V2M-MPS2-SSE-200/SMM-SSE-200/Include/mps2_sse_200.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.V2M-MPS2_SSE_200_BSP.pdsc", "memory": {}, "debug": "SVD/MPS2_SSE_200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "20000000"}}, "STM32F779NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV44F64xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32FG1V131F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F072CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF524K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF524L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF524M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF466N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF466K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460L/Include/mb9b460l.h", "define": "MB9BF466L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F407ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMR21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMR21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5B91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5b91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DL13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "EFM32TG11B140F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1P132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF466R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG995F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG995F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC442VI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EZR32WG330F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4C16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FN1M0xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MK21FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG995F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG995F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54628J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54628_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54628J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54628_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54628.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF514N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32WG842F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG842F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME54N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME54N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32HG108F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG108F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C123GH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32HG220F32R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG220F32R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32MG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC121SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F072C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52243_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123ZD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32BG14P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P732F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F52342_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L073V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC123LC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32BG1P232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMC21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD10C13A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 512]], "algorithm": {"Flash/ATSAMD10_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C13A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC120VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO100SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32WG840F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG840F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SA16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F302RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK40DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG290F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG290F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F030K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3HNFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC505DSA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC845M301JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MB9BF404R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2C4AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF404N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4800-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "GD32F350C4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "EFM32TG11B520F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E12FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2G36J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32MG13P832F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P832F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P832F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2G36H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKM14Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F758F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350C8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "NANO110RD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MIMXRT1051": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 262144]], "algorithm": {"Flash/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.1.0.2.pack", "compile": {"header": "Device/Include/MIMXRT1052.h", "define": "MIMXRT1052"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IRAM2": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MIMXRT1051.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F765II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MIMXRT1052": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 262144]], "algorithm": {"Flash/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.1.0.2.pack", "compile": {"header": "Device/Include/MIMXRT1052.h", "define": "MIMXRT1052"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.iMXRT_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IRAM2": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MIMXRT1052.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M4LEDLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG842F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG842F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC131LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "nRF51802_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "HT32F52241": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L475ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF428S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "DS_CM3": {"core": "Cortex-M3", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.1.1.0.pack", "compile": {"header": "Device/DS_CM3/Include/DS_CM3.h", "define": "DS_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_DSx_BSP.pdsc", "memory": {}, "debug": "SVD/DS_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC4333": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC4330": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "SN32F774T": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "Mini54XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F774S": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F411VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ARMv8MML_DSP_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MKL04Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F132H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F132H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F132H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051R4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMHA1E15AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "samha1b/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1b/svd/ATSAMHA1E15AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F051R6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA0E14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0E14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKV46F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV46F256VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV46F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F358VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MIMXRT1052xxxxB": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096], [1610612736, 262144]], "algorithm": {"arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}, "arm/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1052_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1052DVL6B"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1052_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x040000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MIMXRT1052.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "600000000"}}, "EFM32G200F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G200F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG13P732F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U24FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1225FBD64/321": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "EFR32FG1P131F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F350CB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "nRF51824_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32GG11B310F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B310F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B310F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MKV10Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV10Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV10Z1287.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "EFR32MG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P231F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S8730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8733": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8733.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M451LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EZR32HG320F32R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1765": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M452LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG12P231F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG840F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG840F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F32R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "NANO100SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S8933": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8933.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NM1823ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S8930": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8930.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C19J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32WG232F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG232F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "A31G122": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536866816, 128]], "algorithm": {"A31G12x/Flashloader/A31G12x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G12x/Flashloader/A31G12x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G12x/Core/include/A31G12x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "A31G12x/SVD/A31G12x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "A31G123": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536866816, 128]], "algorithm": {"A31G12x/Flashloader/A31G12x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G12x/Flashloader/A31G12x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G12x/Core/include/A31G12x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "A31G12x/SVD/A31G12x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C129ENCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1345FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1403-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK60DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MCIMX7S5": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S5_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "MKW41Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG232F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG232F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3U4E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256], [1048576, 256]], "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M451RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M052ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1100-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1112FHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM4050": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM4x50.FLM": {"default": "1", "ramsize": null, "size": "0x7F000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM4050.h", "define": "__ADUCM4050__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/ADuCM4050/Releases/AnalogDevices.ADuCM4x50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x7F000"}}, "debug": "SVD/ADuCM4050.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "52000000"}}, "LPC54607J256BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EZR32HG220F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG320F32R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1857": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1850": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F101ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LPC1853": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC18S50": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32HG220F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM0": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM0/Include/CMSDK_CM0.h", "define": "CMSDK_CM0"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TLE9861QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 32768]], "algorithm": {"Flash/TLE9861.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC18S57": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1549JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F450IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM4F211H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F211H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F450IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M058LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F450II": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC54618J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "MB9BF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1B131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF121J": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9B120J_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xJ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMC20J18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P232F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F0008_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFR32MG1P232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKV31F128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F128VLL10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV31F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "HT32F52344_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMR21E19A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E19A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C129XKCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129XKCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F130C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F130C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3N00B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N00A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00400000", "size": "0x00004000"}}, "debug": "SVD/SAM3N/ATSAM3N00A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC54606J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54606J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54606.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM3H4FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2G38J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2HG4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HG4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NM1820LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC4108-F64x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5762": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5762.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F102R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F102R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M052ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F038F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F102R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F767F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M481SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32ZG210F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F779II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG942F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG942F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F100C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1112FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52352": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK24FN256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F25612_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK24FN256VDC12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK24F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK24F25612.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F22366_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MKM33Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAME54N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L051C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKL15Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6753": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6753.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F64R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3X4E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000A0000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3XA/ATSAM3X4E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "NUC100RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M2S005": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LPC11U34FBD48/311": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_40.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xA000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xA000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF141N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1B232F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E1A12B0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG230F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG230F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG230F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG330F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S57": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "LPC43S50": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "EFR32BG1B132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC140LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L021F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4500-F144x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54016": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54016_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54016JET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54016_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54016.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S8938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P233F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F413MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32MG14P733F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P733F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P733F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L485JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L485xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F413MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54606J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54606.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32L443CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F100ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F303C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAME51J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EZR32WG330F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14F512xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_D64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P512_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKE14F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32LG330F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F091RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F102RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G890F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G890F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S2276": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2276.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32ZG108F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TM4C1233C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1233C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM475FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9844-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285274112, 4096]], "algorithm": {"Flash/TLE9844_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100F000"}, "Flash/TLE9844_2.FLM": {"default": "1", "ramsize": null, "size": "0xF000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0x10000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4700-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMC21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC21/ATSAMC21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52253_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M0516ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMV70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F1653_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1517JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG232F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG232F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F072RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2CC9L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F150C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AC33M6128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1343FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2GK8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A12FBD48/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4076FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F150C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152V8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3U4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256], [1048576, 256]], "algorithm": {"Flash/ATSAM3U_128_B1.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00100000"}, "Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00100000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32LG895F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG895F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F071VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF565K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG14V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14V/Include/em_device.h", "define": "EFR32FG14V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14V/EFR32FG14V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD51N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NANO100NE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF344N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF344L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1120DC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF322K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F410T8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TLE9877QXA40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF322L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF322M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ISD9360": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "M4TKLE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKL46Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL46Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL46Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L062K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L062xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L062x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFR32FG1V132F32GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F32GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32HG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKL24Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S3654": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3634.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U14FET48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S3651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52341_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFE00"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1251B": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F125x/ht32f125x.h"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/HT32F125x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMDA0G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMDA0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F479VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF115R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM3H2FSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F103T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32BG1B232F256GM56": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM56.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5U91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5u91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M451MSD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F103T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F723IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F101R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "HT32F50241_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F101R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "XMC1302-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "LM3S1651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM330FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM330_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F437VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11A02UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F265J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC131LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32WG230F256R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52243_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1P332F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L073CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F350R4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "GD32F350R6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LM4F122H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F122H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F350R8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "GD32F170C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C2AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MK53DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32TG11B520F128IQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1104UK": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC1102_04.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L073CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F405ZK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4R5AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW31Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW31Z4.h", "define": "MKW31Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW31Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG995F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG995F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F410RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9792": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9792.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG880F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG880F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM366FWXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SP32A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4SP_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4SP/sam4sp.h", "define": "__SAM4SP32A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00500000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4SP/ATSAM4SP32A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1P732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "Z32F12811ATS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F1281.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F1281.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F1281.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK12DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350RB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "EFM32GG11B120F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F415ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F1654_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF156R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1316FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG1V132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U14FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F247F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1827YB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L162RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F051C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3HPFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32HG310F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG310F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMR21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMR21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF467R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F103ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TM4C123GH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F051C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32L476ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F101RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF467N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F101RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM068FWXBG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM06x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM068.h", "define": "TMPM068FWXBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M068.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Z32F06410AKS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0641.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0641.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0641.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG53N19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B540F64IQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "AC33M8128": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx128/Flashloader/ac33m8128_PFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx128\\Core\\include\\AC33Mx128.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx128\\SVD\\AC33Mx128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM3HNFZDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TMPM4G6F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG13P232F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P232F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P232F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F768F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123GH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC802M001JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFR32FG13P233F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P233F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P233F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C1297NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1297NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F745IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F745IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "IOTKit_ARMv8MBL": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MBL/Include/IOTKit_ARMv8MBL.h", "define": "IOTKit_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L152VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC200SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MK20DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P132F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC824M201JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC824.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F105VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO100SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LPC54005": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54005_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54005JET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54005_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54005.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L151V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC802M001JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "STM32F777ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM343FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S815": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s815.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD10D14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10D14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG51N18": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51N18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L063C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L063xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L063x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S3N26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s3n26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF516T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG11B520F128GM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F248BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54616J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54616.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "EFM32WG942F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG942F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129CNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129CNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC20E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F767BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F103RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF405R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54607J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54607J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54607.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "A31G111": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536867328, 128]], "algorithm": {"A31G11x/Flashloader/A31G11x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G11x/Flashloader/A31G11x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G11x/Core/include/A31G11x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "A31G11x/SVD/A31G11x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F103RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M4TKVE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L082KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F12365_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F103RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S6E2C28H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9AF156N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG14P232F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SKEAZN32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "SN32F759F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54101J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54101J512UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54101.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF405N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B400A\\mb9b400r.h", "define": "MB9BF406R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF40xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L082KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1115FET48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F358CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AFA31N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TMPM362F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M362.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG842F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG842F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG280F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG280F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AFA41M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4S16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4S/ATSAM4S16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B520F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472HG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "MB9BF429S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32LG330F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG330F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF429T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "M054ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M052LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F378RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "NUC100RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG12P431F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L152R6xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M481SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC100LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV58F1M0xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P1024_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV58F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "SRAM_OC": {"start": "0x2f000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x100000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV58F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "HT32F52220": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32MG14P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B110F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "AC33GA256": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024]], "algorithm": {"AC33GA256/Flashloader/AC33GA256_CDFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33GA256\\Core\\include\\AC33GA256.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33GA256\\SVD\\AC33GA256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32JG12B500F1024IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1114FDH28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120DB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3H4FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC11A11FHN33/001": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1435": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005C00"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1435.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TMPM341FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM341_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "S6E2C2AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG360F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG360F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2H46E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG900F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG900F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG900F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F217IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG350F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG350F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG350F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini54TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LM3S5791": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5791.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H46G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H46X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C39H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "TMPM3H4FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1320LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1320_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1320_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1320_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NM1320AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO103SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1202-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG13P732F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4800-E196x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM364F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M364.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ARMCM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC812M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F413RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F038G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MIMX8MD7xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "NUC120VD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "K32W022S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W022S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MK20DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32L053R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L053R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L053xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L053x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F246BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1549JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M0564RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "Musca": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [[2097152, 65536]], "algorithm": {"Flash/MT25QL512_DC.FLM": {"default": "1", "ramsize": "0x00020000", "size": "0x10040000", "ramstart": "0x20000000", "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.Musca_A1_BSP.1.0.2.pack", "compile": {"header": "Device/Include/system_cmsdk_musca.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.Musca_A1_BSP.pdsc", "memory": {}, "debug": "SVD/Musca.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F091CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F450ZI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F405OE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32WG360F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG360F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMHA1G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "samha1a/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1a/svd/ATSAMHA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG222F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F439NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "GD32F450ZG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F450ZE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x030000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MAX32652": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "M2S010": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "MAX32650": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MAX32651": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[268435456, 16384]], "algorithm": {"Flash/MAX32650.FLM": {"default": "1", "ramsize": null, "size": "0x00300000", "ramstart": null, "start": "0x10000000"}, "FlashIAR/FlashMAX32650.flash": {"default": "0", "ramsize": "0x00100000", "size": "0x00300000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32650/Include/max32650.h", "define": "MAX32650"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32650.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00100000"}, "IROM1": {"start": "0x10000000", "size": "0x00300000"}}, "debug": "SVD/MAX32650/max32650.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "nRF51801_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F439NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAML22N16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22N16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK70FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG295F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG295F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "S32K142": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"addon_cmsis/Flash/S32K142_P256_2KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "platform/devices/S32K142/S32K142.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32L072RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF321M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF321L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1547JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MK20DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F417VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO120LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MKE02Z64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C1236H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1236H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1112FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L051T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1112FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F413RH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F301R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC824M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC824.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F301R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L072RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAME51N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME51N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "NM1120FC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L051T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3H5FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF116S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC54101J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "S6E1A12C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A12X0A.FLM": {"default": "1", "ramsize": null, "size": "0x16000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x16000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF116T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L152RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1402-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG332F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32L152RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "Mini52LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "NUC240SE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LPC54114J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM333FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM33x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32LG330F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF218S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF218T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H743BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MB9AF131N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HC32F003C4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F003.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.1.0.0.pack", "compile": {"header": "Device/Include/HC32F003.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32F003.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L4S7AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4TKRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32TG825F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG825F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B520F128GQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z32xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MKE02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}, "arm/MKE02Zxxx_P32KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "M0519LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F706BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F048G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG995F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG995F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG995F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1232C3PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_32.FLM": {"default": "1", "ramsize": null, "size": "0x008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x003000"}, "IROM1": {"start": "0x00000000", "size": "0x008000"}}, "debug": "SVD/TM4C123/TM4C1232C3PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MVF50NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "ATSAMHA1E16AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "samha1b/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1b/svd/ATSAMHA1E16AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFR32MG12P432F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMC20J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2D55GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F767VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4078FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M0518LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F031K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME53N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "ARMCM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "NANO112SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "AC30M1332": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L162VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9DN6": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9dn6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4S2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32PG1B200F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NANO120KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM4G9F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM37AFSQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M37A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF118S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF118T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC220SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMD21G15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F746VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG11B420F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F031E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC200LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6633": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6633.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32GG380F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG380F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG380F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54102J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF121M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG990F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG990F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C38L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32LG995F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG995F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120RD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F170R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM374FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M374.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F469NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF141L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF141M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9xFxxx_DualWflash32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}, "Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F429BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3S1A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S1B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3S1C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3S/ATSAM3S1C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKL26Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL26Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL26Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HC32F146KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32F146FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32F146KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F722ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM3HMFZFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "N572F065": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N572Fxxx.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\N572F065_v3.svd", "processor": {"clock": "48000000"}}, "LPC844M201JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "HT32F50220_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG11B820F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2H44F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H44G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L4A6ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2H44E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H44X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H4/Include/S6E2H4xG/s6e2h4xg.h", "define": "S6E2H46G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h4xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54113J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32LG940F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG940F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKW35Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO103LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F746VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L162VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F779AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E36FHN33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMC21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32L031F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B540F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L031F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "BlueNRG-1": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[268697600, 2048]], "algorithm": {"Flash/STBlueNRG1.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x28000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.1.1.1.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x28000"}}, "debug": "SVD/BlueNRG1.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MCIMX7D3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_A7.h", "define": "iMX7D_A7"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7D3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "NANO120SC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "BlueNRG-2": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[268697600, 2048]], "algorithm": {"Flash/STBlueNRG2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x200002CC", "start": "0x10040000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STBlueNRG-2_DFP.1.0.0.pack", "pdsc_file": "http://www.keil.com/pack/Keil.STBlueNRG-2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x10040000", "size": "0x40000"}}, "debug": "SVD/BlueNRG2.svd", "processor": {"fpu": "0", "endianness": "Little-endian"}}, "MB9BF564L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO100ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "MB9BF564K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F50230_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA31L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF156M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "R-IN32M3-EC": {"core": "Cortex-M3", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [33554432, 65536], [268435456, 8192], [268435456, 131072], [268500992, 65536]], "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_EC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "AC33M4064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B420F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C123AH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123AH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1402-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4800-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKL14Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKE02Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00000100", "ramstart": "0x1FFFFC00", "start": "0x10000000"}, "arm/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "LPC802M001JDH16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC802.h", "define": "LPC802M001JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC802.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "EFM32PG1B200F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "NUC122LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "HT32F5826": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F5826"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F5826.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "TM4C1299KCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C1299KCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F756J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF312L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF312N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54608J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54608_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54608J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54608_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54608.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO130SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "HT32F1755": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini54XFHC": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW20Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW20Z4.h", "define": "MKW20Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW20Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F058C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG1P732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4350": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MK64FN1M0VLL12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.2.3.0.pack", "compile": {"header": "platform/devices/fsl_device_registers.h", "define": "CPU_MK64FN1M0VLL12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "platform/devices/MK64F12/MK64F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4353": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NANO102LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LPC4357": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "MT7687F": {"core": "Cortex-M4", "vendor": "MediaTek:129", "sectors": [[268435456, 4096]], "algorithm": {"tools/keil/mt7687/7687_32M_MXIC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://download.labs.mediatek.com/MediaTek.MTx.4.6.1.pack", "compile": {"header": "driver/CMSIS/Device/MTK/mt7687/Include/mt7687.h"}, "pdsc_file": "http://download.labs.mediatek.com/MediaTek.MTx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IRAM2": {"start": "0x00100000", "size": "0x00010000"}, "IROM1": {"start": "0x10000000", "size": "0x00200000"}}, "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "192000000"}}, "TM4C1233E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1233E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54607J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54607J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54607_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54607.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKV42F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "LPC54101J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4502-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2DH5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F350K4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "NM1100FAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM343F10XBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKV42F64xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP64_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV42F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV42F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV42F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "MKM14Z64Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P131F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F401VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "Mini55TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F423MH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKL34Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL34Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL34Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL34Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL34Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MCIMX6G1": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "S6E2C3AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MCIMX6G3": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MCIMX6G2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TMPM462F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54018": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[268435456, 4096], [268435456, 4096], [268435456, 4096]], "algorithm": {"arm/LPC540xx_MX25L12835FM2I.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_W25Q128JVFM.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}, "arm/LPC540xx_MT25QL128.FLM": {"default": "1", "ramsize": null, "size": "0x1000000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54018_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54018JET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54018_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "SRAMX": {"start": "0x00000000", "size": "0x030000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54018.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32FG14P231F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC505YLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "S6E2C58L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HC32L150K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1138": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1138.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AFA42N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA42M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK60FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK60FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MCIMX6G0": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/iMX6UL.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32LG230F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG230F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK21DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1133": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1133.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U67JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "APOLLO512-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MK50DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NANO130SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ARMCM23": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "QN9083A": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083B": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9083C": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F769AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC845M301JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAMC20G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG13P231F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG842F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG842F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKV56F512xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV56F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV56F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x080000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV56F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "NANO120LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM4F211E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F211E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U35FHI33/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK51DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK51D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F745VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG225F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG225F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F767VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAM4LC2B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG1B200F128GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F217ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F217ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2533": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2533.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M484SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32GG880F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG880F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG880F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG395F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG395F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F769BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL26Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL26Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL26Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL26Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4R5ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM4F110E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F110E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L073VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L471VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "STM32L471VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAML21J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G9FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAML21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG942F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG942F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG942F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/101": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK28FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28F15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK28FN2M0VMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28F15_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK28F15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "LPC11U34FBD48/421": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q040x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "HC32L110C4UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F246J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U34FHN33/421": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32HG322F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG322F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AFA42L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F50230_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HT32F52231_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC230SD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2HG6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1342FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HC32L150F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2C48L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC4402-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "Mini51FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMC20E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMC_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/SAMC20/ATSAMC20E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1F16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s1f16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG330F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG330F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG330F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMDA1E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMG51G18": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG51\\samg51.h", "define": "__SAMG51N18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD\\SAMG51\\ATSAMG51G18.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L083VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1820ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32G280F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G280F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F231H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F231H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM073FSDUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M073.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F405ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32ZG210F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32HG308F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG308F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG308F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1100-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AU9110LF3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/AU9100_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}, "Flash/AU9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/AU9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAM4LS4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC123SD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4LS4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S7ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F469AE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "APOLLO256-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L083VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG230F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG230F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG230F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L4S9ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NANO100KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NANO103ZD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO103\\Include\\Nano103.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO103AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1225FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "TMPM332FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M332.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C5AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M482LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFR32MG13P632F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P632F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P632F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M2S025": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "MKL24Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL24Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H5FSDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC123SC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L152C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S9D96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini58ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TLE9877QXW40": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF421K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A420L\\mb9a420l.h", "define": "MB9AF421L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF42xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TM4C1299NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1299NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M453VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4N8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM4N8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-F64x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG13P932F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P932F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P932F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L162QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32PG12B500F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1313FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC200SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11A14FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG840F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG840F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4500-F100x768": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0xC0000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF368M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1764": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG14P632F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P632F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P632F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G8F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2D55J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F048T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL25Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F1765_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F207ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F207ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "PAC5220": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMA5D31": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D31.svd", "processor": {"fpu": "DP_FPU"}}, "NUC029FAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AE\\Include\\NUC029FAE.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NUC029AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "PAC5223": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NM1120EC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV10Z16xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKV_P16_1KB_SEC.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.1.8.0.pack", "compile": {"header": "Device/Include/MKV10Z1287.h", "define": "MKV10Z64xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KVxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKV10Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MKW21Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F427VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "GD32F450VI": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"Flash/GD32F4xx_2MB.FLM": {"default": "1", "ramsize": null, "size": "0x0200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F450 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x070000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x0200000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M453RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9AF131M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF131L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F427VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM3U1E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x20080000", "size": "0x00002000"}, "IROM1": {"start": "0x00080000", "size": "0x00010000"}}, "debug": "SVD/SAM3U/ATSAM3U1E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC1313FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF131K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440]], "algorithm": {"Flash/MB9AF13x_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9BFD17S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "XMC1404-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BFD17T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32TG232F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG232F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG232F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52241_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKW22D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW22D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG230F128R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF567R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4LC4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LC4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LC4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG222F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32WG330F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF366K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723IC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4078FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL25Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S70": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "MB9BF567N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF567M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NUC120VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKM33Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM33Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "M058SZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAMV70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32MG12P232F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F215ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "M484SIDAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LPC11U23FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG995F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG995F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F215ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FDH20/002": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMDA0G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1313FBD48/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L452CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L152QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF117S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "M453YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L152C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M452LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M0564LE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M451VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM4F110H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F110H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L021G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC4072FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK22FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12365_46QFN": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LM3S9D90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF617S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF617T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32H753XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32GG11B820F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMC20J17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C4AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1301-Q040x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F2451BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U37FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32PG1B200F128IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101T8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32WG895F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG895F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG895F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VE3DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B520F128GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG14P732F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAME53J20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME53J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F417VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L431VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG309F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG309F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F070F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L486VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L031E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM13Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM13Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L031E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F330R8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32LG280F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG280F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F733IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC4315": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "QN9080A": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xA_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908X.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "QN9080C": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xC_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XC.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "QN9080B": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/QN908xB_512K.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x80000", "ramstart": "0x04000400", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.1.1.4.pack", "compile": {"header": "Device/Include/QN908XB.h"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.QN908x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x04000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/qn908XB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54102J512UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC1402-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML22_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML22\\ATSAML22J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U13FBD48/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKL43Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL43Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL43Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1512": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM3HMFDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U36FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1100-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9BF518S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F042C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "RC10001": {"core": "Cortex-M0", "vendor": "RelChip:146", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.relchip.com/Keil/RelChip.RC10000.1.0.0.pack", "compile": {"header": "Device/Include/RC10001.h"}, "pdsc_file": "http://www.relchip.com/Keil/RelChip.RC10000.pdsc", "memory": {"IRAM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD/RC10001.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "4000000"}}, "STM32L031K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK30DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L031K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F330RB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "MKM34Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM34Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32JG1B200F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKV58F512xxx24": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[268435456, 8192]], "algorithm": {"arm/MKV_P512_8KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV58F512VMD24"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV58F24_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x18000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x10000000", "size": "0x080000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV58F24.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "240000000"}}, "LM3S6952": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6952.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM4CP16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF155R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG13P732F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P732F512GM51"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P732F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMG55G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL27Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x400fe000", "size": "0x0200"}, "SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL27Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMR21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMR21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMR21\\Include\\samr21.h", "define": "__SAMR21E19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMR21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMR21\\ATSAMR21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B820F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF521M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MCIMX6V7": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V7.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32BG1B232F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S2608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MCIMX6V2": {"core": "Cortex-A9", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX6_DFP.1.5.0.pack", "compile": {"header": "Device/Include/iMX6SX_A9.h", "define": "iMX6SX_A9"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX6_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX6V2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC804M101JDH24": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "MB9BF521K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF142N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF142L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101TB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM072FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M072.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG230F64R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4367": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "ARMCM33_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EFM32LG395F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG395F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B540F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM372FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M372.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2CC8H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S1R26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG330F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG330F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B320F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B320F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B320F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C29L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M451MRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MK22FN1M0Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F042K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G222F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U35FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TC35678FXG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "TMPM367FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-T016x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E1A11C0A": {"core": "Cortex-M0+", "vendor": "Spansion:100", "sectors": [[0, 8192], [24576, 32768]], "algorithm": {"Flash/S6E1A11X0A.FLM": {"default": "1", "ramsize": null, "size": "0xE000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\S6E1A1\\s6e1a1.h", "define": "S6E1A12C0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM0plus_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\S6E1A1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFB44N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1112FHN24/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P832F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P832F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P832F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG13P632F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F50231_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L471VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R7AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG230F256R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "APOLLO256-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F1656": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1114FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32WG232F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG232F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1P133F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ARMCM33": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ADuCM361": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 512]], "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD/ADuCM361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "ADuCM360": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 512]], "algorithm": {"Flash/ADUCMxxx_128.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x20000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.1.0.2.pack", "compile": {"header": "Device/Include/ADuCM361.h", "define": "ADuCM361"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM36x/Releases/AnalogDevices.ADuCM36x_DFP.pdsc", "memory": {}, "debug": "SVD/ADuCM360.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "16000000"}}, "EFM32LG990F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG990F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P431F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P431F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P431F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F212E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F212E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG14P232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM390FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM39x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM395.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M395.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG290F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG290F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MIMX8MQ6xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MKL04Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL04Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "N571P032": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512]], "algorithm": {"Flash/N571E000.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\N571P032_v3.svd", "processor": {"clock": "23000000"}}, "TMPM367FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM36x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M483SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32L152QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5956": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5956.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TC35679IFTG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "SN32F757F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MVF51NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NN151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "NANO120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM3S5951": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5951.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF315M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF315N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32G890F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G890F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1404-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1937": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1937.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC125ZC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAM4E8E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG230F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LPC4078FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F479VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L152VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK02FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK0x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK02FN64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK02F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MK02F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "LM4F112C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F112C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1202-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F102C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4A6AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG842F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG842F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F102C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32PG1B200F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F102C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F111H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F111H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F190T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini55LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M481LIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "XMC1201-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1100-Q024x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Z32F06423AKE": {"core": "Cortex-M0", "vendor": "Zilog:89", "sectors": [[0, 128]], "algorithm": {"Flash/Z32F0642.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F0642.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F0642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF305N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F746ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F746ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG1P132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TM4C1230H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1230H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MIMXRT1051xxxxB": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096], [1610612736, 262144]], "algorithm": {"arm/MIMXRT105x_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}, "arm/MIMXRT105x_HYPER_256KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x4000000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1051_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1051DVL6B"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1051_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x040000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x020000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MIMXRT1051.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "600000000"}}, "HT32F0008_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "EFM32TG11B340F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "A31G112": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128], [536867328, 128]], "algorithm": {"A31G11x/Flashloader/A31G11x_series_CFG.FLM": {"default": "1", "ramsize": null, "size": "0x600", "ramstart": null, "start": "0x1FFFF200"}, "A31G11x/Flashloader/A31G11x_series_FLASH.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "A31G11x/Core/include/A31G11x_series.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "A31G11x/SVD/A31G11x_series.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC822M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC822.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "NUC130VE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B120F128GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V032F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V032F256GM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V032F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M052LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKV31F512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F51212_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F512VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F51212_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MKV31F51212.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4S5QI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM3H5FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32LG230F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG230F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F038E6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F038xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C59L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4SA16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SA16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32LG230F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG230F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK66FX1M0VMD18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK66F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "M0564LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO100LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F417IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "LPC810M021FN8": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x00001000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/LPC810.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC123ZC2AE1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM4F122C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F122C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21G15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM361F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MVF50NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "EFR32BG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKE15Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE15Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}}, "debug": "MKE15Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMHA1G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}, "samha1a/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1a/svd/ATSAMHA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MVF60NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "EFR32FG1V232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1B231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2C18J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1115JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1402-Q048x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C129LNCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129LNCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG222F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32MG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MD7xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "MB9BF505N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F102CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_MD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F102xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL16Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F256R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1224FBD48/121": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F318C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM4G9F15XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC54616J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54616J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54616.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S9B92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L432KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L432xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "CMSDK_CM7_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF116N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAML21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN256VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF116M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC220LE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO110RE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32TG11B540F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK12DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1B21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1b21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E14FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC230LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F098CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM36BFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM365_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "PAC5210": {"core": "Cortex-M0", "vendor": "Active-Semi:140", "sectors": [[0, 1024]], "algorithm": {"Flash/PAC52XX.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.2.0.0.pack", "compile": {"header": "Device/Include/PAC52XX_device.h"}, "pdsc_file": "http://www.active-semi.com/keil_pack/Active-Semi.PAC52XX.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/PAC52XX.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG11B540F64GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC126RE4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKW24D512xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW24D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32WG230F64R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF616S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F303VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MK70FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "MK70FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK70F15.h", "define": "MK70FX512xxx15"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K70_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK70F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F303VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IRAM2": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF616T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32HG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG108F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32WG230F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG230F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2DH5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG11B420F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF618T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC120RE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L452RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32ZG210F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L452RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF618S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B610T\\mb9b610t.h", "define": "MB9BF618T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF61xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAME51N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME51_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME51J19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LPC11E68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32LG995F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG995F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC230LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32JG1B100F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC220VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F350C6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "SN32F236J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54618J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54618_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54618J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54618_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54618.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM366FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M452RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAM4E16E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16E.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4E16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4E/ATSAM4E16C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1547JBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32G800F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G800F128"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G800F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC43S67": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "TM4C1232H6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1232H6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F105RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120SD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9AF154M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF154N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NANO102ZB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAM4S4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM4S/ATSAM4S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMV70J19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70J19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "GD32F330K8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NANO120ZD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F401RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C129ENCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C129ENCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32HG110F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG110F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG110F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "AC30M1464": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NM1530VE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32TG11B540F64IM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1654_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L081KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L081xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F031G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F0008_24QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32F031G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF154R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF15xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD11C14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD11_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD11\\Include\\samd11.h", "define": "__SAMD11D14AS__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD11_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD11\\ATSAMD11C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C123GH6ZXR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123GH6ZXR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C32E": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32E_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4C32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C32/sam4c32.h", "define": "__SAM4C32E_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4C32/ATSAM4C32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKW40Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW40Z4.h", "define": "MKW40Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW40Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L073RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L021D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L021xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "version": "0.1.0", "STM32L073RZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L073xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M453VE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG980F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG980F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG980F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG980F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "K32W042S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W042S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG295F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG295F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG295F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BFD18T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL33Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL33Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52241_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMD20J14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4402-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F746IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BFD16T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S2D93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s2d93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F131C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F131C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMHA1E14AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024], [4194304, 256]], "algorithm": {"samha1b/keil/flash/ATSAMH_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "samha1b/keil/flash/ATSAMH_16_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000200", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samha1b/svd/ATSAMHA1E14AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "Mini51XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BFD16S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9BD10T\\mb9bd10t.h", "define": "MB9BFD18T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BFD1xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32GG11B520F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C38H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MK11DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK11D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F746IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG110F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1520RC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F50220_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "ATSAMD21J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK51DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF566R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG14P231F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2HE6F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF506N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1233D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG13P632F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF506R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21E17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC126VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F217VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F217xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMC21J18AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1519JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF566L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF566N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG230F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG230F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6610": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6610.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MKE04Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE04Z1284.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L476RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32GG11B110F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B110F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B110F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L476RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100VE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG14P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG332F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG332F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4C4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF314N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1751": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1751.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK60DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK60D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9AF314M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F2755_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B840F1024IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F318K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC4504-F100x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG390F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG390F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4337": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "STM32L151CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151CC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKV10Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKV_P128_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV10Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV10Z1287_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKV10Z1287.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "XMC1404-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11A13FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Axx\\LPC11Axx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Axx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F232E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F232E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M452LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L475ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32WG330F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F239F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4370": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "204000000"}}, "EFM32TG210F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG210F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F705BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F700B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F700B_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F700B.h", "define": "SN32F700B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F700B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF428T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B420T\\mb9b420t.h", "define": "MB9BF429T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IRAM2": {"start": "0x1FFEC000", "size": "0x14000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF42xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "STM32L041K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK20FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NANO130KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF105R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF568R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32GG940F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG940F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG940F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L151C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F268F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112LVFHI33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMHA1G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1a/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "samha1a/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1a/svd/ATSAMHA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF568N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F358RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000A000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF568M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560R/Include/mb9b560r.h", "define": "MB9BF568R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B560R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL13Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL13Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL13Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ARMSC300": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMSC300/Include/ARMSC300.h", "define": "ARMSC300"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMSC300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F765BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L151C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F1653_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1653_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F1653_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32FG14P232F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P232F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P232F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TMPM380FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM38x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M380.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AFA44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFA4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F120H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F120H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC4076FET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1404-Q048x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML22J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML22_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML22_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML22\\ATSAML22J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM4LS4B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAM4L/ATSAM4LS4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMDA1G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1G16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1G16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C129EKCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_512.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x080000"}}, "debug": "SVD/TM4C129/TM4C129EKCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32JG1B200F256GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L486QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK10DX128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "NUC442JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "STM32L100RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011K3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC100LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L011K4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG210F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG210F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1439": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s1439.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2DF5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ADuCM320i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320i.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF61NN15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NN151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "M451LD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG940F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG940F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "nRF51822_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAC": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "nRF51822_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 1024], [0, 1024]], "algorithm": {"Flash/nrf51xxx_ecb.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf51xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF51"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\nrf51.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "16000000"}}, "STM32F412ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32WG230F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52354_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DH5J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL82Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MKL_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL82Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL82Z128VMP7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL82Z7_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x0800"}, "SRAM": {"start": "0x1fffa000", "size": "0x018000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL82Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "96000000"}}, "EZR32WG230F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG230F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F205RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S10": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32PG1B200F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F205RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205RF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1810": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "NUC505DS13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC1812": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1813": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1815": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1817": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L162RCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L475VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L151C8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L475VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S2U93": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s2u93.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK61FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK61FX512xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MK_D512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK61F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "NM1120TC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM036FWFG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM03x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM037.h", "define": "TMPM037FWUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M036.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NM1520LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L162ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAML22J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C1231D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1231D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AFB44L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC4088FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG1B232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F407VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L041E6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC20J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC20/ATSAMC20J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F429IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NUC130LD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F121B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F121B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9B81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9b81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F2755": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NM1120XC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC220LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC029TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512]], "algorithm": {"Flash/NUC029_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC029_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC029AN\\Include\\NUC029xAN.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC029AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1124JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x08000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G230F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G230F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F50220": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F091VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F091VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG880F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG880F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1100-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M451MRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52230_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L471JE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L471JG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM4G9FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MVF50NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NS151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S9C97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9c97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F098RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM440FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 8192], [32768, 16384], [65536, 32768], [131072, 65536], [524288, 8192], [557056, 16384], [589824, 32768], [655360, 65536]], "algorithm": {"Flash/TMPM440_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM440.h", "define": "TMPM440F10XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Configurable", "clock": "100000000"}}, "M487KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F767NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG11B120F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM462F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MVF60NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NN151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "XMC4504-F144x512": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R9VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4R9I_EVAL.FLM": {"default": "0", "ramsize": null, "size": "0x04000000", "ramstart": null, "start": "0x90000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM3S8B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EZR32WG230F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54605J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54605J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54605.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM074FSUG": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 65536]], "algorithm": {"Flash/TMPM07x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.1.3.0.pack", "compile": {"header": "Device/Include/TMPM074.h", "define": "TMPM074FSUG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M074.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1302-Q024x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "SSE-200-MPS3": {"core": "Cortex-M33", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.V2M-MPS3_SSE_200_BSP.1.0.0.pack", "compile": {"header": "Device/V2M-MPS3-SSE-200/SMM-SSE-200/Include/mps3_sse_200.h"}, "pdsc_file": "http://www.keil.com/pack/ARM.V2M-MPS3_SSE_200_BSP.pdsc", "memory": {}, "debug": "SVD/MPS3_SSE_200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V131F32GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F32GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EZR32LG230F256R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "Mini58TDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32WG230F128R60": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R60.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746BE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EZR32WG230F64R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG360F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG360F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG280F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG280F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF368R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2C49J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF368N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4N16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC54607J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54607.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "Mini57XDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HC32M140J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32M140JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG840F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S8738": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8738.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ADuCM3027": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "ATSAMC21N17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21N/ATSAMC21N17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1311FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F50230_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG390F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG390F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52342_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1635": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1635.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADuCM3029": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADuCM302x.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.3.1.2.pack", "compile": {"header": "Include/ADuCM3029.h", "define": "__ADUCM3029__"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM302x/Releases/AnalogDevices.ADuCM302x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x20040000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/ADuCM302x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "26000000"}}, "STM32F100VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MKW21Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW21Z4.h", "define": "MKW21Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F130H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F130H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F100VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "SN32F7651BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L476ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF304R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F439BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO120LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32TG11B320F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini54TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "K32W032S1M2xxx": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [16777216, 2048]], "algorithm": {"Flash/K32W0x2_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x01000000"}, "Flash/K32W0x2_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.1.0.0.pack", "compile": {"header": "Device/Include/K32W042S1M2_cm0plus.h", "define": "K32W042S1M2_CM0PLUS"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K32W_DFP.pdsc", "memory": {"IRAM1": {"start": "0x09000000", "size": "0x00020000"}, "IRAM2": {"start": "0x08000000", "size": "0x00010000"}, "IROM1": {"start": "0x01000000", "size": "0x00040000"}}, "debug": "SVD/K32W032S1M2_cm4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1P632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM4F110B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F110B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9G97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9g97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "HT32F50231_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "TM4C123BH6ZRB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6ZRB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32ZG108F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "M451VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NUC130RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO130KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2C5AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F469NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F415VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "Mini51TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "EFM32ZG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F373C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG330F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG330F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2GM8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F072VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2G28H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM3HNFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAML21E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21E16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F50220_24SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO100KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF505R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "nRF52832_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "IOTKit_CM23": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM23/Include/IOTKit_CM23.h", "define": "IOTKit_CM23"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L433VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21J17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1233D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1233D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9AF115N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF115M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMC20G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20J17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20J17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini55ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F072V8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F031F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22DN512xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P512_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1V132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M058SSAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F413VH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "M452YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M487SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "MB9BF168N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF168M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F405VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32F439BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F765ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF168R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAME70N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAME70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAME70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAME70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFM32HG222F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG222F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2GM8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GMXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GM/Include/S6E2GMxJ/s6e2gmxj.h", "define": "S6E2GM8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gmxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM475FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M451SC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EZR32WG230F128R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG230F128R68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG230F128R68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAM4N8A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4N/ATSAM4N8A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32WG332F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG332F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M485SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F101VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32H753VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32F101VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM383FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F301K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG14P233F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P233F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1960": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1960.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L496ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F52253_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L151RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F301K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L151RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F723VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F769BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MB9BF412R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMA5D33": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D36"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D33.svd", "processor": {"fpu": "DP_FPU"}}, "HC32F005C6PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F005.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.1.0.0.pack", "compile": {"header": "Device/Include/HC32F005.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32F005.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC123ZC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC4200-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4200_4100c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4200_4100_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4200_series/Include/XMC4200.h", "define": "XMC4200_Q48x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x5FC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4200.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG110F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG11B540F64IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF412N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "HC32L157KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L157KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAML22N18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22N18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMV70Q20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70Q20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKL16Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "SH32F205": {"core": "Cortex-M3", "vendor": "Sinowealth:149", "sectors": [[0, 2048]], "algorithm": {"Flash/SH32F2xx.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.sinowealth.com/ftp/tool/Arm32/Sinowealth.SH32Fxxx_DFP.1.0.0.pack", "compile": {"header": "Device/Include/sh32f2xx.h", "define": "SH32F2XX"}, "pdsc_file": "http://www.sinowealth.com/ftp/tool/Arm32/Sinowealth.SH32Fxxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\sh32f2xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AFA32L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AFA32M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32GG890F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG890F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG890F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F423ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F423xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "MKW01Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW01Z4.h", "define": "MKW01Z128xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKW01Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P431F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1100-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LM4F120B2QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_32.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LM4F120B2QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG330F64R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32LG/EZR32LG330F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HC32L157K8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L157KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3N0B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S817": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s817.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC472JI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "M453VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "A33G526": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024], [251658240, 1024]], "algorithm": {"A33G52x/Flashloader/A33G527_DFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x0F000000"}, "A33G52x/Flashloader/A33G527_CFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "A33G52x\\Core\\include\\A33G52x.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {"IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "A33G52x\\SVD\\A33G52x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "A33G527": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 1024], [251658240, 1024]], "algorithm": {"A33G52x/Flashloader/A33G527_DFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x0F000000"}, "A33G52x/Flashloader/A33G527_CFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "A33G52x\\Core\\include\\A33G52x.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "A33G52x\\SVD\\A33G52x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "LPC812M101JTB16": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32L151VBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P333F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P333F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P333F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L151R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM366FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF122K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF122M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3S4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "EFM32LG840F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG840F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3S4A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3N1B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L162VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32TG110F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F334C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "MB9AF144M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF144L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F107VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F334C4": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5K36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5k36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LD4AE0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "NANO120ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "STM32F479BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO100KC3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32MG12P432F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32FG1P131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9AFA32N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA30N\\mb9aa30n.h", "define": "MB9AFA32N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AFA3xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L462CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NANO120KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NANO100NC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S1N11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F302K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "R-IN32M4-CL2": {"core": "Cortex-M4", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [268435456, 131072]], "algorithm": {"Flash/R-IN32M4_MX25L6433F.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M4_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.1.0.1.pack", "compile": {"header": "Device/Include/RIN32M4.h", "define": "RIN32M4_CL2"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M4_CL2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG222F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG222F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HC32L110B4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110B.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1404-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F302K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F302x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "M058LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC100LD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF318S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFR32FG12P431F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S301": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s301.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S300": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s300.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F207VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F439AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B520F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE4G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HE4F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2HE4E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE4X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TM4C1236E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1236E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMD21G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD21_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/SAMD21A/ATSAMD21G18A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1316FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1114FBD48/323": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32H743AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32JG12B500F1024GM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32H743AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "NM1120ZB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S1N16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1n16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG11B820F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F205VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P433F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKM38Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM38Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F0006_48LQFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM369FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1751": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F205VG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F1755_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG395F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG395F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205VF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC4312": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "NUC505YO13Y": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "MKM33Z128Axxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM33ZA5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_CM4": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LPC1825": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x60000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x60000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1827": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC54628J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54628.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LPC1820": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_384_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_384_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x60000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1823": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1822": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MCIMX7S3": {"core": "Cortex-A7", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.1.7.3.pack", "compile": {"header": "Device/Include/iMX7D_M4.h", "define": "iMX7D_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.iMX7D_DFP.pdsc", "memory": {}, "debug": "SVD/MCIMX7S3_A7.svd", "processor": {"fpu": "SP_FPU", "clock": "200000000"}}, "EFR32FG1P133F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG14P632F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK51DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK51D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S9781": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9781.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL16Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P433F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P433F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1100-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11U66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1112FHI33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32HG322F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG322F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG322F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM4F132C4QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F132C4QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L071K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3HMFZDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MK21DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4R9AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF367M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF367N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F411CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32G840F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G840F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NM1100FBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG13P231F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L041F6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F042G6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042G4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F439ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32HG220F64R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG220F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG220F64R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "CMSDK_CM7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L100R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xBA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM4G9FDXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "NANO112SB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ARMCM4": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM4/Include/ARMCM4_FP.h", "define": "ARMCM4_FP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM4.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM7/Include/ARMCM7_DP.h", "define": "ARMCM7_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM7.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM0": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0/Include/ARMCM0.h", "define": "ARMCM0"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM3": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM3/Include/ARMCM3.h", "define": "ARMCM3"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "EZR32WG330F256R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HC32M140F8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32M140FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S328": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s328.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S5T36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s5t36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL36Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151R8xxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M2351KIAAEES": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "EFM32LG380F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG380F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM14Z128xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP128_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM14ZA5.h", "define": "MKM14Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKM14Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4S5AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "EFR32FG13P232F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P232F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P232F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11C14FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Cxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ADSP-CM419F": {"core": "Cortex-M4", "vendor": "Analog Devices:1", "sectors": [[285212672, 4096], [285736960, 4096]], "algorithm": {"Flash/CM41x_FlashB_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11080000"}, "Flash/CM41x_FlashA_512.FLM": {"default": "1", "ramsize": "0x10000", "size": "0x00080000", "ramstart": "0x10008000", "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.1.3.0.pack", "compile": {"header": "Device/inc/M0/CM41x_M0_device.h"}, "pdsc_file": "http://download.analog.com/tools/EZBoards/CM41x/Releases/AnalogDevices.CM4xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x11080000", "size": "0x00080000"}, "IRAM1": {"start": "0x200F0000", "size": "0x00008000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x11000000", "size": "0x00080000"}}, "debug": "SVD/CM41x_M4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L071KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L162RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC240LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "CMSDK_CM3": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM3/Include/CMSDK_CM3.h", "define": "CMSDK_CM3"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM3.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "ATSAMV71N20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71N20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MB9BF216S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NANO100KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EZR32LG230F128R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK22FN512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F51212_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN512VMP12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F51212_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK22F51212.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S6537": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6537.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9997": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9997.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG11B540F64GQ80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG230F128R60": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S2110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MB9AF114L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF114M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF114N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK40DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK40D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "HT32F1655": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32HG320F64R69": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32GG11B510F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3N1A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00010000"}}, "debug": "SVD/SAM3N/ATSAM3N1A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1E14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MKL26Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL26Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9869QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9869.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAM3S4B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3S/ATSAM3S4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "MKV11Z64xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV1x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MKV_P64_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV11Z64VLH7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV11Z7_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKV11Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32G890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L083CB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M054LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F230E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F230E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54101J256UK49": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L083CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F769F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F760_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F760"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SKEAZ64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZ1284.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "XMC1402-F064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F373R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1201-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F373RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S6918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMG54G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32LG900F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG900F256"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG900F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4E8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4E_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4E/sam4e.h", "define": "__SAM4E8E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4E/ATSAM4E8C.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F048C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F048xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52220_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1125JBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC112x\\LPC112x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC112x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MKL27Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL27Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F334C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F205ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C18L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKL43Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL43Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL43Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL43Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG222F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG222F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG222F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF129T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LPC1113FHN33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9AF144N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A140NA\\mb9a140n.h", "define": "MB9AF144N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF14xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MK28FN2M0Axxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28FA15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK28FN2M0AVMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK28FA15_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x34000000", "size": "0x080000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK28FA15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "EFR32FG1V032F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V032F256GM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V032F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200LD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1P131F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2C19H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L072V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ZD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "TMPM4G8FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32FG12P231F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMG55J19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG55\\samg55.h", "define": "__SAMG55J19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG55\\ATSAMG55J19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S612": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s612.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F732RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32GG332F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG332F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15BU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15BU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC472JG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "GD32F330G6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1231E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC131SC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC131\\Include\\NUC131.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC131AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S617": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s617.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC804M101JDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC80x_32.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC804.h", "define": "LPC804M101JHI33"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC804.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "15000000"}}, "MB9AF121K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF121L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192]], "algorithm": {"Flash/MB9A420L_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A120L\\mb9a120l.h", "define": "MB9AF121L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2D35GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1231E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1231E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32BG1V132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF50NN15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF50NN151MK40.svd", "processor": {"fpu": "DP_FPU"}}, "M451MSC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F130C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130C4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "GD32F130C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMG53G19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG53\\samg53.h", "define": "__SAMG53N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG53\\ATSAMG53G19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E13FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32TG108F4": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32TG/EFM32TG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG11B120F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1201-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F190R6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F190R4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32WG330F256R55": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R55.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S3Z26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s3z26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F190R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD51G18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAMD51G18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32TG108F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG108F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF522L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF522M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAM3N0A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100LC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330C4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "MB9BF522K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF52xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F330C8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "Mini51ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "MK27FN2M0Axxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27FA15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK27FN2M0AVMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27FA15_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x34000000", "size": "0x080000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK27FA15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "TLE9867QXW20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9867.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle986x.h", "define": "TLE9869QXA20"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE986x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE986x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F50231": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "HT32F50230": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32L4A6VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "GD32F330CB": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAMV70J20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70J20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F756NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "M451SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG230F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG230F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG230F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L452CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L452xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF132L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "MB9AF132N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32HG309F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG309F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG309F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF132K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [4096, 61440], [65536, 65536]], "algorithm": {"Flash/MB9AF13x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A130N\\mb9a130n.h", "define": "MB9AF132N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3UltraLowLeak_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF13xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F722RE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MKL13Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL13Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL13Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL13Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG110F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4300-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4300_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4300c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4300_series/Include/XMC4300.h", "define": "XMC4300_F100x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x0FFC0"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4300.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S3739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC4500-F100x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NUC442RI8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "M0564RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF504R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM470FZFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F429II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32BG1P232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "GD32F405RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32F768AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC100LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0564VG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/M0564_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0564_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0564_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0564\\Include\\M0564.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M0564AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF504N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC123LC2AN1": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MKV46F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV46F256VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV46F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV46F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "NM1330LC1AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F405RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2C38J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F405RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "XMC1402-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK65FX1M0xxx18WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L451VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM330FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L451VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK63FN1M0xxx12WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK63FN1M0VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK63F12WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK63F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "XMC1301-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NUC120RE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32HG310F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG310F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG310F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32FG13P231F512IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG13P/Include/em_device.h", "define": "EFR32FG13P231F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG13P/EFR32FG13P231F512IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S5R36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s5r36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1776": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1776.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F50231_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "STM32F777II": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "ATSAMC20E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC20/ATSAMC20E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF316M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A310A\\mb9a310n.h", "define": "MB9AF316N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9AF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL05Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4104-Q48x64": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F111E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F111E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M052LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M052_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32GG395F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG395F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG395F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5P31": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p31.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMCM33_DSP_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MIMXRT1021xxxxx": {"core": "Cortex-M7", "vendor": "NXP:11", "sectors": [[1610612736, 4096]], "algorithm": {"arm/MIMXRT1021_QuadSPI_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x800000", "ramstart": null, "start": "0x60000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMXRT1021DAG5A"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.pdsc", "memory": {"SRAM_OC": {"start": "0x20200000", "size": "0x020000"}, "SRAM_DTC": {"start": "0x20000000", "size": "0x010000"}, "SRAM_ITC": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MIMXRT1021.xml", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "500000000"}}, "MK65FN2M0xxx18WS": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18WS_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "MKL17Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL17Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S9AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32WG940F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG940F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "M484SGAAE2U": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC120RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKL33Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL33Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L433CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L433CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C1232E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1232E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B820F2048GL192": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL192.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NANO112RB1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAMD51J20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51J20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "HT32F52241_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM4F120E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F120E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32PG12B500F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L152CBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC54113J128": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54113J256UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54113.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "nRF52832_xxAB": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\nrf52.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F302ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC4074FBD144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "SN32F235J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32PG1B100F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52331": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1403-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S310": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s310.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "MK20DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S316": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s316.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S317": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s317.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LPC11E37FBD64/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S315": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s328.h", "define": "LM3S328"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s315.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F207IF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x000C0000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MK22DX256xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF415R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMDA1G14B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1b/svd/ATSAMDA1G14B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TMPM3H6FSDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1G14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1G14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG842F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG842F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG842F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HT32F52352_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B840F1024GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71Q19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71Q19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC1114FBD48/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1301-T038x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Mini54ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M452SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32L011E4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM341FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM341_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "54000000"}}, "NUC121LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC121_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC121_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC121_LD_4_5.FLM": {"default": "0", "ramsize": null, "size": "0x1200", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC121\\Include\\NUC121.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC121AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TLE9842-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285249536, 4096]], "algorithm": {"Flash/TLE9842_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x11009000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9842_2.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x800"}, "IROM1": {"start": "0x11000000", "size": "0xA000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52354_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1226FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32F030C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG210F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG210F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG210F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC844M201JBD64": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC844.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "MKV44F128xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP128_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "ATSAMD21E16BU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16BU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1P332F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P332F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P332F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG842F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG842F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322i": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F030C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32ZG110F16": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1833": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x40000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x40000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC1830": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436207616, 8192], [436273152, 65536], [436273152, 65536], [452984832, 8192], [452984832, 8192], [453050368, 65536], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_256_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x1B000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW21D256xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/MK_P256_50MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW24D5.h", "define": "MKW24D512xxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00010000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW21D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1837": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "LPC11D14FBD100/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11D14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F350K6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LPC18S30": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x18000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "MKW36Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM461F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM461_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M461.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC18S37": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC18xx.h", "define": "LPC18xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1800_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC18xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F22366_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F0008": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0008"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F0008.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK51DN256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK11DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120SE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "XMC1402-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71N21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71N21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F0006": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL14Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL14Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF117T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B110T\\mb9b110t.h", "define": "MB9BF118T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF11xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F437IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "nRF52840_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\nrf52840.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "STM32F745ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1200-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMS70J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32F446ME": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M058LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32LG940F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG940F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H5FUDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F412VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F412Zx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F412xG.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "NANO110SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F410R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4700-F144x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM370FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM370_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M370.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE02Z16xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "Flash/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.1.8.1.pack", "compile": {"header": "Device/Include/MKE02Z4.h", "define": "MKE02Z16xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KExx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFE00", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MKE02Z2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "ATSAMD51N20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51N20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L041G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC442RG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "NANO102ZC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "LM3S818": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s818.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD10C14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD10_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD10\\Include\\samd10.h", "define": "__SAMD10D14A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD10\\ATSAMD10C14A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMG54N19": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAMG_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMG_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\SAMG54\\samg54.h", "define": "__SAMG54N19__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD\\SAMG54\\ATSAMG54N19.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F042F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MM32x031": {"core": "Cortex-M0", "vendor": "MindMotion:132", "sectors": [[134217728, 1024]], "algorithm": {"Flash/MM32x031_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.1.0.0.pack", "compile": {"header": "Device/Include/MM32x031.h", "define": "MM32x031"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x031_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/MM32x031.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F042F6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F429ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B540F64GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S2671": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2671.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1347FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1315FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM3S2678": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2678.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F745ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NM1824FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0519LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0519_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/M0519_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0519_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0519\\Include\\M0519.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M0519AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L4S5VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC11U67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F401CB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "STM32F401CD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "LPC54608J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54608.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "NUC120VD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG12P332F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P332F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMV71J20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71J20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MK65FN2M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK65FX1M0VMI18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK65F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK65F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "Generic_Mini51_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "STM32F042T6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HC32F003C4UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F003.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.1.0.0.pack", "compile": {"header": "Device/Include/HC32F003.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F003.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32F003.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKM32Z64xxx5": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MKMP64_1KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34ZA5.h", "define": "MKM34Z128Axxx5"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKM32Z5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG13P733F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P733F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P733F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L083RB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M451RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52344": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM46BF10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM46B_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}, "IRAM2": {"start": "0x20080000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M46B.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F479BI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK10DN32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L4S9VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S5Y36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s5y36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9790": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9790.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F405VG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1B132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC120RC1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L052C8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F411VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F411xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F411xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F411xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM470FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1114FHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1302-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L052C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF366R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EZR32HG320F32R60": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R60.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC4800-F144x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKV30F128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV30F64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV30F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L471ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F32R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L471ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L471xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L4R7VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32LG230F128R55": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1317FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1225FBD48/321": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_80.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x14000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x14000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "XMC1202-T016x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1V132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M483KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LM3S828": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s828.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini57EDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32G880F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G880F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MVF60NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "EFM32TG11B540F64GM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P132F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF366N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1958": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1958.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF366L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF366M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003C000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG330F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG330F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC100VD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32MG13P732F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MVF60NS15xxxx40": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF60NS151MK40.svd", "processor": {"fpu": "SP_FPU"}}, "MB9BF306N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F107F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F100_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.1.0.2.pack", "compile": {"header": "Device\\Include\\SN32F100.h", "define": "SN32F100"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F1_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "SN32F766BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC832M101FDH20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC83x.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F078VB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF306R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "CMSDK_CM4_FP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM4/Include/CMSDK_CM4_FP.h", "define": "CMSDK_CM4_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM4_FP.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F401RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F401x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "ADuCM320": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM320.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1C26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1c26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC4700-F100x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM383FSUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L051C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32LG230F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK60FN1M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F15.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "150000000"}}, "M4TKLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "XMC4500-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9879QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 126976]], "algorithm": {"Flash/TLE9879.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1101EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0x1EFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F101T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MK60FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.1.5.0.pack", "compile": {"header": "Device/Include/MK66F18.h", "define": "MK66FX1M0xxx18"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K60_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK60F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476MG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9AF104R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A100A\\mb9a100r.h", "define": "MB9AF104R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S5C36": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c36.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG360F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG360F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-T038x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1112JHI33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9BN5": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9bn5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKE06Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE06Zxxx_P64KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE06Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKE06Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "Mini57FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini57_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini57_AP_29_5.FLM": {"default": "1", "ramsize": null, "size": "0x7600", "ramstart": null, "start": "0x00000000"}, "Flash/Mini57_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini57\\Include\\Mini57Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7600"}}, "debug": "SVD\\Nuvoton\\MINI57DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52344_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H0FSDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F130R8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U68JBD100": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H1FWUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B340F64IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF102N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "HT32F52231_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF102R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9BF10xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1302-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DF5JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S5D91": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d91.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO130SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32LG360F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG360F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2C49H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "M4LEDLG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "AC30M1432": {"core": "Cortex-M0", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC30M1x64/Flashloader/AC30M1x64_64.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.1.0.1.pack", "compile": {"header": "AC30M1x64/Core/include/AC30M1x64.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "AC30M1x64/SVD/AC30M1x64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2C48H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C4/Include/s6e2c4.h", "define": "S6E2C4AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C4.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD21E17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21E17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "SN32F755J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F750_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F750_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760.h", "define": "SN32F750"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F760.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF324L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG14P733F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P733F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P733F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32PG1B100F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B100F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF324K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF32xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO110RD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32WG890F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG890F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1230E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1230E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2DF5G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM4CMS32C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4C32_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM32/Include/sam4cm32.h", "define": "__SAM4CMS32C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x01100000", "size": "0x100000"}, "IRAM1": {"start": "0x20100000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/SAM4CM32/ATSAM4CMS32C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMDA1E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1E15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F105V8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini52ZDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAME53J18A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "svd/ATSAME53J18A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFM32LG390F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG390F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO120SC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFM32PG12B500F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG12B/Include/em_device.h", "define": "EFM32PG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32PG12B/EFM32PG12B500F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1202-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG14P732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P732F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M487JIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32JG12B500F1024IL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024IL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG390F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG390F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG390F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MAX32660": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32660.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32660.flash": {"default": "0", "ramsize": "0x00018000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.1.0.5.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32660/Include/max32660.h", "define": "MAX32660"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32660.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MAX32660/max32660.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "NANO110KC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LPC54113J128BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/LPC54113.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MKW36A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/KW36x_D256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/KW36x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW36Z4.h", "define": "MKW36Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKW36A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD51J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "EFR32FG1V131F32GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F32GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1114LVFHN24/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U35FHN33/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1100DBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "XMC1302-T038x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "M058SFAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1518JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC54605J256ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "HT32F52354_46QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L431RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L431RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L431xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P132F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P132F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P132F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M2351KIAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [268435456, 2048]], "algorithm": {"Flash/M2351_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M2351_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M2351_NS.FLM": {"default": "0", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M2351\\Include\\M2351.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M2351_v1.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "64000000"}}, "EFM32LG332F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG332F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F091CC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F091xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G232F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G232F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "M058ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32JG1B200F256IM48": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9BF414R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EFM32JG1B100F128GM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B100F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B100F128GM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG380F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG380F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF414N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMS70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "STM32L486RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TLE9877QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 61440]], "algorithm": {"Flash/TLE9877.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x1100EFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1800"}, "IROM1": {"start": "0x11000000", "size": "0xEFFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "M452YD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "M451MLC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG14P231F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NANO100LC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32MG1B732F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B732F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK50DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM333FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM33x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32FG12P431F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1301-T016x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MKL43Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL43Z4.h", "define": "MKL43Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL43Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MIMX8MQ6xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "EFM32GG11B510F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM333FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM33x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M333.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32WG295F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG295F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NM1100XBAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F745VG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F745xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32WG942F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG942F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG942F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101T4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFR32FG1P131F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG13P632F512GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32FG1P131F64GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P131F64GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2CC9H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MKE15Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE15Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE15Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM": {"start": "0x1fffe000", "size": "0x8000"}}, "debug": "MKE15Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF124K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF12xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1767": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MB9BF514R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAM4N16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"Flash/ATSAM4N_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4N/sam4n.h", "define": "__SAM4N8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x00400000", "size": "0x100000"}}, "debug": "SVD/SAM4N/ATSAM4N16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "SN32F767BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P16_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B340F64IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMV71Q21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71Q21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKS22FN128xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKS22FN256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKS22F12_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0xc000"}}, "debug": "MKS22F12.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NM1200TAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NM1530VD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1500_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1500_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1500_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1500_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HC32L110C4PA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B4_C4.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "CMSDK_CM7_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_CM7/Include/CMSDK_CM7_DP.h", "define": "CMSDK_CM7_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_CM7_DP.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "MKE14F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 2048]], "algorithm": {"arm/MKE1x_P256_4KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14F512VLL16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14F16_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKE14F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32GG11B510F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "NUC123LD4AN0": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_68.FLM": {"default": "1", "ramsize": null, "size": "0x11000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC123\\Include\\NUC123.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x11000"}}, "debug": "SVD\\Nuvoton\\NUC123AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "TM4C123BH6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F328C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "Mini58FDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2_5.FLM": {"default": "0", "ramsize": null, "size": "0xa00", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini58\\Include\\Mini58Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\MINI58DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F212H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM4F212H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F769NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "TMPM4G8FDXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3HMFYDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG295F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG295F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC472VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TMPM4G7FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_512.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LPC1519JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x9000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX256xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"Flash/MK_D256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S1165": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1165.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F030R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HE6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1162": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1162.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2HE6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HE6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HE/Include/S6E2HExG/s6e2hexg.h", "define": "S6E2HE6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hexg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L082CZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L082xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F417ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "HT32F12365": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NANO112RC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO112\\Include\\Nano1x2Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO112AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "ATSAML22G18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML22_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML22_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML22\\Include\\saml22.h", "define": "__SAML22N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML22\\ATSAML22G18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F768BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC130RD2CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S9U92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32GG11B510F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U90": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u90.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S9U96": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u96.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG840F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG840F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ADuCM322": {"core": "Cortex-M3", "vendor": "Analog Devices:1", "sectors": [[0, 2048]], "algorithm": {"Flash/ADUCM320.FLM": {"default": "1", "ramsize": "0x0800", "size": "0x40000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.1.1.0.pack", "compile": {"header": "ADuCM322\\common\\ADuCM322.h", "define": "ADuCM322"}, "pdsc_file": "http://www.analog.com/media/en/engineering-tools/design-tools/AnalogDevices.ADuCM320_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\ADuCM322.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC11U68JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32G222F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G222F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G222F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC4400-F64x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "MKL17Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL17Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5662": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5662.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L011D3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011D4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EZR32HG320F64R55": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R55.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L476QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMHA1G15AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "samha1ab/keil/flash/ATSAMH_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samha1ab/svd/ATSAMHA1G15AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1G15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1G15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F429IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L052R6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32F401CE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "MK53DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK53D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "MK21DX256Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMV71J19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71b/svd/ATSAMV71J19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFM32TG225F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG225F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG225F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAM3S8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM3SD8/ATSAM3S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "STM32L052R8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F777NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F777xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7652BJ": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F760B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F760B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F760B.h", "define": "SN32F760B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SN32F760B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1P232F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC200LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32H753BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFM32PG1B200F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B120F128GQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4078FBD100": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3J26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3j26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3U2E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3U_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3U/Include/sam3u.h", "define": "__SAM3U4E__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20080000", "size": "0x00004000"}, "IROM1": {"start": "0x00080000", "size": "0x00020000"}}, "debug": "SVD/SAM3U/ATSAM3U2E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "EFM32GG11B840F1024GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32FG1P133F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P133F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P133F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S8630": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s8630.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Generic_Nano100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "NUC505DLA": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096]], "algorithm": {"Flash/NUC505_SPIFLASH.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC505\\Include\\NUC505Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\NUC505_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "100000000"}}, "LPC1226FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "STM32L496VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4CMS4C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMS4C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F765IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "SN32F7741J": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F770_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1fff2000"}, "Flash/SN32F770_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.1.4.3.pack", "compile": {"header": "Device\\Include\\SN32F770.h", "define": "SN32F770"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F7_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\SN32F770.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK81FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK81F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK81FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK81F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK81F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "STM32F303C6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMV71J19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv71/svd/ATSAMV71J19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "S6E2C39J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF518T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "SKEAZN64xxx2": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"Flash/MKE02Zxxx_P64KB.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": null, "size": "0x00000100", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SKEAZN642.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "NANO100SD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32GG11B510F2048GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F1765_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG1B131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1B632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ISD9130": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\ISD9100_v3.svd", "processor": {"clock": "48000000"}}, "MB9BF365L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF365K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG880F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG880F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG880F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF155N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F1656_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TLE9871QXA20": {"core": "Cortex-M3", "vendor": "Infineon:7", "sectors": [[285212672, 32768]], "algorithm": {"Flash/TLE9871.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.1.3.2.pack", "compile": {"header": "Device\\Include\\tle987x.h", "define": "TLE9879QXW40;RTE_DEVICE_BF_STEP"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE987x_DFP.pdsc", "memory": {"IROM2": {"start": "0x11007FFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0xC00"}, "IROM1": {"start": "0x11000000", "size": "0x7FFC"}}, "debug": "SVD\\TLE987x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "MB9AF155M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A150R\\mb9a150r.h", "define": "MB9AF156R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9AF15xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "Mini52ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M451VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32WG840F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG840F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F058T8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F058xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG13P932F512IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P932F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P932F512IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC4088FET208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058SLAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M058S\\Include\\M058S.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M058SAN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S102": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s102.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S101": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s102.h", "define": "LM3S102"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD\\lm3s101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "S6E2D55G0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MKL27Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P64_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00010000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z644_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x400fe000", "size": "0x0200"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}}, "debug": "MKL27Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1402-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "NUC120LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "M0516ZBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC54114J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5411x/chip_5411x/inc/chip.h", "define": "CHIP_LPC5411X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54114_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F733VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "MK40DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x0008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK40D10.h", "define": "MK40DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K40_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK40D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC120LD2DE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC122SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "M453VC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG1V131F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32BG1B132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "S6E2CC8L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM4CMP16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP16C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG1B132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P131F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P131F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P131F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P233F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P233F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P233F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1227FBD64/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "M451LC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32GG11B840F1024IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B520F2048IL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG13P732F512GM51": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG13P/Include/em_device.h", "define": "EFR32MG13P732F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32MG13P/EFR32MG13P732F512GM51.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F207IC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LS8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F207IG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F207xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F401RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F401xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F401xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F401xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "84000000"}}, "EFM32WG395F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG395F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32W108HB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [134481920, 16]], "algorithm": {"Flash/STM32W108_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32W108_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\stm32w108xx.h", "define": "STM32W108HB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32W1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD\\STM32W108.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFR32BG1B132F256GM56": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM56.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC1302-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG232F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG232F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC54605J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54605J512ET180"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54605_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54605.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKV30F64xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}, "arm/MK_P64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV30F64VLH10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV30F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x010000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x2000"}}, "debug": "MKV30F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMD21E16L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000800"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21B/ATSAMD21E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD21_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/SAMD21A/ATSAMD21E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF112N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "TMPM369FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMC20J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC20N/Include/samc20.h", "define": "__SAMC20N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC20/ATSAMC20J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF112M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF112K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [537657344, 8192]], "algorithm": {"Flash/MB9A310_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKE02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512], [268435456, 2]], "algorithm": {"arm/MKE02Zxxx_EE256B.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00000100", "ramstart": "0x1FFFFE00", "start": "0x10000000"}, "arm/MKE02Zxxx_P16KB.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE02Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKE02Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM4CP16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4CP/sam4cp.h", "define": "__SAM4CP16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CP/ATSAM4CP16B_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M2S090": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "LM3S812": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407RG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F52342": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F407RE": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_512KB.FLM": {"default": "1", "ramsize": null, "size": "0x080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x080000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAME53J19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53J19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "LM4F121C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F121C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "NUC140RC1CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ATSAME53N19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME53_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME53_DFP.1.0.1.pack", "compile": {"header": "include/sam.h", "define": "__SAME53J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME53_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAME53N19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M054LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NANO120LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "NUC120VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM3H6FUFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "M054LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1114FN28/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F427IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMV70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70/svd/ATSAMV70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "STM32F417ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F417xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9BF165K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1601": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1601.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMDA1E16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1E16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "MB9BF165L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM3H6FWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAMDA1E16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1E16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "TM4C1237H6PGE": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1237H6PGE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG108F16": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/EFM32TG/EFM32TG108F16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC140LE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32WG360F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG360F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG360F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAML21G17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO110KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "ATSAML21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21G17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX32xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IRAM2": {"start": "0x1FFFF000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO120LD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM376FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM37x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M376.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA0J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMDA0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK20D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B420F2048GQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048GQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG990F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG990F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG990F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MWPR1516xxx": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKPR1516_P16KB.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00004000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MWPR1516.h", "define": "MWPR1516xxx"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWPR1516_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFC00", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/MWPR1516.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC54101J512BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54101.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "XMC4100-Q48x128": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [201326592, 16384]], "algorithm": {"Flash/XMC4200_4100_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4200_4100c_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4100_series/Include/XMC4100.h", "define": "XMC4108_Q48x64"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x20000"}, "IRAM1": {"start": "0x20000000", "size": "0x2FC0"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/XMC4100.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG1B232F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B232F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451MLD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2CCAJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "HT32F12366": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "HT32F52231": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HT32F52230": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32GG11B820F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "S6E2C1AL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC1110FD20": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_4.FLM": {"default": "1", "ramsize": "0x03E0", "size": "0x1000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0400"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1200LAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW41Z512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKWxxZ_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW41Z4.h", "define": "MKW41Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW41Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1B232F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F413ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMV71J21B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71b/svd/ATSAMV71J21B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "MKE06Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE06Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE06Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE06Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKE06Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "NUC200VE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32BG1P232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P232F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32GG11B120F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B120F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B120F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF521L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B520T\\mb9b520t.h", "define": "MB9BF529T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9BF52xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMV70N20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70b/svd/ATSAMV70N20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "TMPM3HQFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32L152ZD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L152ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMCM33_DSP_FP_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h", "define": "ARMCM33_DSP_FP_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "STM32F334R8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L152ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F334R6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F334x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F334x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F031C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG14P532F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P532F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P532F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F031C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F031x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4S8B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4S8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4S8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2C59J0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMD51P20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAMD51P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32F765NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32G842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32G/EFM32G842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F427AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32TG11B120F128GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32JG12B500F1024GL125": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG12B/Include/em_device.h", "define": "EFM32JG12B500F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG12B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32JG12B/EFM32JG12B500F1024GL125.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F070CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2939": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2939.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD51P19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51P19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "M0516ZDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF515N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "STM32F427AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F427xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F427x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF515R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF51xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32LG330F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL03Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P8_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00002000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x2000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM4G8FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMV71Q20B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71b/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv71b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71b/svd/ATSAMV71Q20B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "M482LGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F429BG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "NANO100LE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "M451LG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM3S5P51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S5C51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG380F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG380F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5632": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5632.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG14P733F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG14P/Include/em_device.h", "define": "EFR32MG14P733F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG14P/EFR32MG14P733F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC54606J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54606J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54606_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_0_1": {"start": "0x20000000", "size": "0x018000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54606.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F303ZD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F303ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L443VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L443xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MKL02Z16xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P16_48MHZ.FLM": {"default": "1", "ramsize": "0x00000800", "size": "0x00004000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x4000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070C6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F150C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM411F20XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768], [0, 32768]], "algorithm": {"Flash/TMPM41xA_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM41xB_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM411_unitB.h", "define": "TMPM411F20XBG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20008000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\M411_unitA.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54102J256BD64": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "LPCOpen/lpc5410x/chip_5410x/inc/chip.h", "define": "CHIP_LPC5410X"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x00010000"}, "IRAM2": {"start": "0x02010000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/LPC54102_cm4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG12P231F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P231F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P231F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK20DN512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK20D10.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAMC21J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMC_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD/SAMC21/ATSAMC21J15A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFR32FG14P233F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P233F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P233F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM330FDWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC54616J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54616J512ET100"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54616_DFP.pdsc", "memory": {"USB_RAM": {"start": "0x40100000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}, "SRAM_0_1_2_3": {"start": "0x20000000", "size": "0x028000"}}, "debug": "LPC54616.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFM32WG330F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG330F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "TC35679FSG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "HT32F12345_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "STM32F746BG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5D51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5d51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NUC100LD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "SN32F247BF": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64], [536813568, 64]], "algorithm": {"Flash/SN32F240B_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F240B_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0040", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240B.h", "define": "SN32F240B"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453RD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "S6E2GK8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GKXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GK/Include/S6E2GKxJ/s6e2gkxj.h", "define": "S6E2GK8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2gkxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC4800-F144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4800_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0x1FFC0"}, "IRAM2": {"start": "0x1FFEE000", "size": "0x12000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "STM32L476VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L476VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HC32L110C6UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L110B6_C6.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.1.0.1.pack", "compile": {"header": "Device/Include/HC32L110B.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L110.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32L110C.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L476VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L476xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MB9BF468R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMD20E17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20E14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "M453LE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "LM3S3W26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s3w26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1111FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG11B840F1024GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1B632F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B632F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFR32MG1P132F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF468M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF468N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20038000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32WG395F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG395F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG395F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1R21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1r21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAM4C8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}, "Flash/ATSAM4C_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4C/sam4c.h", "define": "__SAM4C16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4C/ATSAM4C8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "RS14100_1MB": {"core": "Cortex-M4", "vendor": "Redpine Signals:125 ", "sectors": [[134291456, 4096]], "algorithm": {"Flash/RS14100_SF_1MB.FLM": {"default": "1", "ramsize": "0x4000", "size": "0xEE000", "ramstart": "0x00000000", "start": "0x08012000"}}, "debug-interface": [], "pack_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.1.0.2.pack", "compile": {"header": "Driver/Common/chip/inc/RS1xxxx.h"}, "pdsc_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x000000C", "size": "0x2FFF4"}, "IROM1": {"start": "0x08012000", "size": "0xEE000"}}, "debug": "SVD/RS1xxxx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "MB9BF565L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B560L/Include/mb9b560l.h", "define": "MB9BF566L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003D000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD/MB9B560L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F469ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "XMC1401-F064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B520F128IM32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "Mini52XLAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "NUC140RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFM32LG842F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG842F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071CB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SE3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TM4C1290NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1290NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TM4C123FH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123FH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F756ZG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F756xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NUC122SC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "ATSAM3N2A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N2C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3N/ATSAM3N2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F071C8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F071xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151QC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "SN32F237F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L151QD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151QE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S1620": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1620.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1621": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1621.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1150": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s1150.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1625": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1625.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1114FHI33/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF417S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1315FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S8530": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8530.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M453RE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9BF417T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S8538": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s8538.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG842F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG842F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG842F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG1V132F128GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F128GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "SN32F248F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9U81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s9u81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MKL33Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL33Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L152VCxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32BG1B132F256GD1": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GD1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L462RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L462xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32BG14P632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG14P/Include/em_device.h", "define": "EFR32BG14P632F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG14P/EFR32BG14P632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L011G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L496AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21G15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21G15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L011G3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32HG320F64R61": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMD21G15L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21G15L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1E14A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"arm_addon/flash/ATSAMDA1_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x200"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "samda1/svd/ATSAMDA1E14A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "STM32F765ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "M0516ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC4072FET80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG822F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG822F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG822F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG332F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG332F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TM4C1237D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "M0516LDN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9AFB44M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AB40NA\\mb9ab40n.h", "define": "MB9AFB44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9AFB4xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F767ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F767xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x7_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "NANO120LC2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32ZG110F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "MK30DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32WG380F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG380F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG1V132F32GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F32GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "XMC4800-F100x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "MKV44F256xxx16": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [4294901760, 36]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV4x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV44F64VLH16"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV44F16_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MKV44F16.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "168000000"}}, "TMPM4G8FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC4700-E196x1536": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_1536.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4700_series/Include/XMC4700.h", "define": "XMC4700_F100x1536"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x180000"}, "IRAM1": {"start": "0x20000000", "size": "0x2CFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x180000"}}, "debug": "SVD/XMC4700.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "HT32F52243_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "GD32F350G6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "ISD9361": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9300_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/ISD9300_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9300_AP_145.FLM": {"default": "1", "ramsize": null, "size": "0x24400", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x24400"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "S6E2D55JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D5_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D5/Include/s6e2d5.h", "define": "S6E2D55JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S1D21": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d21.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M482SGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "LM3S1D26": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1d26.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ARMv8MML_DP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h", "define": "ARMv8MML_DSP_DP"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMv8MML.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "GD32F350G4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "LM4F212H5BB": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F212H5BB.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32MG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMV71J21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "samv71/svd/ATSAMV71J21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "ATSAMV71J20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv71/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv71/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv71b/include/sam.h", "define": "__SAMV71N20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv71/svd/ATSAMV71J20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "HT32F2755_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B732F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B732F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B732F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F769IG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L475RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L475RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32G840F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G840F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G840F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32G280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM4G7F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32L475RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "IOTKit_ARMv8MML": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_ARMv8MML/Include/IOTKit_ARMv8MML.h", "define": "IOTKit_ARMv8MML"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "LM3S1J16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1J11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1j11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F0006_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F0006"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F0006.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52342_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NUC122LC1AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC122\\Include\\NUC122.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC122_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "60000000"}}, "EFM32HG210F64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG210F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32HG/EFM32HG210F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S2616": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2616.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F1656_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NM1823LB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC812M101JD20": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC812.h", "define": "LPC812M101JTB16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC812.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "LM3S1Z16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\lm3s1z16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG330F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F256R68": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC4500-E144x1024": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4500c_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/XMC4500_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4500_series/Include/XMC4500.h", "define": "XMC4504_F100x512"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x100000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/XMC4500.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG1P132F64GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F64GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKL36Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ.FLM": {"default": "1", "ramsize": "0x00008000", "size": "0x00040000", "ramstart": "0x1FFFE000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL36Z64VLL4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL36Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL36Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM373FWDUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM37x_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M373.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1346FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_48.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xC000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xC000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK30DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MK30D10.h", "define": "MK30DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K30_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK30D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAML21G16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"Flash/ATSAML21_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00800", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IRAM2": {"start": "0x30000000", "size": "0x01000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\SAML21\\ATSAML21G16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL27Z256xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P256_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00040000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL27Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL27Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}}, "debug": "MKL27Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1317FBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M2S150": {"core": "Cortex-M3", "vendor": "Microsemi:112", "sectors": [[0, 4096]], "algorithm": {"Flash/M2Sxxx_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack", "compile": {"header": "CMSIS/m2sxxx.h"}, "pdsc_file": "http://cores.actel-ip.com/CMSIS-Pack/Microsemi.M2Sxxx.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/M2Sxxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "166000000"}}, "STM32L071VZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F100RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "TLE9843-2QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285261824, 4096]], "algorithm": {"Flash/TLE9843_2_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100C000"}, "Flash/TLE9843_2.FLM": {"default": "1", "ramsize": null, "size": "0xC000", "ramstart": null, "start": "0x11000000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0D000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F100RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32L071VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L051K6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "NUC126LG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MKW35A512xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/KW36x_P512_2KB_SEC.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW35Z4.h", "define": "MKW35Z512xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MKW35A4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F1655_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L051K8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L051xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L051x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2DH5GJA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DH_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DH/Include/s6e2dh.h", "define": "S6E2DH5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DH.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "TMPM4G9FEXBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFR32MG1P132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32L4R7ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LS8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/SAM4L/ATSAM4LS8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4LS2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LS8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LS2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32MG12P432F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P432F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P432F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G9F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F098VC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F098xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L4S7VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S7xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC54113J256": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54113J256UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54113_DFP.pdsc", "memory": {"SRAM2": {"start": "0x20020000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x20010000", "size": "0x010000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54113.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32H743ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "ATSAMDA0J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMDA0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.1.0.1.pack", "compile": {"header": "Device\\SAMDA0\\Include\\samda0.h", "define": "__SAMDA0J16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMDA0\\ATSAMDA0J16A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F746NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC1114FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F765VI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11E67JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MML": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32L4R9ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4R9xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4R9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F746NE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2228224, 131072], [2359296, 262144], [134217728, 32768], [134348800, 131072], [134479872, 262144]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F746xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x6_v1r1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG14P231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG14P/Include/em_device.h", "define": "EFR32FG14P231F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG14P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32FG14P/EFR32FG14P231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32ZG110F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F769AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32F405OG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EZR32LG230F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P632F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P632F512IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P632F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32LG380F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG380F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG380F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F105RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F105xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EZR32LG330F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG330F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32HG320F32R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EZR32HG/EZR32HG320F32R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EFM32ZG110F8": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG110F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32ZG/EFM32ZG110F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LM3S808": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s828.h", "define": "LM3S828"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s808.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32LG230F128R67": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG230F128R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K6": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HT32F22366": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LPC11U14FHI33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAML21J18B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAML21_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\SAML21\\ATSAML21J18B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL17Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z64VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z644_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff800", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL17Z644.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F303K8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F303xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F303x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F072R8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F072xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F230H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F230H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TM4C1237E6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF364K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF364L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360L/Include/mb9b360l.h", "define": "MB9BF366L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B360L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F215RG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D42": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D42.svd", "processor": {"fpu": "DP_FPU"}}, "STM32F215RE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F215xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F21x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L071V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L071xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1B132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1B/Include/em_device.h", "define": "EFR32MG1B132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1B/EFR32MG1B132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC11U67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M452RC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "nRF52810_xxAA": {"core": "Cortex-M0", "vendor": "Nordic Semiconductor:54", "sectors": [[0, 4096], [0, 4096], [268439552, 4096]], "algorithm": {"Flash/nrf52xxx_sde.flm": {"default": "0", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx.flm": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/nrf52xxx_uicr.flm": {"default": "1", "ramsize": "0x4000", "size": "0x1000", "ramstart": "0x20000000", "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.8.16.0.pack", "compile": {"header": "Device\\Include\\nrf.h", "define": "NRF52840_XXAA"}, "pdsc_file": "http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/NordicSemiconductor.nRF_DeviceFamilyPack.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x30000"}}, "debug": "SVD\\nrf52810.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "64000000"}}, "TM4C1237E6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C1237E6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S6911": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6911.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F100R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_HD_VL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F100xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ATSAMD51G19A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAMD51_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMD51N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD51_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "svd/ATSAMD51G19A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "STM32L072VB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F469II": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "M483SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "NUC120LC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F150K8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S5P56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s5p56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "S6E2H14G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H14F": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xf.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "S6E2H14E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2H14X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2H1/Include/S6E2H1xG/s6e2h1xg.h", "define": "S6E2H16G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFC000", "size": "0x00004000"}, "IRAM2": {"start": "0x2003E000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/s6e2h1xe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "GD32F150K6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01800"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "S32K148": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"addon_cmsis/Flash/S32K148_P1536_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x00000000"}, "addon_cmsis/Flash/S32K148_D512_4KB_SEC.FLM": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00080000"}, "IRAM1": {"start": "0x20000000", "size": "0x0001F000"}, "IRAM2": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "platform/devices/S32K148/S32K148.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32F469IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MKL33Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL33Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL33Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL33Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B140F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DN128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1403-Q064x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F070RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F070xB"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "HC32L150FA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150FX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMA5D44": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D44.svd", "processor": {"fpu": "DP_FPU"}}, "STM32L4A6QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMA5D41": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D41.svd", "processor": {"fpu": "DP_FPU"}}, "TMPM3HQFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HQ.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMA5D43": {"core": "Cortex-A5", "vendor": "Microchip:3", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.1.1.1.pack", "compile": {"header": "Device/Include/SAMA5D2.h", "define": "SAMA5D44"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMA5_DFP.pdsc", "memory": {}, "debug": "SVD/ATSAMA5D43.svd", "processor": {"fpu": "DP_FPU"}}, "EFM32GG290F512": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG290F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFM32GG/EFM32GG290F512.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAME70Q19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAME7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME70N20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-E_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAME70Q19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "EFR32MG1P632F256IM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P632F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P632F256IM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M0516LDE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051DE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52243": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL16Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL16Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L072KZ": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_192.FLM": {"default": "1", "ramsize": null, "size": "0x00030000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00030000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123BH6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F407RK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LPC11U24FHI33/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L072KB": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134742016, 3072], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07_8x_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001800", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L072xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00005000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L433RB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L433RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L433xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4LC2A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAM4L_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4L/sam4l.h", "define": "__SAM4LC8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAM4L/ATSAM4LC2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MKL17Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P128_48MHZ_KL43.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL17Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL17Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1fffe000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL17Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F190C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NUC472KG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "TM4C123BH6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C123BH6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "GD32F130F8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO130KD2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "TMPM342FYXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 16384], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/TMPM342_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00009000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC1402-F064x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD21E15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21A/ATSAMD21E15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1114JHN33/333": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_56.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0xE000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xE000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAMD21E15L": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAMD21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAMD21_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x00000400"}, "IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/SAMD21B/ATSAMD21E15L.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G290F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G290F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130F4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG11B120F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F130F6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "M481ZIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "TMPM36BF10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040800"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M36B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S9971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s9971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG825F8": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG825F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/EFM32TG/EFM32TG825F8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9AF111K": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768], [537657344, 8192]], "algorithm": {"Flash/MB9A310_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xK.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "NUC240LE3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "MB9AF111N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF111L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 32768]], "algorithm": {"Flash/MB9BFx01_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F405RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F405xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "STM32L4S5ZI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 8192], [134217728, 4096]], "algorithm": {"CMSIS/Flash/STM32L4Rx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L4Rx_2048_Dual.FLM": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4S5xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32L4S5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK12DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"arm/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "arm/MK_D64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK12DX256VMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK12D5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK12D5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1120FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1120_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/NM1120_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1120_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\NM1120AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330F8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "XMC1201-T038x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "AC33M3064": {"core": "Cortex-M3", "vendor": "ABOV Semiconductor:126", "sectors": [[0, 128]], "algorithm": {"AC33Mx064/Flashloader/AC33Mx064_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.1.2.2.pack", "compile": {"header": "AC33Mx064\\Core\\include\\AC33Mx064.h"}, "pdsc_file": "http://www.abov.co.kr/data/mds/PACK/ABOV.CM3_DFP.pdsc", "memory": {}, "debug": "AC33Mx064\\SVD\\AC33Mx064.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F330F4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S2948": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2948.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S9D81": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d81.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F407ZE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "NANO110RC2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F429BE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EZR32WG330F256R67": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R67.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1202-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MK10DX128xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P128_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32WG330F256R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164K": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MIMX8MQ5xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ5DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ5_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ5.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "EFM32GG232F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG232F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG232F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32WG330F256R69": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32WG/EZR32WG330F256R69.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MB9BF164L": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160L/Include/mb9b160l.h", "define": "MB9BF166L"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003E000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/MB9B160L.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "EFM32LG280F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG280F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1811": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1811.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK20FN1M0xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/MK20F12.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F103R4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1816": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1816.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103R6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F437VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F103R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MVF61NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF61NS151MK50.svd", "processor": {"fpu": "SP_FPU"}}, "STM32F107VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM343FEXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM343_768.FLM": {"default": "1", "ramsize": null, "size": "0x000C0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM343.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M343.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F407IG": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"Flash/GD32F4xx_1MB.FLM": {"default": "1", "ramsize": null, "size": "0x0100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F407 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC240LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_LD_8.FLM": {"default": "0", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC230_240\\Include\\NUC230_240.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "ATSAMV70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EZR32WG230F64R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG230F64R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG295F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG295F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG295F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 40]], "algorithm": {"Flash/STM32L1xx_512_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000028", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_512_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00014000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 32]], "algorithm": {"Flash/STM32L1xx_384_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000020", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32L1xx_384_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00003000", "ramstart": null, "start": "0x08080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L151VB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L1xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "XMC1301-Q040x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F101ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "HT32F52352_64LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52342_52"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52342_52.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F101ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "STM32F101ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x14000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "TMPM3H1FUUG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F101ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "MB9BF416T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "TMPM3HMFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF416R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF416S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LPC1112FD20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAMD20E18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20E18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MB9AF342M": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MB9AF342N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A340NA\\mb9a340n.h", "define": "MB9AF344N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF34xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "SN32F249F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F240_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}, "Flash/SN32F240_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F240"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0xFFFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F410TB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F410xx_412xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F410Tx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F410xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32ZG108F4": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32ZG.FLM": {"default": "1", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32ZG/Include/em_device.h", "define": "EFM32ZG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32ZG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00001000"}}, "debug": "SVD/EFM32ZG/EFM32ZG108F4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "EZR32LG330F128R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM3H6FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LM3S1968": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s1968.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC120LD3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF416N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF41xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "EZR32LG330F128R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32LG390F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG390F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG390F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EZR32LG330F128R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32LG/EZR32LG330F128R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKL02Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x1FFFFC00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL02Z8VFG4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL02Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffc00", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL02Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ML630Q466": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "sectors": [[0, 1024]], "algorithm": {"Flash/ML630Q466.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/ML630Q466.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "ML630Q464": {"core": "Cortex-M0+", "vendor": "Lapis Semiconductor:10", "sectors": [[0, 1024]], "algorithm": {"Flash/ML630Q464.FLM": {"default": "1", "ramsize": "0x400", "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.1.0.0.pack", "compile": {"header": "Device/Include/ML630Q466.h"}, "pdsc_file": "http://www.lapis-semi.com/en/data/sample-file_db/miconlp/LAPISSemiconductor.ML630Q46x_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/ML630Q464.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "XMC1402-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMC21J18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21J18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F051K8": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM381FWDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM381_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M381.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F051K6": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC4074FBD80": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F051K4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F051x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11U24FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1800"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1330LD2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/NM1330_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NM1330_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1330_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NM1330AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF217T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF217S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF21xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "ATSAMV70N19B": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70b/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}, "samv70b/keil/flash/ATSAMV7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "samv70b/svd/ATSAMV70N19B.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "EFR32FG1P132F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1P/Include/em_device.h", "define": "EFR32FG1P132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1P/EFR32FG1P132F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MK27FN2M0xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MK_P2M0.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27F15_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK27FN2M0VMI15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK27F15_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x200000"}, "SRAM_LOWER": {"start": "0x1ffc0000", "size": "0x040000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x040000"}}, "debug": "MK27F15.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "MB9BF104N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx04_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B100A\\mb9b100r.h", "define": "MB9BF106R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF10xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3HNFDDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "NANO110KE3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_123.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "EFR32BG1B232F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6965": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000B800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6965.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32BG1B232F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1B/Include/em_device.h", "define": "EFR32BG1B232F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1B/EFR32BG1B232F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF516N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF51xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "NUC100RD2DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "S6E2G38H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G3XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G3/Include/S6E2G3xJ/s6e2g3xj.h", "define": "S6E2G38J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2g3xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TM4C1233H6PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_256.FLM": {"default": "1", "ramsize": null, "size": "0x040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x040000"}}, "debug": "SVD/TM4C123/TM4C1233H6PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32TG11B340F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F103RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1201-T028x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F107RB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F107RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_CL.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_CL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/STM32F107xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1518JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC1548JBD100": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM4F210H5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F232H5BB.h", "define": "LM4F232"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F210H5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32LG842F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG842F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-T038x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF418S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2C28L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFR32MG1V132F256GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1V/Include/em_device.h", "define": "EFR32MG1V132F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1V/EFR32MG1V132F256GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF418T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B410T\\mb9b410t.h", "define": "MB9BF418T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF41xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S32K146": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/S32K146_P1024_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000F000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "platform/devices/S32K146/S32K146.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "SN32F263X": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 64]], "algorithm": {"Flash/SN32F260_30.FLM": {"default": "1", "ramsize": null, "size": "0x7800", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F260.h", "define": "SN32F260"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x77FC"}}, "debug": "SVD\\SN32F260.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S32K144": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"addon_cmsis/Flash/S32K144_P512_4KB_SEC.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.1.2.0.pack", "compile": {"header": "platform/devices/device_registers.h", "define": "CPU_S32K148"}, "pdsc_file": "http://www.keil.com/pack/Keil.S32_SDK_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "platform/devices/S32K144/S32K144.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "112000000"}}, "STM32L475QE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2G26J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32L475QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L475xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "S6E2G26H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2G2XX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2G2/Include/S6E2G2xJ/s6e2g2xj.h", "define": "S6E2G28J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2g2xh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "LM4F112H5QD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54605J512ET180": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54605.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "LM3S1637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Z32F38412ALS": {"core": "Cortex-M3", "vendor": "Zilog:89", "sectors": [[0, 256]], "algorithm": {"Flash/Z32F3841.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.1.0.4.pack", "compile": {"header": "Device/Include/Z32F3841.h"}, "pdsc_file": "http://www.ixys.com/Zilog/packs/Zilog.ZNEO32_DFP.pdsc", "memory": {}, "debug": "SVD/Z32F3841.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "MK10DN64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F112H5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LM4F112H5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC54618J512BD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"Flash/LPC5460x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.2.6.0.pack", "compile": {"header": "Device/Include/LPC54628.h", "define": "LPC54628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC54000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IRAM2": {"start": "0x04000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/LPC54618.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "220000000"}}, "STM32F429VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "Mini52TAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "LPC1112LVFHN24/003": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xxLV\\LPC11xxLV.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11xxLV_LPC111x_LV.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100LD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11U68JBD64": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_160.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\LPC11U6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F22366_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "MKL03Z32xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MK_P32_48MHZ_KL03.FLM": {"default": "1", "ramsize": "0x800", "size": "0x00008000", "ramstart": "0x1FFFFE00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL03Z8VFK4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL03Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffffe00", "size": "0x0800"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x8000"}}, "debug": "MKL03Z4.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC43S37": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[436207616, 8192], [436273152, 65536], [452984832, 8192], [453050368, 65536]], "algorithm": {"Flash/LPC18xx43xx_512_BA.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1A000000"}, "Flash/LPC18xx43xx_512_BB.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x1B000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.2.8.0.pack", "compile": {"header": "Device/Include/LPC43xx.h", "define": "CORE_M0SUB"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4300_DFP.pdsc", "memory": {"IROM2": {"start": "0x1B000000", "size": "0x80000"}, "IRAM1": {"start": "0x10000000", "size": "0x08000"}, "IRAM2": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x1A000000", "size": "0x80000"}}, "debug": "SVD/LPC43xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "204000000"}}, "XMC1202-T028x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "Generic_NUC100_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MIMX8MQ7xxxHZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MQ7DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MQ7_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MQ7.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "LPC845M301JHI48": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "EFR32FG1V131F128GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V131F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V131F128GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "HT32F50241_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F50231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HT32F50231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "EFM32LG890F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG890F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG890F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MKM34Z256xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"Flash/MKMP256_2KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MKM34Z7.h", "define": "MKM34Z256xxx7"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KMxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFE000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MKM34Z7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "75000000"}}, "EFM32WG280F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG280F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG280F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052T8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32LG290F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG290F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L052T6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L052xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L052x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM383FWEFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM383_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM384.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002800"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M383.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32PG1B200F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32PG1B/Include/em_device.h", "define": "EFM32PG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32PG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32PG1B/EFM32PG1B200F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "40000000"}}, "EZR32WG330F64R61": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32WG/EZR32WG330F64R61.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK21FX512Axxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512AVMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21FA12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21FA12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F030F4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG990F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG990F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG990F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F415RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F415xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F41x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "MB9AFA41N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MKL15Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG330F64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG330F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32WG/EFM32WG330F64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "MK66FX1M0xxx18": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MK_P1M0.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "arm/MKD256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK66FX1M0VMD18"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK66F18_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x040000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x100000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK66F18.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM330FYWFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFM32TG11B540F64GM80": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B540F64IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B540F64GM80.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2HG6G": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxg.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9AFA41L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [2097152, 8192]], "algorithm": {"Flash/MB9AB40_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/MB9xFxxx_32DWF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00200000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9AA40NA\\mb9aa40n.h", "define": "MB9AFA44N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3LowPower_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\MB9AFA4xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "S6E2HG6E": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2HG6X0A.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2HG/Include/S6E2HGxG/s6e2hgxg.h", "define": "S6E2HG6G"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF8000", "size": "0x00008000"}, "IRAM2": {"start": "0x2003C000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2hgxe.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F413CH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "S6E2C2AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C2/Include/s6e2c2.h", "define": "S6E2C2AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "GD32F170C8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32G842F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G842F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32G/EFM32G842F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL25Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL26Z4.h", "define": "MKL26Z64xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL25Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S1W16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s1w16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "Mini54LAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "M484KIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "STM32F733ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F733xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "STM32L031G6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LM3S5656": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5656.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "SN32F238F": {"core": "Cortex-M0", "vendor": "SONiX:110", "sectors": [[0, 1024], [536813568, 1024]], "algorithm": {"Flash/SN32F230_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/SN32F230_CO.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FFF2000"}}, "debug-interface": [], "pack_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.1.2.9.pack", "compile": {"header": "Device\\Include\\SN32F240.h", "define": "SN32F230"}, "pdsc_file": "http://liveupdate.sonix.com.tw/sonix/develop_tool/MCU/DFP/SONiX.SN32F2_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7FFC"}}, "debug": "SVD\\SN32F240.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NUC100RC1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L031G4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L031xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F779BI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F779xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LPC11U24FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2793": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2793.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1401-Q048x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MK20DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK20D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "CMSDK_ARMv8MBL": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MBL/Include/CMSDK_ARMv8MBL.h", "define": "CMSDK_ARMv8MBL"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MBL.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "STM32F469VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F469VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2C58H0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C5/Include/s6e2c5.h", "define": "S6E2C5AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/S6E2C5.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "NUC442VG8AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/NUC400_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC400_LD_16.FLM": {"default": "0", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC400_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC400_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "84000000"}}, "S6E2C3AH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "LM3S628": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s628.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFM32GG895F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG895F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG895F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048IM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048IM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F042C4": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}, "CMSIS/Flash/STM32F0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F042x6"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32F0x2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F469AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAMS70N19": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00040000"}, "IROM1": {"start": "0x00400000", "size": "0x00080000"}}, "debug": "svd/ATSAMS70N19.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "NUC120LE3DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "APOLLO512-KCR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 2048]], "algorithm": {"Flash/Apollo.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/apollo1.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "24000000"}}, "NUC130RE3CN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\NUC100CN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "HT32F52231_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52231_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52231_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "EFR32BG12P332F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG12P/Include/em_device.h", "define": "EFR32BG12P332F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32BG12P/EFR32BG12P332F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32G200F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32G/Include/em_device.h", "define": "EFM32G200F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32G/EFM32G200F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKL46Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"arm/MKL_P128_48MHZ.FLM": {"default": "1", "ramsize": "0x00004000", "size": "0x00020000", "ramstart": "0x1FFFF000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKL46Z256VMP4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKL46Z4_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKL46Z4.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1752": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC_IAP_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "TMPM3H6FSFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M3H6.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "LPC1756": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_256.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x40000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1754": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x2007C000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L152RBxxA": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00001000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L152xCA"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "SVD/STM32L15xxxA.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32L011F3": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_8.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00002000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1759": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1758": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.2.4.0.pack", "compile": {"header": "Device/Include/LPC17xx.h", "define": "LPC175x_6x"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1700_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IRAM2": {"start": "0x2007C000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC176x5x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "LPC1342FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32L011F4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L011xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "ARMCA9": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA9/Include/ARMCA9.h", "define": "ARMCA9"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "ARMCM23_TZ": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM23/Include/ARMCM23_TZ.h", "define": "ARMCM23_TZ"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM23.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "LPC1111FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5737": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5737.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5732": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5732.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "ARMCA5": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA5/Include/ARMCA5.h", "define": "ARMCA5"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M0518LC2AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/M0518_AP_36.FLM": {"default": "1", "ramsize": null, "size": "0x9000", "ramstart": null, "start": "0x00000000"}, "Flash/M0518_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M0518_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M0518\\Include\\M0518.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x9000"}}, "debug": "SVD\\Nuvoton\\M0518AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ARMCA7": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCA7/Include/ARMCA7.h", "define": "ARMCA7"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0.svd", "processor": {"fpu": "DP_FPU", "endianness": "Configurable", "clock": "10000000"}}, "M452VG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "EFM32LG232F128": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG232F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32LG/EFM32LG232F128.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "HT32F52331_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52331_41"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HT32F52331_41.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TLE9843QX": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[285212668, 4], [285212672, 4096], [285257728, 4096]], "algorithm": {"Flash/TLE9843_EEP.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1100B000"}, "Flash/TLE984x_OPT.FLM": {"default": "1", "ramsize": null, "size": "4", "ramstart": null, "start": "0x10FFFFFC"}, "Flash/TLE9843.FLM": {"default": "1", "ramsize": null, "size": "0xB000", "ramstart": null, "start": "0x11000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\tle984x.h", "define": "TLE9845QX"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.TLE984x_DFP.pdsc", "memory": {"IROM2": {"start": "0x10FFFFFC", "size": "4"}, "IRAM1": {"start": "0x18000000", "size": "0x1000"}, "IROM1": {"start": "0x11000000", "size": "0xC000"}}, "debug": "SVD\\TLE984x.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "TMPM4G8F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM4F132E5QC": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F132E5QC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "SKEAZN8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"Flash/MKE04Zxxx_P8KB.FLM": {"default": "1", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.1.3.0.pack", "compile": {"header": "Device/Include/SKEAZN642.h", "define": "SKEAZN64xxx2"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KEAxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/SKEAZN84.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "20000000"}}, "LM3S8962": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8962.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M4LEDRG6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F413ZH": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F413xx_423xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1536.FLM": {"default": "1", "ramsize": null, "size": "0x00180000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F413xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00180000"}}, "debug": "CMSIS/SVD/STM32F413.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFM32GG11B510F2048IQ100": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B510F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B510F2048IQ100.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F469AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F469xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F1765_48LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F175x_275x/ht32f175x_275x.h", "define": "USE_HT32F1755_65"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F175x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1100-Q024x0008": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x2000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "S6E2D35JAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2D3_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2D3/Include/s6e2d3.h", "define": "S6E2D35JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2D3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F723ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F723xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x3_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG11B340F64GM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B340F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B340F64GM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC11E37FBD48/501": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S5G51": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_384.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00060000"}}, "debug": "SVD\\lm3s5g51.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMDA1J16B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1b/svd/ATSAMDA1J16B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J16A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"arm_addon/flash/ATSAMDA1_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samda1/svd/ATSAMDA1J16A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LM3S2730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "RS14100_4MB": {"core": "Cortex-M4", "vendor": "Redpine Signals:125 ", "sectors": [[134291456, 4096]], "algorithm": {"Flash/RS14100_SF_4MB.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x3EE000", "ramstart": "0x00000000", "start": "0x08012000"}}, "debug-interface": [], "pack_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.1.0.2.pack", "compile": {"header": "Driver/Common/chip/inc/RS1xxxx.h"}, "pdsc_file": "http://www.redpinesignals.com/downloads/RS14100_DFP/Redpine.RS14100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x000000C", "size": "0x2FFF4"}, "IROM1": {"start": "0x08012000", "size": "0x3EE000"}}, "debug": "SVD/RS1xxxx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAM3S2A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00400000", "size": "0x00020000"}}, "debug": "SVD/SAM3S/ATSAM3S2A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "HT32F12365_100LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12365_66"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x3FC00"}}, "debug": "SVD/HT32F12365_66.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "LM3S2739": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2739.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK21DN512Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048]], "algorithm": {"arm/MK_P512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff8000", "size": "0x8000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MK21DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MAX32630": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32630.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.0.0.1.pack", "compile": {"header": "Libraries/Device/Maxim/MAX3263X/Include/max3263x.h", "define": "TARGET=MAX32631"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32630/max32630.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32631": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32630.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.0.0.1.pack", "compile": {"header": "Libraries/Device/Maxim/MAX3263X/Include/max3263x.h", "define": "TARGET=MAX32631"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32630.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32630/max32630.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MB9BF329T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MB9BF329S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B320T\\mb9b320t.h", "define": "MB9BF329T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF32xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "MK11DX128Axxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MK_D64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK11DX256AVMC5"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK11DA5_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x010000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK11DA5.xml", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1227FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LPC12xx\\LPC122x.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1200_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC122x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "45000000"}}, "LM3S6618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54102J256": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54102J512UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54102_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54102_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "EFR32MG1P132F256GJ43": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GJ43.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM367FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M367.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM3HPFDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}, "Flash/TMPM3Hx_code_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M3HP.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "XMC1201-Q040x0032": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x8000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "EFR32MG1P132F256IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM4G8F10FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_1024.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M4G8.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "M054ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M054_AP_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EFR32FG1V132F128GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG1V/Include/em_device.h", "define": "EFR32FG1V132F64GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFR32FG1V/EFR32FG1V132F128GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "NUC126RG4AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 12]], "algorithm": {"Flash/NUC126_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC126_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC126_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC126\\Include\\NUC126.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\NUC126AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "MB9BF167R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "STM32F373V8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "LPC11U36FBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_96.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x18000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM4F111C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F111C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM366FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M366.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S2139": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s2139.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "EFR32FG12P231F512GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P231F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P231F512GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MKW30Z160xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P160_48MHZ.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00028000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MKW30Z4.h", "define": "MKW30Z160xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KWxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF000", "size": "0x00005000"}, "IROM1": {"start": "0x00000000", "size": "0x00028000"}}, "debug": "SVD/MKW30Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32BG13P532F512GM32": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG13P/Include/em_device.h", "define": "EFR32BG13P532F512GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG13P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/EFR32BG13P/EFR32BG13P532F512GM32.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S6730": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s6730.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF167N": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MB9BF167M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B160R/Include/mb9b160r.h", "define": "MB9BF168R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B160R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "LM3S6100": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "S6E2GH6H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "S6E2GH6J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00080000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ATSAM4S2C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4S_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x20000"}}, "debug": "SVD/SAM4S/ATSAM4S2C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "EFM32TG108F32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 512]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG/Include/em_device.h", "define": "EFM32TG108F8"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32TG/EFM32TG108F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC834M101FHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00008000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC83x.h", "define": "LPC832M101FDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/LPC83x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "ATSAM3X8H": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8H.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "MKL15Z64xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P64_48MHZ.FLM": {"default": "1", "ramsize": "0x00002000", "size": "0x00010000", "ramstart": "0x1FFFF800", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL16Z4.h", "define": "MKL16Z256xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFF800", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MKL15Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2DF5GAA": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2DF_384.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00060000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2DF/Include/s6e2df.h", "define": "S6E2DF5JAA"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {}, "debug": "SVD/S6E2DF.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAM3X8E": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8E.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "ATSAM3X8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[524288, 256]], "algorithm": {"Flash/ATSAM3X_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00080000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3XA/Include/sam3xa.h", "define": "__SAM3X8H__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x000C0000", "size": "0x00040000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x20080000", "size": "0x00008000"}, "IROM1": {"start": "0x00080000", "size": "0x00040000"}}, "debug": "SVD/SAM3XA/ATSAM3X8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "84000000"}}, "TM4C1292NCPDT": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1292NCPDT.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "HT32F12345": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F12345"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xFC00"}}, "debug": "SVD/HT32F12345.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "M0516LBN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM4F110C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F110C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F373VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F373VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F373xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG980F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG980F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG980F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1112FDH20/102": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H2FUQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_96.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00003000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F407IE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFM32HG321F32": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32HG/Include/em_device.h", "define": "EFM32HG321F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD/EFM32HG/EFM32HG321F32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "STM32F407IG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F40xxx_41xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F407xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F40x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "168000000"}}, "EFR32MG1P231F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P231F256GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P231F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LPC1115FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L100R8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 16]], "algorithm": {"Flash/STM32L1xx_128_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_128_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L100xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MK22FN128xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK2x_FAC.FLM": {"default": "0", "ramsize": null, "size": "0x00000024", "ramstart": null, "start": "0xFFFF0000"}, "arm/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12810_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK22FN128VMP10"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK22F12810_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM_LOWER": {"start": "0x1fffe000", "size": "0x2000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x4000"}}, "debug": "MK22F12810.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "100000000"}}, "EZR32HG320F64R63": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "S6E2C39L0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x080000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C3/Include/s6e2c3.h", "define": "S6E2C3AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x20000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD/S6E2C3.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "EFM32GG11B310F2048GL112": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B310F2048GQ100"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00060000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B310F2048GL112.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF318T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx08_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x10000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MKL05Z8xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/MK_P8_48MHZ.FLM": {"default": "1", "ramsize": "0x00000400", "size": "0x00002000", "ramstart": "0x1FFFFF00", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.1.15.0.pack", "compile": {"header": "Device/Include/MKL05Z4.h", "define": "MKL05Z32xxx4"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_KLxx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFFFF00", "size": "0x00000400"}, "IROM1": {"start": "0x00000000", "size": "0x00002000"}}, "debug": "SVD/MKL05Z4.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32TG11B120F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32WG332F128": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG332F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32WG/EFM32WG332F128.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM4SD16C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAM4SD16B": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"Flash/ATSAM4S_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFFFF0"}, "Flash/ATSAM4SD_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/Include/SAM4S/sam4s.h", "define": "__SAM4SD32C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IROM2": {"start": "0x00480000", "size": "0x80000"}, "IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00400000", "size": "0x80000"}}, "debug": "SVD/SAM4S/ATSAM4SD16B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "XMC4800-E196x2048": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [134479872, 262144], [201326592, 16384], [201457664, 131072], [201588736, 262144]], "algorithm": {"Flash/XMC4800_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4800c_2048.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4800_series/Include/XMC4800.h", "define": "XMC4800_F100x1024"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x200000"}, "IRAM1": {"start": "0x20000000", "size": "0x3FFC0"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "SVD/XMC4800.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "144000000"}}, "NANO120SD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "XMC1302-T028x0200": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x32000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "GD32F130G8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130G6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "GD32F130G4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 GD32F130_150 USE_STDPERIPH_DRIVER"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-T028x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "NANO100ND2BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "S6E2GH8J": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxj.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9BF216T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B210T\\mb9b210t.h", "define": "MB9BF218T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF21xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2GH8H": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/S6E2GHXX0A1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00100000", "ramstart": "0x20040000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2GH/Include/S6E2GHxJ/s6e2ghxj.h", "define": "S6E2GH8J"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFE0000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/s6e2ghxh.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "STM32F103C6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F103C4": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_16.FLM": {"default": "1", "ramsize": null, "size": "0x4000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x08000000", "size": "0x4000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MK50DX128xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TC35678FSG-002": {"core": "Cortex-M0", "vendor": "Toshiba:92", "sectors": [[0, 4096]], "algorithm": {"Flash/TC35678-002_NVM.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.0.0.1.pack", "compile": {"header": "Device/Include/TC35678.h", "define": "TC35679"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/bluetooth-publishing-program/Toshiba.TC35678_ROM002.pdsc", "memory": {"IRAM1": {"start": "0x80C000", "size": "0xBB9C"}, "IRAM2": {"start": "0x824000", "size": "0xC000"}}, "debug": "SVD/TC35678.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "13000000"}}, "LM3S6432": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s6432.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103C8": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "MB9BF129S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 8192], [16384, 49152], [65536, 65536], [5275648, 8192]], "algorithm": {"Flash/MB9B520T_ROM1.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00508000"}, "Flash/MB9B520T_1536.FLM": {"default": "1", "ramsize": null, "size": "0x180000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9B120T\\mb9b120t.h", "define": "MB9BF129T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IROM2": {"start": "0x00508000", "size": "0x10000"}, "IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IRAM2": {"start": "0x1FFE8000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x180000"}}, "debug": "SVD\\MB9BF12xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "60000000"}}, "LM3S618": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s618.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NM1821FB0AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1820_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1820_AP_17_5.FLM": {"default": "1", "ramsize": null, "size": "0x4600", "ramstart": null, "start": "0x00000000"}, "Flash/NM1820_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\AU9110\\Include\\AU91xx.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x4600"}}, "debug": "SVD\\Nuvoton\\NM1820AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "GD32F330G8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S2950": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2950.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S613": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s613.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "GD32F330G4": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x04000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x04000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "LM3S611": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s611.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF517S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF517T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx07_768.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B510T\\mb9b510t.h", "define": "MB9BF518T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD\\MB9BF51xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9D92": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s9d92.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S615": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s628.h", "define": "LM3S628"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\lm3s615.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L486ZG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L486xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M4LEDRE6AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M451_AP_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F479NI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "EFR32BG1P333F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1P/Include/em_device.h", "define": "EFR32BG1P333F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1P/EFR32BG1P333F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "LM3S1626": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1626.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F103VE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32TG11B140F64IQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00010000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B140F64IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B140F64IQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "NANO100LD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "LM3S1627": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1627.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC54101J512": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5410x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54101J512UK49"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54101_DFP.pdsc", "memory": {"SRAM2": {"start": "0x03400000", "size": "0x2000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM1": {"start": "0x02010000", "size": "0x8000"}, "SRAM0": {"start": "0x02000000", "size": "0x010000"}}, "debug": "LPC54101.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "ATSAM3SD8B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAM3SD8C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3SD8/Include/sam3sd8.h", "define": "__SAM3SD8C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IROM2": {"start": "0x00440000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0x10000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3SD8/ATSAM3SD8C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "ATSAMC21J17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17AU.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T8": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F301C8": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F301x8"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32F301x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "ARMCM0P_MPU": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/ARM.CMSIS.5.3.0.pack", "compile": {"header": "Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h", "define": "ARMCM0P_MPU"}, "pdsc_file": "http://www.keil.com/pack/ARM.CMSIS.pdsc", "memory": {}, "debug": "Device/ARM/SVD/ARMCM0P.svd", "processor": {"fpu": "NO_FPU", "endianness": "Configurable", "clock": "10000000"}}, "MB9BF316N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "S6E2CCAL0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAML21E15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048], [4194304, 256]], "algorithm": {"Flash/ATSAML21_32_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00400", "ramstart": null, "start": "0x00400000"}, "Flash/ATSAML21_32.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IRAM2": {"start": "0x30000000", "size": "0x00800"}, "IROM1": {"start": "0x00000000", "size": "0x08000"}}, "debug": "SVD\\SAML21\\ATSAML21E15B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG332F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG332F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG332F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T6": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F030RC": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F030xC"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F0x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F170T4": {"core": "Cortex-M3", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F1x0_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.3.1.0.pack", "compile": {"header": "Device/Include/gd32f1x0.h", "define": "GD32F1x0 USE_STDPERIPH_DRIVER GD32F170_190"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F1x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "SVD/GD32F1x0.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "S6E2C1AJ0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2C1/Include/s6e2c1.h", "define": "S6E2C1AL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2C1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "S6E2CCAH0A": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536], [1048576, 8192], [1081344, 32768], [1114112, 65536]], "algorithm": {"Flash/S6E2CC_MACRO0_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00000000"}, "Flash/S6E2CC_MACRO1_1024KB.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x100000", "ramstart": "0x2003C000", "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/S6E2CC/Include/s6e2cc.h", "define": "S6E2CCAL0A"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x1FFD0000", "size": "0x30000"}, "IROM1": {"start": "0x00000000", "size": "0x200000"}}, "debug": "SVD/S6E2CC.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "STM32L4A6RG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L4A6xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32MG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P232F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "MB9BF316S": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xS.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF316R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072], [537657344, 8192]], "algorithm": {"Flash/MB9xFxxx_32WF.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x200C0000"}, "Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IROM2": {"start": "0x200C0000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "MB9BF316T": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx06_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B310T\\mb9b310t.h", "define": "MB9BF318T"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\MB9BF31xT.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "144000000"}}, "LM3S9L97": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s9u96.h", "define": "LM3S9U96"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s9l97.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F103CB": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "AMAPH1KK-KBR": {"core": "Cortex-M4", "vendor": "Ambiq Micro:120", "sectors": [[0, 8192]], "algorithm": {"Flash/Apollo2.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.1.0.0.pack", "compile": {"header": "Device/Include/system_apollo2.h", "define": "APOLLO2_1024"}, "pdsc_file": "http://s3.asia.ambiqmicro.com/pack/AmbiqMicro.Apollo_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x40000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/apollo2.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1113FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L162RC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L162xD"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L100.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MB9BF500R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [16384, 49152], [65536, 65536]], "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M481ZGAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32JG1B200F256IM32": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32JG1B/Include/em_device.h", "define": "EFM32JG1B200F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32JG1B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32JG1B/EFM32JG1B200F256IM32.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F722VC": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x40000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32FG12P433F1024GM68": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P433F1024GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P433F1024GM68.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F722VE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F722xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFR32BG1V132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32BG1V/Include/em_device.h", "define": "EFR32BG1V132F256IM32"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32BG1V_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32BG1V/EFR32BG1V132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32TG11B520F128GQ48": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B520F128IQ80"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B520F128GQ48.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMS70Q20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70Q20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70Q21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70Q21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LPC845M301JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC84x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC845.h", "define": "LPC845M301JHI48"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/LPC845.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "TMPM475FDFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\M475.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LM3S3749": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s3z26.h", "define": "LM3S3Z26"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s3749.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF500N": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 4096], [16384, 49152], [65536, 65536]], "algorithm": {"Flash/MB9BF500_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B500B\\mb9b500r.h", "define": "MB9BF506R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD\\MB9BF50xN.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MB9BF305R": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304], [131072, 131072]], "algorithm": {"Flash/MB9BFx05_384.FLM": {"default": "1", "ramsize": null, "size": "0x60000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\MB9B300B\\mb9b300r.h", "define": "MB9BF306R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3HighPerformance_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x6000"}, "IRAM2": {"start": "0x1FFFA000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x60000"}}, "debug": "SVD\\MB9BF30xR.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "M453SD3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_72.FLM": {"default": "1", "ramsize": null, "size": "0x12000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x12000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "GD32F405VK": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [136314880, 262144]], "algorithm": {"Flash/GD32F4xx_3MB.FLM": {"default": "1", "ramsize": null, "size": "0x0300000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.1.0.1.pack", "compile": {"header": "Device/Include/gd32f4xx.h", "define": "GD32F405 USE_STDPERIPH_DRIVER "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4/GigaDevice.GD32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x020000"}, "IRAM2": {"start": "0x10000000", "size": "0x010000"}, "IROM1": {"start": "0x08000000", "size": "0x300000"}}, "debug": "SVD/GD32F4xx.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "200000000"}}, "ATSAMC21J17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAMC_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/SAMC21/ATSAMC21J17A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1111FHN33/103": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x07E0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "M482SIDAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 4096], [1048576, 4096], [3145728, 16]], "algorithm": {"Flash/M481_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M481_AP_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00000000"}, "Flash/M481_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M480\\Include\\M480.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x28000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD\\Nuvoton\\M481_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "192000000"}}, "EFM32TG11B120F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B120F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B120F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM4F120C4QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_64.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x6000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LM4F120C4QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EFM32WG290F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG290F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG290F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "NUC220SD2AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC200_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC200_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/NUC200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC200\\Include\\NUC200Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC200AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC11E14FBD48/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2800"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\LPC11Exx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1294NCZAD": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 16384]], "algorithm": {"Flash/TM4C129_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C129/TM4C129.h", "define": "TM4C129XNCZAD"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x040000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD/TM4C129/TM4C1294NCZAD.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1311FHN33/01": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32LG995F64": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG995F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EFM32LG/EFM32LG995F64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S5C56": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s5c56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "EFR32FG12P232F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F103ZF": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x18000"}, "IROM1": {"start": "0x08000000", "size": "0xC0000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32MG12P433F1024IL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024IL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "EFM32WG980F256": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32WG/Include/em_device.h", "define": "EFM32WG980F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32WG/EFM32WG980F256.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L451RE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FX512xxx10": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"Flash/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.1.7.0.pack", "compile": {"header": "Device/Include/MK22F10.h", "define": "MK22FX512xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K20_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00020000"}, "IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IRAM2": {"start": "0x1FFF0000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MK21F10.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "STM32L451RC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L451xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x1.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "MK21FX512xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [268435456, 4096]], "algorithm": {"arm/MKD128_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x10000000"}, "arm/MK_P512X.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.10.0.1.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK21FX512VMD12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK21F12_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x1000"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x020000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x080000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x010000"}}, "debug": "MK21F12.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "STM32H753AG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "EFR32MG12P433F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG12P/Include/em_device.h", "define": "EFR32MG12P433F1024IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32MG12P/EFR32MG12P433F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAM4CMP8C": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[16777216, 8192]], "algorithm": {"Flash/ATSAM4C_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x01000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM4_DFP.1.6.1.pack", "compile": {"header": "Device/SAM4CM/Include/sam4cm.h", "define": "__SAM4CMS16C_1__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20100000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD/SAM4CM/ATSAM4CMP8C_0.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "TMPM361FYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M361.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LPC11U12FHN33/201": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x4000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x4000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32H753AI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "MKV31F256xxx12": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [4294901760, 36]], "algorithm": {"arm/MK_P256.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}, "arm/MKV3x_FAC.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00000024", "ramstart": "0x20000000", "start": "0xFFFF0000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F25612_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKV31F256VLL12"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKV31F25612_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fffc000", "size": "0x4000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x8000"}}, "debug": "MKV31F25612.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "120000000"}}, "STM32L496QG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L496xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32L4x6.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "ATSAMD21G17AU": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21G17AU.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "MKE14Z128xxx7": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 2048]], "algorithm": {"arm/MKE1x_D32_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x10000000"}, "arm/MKE1x_P256_2KB_SEC.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE14Z256VLL7"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE14Z7_DFP.pdsc", "memory": {"FLEX_RAM": {"start": "0x14000000", "size": "0x0800"}, "FLEX_NVM": {"start": "0x10000000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}, "SRAM": {"start": "0x1ffff000", "size": "0x4000"}}, "debug": "MKE14Z7.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B820F2048GQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B820F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B820F2048GQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "MB9BF467M": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B460R/Include/mb9b460r.h", "define": "MB9BF468R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B460R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "XMC1302-T038x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMHA1G16AB": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096], [4194304, 256]], "algorithm": {"samha1ab/keil/flash/ATSAMH_64_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x00400000"}, "samha1ab/keil/flash/ATSAMH_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.1.1.1.pack", "compile": {"header": "samha1b/include/sam.h", "define": "__SAMHA1E14AB__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMHA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x800"}, "IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "samha1ab/svd/ATSAMHA1G16AB.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "EFM32TG11B320F128IM64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IM64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "EFR32FG12P232F1024GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P232F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P232F1024GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "STM32F101RD": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"Flash/STM32F10x_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0xC000"}, "IROM1": {"start": "0x08000000", "size": "0x60000"}}, "debug": "SVD/STM32F101xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "36000000"}}, "EFM32GG11B840F1024GM64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B840F1024IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B840F1024GM64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "ATSAM3N4B": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x06000"}, "IROM1": {"start": "0x00400000", "size": "0x40000"}}, "debug": "SVD/SAM3N/ATSAM3N4C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAM3N4A": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x00400000", "size": "0x00040000"}}, "debug": "SVD/SAM3N/ATSAM3N4A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "MK10DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LPC54114J256": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 32768]], "algorithm": {"arm/LPC5411x_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54114_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_LPC54114J256UK49_cm0plus"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.LPC54114_DFP.pdsc", "memory": {"SRAM2": {"start": "0x20020000", "size": "0x8000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM1": {"start": "0x20010000", "size": "0x010000"}, "SRAM0": {"start": "0x20000000", "size": "0x010000"}, "SRAMX": {"start": "0x04000000", "size": "0x8000"}}, "debug": "LPC54114_cm0plus.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "100000000"}}, "LM3S2918": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s2918.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S1608": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1608.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK80FN256xxx15": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"arm/MKP256_4KB_SECTOR.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK80F25615_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MK80FN256VLQ15"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MK80F25615_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x00000000", "size": "0x040000"}, "SRAM_LOWER": {"start": "0x1fff0000", "size": "0x010000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x030000"}}, "debug": "MK80F25615.xml", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "150000000"}}, "LM3S1607": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s1607.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F439VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MK50DX256xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}, "Flash/MK_P256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.1.2.0.pack", "compile": {"header": "Device/Include/MK53D10.h", "define": "MK53DX256xxx10"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K50_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IRAM2": {"start": "0x1FFF8000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/MK50D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM330FDFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM330_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM333.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M330.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "MIMX8MD6xxxJZ": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.10.0.0.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MIMX8MD6DVAJZ"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMX8MD6_DFP.pdsc", "memory": {"QSPI_FLASH": {"start": "0xc0000000", "size": "0x10000000"}, "SRAM_LOWER": {"start": "0x1ffe0000", "size": "0x020000"}, "SRAM_UPPER": {"start": "0x20000000", "size": "0x020000"}}, "debug": "MIMX8MD6.xml", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "266000000"}}, "STM32F302VC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VB": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00006000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F30x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "HC32F005C6UA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F005.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.1.0.0.pack", "compile": {"header": "Device/Include/HC32F005.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F005.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/HC32F005.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F429AG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "R-IN32M3-CL": {"core": "Cortex-M3", "vendor": "Renesas:117", "sectors": [[33554432, 65536], [33554432, 65536], [268435456, 8192], [268435456, 131072], [268500992, 65536]], "algorithm": {"Flash/R-IN32M3_S25FL064P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00800000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29AL032D.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x10000000"}, "Flash/R-IN32M3_S25FL032P.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x00400000", "ramstart": "0x20000000", "start": "0x02000000"}, "Flash/R-IN32M3_S29GL128S.FLM": {"default": "0", "ramsize": "0x1000", "size": "0x01000000", "ramstart": "0x20000000", "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.1.3.0.pack", "compile": {"header": "Device/Include/RIN32M3.h", "define": "RIN32M3_EC"}, "pdsc_file": "http://www.keil.com/pack/Keil.R-IN32M3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x80000"}}, "debug": "SVD/RIN32M3_CL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "100000000"}}, "STM32F302VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F302VD": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00060000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F302xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00060000"}}, "debug": "CMSIS/SVD/STM32F303xE.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "EFR32FG12P432F1024GL125": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P432F1024GM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P432F1024GL125.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "M451YC3AE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 2048], [1048576, 2048], [3145728, 16]], "algorithm": {"Flash/M451_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/M451_AP_40.FLM": {"default": "1", "ramsize": null, "size": "0xa000", "ramstart": null, "start": "0x00000000"}, "Flash/M451_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M451\\Include\\M451Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0xa000"}}, "debug": "SVD\\Nuvoton\\M451_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "72000000"}}, "STM32F205ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00018000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F769NI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2097152, 32768], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [3145728, 16384], [3211264, 65536], [3276800, 131072], [134217728, 16384], [134217728, 32768], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [135266304, 16384], [135331840, 65536], [135397376, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048dual.FLM": {"default": "0", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7xTCM_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F769xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x200000"}, "IROM1": {"start": "0x08000000", "size": "0x200000"}}, "debug": "CMSIS/SVD/STM32F7x9_v1r2.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "XMC1402-Q040x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H753ZI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H753xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "STM32L442KC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048]], "algorithm": {"CMSIS/Flash/STM32L4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h", "define": "STM32L442xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L4xx_DFP.pdsc", "memory": {"IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32L4x2.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "M058ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M058_AP_32.FLM": {"default": "1", "ramsize": null, "size": "0x8000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\M051\\Include\\M051Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LPC1548JBD64": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC15xx_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x02000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.1.2.1.pack", "compile": {"header": "LPCOpen/software/lpc_core/lpc_chip/chip_15xx/chip.h", "define": "LPC1549JBD100"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1500_DFP.pdsc", "memory": {"IRAM1": {"start": "0x02000000", "size": "0x5000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/LPC15xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "NANO120KD3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "MB9BF367R": {"core": "Cortex-M4", "vendor": "Spansion:100", "sectors": [[0, 8192], [32768, 32768], [65536, 65536]], "algorithm": {"Flash/MB9B560_1024.FLM": {"default": "1", "ramsize": null, "size": "0xC0000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM4_DFP.1.5.1.pack", "compile": {"header": "Device/MB9B360R/Include/mb9b360r.h", "define": "MB9BF368R"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x2003A000", "size": "0xC000"}, "IRAM2": {"start": "0x1FFF4000", "size": "0xC000"}, "IROM1": {"start": "0x00000000", "size": "0xC0000"}}, "debug": "SVD/MB9B360R.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "HT32F1655_64LQFP": {"core": "Cortex-M3", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F1xxxx/ht32f1xxxx_01.h", "define": "USE_HT32F1655_56"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HT32F1655_56.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "ATSAMD21G17A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD21_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.1.3.0.pack", "compile": {"header": "Device/SAMD21A/Include/samd21.h", "define": "__SAMD21J18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD21_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/SAMD21A/ATSAMD21G17A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "IOTKit_CM33_FP": {"core": "ARMV8MBL", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.1.4.0.pack", "compile": {"header": "Device/IOTKit_CM33/Include/IOTKit_CM33_FP.h", "define": "IOTKit_CM33_FP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_IOTKit_BSP.pdsc", "memory": {}, "debug": "SVD/IOTKit_CM33.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "25000000"}}, "NUC120RD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32HG320F64R67": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R67.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "HT32F52253_48LQFP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52243_53"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x1FC00"}}, "debug": "SVD/HT32F52243_53.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "XMC4400-F100x256": {"core": "Cortex-M4", "vendor": "Infineon:7", "sectors": [[134217728, 16384], [134348800, 131072], [201326592, 16384], [201457664, 131072]], "algorithm": {"Flash/XMC4400_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x0C000000"}, "Flash/XMC4400c_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.2.10.0.pack", "compile": {"header": "Device/XMC4400_series/Include/XMC4400.h", "define": "XMC4402_F64x256"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC4000_DFP.pdsc", "memory": {"IROM2": {"start": "0x0C000000", "size": "0x40000"}, "IRAM1": {"start": "0x20000000", "size": "0xFFC0"}, "IRAM2": {"start": "0x1FFFC000", "size": "0x4000"}, "IROM1": {"start": "0x08000000", "size": "0x40000"}}, "debug": "SVD/XMC4400.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "120000000"}}, "NANO100VD3AN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100AN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "32000000"}}, "EFM32LG940F256": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32LG/Include/em_device.h", "define": "EFM32LG940F64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFM32LG/EFM32LG940F256.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G18": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384]], "algorithm": {"Flash/ATSAMD20_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G18.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F350G8": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F350"}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x02000"}, "IROM1": {"start": "0x08000000", "size": "0x10000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "108000000"}}, "STM32F103T6": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"Flash/STM32F10x_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}, "Flash/STM32F10x_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x0010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.2.0.pack", "compile": {"header": "Device/Include/stm32f10x.h", "define": "STM32F10X_XL"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2800"}, "IROM1": {"start": "0x08000000", "size": "0x8000"}}, "debug": "SVD/STM32F103xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "TMPM4G9F15FG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}, "Flash/TMPM4Gx_code_1536.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00180000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IROM1": {"start": "0x00000000", "size": "0x00180000"}}, "debug": "SVD/M4G9.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "MK10DX64xxx5": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 1024], [268435456, 1024]], "algorithm": {"Flash/MK_P64_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_50MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D5.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "MK10DX64xxx7": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 2048], [268435456, 1024]], "algorithm": {"Flash/MK_P64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/MK_D32_72MHZ.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x10000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.1.3.0.pack", "compile": {"header": "Device/Include/MK10F12.h", "define": "MK10FX512xxx12"}, "pdsc_file": "http://www.keil.com/pack/Keil.Kinetis_K10_DFP.pdsc", "memory": {"IROM2": {"start": "0x10000000", "size": "0x00008000"}, "IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/MK10D7.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "Mini51ZAN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_AP_4.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00000000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini51\\Include\\Mini51Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x1000"}}, "debug": "SVD\\Nuvoton\\MINI51AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "24000000"}}, "ATSAMD20G15": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"Flash/ATSAMD20_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00008000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G15.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G14": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 1024]], "algorithm": {"Flash/ATSAMD20_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G14.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G17": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"Flash/ATSAMD20_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G17.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMD20G16": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 4096]], "algorithm": {"Flash/ATSAMD20_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.1.1.1.pack", "compile": {"header": "Device\\SAMD20\\Include\\samd20.h", "define": "__SAMD20J18__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMD20_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\SAMD20\\ATSAMD20G16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1301-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "STM32F446MC": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 4]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F446xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F446xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "CMSIS/SVD/STM32F446x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "CMSDK_ARMv8MML_SP": {"core": "Cortex-M0", "vendor": "ARM:82", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.7.0.pack", "compile": {"header": "Device/CMSDK_ARMv8MML/Include/CMSDK_ARMv8MML_DP.h", "define": "CMSDK_ARMv8MML_DP"}, "pdsc_file": "http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.pdsc", "memory": {}, "debug": "SVD/CMSDK_ARMv8MML_SP.svd", "processor": {"fpu": "SP_FPU", "endianness": "Configurable", "clock": "25000000"}}, "TM4C1237D5PZ": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1237D5PZ.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "TMPM375FSDMG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM37x_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM37A.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/M375.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "ATSAM3N0C": {"core": "Cortex-M3", "vendor": "Microchip:3", "sectors": [[4194304, 256]], "algorithm": {"Flash/ATSAM3N_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM3_DFP.1.2.1.pack", "compile": {"header": "Device/SAM3N/Include/sam3n.h", "define": "__SAM3N4C__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00400000", "size": "0x00008000"}}, "debug": "SVD/SAM3N/ATSAM3N0C.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "ATSAMDA1J15B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1b/svd/ATSAMDA1J15B.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "ATSAMDA1J15A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 2048]], "algorithm": {"arm_addon/flash/ATSAMDA1_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.1.1.1.pack", "compile": {"header": "samda1/include/sam.h", "define": "__SAMDA1E16A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAMDA1_DFP.pdsc", "memory": {"IROM2": {"start": "0x00400000", "size": "0x400"}, "IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "samda1/svd/ATSAMDA1J15A.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian"}}, "LPC11E66JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HT32F52354_33QFN": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x0400", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52344_54"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x1FE00"}}, "debug": "SVD/HT32F52344_54.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F765NG": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 32768], [2097152, 16384], [2162688, 65536], [2228224, 131072], [2228224, 131072], [2359296, 262144], [2621440, 16384], [2686976, 65536], [2752512, 131072], [134217728, 32768], [134217728, 16384], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134479872, 262144], [134742016, 16384], [134807552, 65536], [134873088, 131072]], "algorithm": {"CMSIS/Flash/STM32F7xTCM_1024.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7xTCM_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F7x_1024dual.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F765xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x100000"}, "IROM1": {"start": "0x08000000", "size": "0x100000"}}, "debug": "CMSIS/SVD/STM32F7x5_v1r1.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "EFM32TG11B320F128IQ64": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOT1.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOT1.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32TG11B/Include/em_device.h", "define": "EFM32TG11B320F128IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32TG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EFM32TG11B/EFM32TG11B320F128IQ64.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "GD32F330C6": {"core": "Cortex-M4", "vendor": "GigaDevice:123", "sectors": [[134217728, 1024]], "algorithm": {"Flash/GD32F3x0.FLM": {"default": "1", "ramsize": null, "size": "0x08000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.1.0.0.pack", "compile": {"header": "Device/Include/gd32f3x0.h", "define": "USE_STDPERIPH_DRIVER GD32F3x0 GD32F330 "}, "pdsc_file": "http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GigaDevice.GD32F3x0_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x01000"}, "IROM1": {"start": "0x08000000", "size": "0x08000"}}, "debug": "SVD/GD32F3x0.svd", "processor": {"fpu": "0 ", "endianness": "Little-endian", "clock": "84000000"}}, "XMC1202-T016x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1200_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1200_series/Include/XMC1200.h", "define": "XMC1202_T016x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1200.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1113FBD48/301": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EZR32HG320F64R68": {"core": "Cortex-M0+", "vendor": "Silicon Labs:21", "sectors": [[0, 1024]], "algorithm": {"Flash/EFM32M0P.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}, "Flash/FlashEFM32M0P.flash": {"default": "0", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32HG/Include/em_device.h", "define": "EZR32HG320F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32HG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD/EZR32HG/EZR32HG320F64R68.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "24000000"}}, "LPC1113FBD48/303": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FBD48/302": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32L041C6": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00008000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "MKE04Z128xxx4": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 512]], "algorithm": {"arm/MKE04Zxxx_P128KB.FLM": {"default": "1", "ramsize": "0x00001000", "size": "0x00020000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.10.0.2.pack", "compile": {"header": "fsl_device_registers.h", "define": "CPU_MKE04Z64VQH4"}, "pdsc_file": "http://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MKE04Z1284_DFP.pdsc", "memory": {"SRAM": {"start": "0x1ffff000", "size": "0x4000"}, "PROGRAM_FLASH": {"start": "0x00000000", "size": "0x020000"}}, "debug": "MKE04Z1284.xml", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "40000000"}}, "STM32L041C4": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128]], "algorithm": {"CMSIS/Flash/STM32L0xx_16.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L041xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00002000"}, "IROM1": {"start": "0x08000000", "size": "0x00004000"}}, "debug": "CMSIS/SVD/STM32L0x1.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TMPM3HMFYFG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00004000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/M3HM.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "Mini52XZAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Mini51_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}, "Flash/Mini51_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Mini51_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\Mini55\\Include\\Mini55Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\MINI51XAE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "TMPM4G7FEFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 4096], [805306368, 4096]], "algorithm": {"Flash/TMPM4Gx_code_768.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x000C0000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/TMPM4Gx_data_32.FLM": {"default": "1", "ramsize": "0x2000", "size": "0x00008000", "ramstart": "0x20000000", "start": "0x30000000"}}, "debug-interface": [], "pack_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.1.0.1.pack", "compile": {"header": "Device/Include/TMPM4G6.h", "define": "TMPM4G6"}, "pdsc_file": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/Toshiba.TXZ4-M4G_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x000C0000"}}, "debug": "SVD/M4G7.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "160000000"}}, "ATSAMS70N21": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00200000"}}, "debug": "svd/ATSAMS70N21.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "ATSAMS70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192]], "algorithm": {"flash/ATSAMS7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.2.1.2.pack", "compile": {"header": "include/sam.h", "define": "__SAMS70Q20__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-S_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "svd/ATSAMS70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "300000000"}}, "LM3S2637": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s2637.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "NANO100ND3BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/Nano100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/Nano100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/Nano100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NANO100BN\\Include\\Nano100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NANO100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "42000000"}}, "STM32F398VE": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 2048], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F3xx_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F3xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h", "define": "STM32F398xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F3xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F37x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F732ZE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM4F130E5QR": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM4F_128.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM4F_DFP.1.0.0.pack", "compile": {"header": "Device\\Include\\LM4F132H5QD.h", "define": "LM4F132"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM4F_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LM4F130E5QR.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "LPC1345FHN33": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "STM32F429VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "TMPM363F10FG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/M363.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "64000000"}}, "LM3S5651": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5651.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "STM32F732IE": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[2097152, 16384], [2162688, 65536], [2228224, 131072], [134217728, 16384], [134283264, 65536], [134348800, 131072]], "algorithm": {"CMSIS/Flash/STM32F7x2TCM_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x00200000"}, "CMSIS/Flash/STM32F7x2_512.FLM": {"default": "1", "ramsize": null, "size": "0x80000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.2.10.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h", "define": "STM32F732xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F7xx_DFP.pdsc", "memory": {"IROM2": {"start": "0x00200000", "size": "0x80000"}, "IROM1": {"start": "0x08000000", "size": "0x80000"}}, "debug": "CMSIS/SVD/STM32F7x2_v1r0.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian", "clock": "216000000"}}, "LM3S5652": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s5y36.h", "define": "LM3S5Y36"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD\\lm3s5652.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "STM32F429VI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F429xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F429x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MB9AF112L": {"core": "Cortex-M3", "vendor": "Spansion:100", "sectors": [[0, 16384], [32768, 98304]], "algorithm": {"Flash/MB9BFx02_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.1.0.1.pack", "compile": {"header": "Device\\Include\\MB9A110A\\mb9a110n.h", "define": "MB9AF116N"}, "pdsc_file": "http://www.keil.com/pack/Keil.FM3Basic_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IRAM2": {"start": "0x1FFFE000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\MB9AF11xL.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "HC32M140KA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32F_M14.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.1.0.0.pack", "compile": {"header": "Device/Include/HC32M140FX.h"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32F_M14.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32M140KX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "XMC1404-Q064x0128": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x20000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "EFM32GG11B520F2048GL120": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B520F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B520F2048GL120.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LPC4078FBD208": {"core": "Cortex-M4", "vendor": "NXP:11", "sectors": [[0, 4096], [65536, 32768]], "algorithm": {"Flash/LPC_IAP_512.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x80000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.2.0.0.pack", "compile": {"header": "Device/Include/LPC407x_8x_177x_8x.h", "define": "CORE_M4"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC4000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x10000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x80000"}}, "debug": "SVD/LPC408x_7x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "LPC1111FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_8.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x2000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TMPM3H2FWQG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 4096], [32768, 32768], [805306368, 256]], "algorithm": {"Flash/TMPM3Hx_code_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/TMPM3Hx_data_32.FLM": {"default": "1", "ramsize": null, "size": "0x00008000", "ramstart": null, "start": "0x30000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TMPM3Hy.h", "define": "TMPM3HMFYDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TXZ3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/M3H2.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F078RB": {"core": "Cortex-M0", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 1024], [536868864, 16]], "algorithm": {"CMSIS/Flash/STM32F0xx_128.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F0xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFF800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h", "define": "STM32F078xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x08000000", "size": "0x00020000"}}, "debug": "CMSIS/SVD/STM32F0x8.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM462F10XBG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM462_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM46B.h", "define": "TMPM46BF10FG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x30000"}, "IRAM2": {"start": "0x20030000", "size": "0x00400"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "SVD\\M462.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "EFR32FG12P431F1024IM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/GECKOS1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}, "Flash/FlashGECKOS1.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32FG12P/Include/em_device.h", "define": "EFR32FG12P431F512GM68"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32FG12P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00040000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFR32FG12P/EFR32FG12P431F1024IM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "TMPM369FDXBG": {"core": "Cortex-M3", "vendor": "Toshiba:92", "sectors": [[0, 32768], [65536, 65536], [131072, 131072]], "algorithm": {"Flash/TMPM36x_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.1.4.0.pack", "compile": {"header": "Device/Include/TMPM36B.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM3_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/M369.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "MVF51NS15xxxx50": {"core": "Cortex-A5", "vendor": "NXP:11", "sectors": [], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.1.1.1.pack", "compile": {"header": "Device/Include/MVF6X.h", "define": "MVF62NN15xxxx40"}, "pdsc_file": "http://www.keil.com/pack/Keil.VFxxx_DFP.pdsc", "memory": {}, "debug": "SVD/MVF51NS151MK50.svd", "processor": {"fpu": "DP_FPU"}}, "LM3S8971": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8971.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S8970": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s8971.h", "define": "LM3S8971"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s8970.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "TM4C1230D5PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_64.FLM": {"default": "1", "ramsize": null, "size": "0x010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x006000"}, "IROM1": {"start": "0x00000000", "size": "0x010000"}}, "debug": "SVD/TM4C123/TM4C1230D5PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "HC32L150JA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L150JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC11E67JBD48": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096], [98304, 32768]], "algorithm": {"Flash/LPC1xxx_96_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Exx\\LPC11E6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x4000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11E6x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC11U37HFBD64/401": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_128.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x20000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11Uxx\\LPC11U6x.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20004000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\LPC11Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "EFR32MG1P132F256GM48": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashGECKOP2.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOP2.FLM": {"default": "1", "ramsize": "0x1000", "size": "0x00040000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFR32MG1P/Include/em_device.h", "define": "EFR32MG1P132F256IM48"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFR32MG1P_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00007C00"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EFR32MG1P/EFR32MG1P132F256GM48.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "38400000"}}, "ATSAME54P20A": {"core": "Cortex-M4", "vendor": "Microchip:3", "sectors": [[0, 8192]], "algorithm": {"arm_addon/flash/ATSAME54_1024.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAME54_DFP.1.0.2.pack", "compile": {"header": "include/sam.h", "define": "__SAME54N19A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAME54_DFP.pdsc", "memory": {"IRAM4": {"start": "0x47000000", "size": "0x2000"}, "IRAM3": {"start": "0x20000000", "size": "0x8000"}, "IRAM1": {"start": "0x20000000", "size": "0x40000"}, "IRAM2": {"start": "0x20000000", "size": "0x8000"}, "IROM1": {"start": "0x00000000", "size": "0x100000"}}, "debug": "svd/ATSAME54P20A.svd", "processor": {"fpu": "SP_FPU", "endianness": "Little-endian"}}, "XMC1100-Q024x0016": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1100_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1100_series/Include/XMC1100.h", "define": "XMC1100_T038x0064"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x4000"}}, "debug": "SVD/XMC1100.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "ATSAMC21E18A": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 16384], [4194304, 256]], "algorithm": {"Flash/ATSAMC_256.FLM": {"default": "1", "ramsize": null, "size": "0x40000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAMC_256_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x02000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.1.4.1.pack", "compile": {"header": "Device/SAMC21N/Include/samc21.h", "define": "__SAMC21N18A__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x08000"}, "IROM1": {"start": "0x00000000", "size": "0x40000"}}, "debug": "SVD/SAMC21/ATSAMC21E18A.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F205ZE": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00080000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "STM32F205ZG": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [536836096, 528], [536854528, 16]], "algorithm": {"CMSIS/Flash/STM32F2xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F2xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F2xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.2.9.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h", "define": "STM32F205xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F2xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F20x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "120000000"}}, "MM32x103": {"core": "Cortex-M3", "vendor": "MindMotion:132", "sectors": [[134217728, 1024]], "algorithm": {"Flash/MM32x103_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.1.1.0.pack", "compile": {"header": "Device/Include/MM32x103.h", "define": "MM32x103_MD"}, "pdsc_file": "http://www.mindmotion.com.cn/Download/MDK_KEIL/MindMotion.MM32x103_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x5000"}, "IROM1": {"start": "0x08000000", "size": "0x20000"}}, "debug": "SVD/MM32x103.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "96000000"}}, "NM1100XAAE": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NM1200_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NM1200_AP_8.FLM": {"default": "1", "ramsize": null, "size": "0x2000", "ramstart": null, "start": "0x00000000"}, "Flash/NM1200_LD_2.FLM": {"default": "0", "ramsize": null, "size": "0x800", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NM1200\\Include\\NM1200_NM1100.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x800"}, "IROM1": {"start": "0x00000000", "size": "0x2000"}}, "debug": "SVD\\Nuvoton\\NM1200AE_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "EZR32LG230F256R69": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R69.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32H743XI": {"core": "Cortex-M7", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 131072]], "algorithm": {"CMSIS/Flash/STM32H7x_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.2.1.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h", "define": "STM32H743xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32H7xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IRAM2": {"start": "0x24000000", "size": "0x00080000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32H7x3.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian", "clock": "400000000"}}, "LPC1113FHN33/202": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "LPC1113FHN33/203": {"core": "Cortex-M0", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_24.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x6000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.1.4.0.pack", "compile": {"header": "Device\\Include\\LPC11xx\\LPC11xx.h", "define": "LPC1125"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1100_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x6000"}}, "debug": "SVD\\LPC111x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "XMC1401-Q048x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1400_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1400_series/Include/XMC1400.h", "define": "XMC1404_F064x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1400.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "48000000"}}, "LPC822M101JHI33": {"core": "Cortex-M0+", "vendor": "NXP:11", "sectors": [[0, 1024]], "algorithm": {"Flash/LPC8xx_16.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x00004000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC800_DFP.1.9.0.pack", "compile": {"header": "Device/Include/LPC822.h", "define": "LPC822M101JDH20"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC800_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x00001000"}, "IROM1": {"start": "0x00000000", "size": "0x00004000"}}, "debug": "SVD/LPC822.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "30000000"}}, "STM32F479NG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536854528, 8], [2415919104, 65536]], "algorithm": {"CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F469xx_479xx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F469_Quad_SPI.FLM": {"default": "1", "ramsize": null, "size": "0x02000000", "ramstart": null, "start": "0x90000000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F479xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F46_79x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "HT32F52230_28SSOP": {"core": "Cortex-M0+", "vendor": "Holtek:106", "sectors": [[0, 512], [535822336, 512]], "algorithm": {"ARM/Flash/HT32F.FLM": {"default": "1", "ramsize": null, "size": "0x100000", "ramstart": null, "start": "0x00000000"}, "ARM/Flash/HT32F_OPT.FLM": {"default": "1", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x1FF00000"}}, "debug-interface": [], "pack_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.1.0.15.pack", "compile": {"header": "ARM/INC/Holtek/HT32F5xxxx/ht32f5xxxx_01.h", "define": "USE_HT32F52220_30"}, "pdsc_file": "http://mcu.holtek.com.tw/pack/Holtek.HT32_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x7C00"}}, "debug": "SVD/HT32F52220_30.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "40000000"}}, "STM32F439VG": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134217728, 16384], [134283264, 65536], [134283264, 65536], [134348800, 131072], [134348800, 131072], [134742016, 16384], [134807552, 65536], [134873088, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F4xx_1024dual.FLM": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}, "CMSIS/Flash/STM32F4xx_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F439xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00100000"}}, "debug": "CMSIS/SVD/STM32F439x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "MAX32621": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32620.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32620.flash": {"default": "0", "ramsize": "0x00020000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.1.0.2.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32620/Include/max32620.h"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32620/max32620.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32620": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32620.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32620.flash": {"default": "0", "ramsize": "0x00020000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.1.0.2.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32620/Include/max32620.h"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32620.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/MAX32620/max32620.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32626": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32625.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32625.flash": {"default": "0", "ramsize": "0x00028000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.1.0.0.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32625/Include/max32625.h", "define": "MAX32626"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MAX32625/max32625.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "MAX32625": {"core": "Cortex-M4", "vendor": "Maxim:23", "sectors": [[0, 8192]], "algorithm": {"Flash/MAX32625.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}, "FlashIAR/FlashMAX32625.flash": {"default": "0", "ramsize": "0x00028000", "size": "0x00080000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.1.0.0.pack", "compile": {"header": "Libraries/Device/Maxim/MAX32625/Include/max32625.h", "define": "MAX32626"}, "pdsc_file": "http://www.mxim.net/microcontroller/pack/Maxim.MAX32625.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00028000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD/MAX32625/max32625.svd", "processor": {"fpu": "FPU", "endianness": "Little-endian", "clock": "96000000"}}, "ATSAML21J17B": {"core": "Cortex-M0+", "vendor": "Microchip:3", "sectors": [[0, 8192], [4194304, 256]], "algorithm": {"Flash/ATSAML21_128.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}, "Flash/ATSAML21_128_EEPROM.FLM": {"default": "1", "ramsize": null, "size": "0x01000", "ramstart": null, "start": "0x00400000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.1.2.1.pack", "compile": {"header": "Device\\SAML21\\Include\\saml21.h", "define": "__SAML21J18B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-L_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x04000"}, "IRAM2": {"start": "0x30000000", "size": "0x02000"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD\\SAML21\\ATSAML21J17B.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LPC1343FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_32.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x8000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IROM1": {"start": "0x00000000", "size": "0x8000"}}, "debug": "SVD/LPC13xx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "XMC1302-Q040x0064": {"core": "Cortex-M0", "vendor": "Infineon:7", "sectors": [[268439552, 4096]], "algorithm": {"Flash/XMC1300_200.FLM": {"default": "1", "ramsize": null, "size": "0x32000", "ramstart": null, "start": "0x10001000"}}, "debug-interface": [], "pack_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.2.8.0.pack", "compile": {"header": "Device/XMC1300_series/Include/XMC1300.h", "define": "XMC1302_Q040x0200"}, "pdsc_file": "http://dave.infineon.com/Libraries/CMSIS_PACK/Infineon.XMC1000_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3FFC"}, "IROM1": {"start": "0x10001000", "size": "0x10000"}}, "debug": "SVD/XMC1300.svd", "processor": {"fpu": "NO_FPU", "endianness": "Little-endian", "clock": "32000000"}}, "HC32L156JA": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x20000"}}, "debug": "SVD/HC32L156JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EFM32GG280F1024": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32GG.FLM": {"default": "1", "ramsize": "0x8000", "size": "0x00100000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG/Include/em_device.h", "define": "EFM32GG280F512"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00020000"}, "IROM1": {"start": "0x00000000", "size": "0x00100000"}}, "debug": "SVD/EFM32GG/EFM32GG280F1024.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "STM32F437AI": {"core": "Cortex-M4", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 16384], [134283264, 65536], [134348800, 131072], [135266304, 16384], [135331840, 65536], [135397376, 131072], [536836096, 528], [536854528, 8]], "algorithm": {"CMSIS/Flash/STM32F4xx_2048.FLM": {"default": "1", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32F4xx_OTP.FLM": {"default": "0", "ramsize": null, "size": "0x00000210", "ramstart": null, "start": "0x1FFF7800"}, "CMSIS/Flash/STM32F42xxx_43xxx_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000008", "ramstart": null, "start": "0x1FFFC000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.13.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h", "define": "STM32F437xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32F4xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00030000"}, "IRAM2": {"start": "0x10000000", "size": "0x00010000"}, "IROM1": {"start": "0x08000000", "size": "0x00200000"}}, "debug": "CMSIS/SVD/STM32F437x.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "180000000"}}, "ISD9341": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x4000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "EZR32LG230F256R63": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R63.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "TMPM470FYFG": {"core": "Cortex-M4", "vendor": "Toshiba:92", "sectors": [[0, 32768]], "algorithm": {"Flash/TMPM470_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.1.2.0.pack", "compile": {"header": "Device\\Include\\TMPM475.h", "define": "TMPM475FDFG"}, "pdsc_file": "http://www.keil.com/pack/Keil.TMPM4_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IRAM2": {"start": "0x20008000", "size": "0x00000800"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\M470.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "120000000"}}, "NUC100LD1DN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100DN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "ISD9340": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 1024], [1048576, 1024], [3145728, 8]], "algorithm": {"Flash/ISD9100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/ISD9100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x18000", "ramstart": null, "start": "0x00000000"}, "Flash/ISD9100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x3000"}, "IROM1": {"start": "0x00000000", "size": "0x18000"}}, "debug": "SVD\\Nuvoton\\ISD9300_v3.svd", "processor": {"clock": "48000000"}}, "Generic_M051_Series": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 4]], "algorithm": {"Flash/M051_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/M0516_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}, "Flash/M051_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC472\\Include\\NUC472_442.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\M051AN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "STM32L083V8": {"core": "Cortex-M0+", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 128], [134745088, 3072]], "algorithm": {"CMSIS/Flash/STM32L0xx_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x08000000"}, "CMSIS/Flash/STM32L07x_64_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00000800", "ramstart": null, "start": "0x08080C00"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.2.0.0.pack", "compile": {"header": "Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h", "define": "STM32L083xx"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L0xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00050000"}, "IROM1": {"start": "0x08000000", "size": "0x00010000"}}, "debug": "CMSIS/SVD/STM32L07x.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "TM4C123FE6PM": {"core": "Cortex-M4", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/TM4C123_128.FLM": {"default": "1", "ramsize": null, "size": "0x020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack", "compile": {"header": "Device/Include/TM4C123/TM4C123.h", "define": "TM4C123GH6ZXR"}, "pdsc_file": "http://www.keil.com/pack/Keil.TM4C_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x008000"}, "IROM1": {"start": "0x00000000", "size": "0x020000"}}, "debug": "SVD/TM4C123/TM4C123FE6PM.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "80000000"}}, "EZR32LG230F256R61": {"core": "Cortex-M3", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32LG.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32LG/Include/em_device.h", "define": "EZR32LG230F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32LG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD/EZR32LG/EZR32LG230F256R61.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "48000000"}}, "LM3S6938": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00010000"}, "IROM1": {"start": "0x00000000", "size": "0x00040000"}}, "debug": "SVD\\lm3s6938.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "50000000"}}, "HC32L150J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L150JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "EZR32WG330F128R63": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 2048]], "algorithm": {"Flash/FlashEFM32.flash": {"default": "0", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}, "Flash/EFM32WG.FLM": {"default": "1", "ramsize": null, "size": "0x00020000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EZR32WG/Include/em_device.h", "define": "EZR32WG330F64R69"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EZR32WG_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00020000"}}, "debug": "SVD/EZR32WG/EZR32WG330F128R63.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "48000000"}}, "STM32L151ZC": {"core": "Cortex-M3", "vendor": "STMicroelectronics:13", "sectors": [[134217728, 256], [134742016, 256], [536346624, 24]], "algorithm": {"Flash/STM32L1xx_256_EEPROM.FLM": {"default": "0", "ramsize": null, "size": "0x00002000", "ramstart": null, "start": "0x08080000"}, "Flash/STM32L1xx_256_OPT.FLM": {"default": "0", "ramsize": null, "size": "0x00000018", "ramstart": null, "start": "0x1FF80000"}, "Flash/STM32L1xx_256.FLM": {"default": "1", "ramsize": null, "size": "0x00040000", "ramstart": null, "start": "0x08000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.1.2.0.pack", "compile": {"header": "Device/Include/stm32l1xx.h", "define": "STM32L151xE"}, "pdsc_file": "http://www.keil.com/pack/Keil.STM32L1xx_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x08000000", "size": "0x00040000"}}, "debug": "SVD/STM32L15xC.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "HC32L156J8": {"core": "Cortex-M0+", "vendor": "HDSC:145", "sectors": [[0, 512]], "algorithm": {"Flash/HC32L15.FLM": {"default": "1", "ramsize": null, "size": "0x20000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.1.0.1.pack", "compile": {"header": "Device/Include/hc32l15.h", "define": "__HC32L1567X__"}, "pdsc_file": "https://raw.githubusercontent.com/hdscmcu/pack/master/HDSC.HC32L15.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/HC32L156JX.SFR", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "32000000"}}, "LPC1317FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "LM3S1H11": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h11.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "LM3S1H16": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_512.FLM": {"default": "1", "ramsize": null, "size": "0x00080000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s1z16.h", "define": "LM3S1Z16"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x0000C000"}, "IROM1": {"start": "0x00000000", "size": "0x00080000"}}, "debug": "SVD\\lm3s1h16.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "80000000"}}, "ATSAMV70N20": {"core": "Cortex-M7", "vendor": "Microchip:3", "sectors": [[4194304, 8192], [536870896, 16]], "algorithm": {"samv70/keil/flash/ATSAMV7x_1024.FLM": {"default": "1", "ramsize": null, "size": "0x00100000", "ramstart": null, "start": "0x00400000"}, "samv70/keil/flash/ATSAMV7x_GPNVM.FLM": {"default": "0", "ramsize": null, "size": "0x00000010", "ramstart": null, "start": "0x1FFFFFF0"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.2.4.1.pack", "compile": {"header": "samv70b/include/sam.h", "define": "__SAMV70J20B__"}, "pdsc_file": "http://www.keil.com/pack/Keil.SAM-V_DFP.pdsc", "memory": {"IROM2": {"start": "0x00800000", "size": "0x00004000"}, "IRAM1": {"start": "0x20400000", "size": "0x00060000"}, "IROM1": {"start": "0x00400000", "size": "0x00100000"}}, "debug": "samv70/svd/ATSAMV70N20.svd", "processor": {"fpu": "DP_FPU", "endianness": "Little-endian"}}, "LPC1347FBD48": {"core": "Cortex-M3", "vendor": "NXP:11", "sectors": [[0, 4096]], "algorithm": {"Flash/LPC1xxx_64.FLM": {"default": "1", "ramsize": "0x0FE0", "size": "0x10000", "ramstart": "0x10000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.1.1.0.pack", "compile": {"header": "Device/Include/LPC13Uxx/LPC13Uxx.h"}, "pdsc_file": "http://www.keil.com/pack/Keil.LPC1300_DFP.pdsc", "memory": {"IRAM1": {"start": "0x10000000", "size": "0x2000"}, "IRAM2": {"start": "0x20000000", "size": "0x0800"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD/LPC13Uxx.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "72000000"}}, "EFM32GG11B420F2048IQ64": {"core": "Cortex-M4", "vendor": "Silicon Labs:21", "sectors": [[0, 4096]], "algorithm": {"Flash/FlashGECKOG1.flash": {"default": "0", "ramsize": null, "size": "0x00200000", "ramstart": null, "start": "0x00000000"}, "Flash/GECKOG1.FLM": {"default": "1", "ramsize": "0x4000", "size": "0x00200000", "ramstart": "0x20000000", "start": "0x00000000"}}, "debug-interface": [], "pack_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.5.5.0.pack", "compile": {"header": "Device/SiliconLabs/EFM32GG11B/Include/em_device.h", "define": "EFM32GG11B420F2048IQ64"}, "pdsc_file": "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.EFM32GG11B_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00080000"}, "IROM1": {"start": "0x00000000", "size": "0x00200000"}}, "debug": "SVD/EFM32GG11B/EFM32GG11B420F2048IQ64.svd", "processor": {"fpu": "1", "endianness": "Little-endian", "clock": "50000000"}}, "LM3S2410": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_128.FLM": {"default": "1", "ramsize": null, "size": "0x00018000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s2u93.h", "define": "LM3S2U93"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00008000"}, "IROM1": {"start": "0x00000000", "size": "0x00018000"}}, "debug": "SVD\\lm3s2410.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "NUC100RD1BN": {"core": "Cortex-M0", "vendor": "Nuvoton:18", "sectors": [[0, 512], [1048576, 512], [3145728, 8]], "algorithm": {"Flash/NUC100_CFG.FLM": {"default": "0", "ramsize": null, "size": "0x00000004", "ramstart": null, "start": "0x00300000"}, "Flash/NUC100_LD_4.FLM": {"default": "0", "ramsize": null, "size": "0x1000", "ramstart": null, "start": "0x00100000"}, "Flash/NUC100_AP_64.FLM": {"default": "1", "ramsize": null, "size": "0x10000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.2.1.pack", "compile": {"header": "Device\\NUC100\\Include\\NUC100Series.h"}, "pdsc_file": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x1000"}, "IROM1": {"start": "0x00000000", "size": "0x10000"}}, "debug": "SVD\\Nuvoton\\NUC100BN_v1.svd", "processor": {"fpu": "FPU", "endianness": "Configurable", "clock": "50000000"}}, "LM3S6110": {"core": "Cortex-M3", "vendor": "Texas Instruments:16", "sectors": [[0, 1024]], "algorithm": {"Flash/LM3S_64.FLM": {"default": "1", "ramsize": null, "size": "0x00010000", "ramstart": null, "start": "0x00000000"}}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.LM3S_DFP.1.1.0.pack", "compile": {"header": "Device\\Include\\lm3s6965.h", "define": "LM3S6965"}, "pdsc_file": "http://www.keil.com/pack/Keil.LM3S_DFP.pdsc", "memory": {"IRAM1": {"start": "0x20000000", "size": "0x00004000"}, "IROM1": {"start": "0x00000000", "size": "0x00010000"}}, "debug": "SVD\\lm3s6110.svd", "processor": {"fpu": "0", "endianness": "Little-endian", "clock": "25000000"}}, "R7S72103": {"core": "Cortex-A9", "vendor": "Renesas:117", "sectors": [[0, 4096]], "algorithm": {}, "debug-interface": [], "pack_file": "http://www.keil.com/pack/Keil.RZ_DFP.1.1.0.pack", "compile": {"header": "Device/Include/RZ_A1LU.h", "define": "RZ_A1LU"}, "pdsc_file": "http://www.keil.com/pack/Keil.RZ_DFP.pdsc", "memory": {"PROGRAM_FLASH": {"start": "0x18000000", "size": "0x800000"}}, "processor": {"fpu": "DP_FPU"}}}
\ No newline at end of file
--- a/arm_pack_manager/pack_manager.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/arm_pack_manager/pack_manager.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,3 +1,4 @@
+from __future__ import print_function, division, absolute_import
 import argparse
 from os.path import basename
 from tools.arm_pack_manager import Cache
@@ -5,7 +6,7 @@
 from os import makedirs
 from itertools import takewhile
 from fuzzywuzzy import process
-from tools.arm_pack_manager import Cache
+from .arm_pack_manager import Cache
 
 parser = argparse.ArgumentParser(description='A Handy little utility for keeping your cache of pack files up to date.')
 subparsers = parser.add_subparsers(title="Commands")
@@ -69,7 +70,7 @@
         for key, value in process.extract(match, urls, limit=None) :
             choices.setdefault(key, 0)
             choices[key] += value
-    choices = sorted([(v, k) for k, v in choices.iteritems()], reverse=True)
+    choices = sorted([(v, k) for k, v in choices.items()], reverse=True)
     if not choices : return []
     elif len(choices) == 1 : return [choices[0][1]]
     elif choices[0][0] > choices[1][0] : choices = choices[:1]
@@ -133,12 +134,12 @@
         aliases = sum([fuzzy_find([m], cache.aliases.keys()) for m in matches], [])
     if print_parts:
         for part in choices :
-            print part
+            print(part)
             if long :
                 pp.pprint(cache.index[part])
     if print_aliases:
         for alias in aliases :
-            print alias
+            print(alias)
             if long :
                 pp.pprint(cache.index[cache.aliases[alias]])
 
@@ -155,7 +156,7 @@
     else :
         for part in parts :
             index.update(dict(cache.find_device(part)))
-    for n, p in index.iteritems() :
+    for n, p in index.items() :
         try :
             if not exists(join(out, dirname(p['algorithm']['file']))) :
                 makedirs(join(out, dirname(p['algorithm']['file'])))
Binary file bootloaders/MTB_MTS_DRAGONFLY/bootloader.bin has changed
Binary file bootloaders/MTS_MDOT_F411RE/bootloader.bin has changed
Binary file bootloaders/REALTEK_RTL8195AM/ram_1.bin has changed
--- a/build.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/build.py	Tue Sep 25 13:43:09 2018 -0500
@@ -17,6 +17,8 @@
 
 LIBRARIES BUILD
 """
+from __future__ import print_function, division, absolute_import
+
 import sys
 from time import time
 from os.path import join, abspath, dirname
@@ -37,9 +39,10 @@
 from tools.build_api import mcu_toolchain_matrix
 from tools.build_api import print_build_results
 from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT
-from utils import argparse_filestring_type, args_error
 from tools.settings import CPPCHECK_CMD, CPPCHECK_MSG_FORMAT, CLI_COLOR_MAP
-from utils import argparse_filestring_type, argparse_dir_not_parent
+from tools.notifier.term import TerminalNotifier
+from tools.utils import argparse_filestring_type, args_error, argparse_many
+from tools.utils import argparse_filestring_type, argparse_dir_not_parent
 
 if __name__ == '__main__':
     start = time()
@@ -126,11 +129,14 @@
                       default=False,
                       help="Makes compiler more verbose, CI friendly.")
 
+    parser.add_argument("--ignore", dest="ignore", type=argparse_many(str),
+                        default=None, help="Comma separated list of patterns to add to mbedignore (eg. ./main.cpp)")
+
     options = parser.parse_args()
 
     # Only prints matrix of supported toolchains
     if options.supported_toolchains:
-        print mcu_toolchain_matrix(platform_filter=options.general_filter_regex)
+        print(mcu_toolchain_matrix(platform_filter=options.general_filter_regex))
         exit(0)
 
 
@@ -143,16 +149,6 @@
     if options.source_dir and not options.build_dir:
         args_error(parser, "argument --build is required by argument --source")
 
-    if options.color:
-        # This import happens late to prevent initializing colorization when we don't need it
-        import colorize
-        if options.verbose:
-            notify = mbedToolchain.print_notify_verbose
-        else:
-            notify = mbedToolchain.print_notify
-        notify = colorize.print_in_color_notifier(CLI_COLOR_MAP, notify)
-    else:
-        notify = None
 
     # Get libraries list
     libraries = []
@@ -184,66 +180,66 @@
             tt_id = "%s::%s" % (toolchain, target)
             if toolchain not in TARGET_MAP[target].supported_toolchains:
                 # Log this later
-                print "%s skipped: toolchain not supported" % tt_id
+                print("%s skipped: toolchain not supported" % tt_id)
                 skipped.append(tt_id)
             else:
                 try:
+                    notifier = TerminalNotifier(options.verbose, options.silent)
                     mcu = TARGET_MAP[target]
                     profile = extract_profile(parser, options, toolchain)
                     if options.source_dir:
-                        lib_build_res = build_library(options.source_dir, options.build_dir, mcu, toolchain,
-                                                    extra_verbose=options.extra_verbose_notify,
-                                                    verbose=options.verbose,
-                                                    silent=options.silent,
-                                                    jobs=options.jobs,
-                                                    clean=options.clean,
-                                                    archive=(not options.no_archive),
-                                                    macros=options.macros,
-                                                    name=options.artifact_name,
-                                                    build_profile=profile)
+                        lib_build_res = build_library(
+                            options.source_dir, options.build_dir, mcu, toolchain,
+                            jobs=options.jobs,
+                            clean=options.clean,
+                            archive=(not options.no_archive),
+                            macros=options.macros,
+                            name=options.artifact_name,
+                            build_profile=profile,
+                            ignore=options.ignore,
+                            notify = notifier,
+                        )
                     else:
-                        lib_build_res = build_mbed_libs(mcu, toolchain,
-                                                    extra_verbose=options.extra_verbose_notify,
-                                                    verbose=options.verbose,
-                                                    silent=options.silent,
-                                                    jobs=options.jobs,
-                                                    clean=options.clean,
-                                                        macros=options.macros,
-                                                        build_profile=profile)
+                        lib_build_res = build_mbed_libs(
+                            mcu, toolchain,
+                            jobs=options.jobs,
+                            clean=options.clean,
+                            macros=options.macros,
+                            build_profile=profile,
+                            ignore=options.ignore,
+                            notify=notifier,
+                        )
 
                     for lib_id in libraries:
-                        build_lib(lib_id, mcu, toolchain,
-                                extra_verbose=options.extra_verbose_notify,
-                                verbose=options.verbose,
-                                silent=options.silent,
-                                clean=options.clean,
-                                macros=options.macros,
-                                    jobs=options.jobs,
-                                    build_profile=profile)
+                        build_lib(
+                            lib_id, mcu, toolchain,
+                            clean=options.clean,
+                            macros=options.macros,
+                            jobs=options.jobs,
+                            build_profile=profile,
+                            ignore=options.ignore,
+                        )
                     if lib_build_res:
                         successes.append(tt_id)
                     else:
                         skipped.append(tt_id)
-                except Exception, e:
+                except Exception as e:
                     if options.verbose:
                         import traceback
                         traceback.print_exc(file=sys.stdout)
                         sys.exit(1)
                     failures.append(tt_id)
-                    print e
-
+                    print(e)
 
     # Write summary of the builds
-    print
-    print "Completed in: (%.2f)s" % (time() - start)
-    print
+    print("\nCompleted in: (%.2f)s\n" % (time() - start))
 
     for report, report_name in [(successes, "Build successes:"),
                                 (skipped, "Build skipped:"),
                                 (failures, "Build failures:"),
                                ]:
         if report:
-            print print_build_results(report, report_name),
+            print(print_build_results(report, report_name))
 
     if failures:
         sys.exit(1)
--- a/build_api.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/build_api.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,12 +14,15 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, division, absolute_import
 
 import re
 import tempfile
 import datetime
 import uuid
-from types import ListType
+import struct
+import zlib
+import hashlib
 from shutil import rmtree
 from os.path import join, exists, dirname, basename, abspath, normpath, splitext
 from os.path import relpath
@@ -27,20 +30,25 @@
 from time import time
 from intelhex import IntelHex
 from json import load, dump
-
-from tools.utils import mkdir, run_cmd, run_cmd_ext, NotSupportedException,\
-    ToolException, InvalidReleaseTargetException, intelhex_offset
-from tools.paths import MBED_CMSIS_PATH, MBED_TARGETS_PATH, MBED_LIBRARIES,\
-    MBED_HEADER, MBED_DRIVERS, MBED_PLATFORM, MBED_HAL, MBED_CONFIG_FILE,\
-    MBED_LIBRARIES_DRIVERS, MBED_LIBRARIES_PLATFORM, MBED_LIBRARIES_HAL,\
-    BUILD_DIR
-from tools.targets import TARGET_NAMES, TARGET_MAP, set_targets_json_location
-from tools.libraries import Library
-from tools.toolchains import TOOLCHAIN_CLASSES, mbedToolchain
 from jinja2 import FileSystemLoader
 from jinja2.environment import Environment
-from tools.config import Config
-from tools.build_profiles import find_build_profile, get_toolchain_profile, find_targets_json
+
+from .arm_pack_manager import Cache
+from .utils import (mkdir, run_cmd, run_cmd_ext, NotSupportedException,
+                    ToolException, InvalidReleaseTargetException,
+                    intelhex_offset, integer)
+from .paths import (MBED_CMSIS_PATH, MBED_TARGETS_PATH, MBED_LIBRARIES,
+                    MBED_HEADER, MBED_DRIVERS, MBED_PLATFORM, MBED_HAL,
+                    MBED_CONFIG_FILE, MBED_LIBRARIES_DRIVERS,
+                    MBED_LIBRARIES_PLATFORM, MBED_LIBRARIES_HAL,
+                    BUILD_DIR)
+from .resources import Resources, FileType, FileRef
+from .notifier.mock import MockNotifier
+from .targets import TARGET_NAMES, TARGET_MAP, CORE_ARCH, set_targets_json_location
+from .libraries import Library
+from .toolchains import TOOLCHAIN_CLASSES, mbedToolchain
+from .config import Config
+from .build_profiles import find_build_profile, get_toolchain_profile, find_targets_json
 
 RELEASE_VERSIONS = ['2', '5']
 
@@ -115,7 +123,7 @@
     result_wrap = {0: result}
     report[target][toolchain][id_name].append(result_wrap)
 
-def get_config(src_paths, target, toolchain_name):
+def get_config(src_paths, target, toolchain_name=None, app_config=None):
     """Get the configuration object for a target-toolchain combination
 
     Positional arguments:
@@ -124,39 +132,23 @@
     toolchain_name - the string that identifies the build tools
     """
     # Convert src_paths to a list if needed
-    if type(src_paths) != ListType:
+    if not isinstance(src_paths, list):
         src_paths = [src_paths]
 
-    # Pass all params to the unified prepare_resources()
-    toolchain = prepare_toolchain(src_paths, None, target, toolchain_name)
-
-    # Scan src_path for config files
-    resources = toolchain.scan_resources(src_paths[0])
-    for path in src_paths[1:]:
-        resources.add(toolchain.scan_resources(path))
-
-    # Update configuration files until added features creates no changes
-    prev_features = set()
-    while True:
-        # Update the configuration with any .json files found while scanning
-        toolchain.config.add_config_files(resources.json_files)
+    res = Resources(MockNotifier())
+    if toolchain_name:
+        toolchain = prepare_toolchain(src_paths, None, target, toolchain_name,
+                                      app_config=app_config)
+        config = toolchain.config
+        res.scan_with_toolchain(src_paths, toolchain, exclude=False)
+    else:
+        config = Config(target, src_paths, app_config=app_config)
+        res.scan_with_config(src_paths, config)
+    if config.has_regions:
+        _ = list(config.regions)
 
-        # Add features while we find new ones
-        features = set(toolchain.config.get_features())
-        if features == prev_features:
-            break
-
-        for feature in features:
-            if feature in resources.features:
-                resources += resources.features[feature]
-
-        prev_features = features
-    toolchain.config.validate_config()
-    if toolchain.config.has_regions:
-        _ = list(toolchain.config.regions)
-
-    cfg, macros = toolchain.config.get_config_data()
-    features = toolchain.config.get_features()
+    cfg, macros = config.get_config_data()
+    features = config.get_features()
     return cfg, macros, features
 
 def is_official_target(target_name, version):
@@ -193,22 +185,22 @@
 
         elif version == '5':
             # For version 5, ARM, GCC_ARM, and IAR toolchain support is required
-            required_toolchains = set(['ARM', 'GCC_ARM', 'IAR'])
-            required_toolchains_sorted = list(required_toolchains)
-            required_toolchains_sorted.sort()
+            required_toolchains = [
+                set(['ARM', 'GCC_ARM', 'IAR']),
+                set(['ARMC6'])
+            ]
             supported_toolchains = set(target.supported_toolchains)
-            supported_toolchains_sorted = list(supported_toolchains)
-            supported_toolchains_sorted.sort()
 
-            if not required_toolchains.issubset(supported_toolchains):
+            if not any(r.issubset(supported_toolchains)
+                       for r in required_toolchains):
                 result = False
                 reason = ("Target '%s' must support " % target.name) + \
                     ("ALL of the folowing toolchains to be included in the") + \
                     ((" mbed OS 5.0 official release: %s" + linesep) %
-                     ", ".join(required_toolchains_sorted)) + \
+                     ", ".join(sorted(required_toolchains[0]))) + \
                     ("Currently it is only configured to support the ") + \
                     ("following toolchains: %s" %
-                     ", ".join(supported_toolchains_sorted))
+                     ", ".join(sorted(supported_toolchains)))
 
             elif not target.default_lib == 'std':
                 result = False
@@ -284,37 +276,18 @@
 
     return mbed_official_release
 
-def add_regions_to_profile(profile, config, toolchain_class):
-    """Add regions to the build profile, if there are any.
-
-    Positional Arguments:
-    profile - the profile to update
-    config - the configuration object that owns the region
-    toolchain_class - the class of the toolchain being used
-    """
-    if not profile:
-        return
-    regions = list(config.regions)
-    for region in regions:
-        for define in [(region.name.upper() + "_ADDR", region.start),
-                       (region.name.upper() + "_SIZE", region.size)]:
-            profile["common"].append("-D%s=0x%x" %  define)
-    active_region = [r for r in regions if r.active][0]
-    for define in [("MBED_APP_START", active_region.start),
-                   ("MBED_APP_SIZE", active_region.size)]:
-        profile["ld"].append(toolchain_class.make_ld_define(*define))
-
-    print("Using regions in this build:")
-    for region in regions:
-        print("  Region %s size 0x%x, offset 0x%x"
-              % (region.name, region.size, region.start))
+ARM_COMPILERS = ("ARM", "ARMC6", "uARM")
+def target_supports_toolchain(target, toolchain_name):
+    if toolchain_name in ARM_COMPILERS:
+        return any(tc in target.supported_toolchains for tc in ARM_COMPILERS)
+    else:
+        return toolchain_name in target.supported_toolchains
 
 
 def prepare_toolchain(src_paths, build_dir, target, toolchain_name,
                       macros=None, clean=False, jobs=1,
-                      notify=None, silent=False, verbose=False,
-                      extra_verbose=False, config=None,
-                      app_config=None, build_profile=None):
+                      notify=None, config=None, app_config=None,
+                      build_profile=None, ignore=None):
     """ Prepares resource related objects - toolchain, target, config
 
     Positional arguments:
@@ -327,12 +300,10 @@
     clean - Rebuild everything if True
     jobs - how many compilers we can run at once
     notify - Notify function for logs
-    silent - suppress printing of progress indicators
-    verbose - Write the actual tools command lines used if True
-    extra_verbose - even more output!
     config - a Config object to use instead of creating one
     app_config - location of a chosen mbed_app.json file
     build_profile - a list of mergeable build profiles
+    ignore - list of paths to add to mbedignore
     """
 
     # We need to remove all paths which are repeated to avoid
@@ -342,6 +313,13 @@
     # If the configuration object was not yet created, create it now
     config = config or Config(target, src_paths, app_config=app_config)
     target = config.target
+    if not target_supports_toolchain(target, toolchain_name):
+        raise NotSupportedException(
+            "Target {} is not supported by toolchain {}".format(
+                target.name, toolchain_name))
+    if (toolchain_name == "ARM" and CORE_ARCH[target.core] == 8):
+        toolchain_name = "ARMC6"
+
     try:
         cur_tc = TOOLCHAIN_CLASSES[toolchain_name]
     except KeyError:
@@ -350,23 +328,82 @@
     profile = {'c': [], 'cxx': [], 'common': [], 'asm': [], 'ld': []}
     for contents in build_profile or []:
         for key in profile:
-            profile[key].extend(contents[toolchain_name][key])
+            profile[key].extend(contents[toolchain_name].get(key, []))
 
-    if config.has_regions:
-        add_regions_to_profile(profile, config, cur_tc)
-
-    toolchain = cur_tc(target, notify, macros, silent, build_dir=build_dir,
-                       extra_verbose=extra_verbose, build_profile=profile)
+    toolchain = cur_tc(
+        target, notify, macros, build_dir=build_dir, build_profile=profile)
 
     toolchain.config = config
     toolchain.jobs = jobs
     toolchain.build_all = clean
-    toolchain.VERBOSE = verbose
+
+    if ignore:
+        toolchain.add_ignore_patterns(root=".", base_path=".", patterns=ignore)
 
     return toolchain
 
-def merge_region_list(region_list, destination, padding=b'\xFF'):
-    """Merege the region_list into a single image
+def _printihex(ihex):
+    import pprint
+    pprint.PrettyPrinter().pprint(ihex.todict())
+
+def _real_region_size(region):
+    try:
+        part = intelhex_offset(region.filename, offset=region.start)
+        return (part.maxaddr() - part.minaddr()) + 1
+    except AttributeError:
+        return region.size
+
+
+def _fill_header(region_list, current_region):
+    """Fill an application header region
+
+    This is done it three steps:
+     * Fill the whole region with zeros
+     * Fill const, timestamp and size entries with their data
+     * Fill the digests using this header as the header region
+    """
+    region_dict = {r.name: r for r in region_list}
+    header = IntelHex()
+    header.puts(current_region.start, b'\x00' * current_region.size)
+    start = current_region.start
+    for member in current_region.filename:
+        _, type, subtype, data = member
+        member_size = Config.header_member_size(member)
+        if type == "const":
+            fmt = {
+                "8le": ">B", "16le": "<H", "32le": "<L", "64le": "<Q",
+                "8be": "<B", "16be": ">H", "32be": ">L", "64be": ">Q"
+            }[subtype]
+            header.puts(start, struct.pack(fmt, integer(data, 0)))
+        elif type == "timestamp":
+            fmt = {"32le": "<L", "64le": "<Q",
+                   "32be": ">L", "64be": ">Q"}[subtype]
+            header.puts(start, struct.pack(fmt, time()))
+        elif type == "size":
+            fmt = {"32le": "<L", "64le": "<Q",
+                   "32be": ">L", "64be": ">Q"}[subtype]
+            size = sum(_real_region_size(region_dict[r]) for r in data)
+            header.puts(start, struct.pack(fmt, size))
+        elif type  == "digest":
+            if data == "header":
+                ih = header[:start]
+            else:
+                ih = intelhex_offset(region_dict[data].filename, offset=region_dict[data].start)
+            if subtype.startswith("CRCITT32"):
+                fmt = {"CRCITT32be": ">l", "CRCITT32le": "<l"}[subtype]
+                header.puts(start, struct.pack(fmt, zlib.crc32(ih.tobinarray())))
+            elif subtype.startswith("SHA"):
+                if subtype == "SHA256":
+                    hash = hashlib.sha256()
+                elif subtype == "SHA512":
+                    hash = hashlib.sha512()
+                hash.update(ih.tobinarray())
+                header.puts(start, hash.digest())
+        start += Config.header_member_size(member)
+    return header
+
+def merge_region_list(region_list, destination, notify, padding=b'\xFF'):
+    """Merge the region_list into a single image
 
     Positional Arguments:
     region_list - list of regions, which should contain filenames
@@ -374,15 +411,22 @@
     padding - bytes to fill gapps with
     """
     merged = IntelHex()
+    _, format = splitext(destination)
 
-    print("Merging Regions:")
+    notify.info("Merging Regions")
 
     for region in region_list:
         if region.active and not region.filename:
             raise ToolException("Active region has no contents: No file found.")
+        if isinstance(region.filename, list):
+            header_basename, _ = splitext(destination)
+            header_filename = header_basename + "_header.hex"
+            _fill_header(region_list, region).tofile(header_filename, format='hex')
+            region = region._replace(filename=header_filename)
         if region.filename:
-            print("  Filling region %s with %s" % (region.name, region.filename))
+            notify.info("  Filling region %s with %s" % (region.name, region.filename))
             part = intelhex_offset(region.filename, offset=region.start)
+            part.start_addr = None
             part_size = (part.maxaddr() - part.minaddr()) + 1
             if part_size > region.size:
                 raise ToolException("Contents of region %s does not fit"
@@ -390,76 +434,32 @@
             merged.merge(part)
             pad_size = region.size - part_size
             if pad_size > 0 and region != region_list[-1]:
-                print("  Padding region %s with 0x%x bytes" % (region.name, pad_size))
-                merged.puts(merged.maxaddr() + 1, padding * pad_size)
+                notify.info("  Padding region %s with 0x%x bytes" %
+                            (region.name, pad_size))
+                if format is ".hex":
+                    """The offset will be in the hex file generated when we're done,
+                    so we can skip padding here"""
+                else:
+                    merged.puts(merged.maxaddr() + 1, padding * pad_size)
 
     if not exists(dirname(destination)):
         makedirs(dirname(destination))
-    print("Space used after regions merged: 0x%x" %
-          (merged.maxaddr() - merged.minaddr() + 1))
-    with open(destination, "wb+") as output:
-        merged.tofile(output, format='bin')
-
-def scan_resources(src_paths, toolchain, dependencies_paths=None,
-                   inc_dirs=None, base_path=None, collect_ignores=False):
-    """ Scan resources using initialized toolcain
+    notify.info("Space used after regions merged: 0x%x" %
+                (merged.maxaddr() - merged.minaddr() + 1))
+    merged.tofile(destination, format=format.strip("."))
 
-    Positional arguments
-    src_paths - the paths to source directories
-    toolchain - valid toolchain object
-    dependencies_paths - dependency paths that we should scan for include dirs
-    inc_dirs - additional include directories which should be added to
-               the scanner resources
-    """
-
-    # Scan src_path
-    resources = toolchain.scan_resources(src_paths[0], base_path=base_path,
-                                         collect_ignores=collect_ignores)
-    for path in src_paths[1:]:
-        resources.add(toolchain.scan_resources(path, base_path=base_path,
-                                               collect_ignores=collect_ignores))
 
-    # Scan dependency paths for include dirs
-    if dependencies_paths is not None:
-        for path in dependencies_paths:
-            lib_resources = toolchain.scan_resources(path)
-            resources.inc_dirs.extend(lib_resources.inc_dirs)
-
-    # Add additional include directories if passed
-    if inc_dirs:
-        if type(inc_dirs) == ListType:
-            resources.inc_dirs.extend(inc_dirs)
-        else:
-            resources.inc_dirs.append(inc_dirs)
-
-    # Load resources into the config system which might expand/modify resources
-    # based on config data
-    resources = toolchain.config.load_resources(resources)
+UPDATE_WHITELIST = (
+    "application",
+)
 
-    # Set the toolchain's configuration data
-    toolchain.set_config_data(toolchain.config.get_config_data())
-
-    if  (hasattr(toolchain.target, "release_versions") and
-            "5" not in toolchain.target.release_versions and
-            "rtos" in toolchain.config.lib_config_data):
-        if "Cortex-A" in toolchain.target.core:
-            raise NotSupportedException(
-                ("%s Will be supported in mbed OS 5.6. "
-                    "To use the %s, please checkout the mbed OS 5.4 release branch. "
-                    "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice "
-                    "for more information") % (toolchain.target.name, toolchain.target.name))
-        else:
-            raise NotSupportedException("Target does not support mbed OS 5")
-
-    return resources
 
 def build_project(src_paths, build_path, target, toolchain_name,
-                  libraries_paths=None, linker_script=None,
-                  clean=False, notify=None, verbose=False, name=None,
-                  macros=None, inc_dirs=None, jobs=1, silent=False,
+                  libraries_paths=None, linker_script=None, clean=False,
+                  notify=None, name=None, macros=None, inc_dirs=None, jobs=1,
                   report=None, properties=None, project_id=None,
-                  project_description=None, extra_verbose=False, config=None,
-                  app_config=None, build_profile=None, stats_depth=None):
+                  project_description=None, config=None,
+                  app_config=None, build_profile=None, stats_depth=None, ignore=None):
     """ Build a project. A project may be a test or a user program.
 
     Positional arguments:
@@ -474,25 +474,22 @@
     linker_script - the file that drives the linker to do it's job
     clean - Rebuild everything if True
     notify - Notify function for logs
-    verbose - Write the actual tools command lines used if True
     name - the name of the project
     macros - additional macros
     inc_dirs - additional directories where include files may be found
     jobs - how many compilers we can run at once
-    silent - suppress printing of progress indicators
     report - a dict where a result may be appended
     properties - UUUUHHHHH beats me
     project_id - the name put in the report
     project_description - the human-readable version of what this thing does
-    extra_verbose - even more output!
     config - a Config object to use instead of creating one
     app_config - location of a chosen mbed_app.json file
     build_profile - a dict of flags that will be passed to the compiler
     stats_depth - depth level for memap to display file/dirs
+    ignore - list of paths to add to mbedignore
     """
-
     # Convert src_path to a list if needed
-    if type(src_paths) != ListType:
+    if not isinstance(src_paths, list):
         src_paths = [src_paths]
     # Extend src_paths wiht libraries_paths
     if libraries_paths is not None:
@@ -528,8 +525,7 @@
             profile_data = get_toolchain_profile(self.name, profile)
             if not profile_data:
                 return
-            if verbose:
-                self.info("Using toolchain %s profile %s" % (self.name, profile))
+            notify.info("Using toolchain %s profile %s" % (self.name, profile))
 
             for k,v in profile_data.items():
                 if self.flags.has_key(k):
@@ -544,15 +540,15 @@
 
     toolchain = prepare_toolchain(
         src_paths, build_path, target, toolchain_name, macros=macros,
-        clean=clean, jobs=jobs, notify=notify, silent=silent, verbose=verbose,
-        extra_verbose=extra_verbose, config=config, app_config=app_config,
-        build_profile=build_profile)
+        clean=clean, jobs=jobs, notify=notify, config=config,
+        app_config=app_config, build_profile=build_profile, ignore=ignore)
+    toolchain.version_check()
 
     # The first path will give the name to the library
     name = (name or toolchain.config.name or
             basename(normpath(abspath(src_paths[0]))))
-    toolchain.info("Building project %s (%s, %s)" %
-                   (name, toolchain.target.name, toolchain_name))
+    notify.info("Building project %s (%s, %s)" %
+                (name, toolchain.target.name, toolchain_name))
 
     # Initialize reporting
     if report != None:
@@ -569,36 +565,48 @@
                             vendor_label)
 
     try:
-        # Call unified scan_resources
-        resources = scan_resources(src_paths, toolchain, inc_dirs=inc_dirs)
+        resources = Resources(notify).scan_with_toolchain(
+            src_paths, toolchain, inc_dirs=inc_dirs)
 
         # Change linker script if specified
         if linker_script is not None:
-            resources.linker_script = linker_script
+            resources.add_file_ref(linker_script, linker_script)
 
         # Compile Sources
-        objects = toolchain.compile_sources(resources, resources.inc_dirs)
-        resources.objects.extend(objects)
+        objects = toolchain.compile_sources(resources, sorted(resources.get_file_paths(FileType.INC_DIR)))
+        resources.add_files_to_type(FileType.OBJECT, objects)
 
         # Link Program
         if toolchain.config.has_regions:
-            res, _ = toolchain.link_program(resources, build_path, name + "_application")
+            binary, _ = toolchain.link_program(resources, build_path, name + "_application")
             region_list = list(toolchain.config.regions)
-            region_list = [r._replace(filename=res) if r.active else r
+            region_list = [r._replace(filename=binary) if r.active else r
                            for r in region_list]
-            res = join(build_path, name) + ".bin"
-            merge_region_list(region_list, res)
+            res = "%s.%s" % (join(build_path, name),
+                             getattr(toolchain.target, "OUTPUT_EXT", "bin"))
+            merge_region_list(region_list, res, notify)
+            update_regions = [
+                r for r in region_list if r.name in UPDATE_WHITELIST
+            ]
+            if update_regions:
+                update_res = "%s_update.%s" % (
+                    join(build_path, name),
+                    getattr(toolchain.target, "OUTPUT_EXT", "bin")
+                )
+                merge_region_list(update_regions, update_res, notify)
+                res = (res, update_res)
+            else:
+                res = (res, None)
         else:
             res, _ = toolchain.link_program(resources, build_path, name)
+            res = (res, None)
 
         memap_instance = getattr(toolchain, 'memap_instance', None)
         memap_table = ''
         if memap_instance:
             # Write output to stdout in text (pretty table) format
             memap_table = memap_instance.generate_output('table', stats_depth)
-
-            if not silent:
-                print memap_table
+            notify.info(memap_table)
 
             # Write output to file in JSON format
             map_out = join(build_path, name + "_map.json")
@@ -608,16 +616,19 @@
             map_csv = join(build_path, name + "_map.csv")
             memap_instance.generate_output('csv-ci', stats_depth, map_csv)
 
-        resources.detect_duplicates(toolchain)
+            map_html = join(build_path, name + "_map.html")
+            memap_instance.generate_output('html', stats_depth, map_html)
+
+        resources.detect_duplicates()
 
         if report != None:
             end = time()
             cur_result["elapsed_time"] = end - start
-            cur_result["output"] = toolchain.get_output() + memap_table
             cur_result["result"] = "OK"
-            cur_result["memory_usage"] = memap_instance.mem_report
-            cur_result["bin"] = res
-            cur_result["elf"] = splitext(res)[0] + ".elf"
+            cur_result["memory_usage"] = (memap_instance.mem_report
+                                          if memap_instance is not None else None)
+            cur_result["bin"] = res[0]
+            cur_result["elf"] = splitext(res[0])[0] + ".elf"
             cur_result.update(toolchain.report)
 
             add_result_to_report(report, cur_result)
@@ -635,22 +646,16 @@
 
             cur_result["elapsed_time"] = end - start
 
-            toolchain_output = toolchain.get_output()
-            if toolchain_output:
-                cur_result["output"] += toolchain_output
-
             add_result_to_report(report, cur_result)
-
         # Let Exception propagate
         raise
 
 def build_library(src_paths, build_path, target, toolchain_name,
                   dependencies_paths=None, name=None, clean=False,
-                  archive=True, notify=None, verbose=False, macros=None,
-                  inc_dirs=None, jobs=1, silent=False, report=None,
-                  properties=None, extra_verbose=False, project_id=None,
+                  archive=True, notify=None, macros=None, inc_dirs=None, jobs=1,
+                  report=None, properties=None, project_id=None,
                   remove_config_header_file=False, app_config=None,
-                  build_profile=None):
+                  build_profile=None, ignore=None):
     """ Build a library
 
     Positional arguments:
@@ -666,23 +671,22 @@
     clean - Rebuild everything if True
     archive - whether the library will create an archive file
     notify - Notify function for logs
-    verbose - Write the actual tools command lines used if True
     macros - additional macros
     inc_dirs - additional directories where include files may be found
     jobs - how many compilers we can run at once
-    silent - suppress printing of progress indicators
     report - a dict where a result may be appended
     properties - UUUUHHHHH beats me
-    extra_verbose - even more output!
     project_id - the name that goes in the report
     remove_config_header_file - delete config header file when done building
     app_config - location of a chosen mbed_app.json file
     build_profile - a dict of flags that will be passed to the compiler
+    ignore - list of paths to add to mbedignore
     """
 
     # Convert src_path to a list if needed
-    if type(src_paths) != ListType:
+    if not isinstance(src_paths, list):
         src_paths = [src_paths]
+    src_paths = [relpath(s) for s in src_paths]
 
     # Build path
     if archive:
@@ -700,14 +704,13 @@
     # Pass all params to the unified prepare_toolchain()
     toolchain = prepare_toolchain(
         src_paths, build_path, target, toolchain_name, macros=macros,
-        clean=clean, jobs=jobs, notify=notify, silent=silent,
-        verbose=verbose, extra_verbose=extra_verbose, app_config=app_config,
-        build_profile=build_profile)
+        clean=clean, jobs=jobs, notify=notify, app_config=app_config,
+        build_profile=build_profile, ignore=ignore)
 
     # The first path will give the name to the library
     if name is None:
         name = basename(normpath(abspath(src_paths[0])))
-    toolchain.info("Building library %s (%s, %s)" %
+    notify.info("Building library %s (%s, %s)" %
                    (name, toolchain.target.name, toolchain_name))
 
     # Initialize reporting
@@ -735,31 +738,25 @@
             raise Exception(error_msg)
 
     try:
-        # Call unified scan_resources
-        resources = scan_resources(src_paths, toolchain,
-                                   dependencies_paths=dependencies_paths,
-                                   inc_dirs=inc_dirs)
-
+        res = Resources(notify).scan_with_toolchain(
+            src_paths, toolchain, dependencies_paths, inc_dirs=inc_dirs)
 
         # Copy headers, objects and static libraries - all files needed for
         # static lib
-        toolchain.copy_files(resources.headers, build_path, resources=resources)
-        toolchain.copy_files(resources.objects, build_path, resources=resources)
-        toolchain.copy_files(resources.libraries, build_path,
-                             resources=resources)
-        toolchain.copy_files(resources.json_files, build_path,
-                             resources=resources)
-        if resources.linker_script:
-            toolchain.copy_files(resources.linker_script, build_path,
-                                 resources=resources)
-
-        if resources.hex_files:
-            toolchain.copy_files(resources.hex_files, build_path,
-                                 resources=resources)
-
+        to_copy = (
+            res.get_file_refs(FileType.HEADER) +
+            res.get_file_refs(FileType.OBJECT) +
+            res.get_file_refs(FileType.LIB) +
+            res.get_file_refs(FileType.JSON) +
+            res.get_file_refs(FileType.LD_SCRIPT) +
+            res.get_file_refs(FileType.HEX) +
+            res.get_file_refs(FileType.BIN)
+        )
+        toolchain.copy_files(to_copy, build_path)
         # Compile Sources
-        objects = toolchain.compile_sources(resources, resources.inc_dirs)
-        resources.objects.extend(objects)
+        objects = toolchain.compile_sources(
+            res, res.get_file_paths(FileType.INC_DIR))
+        res.add_files_to_type(FileType.OBJECT, objects)
 
         if archive:
             toolchain.build_library(objects, build_path, name)
@@ -772,10 +769,7 @@
         if report != None:
             end = time()
             cur_result["elapsed_time"] = end - start
-            cur_result["output"] = toolchain.get_output()
             cur_result["result"] = "OK"
-
-
             add_result_to_report(report, cur_result)
         return True
 
@@ -790,10 +784,6 @@
 
             cur_result["elapsed_time"] = end - start
 
-            toolchain_output = toolchain.get_output()
-            if toolchain_output:
-                cur_result["output"] += toolchain_output
-
             add_result_to_report(report, cur_result)
 
         # Let Exception propagate
@@ -807,10 +797,9 @@
     real_tc_name = TOOLCHAIN_CLASSES[toolchain_name].__name__
     return join("TARGET_" + target_name, "TOOLCHAIN_" + real_tc_name)
 
-def build_lib(lib_id, target, toolchain_name, verbose=False,
-              clean=False, macros=None, notify=None, jobs=1, silent=False,
-              report=None, properties=None, extra_verbose=False,
-              build_profile=None):
+def build_lib(lib_id, target, toolchain_name, clean=False, macros=None,
+              notify=None, jobs=1, report=None, properties=None,
+              build_profile=None, ignore=None):
     """ Legacy method for building mbed libraries
 
     Positional arguments:
@@ -820,15 +809,13 @@
 
     Keyword arguments:
     clean - Rebuild everything if True
-    verbose - Write the actual tools command lines used if True
     macros - additional macros
     notify - Notify function for logs
     jobs - how many compilers we can run at once
-    silent - suppress printing of progress indicators
     report - a dict where a result may be appended
     properties - UUUUHHHHH beats me
-    extra_verbose - even more output!
     build_profile - a dict of flags that will be passed to the compiler
+    ignore - list of paths to add to mbedignore
     """
     lib = Library(lib_id)
     if not lib.is_supported(target, toolchain_name):
@@ -848,15 +835,14 @@
     build_path = lib.build_dir
     dependencies_paths = lib.dependencies
     inc_dirs = lib.inc_dirs
-    inc_dirs_ext = lib.inc_dirs_ext
 
-    if type(src_paths) != ListType:
+    if not isinstance(src_paths, list):
         src_paths = [src_paths]
 
     # The first path will give the name to the library
     name = basename(src_paths[0])
 
-    if report != None:
+    if report is not None:
         start = time()
         id_name = name.upper()
         description = name
@@ -892,52 +878,26 @@
 
         toolchain = prepare_toolchain(
             src_paths, tmp_path, target, toolchain_name, macros=macros,
-            notify=notify, silent=silent, extra_verbose=extra_verbose,
-            build_profile=build_profile, jobs=jobs, clean=clean)
+            notify=notify, build_profile=build_profile, jobs=jobs, clean=clean,
+            ignore=ignore)
 
-        toolchain.info("Building library %s (%s, %s)" %
-                       (name.upper(), target.name, toolchain_name))
+        notify.info("Building library %s (%s, %s)" %
+                    (name.upper(), target.name, toolchain_name))
 
         # Take into account the library configuration (MBED_CONFIG_FILE)
         config = toolchain.config
         config.add_config_files([MBED_CONFIG_FILE])
 
         # Scan Resources
-        resources = []
-        for src_path in src_paths:
-            resources.append(toolchain.scan_resources(src_path))
-
-        # Add extra include directories / files which are required by library
-        # This files usually are not in the same directory as source files so
-        # previous scan will not include them
-        if inc_dirs_ext is not None:
-            for inc_ext in inc_dirs_ext:
-                resources.append(toolchain.scan_resources(inc_ext))
-
-        # Dependencies Include Paths
-        dependencies_include_dir = []
-        if dependencies_paths is not None:
-            for path in dependencies_paths:
-                lib_resources = toolchain.scan_resources(path)
-                dependencies_include_dir.extend(lib_resources.inc_dirs)
-                dependencies_include_dir.extend(map(dirname, lib_resources.inc_dirs))
-
-        if inc_dirs:
-            dependencies_include_dir.extend(inc_dirs)
-
-        # Add other discovered configuration data to the configuration object
-        for res in resources:
-            config.load_resources(res)
-        toolchain.set_config_data(toolchain.config.get_config_data())
-
+        resources = Resources(notify).scan_with_toolchain(
+            src_paths + (lib.inc_dirs_ext or []), toolchain,
+            inc_dirs=inc_dirs, dependencies_paths=dependencies_paths)
 
         # Copy Headers
-        for resource in resources:
-            toolchain.copy_files(resource.headers, build_path,
-                                 resources=resource)
+        toolchain.copy_files(
+            resources.get_file_refs(FileType.HEADER), build_path)
 
-        dependencies_include_dir.extend(
-            toolchain.scan_resources(build_path).inc_dirs)
+        dependencies_include_dir = Resources(notify).sacn_with_toolchain([build_path], toolchain).inc_dirs
 
         # Compile Sources
         objects = []
@@ -949,7 +909,6 @@
         if report != None and needed_update:
             end = time()
             cur_result["elapsed_time"] = end - start
-            cur_result["output"] = toolchain.get_output()
             cur_result["result"] = "OK"
 
             add_result_to_report(report, cur_result)
@@ -961,65 +920,80 @@
             cur_result["result"] = "FAIL"
             cur_result["elapsed_time"] = end - start
 
-            toolchain_output = toolchain.get_output()
-            if toolchain_output:
-                cur_result["output"] += toolchain_output
-
             add_result_to_report(report, cur_result)
 
         # Let Exception propagate
         raise
 
-# We do have unique legacy conventions about how we build and package the mbed
-# library
-def build_mbed_libs(target, toolchain_name, verbose=False,
-                    clean=False, macros=None, notify=None, jobs=1, silent=False,
-                    report=None, properties=None, extra_verbose=False,
-                    build_profile=None):
-    """ Function returns True is library was built and false if building was
-    skipped
+
+# A number of compiled files need to be copied as objects as the linker
+# will not search for weak symbol overrides in archives. These are:
+#   - mbed_retarget.o: to make sure that the C standard lib symbols get
+#                      overridden
+#   - mbed_board.o: `mbed_die` is weak
+#   - mbed_overrides.o: this contains platform overrides of various
+#                       weak SDK functions
+#   - mbed_main.o: this contains main redirection
+#   - mbed_sdk_boot.o: this contains the main boot code in
+#   - PeripheralPins.o: PinMap can be weak
+SEPARATE_NAMES = [
+    'PeripheralPins.o',
+    'mbed_retarget.o',
+    'mbed_board.o',
+    'mbed_overrides.o',
+    'mbed_main.o',
+    'mbed_sdk_boot.o',
+]
+
+
+def build_mbed_libs(target, toolchain_name, clean=False, macros=None,
+                    notify=None, jobs=1, report=None, properties=None,
+                    build_profile=None, ignore=None):
+    """ Build legacy libraries for a target and toolchain pair
 
     Positional arguments:
     target - the MCU or board that the project will compile for
     toolchain_name - the name of the build tools
 
     Keyword arguments:
-    verbose - Write the actual tools command lines used if True
     clean - Rebuild everything if True
     macros - additional macros
     notify - Notify function for logs
     jobs - how many compilers we can run at once
-    silent - suppress printing of progress indicators
     report - a dict where a result may be appended
     properties - UUUUHHHHH beats me
-    extra_verbose - even more output!
     build_profile - a dict of flags that will be passed to the compiler
+    ignore - list of paths to add to mbedignore
+
+    Return - True if target + toolchain built correctly, False if not supported
     """
 
-    if report != None:
+    if report is not None:
         start = time()
         id_name = "MBED"
         description = "mbed SDK"
         vendor_label = target.extra_labels[0]
         cur_result = None
         prep_report(report, target.name, toolchain_name, id_name)
-        cur_result = create_result(target.name, toolchain_name, id_name,
-                                   description)
+        cur_result = create_result(
+            target.name, toolchain_name, id_name, description)
+        if properties is not None:
+            prep_properties(
+                properties, target.name, toolchain_name, vendor_label)
 
-        if properties != None:
-            prep_properties(properties, target.name, toolchain_name,
-                            vendor_label)
-
-    # Check toolchain support
     if toolchain_name not in target.supported_toolchains:
         supported_toolchains_text = ", ".join(target.supported_toolchains)
-        print('%s target is not yet supported by toolchain %s' %
-              (target.name, toolchain_name))
-        print('%s target supports %s toolchain%s' %
-              (target.name, supported_toolchains_text, 's'
-               if len(target.supported_toolchains) > 1 else ''))
+        notify.info('The target {} does not support the toolchain {}'.format(
+            target.name,
+            toolchain_name
+        ))
+        notify.info('{} supports {} toolchain{}'.format(
+            target.name,
+            supported_toolchains_text,
+            's' if len(target.supported_toolchains) > 1 else ''
+        ))
 
-        if report != None:
+        if report is not None:
             cur_result["result"] = "SKIP"
             add_result_to_report(report, cur_result)
 
@@ -1027,88 +1001,59 @@
 
     try:
         # Source and Build Paths
-        build_target = join(MBED_LIBRARIES, "TARGET_" + target.name)
-        build_toolchain = join(MBED_LIBRARIES, mbed2_obj_path(target.name, toolchain_name))
+        build_toolchain = join(
+            MBED_LIBRARIES, mbed2_obj_path(target.name, toolchain_name))
         mkdir(build_toolchain)
 
-        # Toolchain
-        tmp_path = join(MBED_LIBRARIES, '.temp', mbed2_obj_path(target.name, toolchain_name))
+        tmp_path = join(
+            MBED_LIBRARIES,
+            '.temp',
+            mbed2_obj_path(target.name, toolchain_name)
+        )
         mkdir(tmp_path)
 
+        # Toolchain and config
         toolchain = prepare_toolchain(
-            [""], tmp_path, target, toolchain_name, macros=macros,verbose=verbose,
-            notify=notify, silent=silent, extra_verbose=extra_verbose,
-            build_profile=build_profile, jobs=jobs, clean=clean)
+            [""], tmp_path, target, toolchain_name, macros=macros, notify=notify,
+            build_profile=build_profile, jobs=jobs, clean=clean, ignore=ignore)
 
-        # Take into account the library configuration (MBED_CONFIG_FILE)
         config = toolchain.config
         config.add_config_files([MBED_CONFIG_FILE])
         toolchain.set_config_data(toolchain.config.get_config_data())
 
-        # CMSIS
-        toolchain.info("Building library %s (%s, %s)" %
-                       ('CMSIS', target.name, toolchain_name))
-        cmsis_src = MBED_CMSIS_PATH
-        resources = toolchain.scan_resources(cmsis_src)
-
-        toolchain.copy_files(resources.headers, build_target)
-        toolchain.copy_files(resources.linker_script, build_toolchain)
-        toolchain.copy_files(resources.bin_files, build_toolchain)
-
-        objects = toolchain.compile_sources(resources, tmp_path)
-        toolchain.copy_files(objects, build_toolchain)
-
-        # mbed
-        toolchain.info("Building library %s (%s, %s)" %
-                       ('MBED', target.name, toolchain_name))
-
-        # Common Headers
-        toolchain.copy_files([MBED_HEADER], MBED_LIBRARIES)
+        # distribute header files
+        toolchain.copy_files(
+            [FileRef(basename(MBED_HEADER),MBED_HEADER)], MBED_LIBRARIES)
         library_incdirs = [dirname(MBED_LIBRARIES), MBED_LIBRARIES]
 
         for dir, dest in [(MBED_DRIVERS, MBED_LIBRARIES_DRIVERS),
                           (MBED_PLATFORM, MBED_LIBRARIES_PLATFORM),
                           (MBED_HAL, MBED_LIBRARIES_HAL)]:
-            resources = toolchain.scan_resources(dir)
-            toolchain.copy_files(resources.headers, dest)
+            resources = Resources(notify).scan_with_toolchain([dir], toolchain)
+            toolchain.copy_files(
+                [FileRef(basename(p), p) for p
+                 in resources.get_file_paths(FileType.HEADER)] ,
+                dest)
             library_incdirs.append(dest)
 
-        # Target specific sources
-        hal_src = MBED_TARGETS_PATH
-        hal_implementation = toolchain.scan_resources(hal_src)
-        toolchain.copy_files(hal_implementation.headers +
-                             hal_implementation.hex_files +
-                             hal_implementation.libraries +
-                             [MBED_CONFIG_FILE],
-                             build_target, resources=hal_implementation)
-        toolchain.copy_files(hal_implementation.linker_script, build_toolchain)
-        toolchain.copy_files(hal_implementation.bin_files, build_toolchain)
-        incdirs = toolchain.scan_resources(build_target).inc_dirs
-        objects = toolchain.compile_sources(hal_implementation,
-                                            library_incdirs + incdirs)
-        toolchain.copy_files(objects, build_toolchain)
+        # collect resources of the libs to compile
+        cmsis_res = Resources(notify).scan_with_toolchain(
+            [MBED_CMSIS_PATH], toolchain)
+        hal_res = Resources(notify).scan_with_toolchain(
+            [MBED_TARGETS_PATH], toolchain)
+        mbed_resources = Resources(notify).scan_with_toolchain(
+            [MBED_DRIVERS, MBED_PLATFORM, MBED_HAL], toolchain)
 
-        # Common Sources
-        mbed_resources = None
-        for dir in [MBED_DRIVERS, MBED_PLATFORM, MBED_HAL]:
-            mbed_resources += toolchain.scan_resources(dir)
-
-        objects = toolchain.compile_sources(mbed_resources,
-                                            library_incdirs + incdirs)
+        incdirs = cmsis_res.inc_dirs + hal_res.inc_dirs + library_incdirs
 
-        # A number of compiled files need to be copied as objects as opposed to
-        # way the linker search for symbols in archives. These are:
-        #   - mbed_retarget.o: to make sure that the C standard lib symbols get
-        #                 overridden
-        #   - mbed_board.o: mbed_die is weak
-        #   - mbed_overrides.o: this contains platform overrides of various
-        #                       weak SDK functions
-        #   - mbed_main.o: this contains main redirection
-        separate_names, separate_objects = ['mbed_retarget.o', 'mbed_board.o',
-                                            'mbed_overrides.o', 'mbed_main.o', 'mbed_sdk_boot.o'], []
+        # Build Things
+        notify.info("Building library %s (%s, %s)" %
+                    ('MBED', target.name, toolchain_name))
+        objects = toolchain.compile_sources(mbed_resources, incdirs)
+        separate_objects = []
 
         for obj in objects:
-            for name in separate_names:
+            for name in SEPARATE_NAMES:
                 if obj.endswith(name):
                     separate_objects.append(obj)
 
@@ -1116,35 +1061,48 @@
             objects.remove(obj)
 
         toolchain.build_library(objects, build_toolchain, "mbed")
+        notify.info("Building library %s (%s, %s)" %
+                    ('CMSIS', target.name, toolchain_name))
+        cmsis_objects = toolchain.compile_sources(cmsis_res, incdirs + [tmp_path])
+        notify.info("Building library %s (%s, %s)" %
+                    ('HAL', target.name, toolchain_name))
+        hal_objects = toolchain.compile_sources(hal_res, incdirs + [tmp_path])
 
-        for obj in separate_objects:
-            toolchain.copy_files(obj, build_toolchain)
+        # Copy everything into the build directory
+        to_copy_paths = [
+            hal_res.get_file_paths(FileType.HEADER),
+            hal_res.get_file_paths(FileType.HEX),
+            hal_res.get_file_paths(FileType.BIN),
+            hal_res.get_file_paths(FileType.LIB),
+            cmsis_res.get_file_paths(FileType.HEADER),
+            cmsis_res.get_file_paths(FileType.BIN),
+            cmsis_res.get_file_paths(FileType.LD_SCRIPT),
+            hal_res.get_file_paths(FileType.LD_SCRIPT),
+            [MBED_CONFIG_FILE],
+            cmsis_objects,
+            hal_objects,
+            separate_objects,
+        ]
+        to_copy = [FileRef(basename(p), p) for p in sum(to_copy_paths, [])]
+        toolchain.copy_files(to_copy, build_toolchain)
 
-        if report != None:
+        if report is not None:
             end = time()
             cur_result["elapsed_time"] = end - start
-            cur_result["output"] = toolchain.get_output()
             cur_result["result"] = "OK"
-
             add_result_to_report(report, cur_result)
 
         return True
 
     except Exception as exc:
-        if report != None:
+        if report is not None:
             end = time()
             cur_result["result"] = "FAIL"
             cur_result["elapsed_time"] = end - start
 
-            toolchain_output = toolchain.get_output()
-            if toolchain_output:
-                cur_result["output"] += toolchain_output
-
             cur_result["output"] += str(exc)
 
             add_result_to_report(report, cur_result)
-
-        # Let Exception propagate
         raise
 
 
@@ -1169,24 +1127,20 @@
                 if toolchain not in unique_supported_toolchains:
                     unique_supported_toolchains.append(toolchain)
 
-    if "ARM" in unique_supported_toolchains:
-        unique_supported_toolchains.append("ARMC6")
+    return unique_supported_toolchains
+
 
-    return unique_supported_toolchains
+def _lowercase_release_version(release_version):
+    try:
+        return release_version.lower()
+    except AttributeError:
+        return 'all'
 
 def mcu_toolchain_list(release_version='5'):
     """  Shows list of toolchains
 
     """
-
-    if isinstance(release_version, basestring):
-        # Force release_version to lowercase if it is a string
-        release_version = release_version.lower()
-    else:
-        # Otherwise default to printing all known targets and toolchains
-        release_version = 'all'
-
-
+    release_version = _lowercase_release_version(release_version)
     version_release_targets = {}
     version_release_target_names = {}
 
@@ -1211,15 +1165,7 @@
     """  Shows target list
 
     """
-
-    if isinstance(release_version, basestring):
-        # Force release_version to lowercase if it is a string
-        release_version = release_version.lower()
-    else:
-        # Otherwise default to printing all known targets and toolchains
-        release_version = 'all'
-
-
+    release_version = _lowercase_release_version(release_version)
     version_release_targets = {}
     version_release_target_names = {}
 
@@ -1254,16 +1200,8 @@
     release_version - get the matrix for this major version number
     """
     # Only use it in this function so building works without extra modules
-    from prettytable import PrettyTable
-
-    if isinstance(release_version, basestring):
-        # Force release_version to lowercase if it is a string
-        release_version = release_version.lower()
-    else:
-        # Otherwise default to printing all known targets and toolchains
-        release_version = 'all'
-
-
+    from prettytable import PrettyTable, HEADER
+    release_version = _lowercase_release_version(release_version)
     version_release_targets = {}
     version_release_target_names = {}
 
@@ -1284,7 +1222,7 @@
 
     # All tests status table print
     columns = prepend_columns + unique_supported_toolchains
-    table_printer = PrettyTable(columns)
+    table_printer = PrettyTable(columns, junction_char="|", hrules=HEADER)
     # Align table
     for col in columns:
         table_printer.align[col] = "c"
@@ -1317,9 +1255,13 @@
             row.append(text)
 
         for unique_toolchain in unique_supported_toolchains:
-            if (unique_toolchain in TARGET_MAP[target].supported_toolchains or
+            tgt_obj = TARGET_MAP[target]
+            if (unique_toolchain in tgt_obj.supported_toolchains or
                 (unique_toolchain == "ARMC6" and
-                 "ARM" in TARGET_MAP[target].supported_toolchains)):
+                 "ARM" in tgt_obj.supported_toolchains) or
+                (unique_toolchain == "ARM" and
+                 "ARMC6" in tgt_obj.supported_toolchains and
+                 CORE_ARCH[tgt_obj.core] == 8)):
                 text = "Supported"
                 perm_counter += 1
             else:
@@ -1368,10 +1310,10 @@
     Positional arguments:
     report - Report generated during build procedure.
     """
-    from prettytable import PrettyTable
+    from prettytable import PrettyTable, HEADER
     columns_text = ['name', 'target', 'toolchain']
     columns_int = ['static_ram', 'total_flash']
-    table = PrettyTable(columns_text + columns_int)
+    table = PrettyTable(columns_text + columns_int, junction_char="|", hrules=HEADER)
 
     for col in columns_text:
         table.align[col] = 'l'
@@ -1445,11 +1387,13 @@
             for project in tc.values():
                 for build in project:
                     try:
+                        build[0]['bin_fullpath'] = build[0]['bin']
+                        build[0]['elf_fullpath'] = build[0]['elf']
                         build[0]['elf'] = relpath(build[0]['elf'], path_to_file)
                         build[0]['bin'] = relpath(build[0]['bin'], path_to_file)
                     except KeyError:
                         pass
                     if 'type' not in build[0]:
                         build[0]['type'] = app_type
-                    build_data['builds'].append(build[0])
+                    build_data['builds'].insert(0, build[0])
     dump(build_data, open(filename, "wb"), indent=4, separators=(',', ': '))
--- a/config/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/config/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,21 +14,62 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, division, absolute_import
 
 from copy import deepcopy
+from six import moves
+import json
+import six
 import os
-from os.path import dirname, abspath, exists, join
+from os.path import dirname, abspath, exists, join, isabs
 import sys
 from collections import namedtuple
 from os.path import splitext, relpath
 from intelhex import IntelHex
 from jinja2 import FileSystemLoader, StrictUndefined
 from jinja2.environment import Environment
-# Implementation of mbed configuration mechanism
-from tools.utils import json_file_to_dict, intelhex_offset
-from tools.arm_pack_manager import Cache
-from tools.targets import CUMULATIVE_ATTRIBUTES, TARGET_MAP, \
-    generate_py_target, get_resolution_order
+from jsonschema import Draft4Validator, RefResolver
+
+from ..resources import FileType
+from ..utils import (json_file_to_dict, intelhex_offset, integer,
+                     NotSupportedException)
+from ..arm_pack_manager import Cache
+from ..targets import (CUMULATIVE_ATTRIBUTES, TARGET_MAP, generate_py_target,
+                       get_resolution_order, Target)
+
+try:
+    unicode
+except NameError:
+    unicode = str
+PATH_OVERRIDES = set(["target.bootloader_img"])
+ROM_OVERRIDES = set([
+    # managed BL
+    "target.bootloader_img", "target.restrict_size",
+    "target.header_format", "target.header_offset",
+    "target.app_offset",
+
+    # unmanaged BL
+    "target.mbed_app_start", "target.mbed_app_size",
+
+    # both
+    "target.mbed_rom_start", "target.mbed_rom_size",
+])
+RAM_OVERRIDES = set([
+    # both
+    "target.mbed_ram_start", "target.mbed_ram_size",
+])
+
+BOOTLOADER_OVERRIDES = ROM_OVERRIDES | RAM_OVERRIDES
+
+
+ALLOWED_FEATURES = [
+    "BOOTLOADER","UVISOR", "BLE", "CLIENT", "IPV4", "LWIP", "COMMON_PAL", "STORAGE",
+    "NANOSTACK","CRYPTOCELL310",
+    # Nanostack configurations
+    "LOWPAN_BORDER_ROUTER", "LOWPAN_HOST", "LOWPAN_ROUTER", "NANOSTACK_FULL",
+    "THREAD_BORDER_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER",
+    "ETHERNET_HOST",
+]
 
 # Base class for all configuration exceptions
 class ConfigException(Exception):
@@ -36,6 +77,19 @@
     errors"""
     pass
 
+class UndefinedParameter(ConfigException):
+    def __init__(self, param, name, kind, label):
+        self.param = param
+        self.name = name
+        self.kind = kind
+        self.label = label
+
+    def __str__(self):
+        return "Attempt to override undefined parameter '{}' in '{}'".format(
+            self.param,
+            ConfigParameter.get_display_name(self.name, self.kind, self.label),
+        )
+
 class ConfigParameter(object):
     """This class keeps information about a single configuration parameter"""
 
@@ -84,6 +138,8 @@
             else:
                 prefix = unit_name + '.'
             return prefix + name
+        if name in BOOTLOADER_OVERRIDES:
+            return name
         # The name has a prefix, so check if it is valid
         if not allow_prefix:
             raise ConfigException("Invalid parameter name '%s' in '%s'" %
@@ -98,7 +154,7 @@
                                       unit_name, unit_kind, label)))
         prefix = temp[0]
         # Check if the given parameter prefix matches the expected prefix
-        if (unit_kind == "library" and prefix != unit_name) or \
+        if (unit_kind == "library" and prefix not in [unit_name, "target"]) or \
            (unit_kind == "target" and prefix != "target"):
             raise ConfigException(
                 "Invalid prefix '%s' for parameter name '%s' in '%s'" %
@@ -335,13 +391,8 @@
         macros[macro.macro_name] = macro
 
 
-def check_dict_types(dict, type_dict, dict_loc):
-    for key, value in dict.iteritems():
-        if not isinstance(value, type_dict[key]):
-            raise ConfigException("The value of %s.%s is not of type %s" %
-                                  (dict_loc, key, type_dict[key].__name__))
-
 Region = namedtuple("Region", "name start size active filename")
+RamRegion = namedtuple("RamRegion", "name start size active")
 
 class Config(object):
     """'Config' implements the mbed configuration mechanism"""
@@ -351,26 +402,30 @@
     __mbed_app_config_name = "mbed_app.json"
     __mbed_lib_config_name = "mbed_lib.json"
 
-    # Allowed keys in configuration dictionaries, and their types
-    # (targets can have any kind of keys, so this validation is not applicable
-    # to them)
-    __allowed_keys = {
-        "library": {"name": str, "config": dict, "target_overrides": dict,
-                    "macros": list, "__config_path": str},
-        "application": {"config": dict, "target_overrides": dict,
-                        "macros": list, "__config_path": str,
-                        "artifact_name": str}
-    }
-
     __unused_overrides = set(["target.bootloader_img", "target.restrict_size",
                               "target.mbed_app_start", "target.mbed_app_size"])
 
-    # Allowed features in configurations
-    __allowed_features = [
-        "UVISOR", "BLE", "CLIENT", "IPV4", "LWIP", "COMMON_PAL", "STORAGE", "NANOSTACK",
-        # Nanostack configurations
-        "LOWPAN_BORDER_ROUTER", "LOWPAN_HOST", "LOWPAN_ROUTER", "NANOSTACK_FULL", "THREAD_BORDER_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER", "ETHERNET_HOST"
-        ]
+    @classmethod
+    def find_app_config(cls, top_level_dirs):
+        app_config_location = None
+        for directory in top_level_dirs:
+            full_path = os.path.join(directory, cls.__mbed_app_config_name)
+            if os.path.isfile(full_path):
+                if app_config_location is not None:
+                    raise ConfigException("Duplicate '%s' file in '%s' and '%s'"
+                                            % (cls.__mbed_app_config_name,
+                                               cls.app_config_location, full_path))
+                else:
+                    app_config_location = full_path
+        return app_config_location
+
+    def format_validation_error(self, error, path):
+        if error.context:
+            return self.format_validation_error(error.context[0], path)
+        else:
+            return "in {} element {}: {}".format(
+                path, ".".join(p for p in error.absolute_path),
+                error.message.replace('u\'','\''))
 
     def __init__(self, tgt, top_level_dirs=None, app_config=None):
         """Construct a mbed configuration
@@ -390,17 +445,10 @@
         search for a configuration file).
         """
         config_errors = []
+        self.config_errors = []
         self.app_config_location = app_config
-        if self.app_config_location is None:
-            for directory in top_level_dirs or []:
-                full_path = os.path.join(directory, self.__mbed_app_config_name)
-                if os.path.isfile(full_path):
-                    if self.app_config_location is not None:
-                        raise ConfigException("Duplicate '%s' file in '%s' and '%s'"
-                                              % (self.__mbed_app_config_name,
-                                                 self.app_config_location, full_path))
-                    else:
-                        self.app_config_location = full_path
+        if self.app_config_location is None and top_level_dirs:
+            self.app_config_location = self.find_app_config(top_level_dirs)
         try:
             self.app_config_data = json_file_to_dict(self.app_config_location) \
                                    if self.app_config_location else {}
@@ -410,31 +458,44 @@
                 ConfigException("Could not parse mbed app configuration from %s"
                                 % self.app_config_location))
 
-        # Check the keys in the application configuration data
-        unknown_keys = set(self.app_config_data.keys()) - \
-                       set(self.__allowed_keys["application"].keys())
-        if unknown_keys:
-            raise ConfigException("Unknown key(s) '%s' in %s" %
-                                  (",".join(unknown_keys),
-                                   self.__mbed_app_config_name))
-        check_dict_types(self.app_config_data, self.__allowed_keys["application"],
-                         "app-config")
+
+        if self.app_config_location is not None:
+            # Validate the format of the JSON file based on schema_app.json
+            schema_root = os.path.dirname(os.path.abspath(__file__))
+            schema_path = os.path.join(schema_root, "schema_app.json")
+            schema      = json_file_to_dict(schema_path)
+
+            url = moves.urllib.request.pathname2url(schema_path)
+            uri = moves.urllib_parse.urljoin("file://", url)
+
+            resolver = RefResolver(uri, schema)
+            validator = Draft4Validator(schema, resolver=resolver)
+
+            errors = sorted(validator.iter_errors(self.app_config_data))
+
+            if errors:
+                raise ConfigException("; ".join(
+                    self.format_validation_error(x, self.app_config_location)
+                    for x in errors))
+
         # Update the list of targets with the ones defined in the application
         # config, if applicable
         self.lib_config_data = {}
         # Make sure that each config is processed only once
         self.processed_configs = {}
-        if isinstance(tgt, basestring):
+        if isinstance(tgt, Target):
+            self.target = tgt
+        else:
             if tgt in TARGET_MAP:
                 self.target = TARGET_MAP[tgt]
             else:
                 self.target = generate_py_target(
                     self.app_config_data.get("custom_targets", {}), tgt)
-
-        else:
-            self.target = tgt
         self.target = deepcopy(self.target)
         self.target_labels = self.target.labels
+        for override in BOOTLOADER_OVERRIDES:
+            _, attr = override.split(".")
+            setattr(self.target, attr, None)
 
         self.cumulative_overrides = {key: ConfigCumulativeOverride(key)
                                      for key in CUMULATIVE_ATTRIBUTES}
@@ -454,7 +515,7 @@
                 continue
             full_path = os.path.normpath(os.path.abspath(config_file))
             # Check that we didn't already process this file
-            if self.processed_configs.has_key(full_path):
+            if full_path in self.processed_configs:
                 continue
             self.processed_configs[full_path] = True
             # Read the library configuration and add a "__full_config_path"
@@ -462,17 +523,31 @@
             try:
                 cfg = json_file_to_dict(config_file)
             except ValueError as exc:
-                sys.stderr.write(str(exc) + "\n")
-                continue
+                raise ConfigException(str(exc))
+
+            # Validate the format of the JSON file based on the schema_lib.json
+            schema_root = os.path.dirname(os.path.abspath(__file__))
+            schema_path = os.path.join(schema_root, "schema_lib.json")
+            schema_file = json_file_to_dict(schema_path)
+
+            url = moves.urllib.request.pathname2url(schema_path)
+            uri = moves.urllib_parse.urljoin("file://", url)
+
+            resolver = RefResolver(uri, schema_file)
+            validator = Draft4Validator(schema_file, resolver=resolver)
+
+            errors = sorted(validator.iter_errors(cfg))
+
+            if errors:
+                raise ConfigException("; ".join(
+                    self.format_validation_error(x, config_file)
+                    for x in errors))
 
             cfg["__config_path"] = full_path
 
-            if "name" not in cfg:
-                raise ConfigException(
-                    "Library configured at %s has no name field." % full_path)
             # If there's already a configuration for a module with the same
             # name, exit with error
-            if self.lib_config_data.has_key(cfg["name"]):
+            if cfg["name"] in self.lib_config_data:
                 raise ConfigException(
                     "Library name '%s' is not unique (defined in '%s' and '%s')"
                     % (cfg["name"], full_path,
@@ -482,20 +557,37 @@
     @property
     def has_regions(self):
         """Does this config have regions defined?"""
-        if 'target_overrides' in self.app_config_data:
-            target_overrides = self.app_config_data['target_overrides'].get(
-                self.target.name, {})
-            return ('target.bootloader_img' in target_overrides or
-                    'target.restrict_size' in target_overrides or
-                    'target.mbed_app_start' in target_overrides or
-                    'target.mbed_app_size' in target_overrides)
-        else:
-            return False
+        for override in ROM_OVERRIDES:
+            _, attr = override.split(".")
+            if getattr(self.target, attr, None):
+                return True
+        return False
+
+    @property
+    def has_ram_regions(self):
+        """Does this config have regions defined?"""
+        for override in RAM_OVERRIDES:
+            _, attr = override.split(".")
+            if getattr(self.target, attr, None):
+                return True
+        return False
 
     @property
-    def regions(self):
-        """Generate a list of regions from the config"""
-        if not self.target.bootloader_supported:
+    def sectors(self):
+        """Return a list of tuples of sector start,size"""
+        cache = Cache(False, False)
+        if self.target.device_name not in cache.index:
+            raise ConfigException("Bootloader not supported on this target: "
+                                  "targets.json `device_name` not found in "
+                                  "arm_pack_manager index.")
+        cmsis_part = cache.index[self.target.device_name]
+        sectors = cmsis_part['sectors']
+        if sectors:
+            return sectors
+        raise ConfigException("No sector info available")
+
+    def _get_cmsis_part(self):
+        if not getattr(self.target, "bootloader_supported", False):
             raise ConfigException("Bootloader not supported on this target.")
         if not hasattr(self.target, "device_name"):
             raise ConfigException("Bootloader not supported on this target: "
@@ -505,40 +597,113 @@
             raise ConfigException("Bootloader not supported on this target: "
                                   "targets.json `device_name` not found in "
                                   "arm_pack_manager index.")
-        cmsis_part = cache.index[self.target.device_name]
-        target_overrides = self.app_config_data['target_overrides'].get(
-            self.target.name, {})
-        if  (('target.bootloader_img' in target_overrides or
-              'target.restrict_size' in target_overrides) and
-             ('target.mbed_app_start' in target_overrides or
-              'target.mbed_app_size' in target_overrides)):
+        return cache.index[self.target.device_name]
+
+    def _get_mem_specs(self, memories, cmsis_part, exception_text):
+        for memory in memories:
+            try:
+                size = cmsis_part['memory'][memory]['size']
+                start = cmsis_part['memory'][memory]['start']
+                return (start, size)
+            except KeyError:
+                continue
+        raise ConfigException(exception_text)
+
+    @property
+    def rom(self):
+        """Get rom information as a pair of start_addr, size"""
+        # Override rom_start/rom_size
+        #
+        # This is usually done for a target which:
+        # 1. Doesn't support CMSIS pack, or
+        # 2. Supports TrustZone and user needs to change its flash partition
+        cmsis_part = self._get_cmsis_part()
+        rom_start, rom_size = self._get_mem_specs(
+            ["IROM1", "PROGRAM_FLASH"],
+            cmsis_part,
+            "Not enough information in CMSIS packs to build a bootloader "
+            "project"
+        )
+        rom_start = int(getattr(self.target, "mbed_rom_start", False) or rom_start, 0)
+        rom_size = int(getattr(self.target, "mbed_rom_size", False) or rom_size, 0)
+        return (rom_start, rom_size)
+
+    @property
+    def ram_regions(self):
+        """Generate a list of ram regions from the config"""
+        cmsis_part = self._get_cmsis_part()
+        ram_start, ram_size = self._get_mem_specs(
+            ["IRAM1", "SRAM0"],
+            cmsis_part,
+            "Not enough information in CMSIS packs to build a ram sharing project"
+        )
+        # Override ram_start/ram_size
+        #
+        # This is usually done for a target which:
+        # 1. Doesn't support CMSIS pack, or
+        # 2. Supports TrustZone and user needs to change its flash partition
+        ram_start = getattr(self.target, "mbed_ram_start", False) or ram_start
+        ram_size = getattr(self.target, "mbed_ram_size", False) or ram_size
+        return [RamRegion("application_ram", int(ram_start, 0), int(ram_size, 0), True)]
+
+    @property
+    def regions(self):
+        """Generate a list of regions from the config"""
+        if  ((self.target.bootloader_img or self.target.restrict_size) and
+             (self.target.mbed_app_start or self.target.mbed_app_size)):
             raise ConfigException(
                 "target.bootloader_img and target.restirct_size are "
                 "incompatible with target.mbed_app_start and "
                 "target.mbed_app_size")
+        if self.target.bootloader_img or self.target.restrict_size:
+            return self._generate_bootloader_build(*self.rom)
+        else:
+            return self._generate_linker_overrides(*self.rom)
+
+    @staticmethod
+    def header_member_size(member):
+        _, _, subtype, _ = member
         try:
-            rom_size = int(cmsis_part['memory']['IROM1']['size'], 0)
-            rom_start = int(cmsis_part['memory']['IROM1']['start'], 0)
-        except KeyError:
-            raise ConfigException("Not enough information in CMSIS packs to "
-                                  "build a bootloader project")
-        if  ('target.bootloader_img' in target_overrides or
-             'target.restrict_size' in target_overrides):
-            return self._generate_booloader_build(target_overrides,
-                                                  rom_start, rom_size)
-        elif ('target.mbed_app_start' in target_overrides or
-              'target.mbed_app_size' in target_overrides):
-            return self._generate_linker_overrides(target_overrides,
-                                                   rom_start, rom_size)
-        else:
+            return int(subtype[:-2]) // 8
+        except:
+            if subtype.startswith("CRCITT32"):
+                return 32 // 8
+            elif subtype == "SHA256":
+                return 256 // 8
+            elif subtype == "SHA512":
+                return 512 // 8
+            else:
+                raise ValueError("target.header_format: subtype %s is not "
+                                 "understood" % subtype)
+
+    @staticmethod
+    def _header_size(format):
+        return sum(Config.header_member_size(m) for m in format)
+
+    def _make_header_region(self, start, header_format, offset=None):
+        size = self._header_size(header_format)
+        region = Region("header", start, size, False, None)
+        start += size
+        start = ((start + 7) // 8) * 8
+        return (start, region)
+
+    @staticmethod
+    def _assign_new_offset(rom_start, start, new_offset, region_name):
+        newstart = rom_start + integer(new_offset, 0)
+        if newstart < start:
             raise ConfigException(
-                "Bootloader build requested but no bootlader configuration")
+                "Can not place % region inside previous region" % region_name)
+        return newstart
 
-    def _generate_booloader_build(self, target_overrides, rom_start, rom_size):
-        start = 0
-        if 'target.bootloader_img' in target_overrides:
-            basedir = abspath(dirname(self.app_config_location))
-            filename = join(basedir, target_overrides['target.bootloader_img'])
+    def _generate_bootloader_build(self, rom_start, rom_size):
+        start = rom_start
+        rom_end = rom_start + rom_size
+        if self.target.bootloader_img:
+            if isabs(self.target.bootloader_img):
+                filename = self.target.bootloader_img
+            else:
+                basedir = abspath(dirname(self.app_config_location))
+                filename = join(basedir, self.target.bootloader_img)
             if not exists(filename):
                 raise ConfigException("Bootloader %s not found" % filename)
             part = intelhex_offset(filename, offset=rom_start)
@@ -546,35 +711,81 @@
                 raise ConfigException("bootloader executable does not "
                                       "start at 0x%x" % rom_start)
             part_size = (part.maxaddr() - part.minaddr()) + 1
-            yield Region("bootloader", rom_start + start, part_size, False,
+            part_size = Config._align_ceiling(rom_start + part_size, self.sectors) - rom_start
+            yield Region("bootloader", rom_start, part_size, False,
                          filename)
-            start += part_size
-        if 'target.restrict_size' in target_overrides:
-            new_size = int(target_overrides['target.restrict_size'], 0)
-            yield Region("application", rom_start + start, new_size, True, None)
+            start = rom_start + part_size
+            if self.target.header_format:
+                if self.target.header_offset:
+                    start = self._assign_new_offset(
+                        rom_start, start, self.target.header_offset, "header")
+                start, region = self._make_header_region(
+                    start, self.target.header_format)
+                yield region._replace(filename=self.target.header_format)
+        if self.target.restrict_size is not None:
+            new_size = int(self.target.restrict_size, 0)
+            new_size = Config._align_floor(start + new_size, self.sectors) - start
+            yield Region("application", start, new_size, True, None)
             start += new_size
-            yield Region("post_application", rom_start +start, rom_size - start,
+            if self.target.header_format and not self.target.bootloader_img:
+                if self.target.header_offset:
+                    start = self._assign_new_offset(
+                        rom_start, start, self.target.header_offset, "header")
+                start, region = self._make_header_region(
+                    start, self.target.header_format)
+                yield region
+            if self.target.app_offset:
+                start = self._assign_new_offset(
+                    rom_start, start, self.target.app_offset, "application")
+            yield Region("post_application", start, rom_end - start,
                          False, None)
         else:
-            yield Region("application", rom_start + start, rom_size - start,
+            if self.target.app_offset:
+                start = self._assign_new_offset(
+                    rom_start, start, self.target.app_offset, "application")
+            yield Region("application", start, rom_end - start,
                          True, None)
-        if start > rom_size:
+        if start > rom_start + rom_size:
             raise ConfigException("Not enough memory on device to fit all "
                                   "application regions")
+    
+    @staticmethod
+    def _find_sector(address, sectors):
+        target_size = -1
+        target_start = -1
+        for (start, size) in sectors:
+            if address < start:
+                break
+            target_start = start
+            target_size = size
+        if (target_size < 0):
+            raise ConfigException("No valid sector found")
+        return target_start, target_size
+        
+    @staticmethod
+    def _align_floor(address, sectors):
+        target_start, target_size = Config._find_sector(address, sectors)
+        sector_num = (address - target_start) // target_size
+        return target_start + (sector_num * target_size)
+    
+    @staticmethod
+    def _align_ceiling(address, sectors):
+        target_start, target_size = Config._find_sector(address, sectors)
+        sector_num = ((address - target_start) + target_size - 1) // target_size
+        return target_start + (sector_num * target_size)
 
     @property
     def report(self):
         return {'app_config': self.app_config_location,
                 'library_configs': map(relpath, self.processed_configs.keys())}
 
-    @staticmethod
-    def _generate_linker_overrides(target_overrides, rom_start, rom_size):
-        if 'target.mbed_app_start' in target_overrides:
-            start = int(target_overrides['target.mbed_app_start'], 0)
+    def _generate_linker_overrides(self, rom_start, rom_size):
+        if self.target.mbed_app_start is not None:
+            start = int(self.target.mbed_app_start, 0)
         else:
             start = rom_start
-        if 'target.mbed_app_size' in target_overrides:
-            size = int(target_overrides['target.mbed_app_size'], 0)
+        if self.target.mbed_app_size is not None:
+            size = int(self.target.mbed_app_size, 0)
         else:
             size = (rom_size + rom_start) - start
         if start < rom_start:
@@ -593,7 +804,6 @@
         unit_name - the unit (library/application) that defines this parameter
         unit_kind - the kind of the unit ("library" or "application")
         """
-        self.config_errors = []
         _process_config_parameters(data.get("config", {}), params, unit_name,
                                    unit_kind)
         for label, overrides in data.get("target_overrides", {}).items():
@@ -603,7 +813,7 @@
                 # Check for invalid cumulative overrides in libraries
                 if (unit_kind == 'library' and
                     any(attr.startswith('target.extra_labels') for attr
-                        in overrides.iterkeys())):
+                        in overrides.keys())):
                     raise ConfigException(
                         "Target override 'target.extra_labels' in " +
                         ConfigParameter.get_display_name(unit_name, unit_kind,
@@ -611,7 +821,7 @@
                         " is only allowed at the application level")
 
                 # Parse out cumulative overrides
-                for attr, cumulatives in self.cumulative_overrides.iteritems():
+                for attr, cumulatives in self.cumulative_overrides.items():
                     if 'target.'+attr in overrides:
                         key = 'target.' + attr
                         if not isinstance(overrides[key], list):
@@ -644,29 +854,28 @@
 
                 # Consider the others as overrides
                 for name, val in overrides.items():
+                    if (name in PATH_OVERRIDES and "__config_path" in data):
+                        val = os.path.join(
+                            os.path.dirname(data["__config_path"]), val)
+
                     # Get the full name of the parameter
                     full_name = ConfigParameter.get_full_name(name, unit_name,
                                                               unit_kind, label)
                     if full_name in params:
                         params[full_name].set_value(val, unit_name, unit_kind,
                                                     label)
-                    elif name in self.__unused_overrides:
-                        pass
                     elif (name.startswith("target.") and
-                          unit_kind is "application"):
+                        (unit_kind is "application" or
+                         name in BOOTLOADER_OVERRIDES)):
                         _, attribute = name.split(".")
                         setattr(self.target, attribute, val)
+                        continue
                     else:
                         self.config_errors.append(
-                            ConfigException(
-                                "Attempt to override undefined parameter" +
-                                (" '%s' in '%s'"
-                                 % (full_name,
-                                    ConfigParameter.get_display_name(unit_name,
-                                                                     unit_kind,
-                                                                     label)))))
+                            UndefinedParameter(
+                                full_name, unit_name, unit_kind, label))
 
-        for cumulatives in self.cumulative_overrides.itervalues():
+        for cumulatives in self.cumulative_overrides.values():
             cumulatives.update_target(self.target)
 
         return params
@@ -708,39 +917,29 @@
                 rel_names = [tgt for tgt, _ in
                              get_resolution_order(self.target.json_data, tname,
                                                   [])]
-                if full_name in self.__unused_overrides:
+                if full_name in BOOTLOADER_OVERRIDES:
                     continue
                 if (full_name not in params) or \
                    (params[full_name].defined_by[7:] not in rel_names):
-                    raise ConfigException(
-                        "Attempt to override undefined parameter '%s' in '%s'"
-                        % (name,
-                           ConfigParameter.get_display_name(tname, "target")))
+                    raise UndefinedParameter(name, tname, "target", "")
                 # Otherwise update the value of the parameter
                 params[full_name].set_value(val, tname, "target")
         return params
 
-    def get_lib_config_data(self):
+    def get_lib_config_data(self, target_data):
         """ Read and interpret configuration data defined by libraries. It is
         assumed that "add_config_files" above was already called and the library
         configuration data exists in self.lib_config_data
 
         Arguments: None
         """
-        all_params, macros = {}, {}
+        macros = {}
         for lib_name, lib_data in self.lib_config_data.items():
-            unknown_keys = (set(lib_data.keys()) -
-                            set(self.__allowed_keys["library"].keys()))
-            if unknown_keys:
-                raise ConfigException("Unknown key(s) '%s' in %s" %
-                                      (",".join(unknown_keys), lib_name))
-            check_dict_types(lib_data, self.__allowed_keys["library"], lib_name)
-            all_params.update(self._process_config_and_overrides(lib_data, {},
-                                                                 lib_name,
-                                                                 "library"))
+            self._process_config_and_overrides(
+                lib_data, target_data, lib_name, "library")
             _process_macros(lib_data.get("macros", []), macros, lib_name,
                             "library")
-        return all_params, macros
+        return target_data, macros
 
     def get_app_config_data(self, params, macros):
         """ Read and interpret the configuration data defined by the target. The
@@ -770,10 +969,9 @@
         Arguments: None
         """
         all_params = self.get_target_config_data()
-        lib_params, macros = self.get_lib_config_data()
-        all_params.update(lib_params)
-        self.get_app_config_data(all_params, macros)
-        return all_params, macros
+        lib_params, macros = self.get_lib_config_data(all_params)
+        self.get_app_config_data(lib_params, macros)
+        return lib_params, macros
 
     @staticmethod
     def _check_required_parameters(params):
@@ -854,8 +1052,13 @@
 
         Arguments: None
         """
-        if self.config_errors:
-            raise self.config_errors[0]
+        params, _ = self.get_config_data()
+        for error in self.config_errors:
+            if  (isinstance(error, UndefinedParameter) and
+                 error.param in params):
+                continue
+            else:
+                raise error
         return True
 
 
@@ -875,25 +1078,27 @@
         """
         # Update configuration files until added features creates no changes
         prev_features = set()
-        self.validate_config()
         while True:
             # Add/update the configuration with any .json files found while
             # scanning
-            self.add_config_files(resources.json_files)
+            self.add_config_files(
+                f.path for f in resources.get_file_refs(FileType.JSON)
+            )
 
             # Add features while we find new ones
             features = set(self.get_features())
             if features == prev_features:
                 break
 
-            for feature in features:
-                if feature in resources.features:
-                    resources.add(resources.features[feature])
+            resources.add_features(features)
 
             prev_features = features
         self.validate_config()
 
-        return resources
+        if  (hasattr(self.target, "release_versions") and
+             "5" not in self.target.release_versions and
+             "rtos" in self.lib_config_data):
+            raise NotSupportedException("Target does not support mbed OS 5")
 
     @staticmethod
     def config_to_header(config, fname=None):
@@ -914,10 +1119,14 @@
         Config._check_required_parameters(params)
         params_with_values = [p for p in params.values() if p.value is not None]
         ctx = {
-            "cfg_params" : [(p.macro_name, str(p.value), p.set_by)
-                            for p in params_with_values],
-            "macros": [(m.macro_name, str(m.macro_value or ""), m.defined_by)
-                       for m in macros.values()],
+            "cfg_params": sorted([
+                (p.macro_name, str(p.value), p.set_by)
+                for p in params_with_values
+            ]),
+            "macros": sorted([
+                (m.macro_name, str(m.macro_value or ""), m.defined_by)
+                for m in macros.values()
+            ]),
             "name_len":  max([len(m.macro_name) for m in macros.values()] +
                              [len(m.macro_name) for m in params_with_values]
                              + [0]),
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/config/definitions.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,100 @@
+{
+  "name_definition": {
+    "description": "Name of the library",
+    "type": "string",
+    "items": {
+      "type": "string"
+    }
+  },
+  "macro_definition": {
+    "description": "A list of extra macros that will be defined when compiling a project that includes this library.",
+    "type": "array",
+    "items": {
+      "type": "string",
+      "pattern": "(^[\\w()_]+$|^[\\w()_]+=.+$)"
+    }
+  },
+  "config_definition": {
+    "description": "List of configuration parameters",
+    "type": "object",
+    "patternProperties": {
+      "^[^ ]+$": {
+        "$ref": "#/config_parameter_base"
+      }
+    },
+    "additionalProperties": false
+  },
+  "target_overrides_definition": {
+    "description": "List of overrides for specific targets",
+    "type": "object",
+    "patternProperties": {
+      "\\*": {
+        "$ref": "#/target_override_entry"
+      },
+      "^\\S+$": {
+        "$ref": "#/target_override_entry"
+      }
+    },
+    "additionalProperties": false
+  },
+  "config_parameter_long": {
+    "type": "object",
+    "properties": {
+      "help": {
+        "description": "An optional help message that describes the purpose of the parameter",
+        "type": "string"
+      },
+      "value": {
+        "description": "An optional field that defines the value of the parameter",
+        "type": [
+          "integer",
+          "string",
+          "boolean",
+          "null"
+        ]
+      },
+      "required": {
+        "description": "An optional field that specifies whether the parameter must be given a value before compiling the code. (False by default)",
+        "type": "boolean"
+      },
+      "macro_name": {
+        "description": "An optional field for the macro defined at compile time for this configuration parameter. The system will automatically figure out the macro name from the configuration parameter, but this field will override it",
+        "type": "string"
+      }
+    }
+  },
+  "config_parameter_short": {
+    "type": [
+      "array",
+      "string",
+      "integer",
+      "boolean",
+      "null"
+    ]
+  },
+  "config_parameter_base": {
+    "oneOf": [
+      {
+        "$ref": "#/config_parameter_long"
+      },
+      {
+        "$ref": "#/config_parameter_short"
+      }
+    ]
+  },
+  "target_override_entry": {
+    "type": "object",
+    "patternProperties": {
+      "^\\S+$": {
+        "type": [
+          "array",
+          "string",
+          "integer",
+          "boolean",
+          "null"
+        ]
+      }
+    },
+    "additionalProperties": false
+  }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/config/schema_app.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,24 @@
+{
+  "$schema": "http://json-schema.org/draft-06/schema#",
+  "title": "Mbed Library Schema",
+  "description": "Configuration file for an mbed application",
+  "type": "object",
+  "properties": {
+    "name": {
+      "$ref": "definitions.json#/name_definition"
+    },
+    "config": {
+      "$ref": "definitions.json#/config_definition"
+    },
+    "target_overrides": {
+      "$ref": "definitions.json#/target_overrides_definition"
+    },
+    "macros": {
+      "$ref": "definitions.json#/macro_definition"
+    },
+    "artifact_name": {
+      "type": "string"
+    }
+  },
+  "additionalProperties": false
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/config/schema_lib.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,24 @@
+{
+  "$schema": "http://json-schema.org/draft-06/schema#",
+  "title": "Mbed Library Schema",
+  "description": "Configuration file for an mbed library",
+  "type": "object",
+  "properties": {
+    "name": {
+      "$ref": "definitions.json#/name_definition"
+    },
+    "config": {
+      "$ref": "definitions.json#/config_definition"
+    },
+    "target_overrides": {
+      "$ref": "definitions.json#/target_overrides_definition"
+    },
+    "macros": {
+      "$ref": "definitions.json#/macro_definition"
+    }
+  },
+  "required": [
+    "name"
+  ],
+  "additionalProperties": false
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/debug_tools/crash_log_parser/README.md	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,79 @@
+## Crash Log Parser Tool
+This post-processing tool can be used to parse crash log generated by Mbed-OS when an exception happens. 
+
+## Capturing crash log
+When an exception happens Mbed-OS will print out the crash information to STDOUT.
+The crash information contains register context at the time exception and current threads in the system.
+The information printed out to STDOUT will be similar to below. Registers captured depends on specific
+Cortex-M core you are using. For example, if your target is using Cortex-M0, some registers like 
+MMFSR, BFSR, UFSR may not be available and will not appear in the crash log.
+
+++ MbedOS Fault Handler ++
+
+FaultType: HardFault
+
+Context:
+R0   : 0000AAA3
+R1   : 20002070
+R2   : 00009558
+R3   : 00412A02
+R4   : E000ED14
+R5   : 00000000
+R6   : 00000000
+R7   : 00000000
+R8   : 00000000
+R9   : 00000000
+R10  : 00000000
+R11  : 00000000
+R12  : 0000BCE5
+SP   : 20002070
+LR   : 00009E75
+PC   : 00009512
+xPSR : 01000000
+PSP  : 20002008
+MSP  : 2002FFD8
+CPUID: 410FC241
+HFSR : 40000000
+MMFSR: 00000000
+BFSR : 00000000
+UFSR : 00000100
+DFSR : 00000008
+AFSR : 00000000
+SHCSR: 00000000
+
+Thread Info:
+Current:
+State: 00000002 EntryFn: 0000ADF5 Stack Size: 00001000 Mem: 20001070 SP: 20002030
+Next:
+State: 00000002 EntryFn: 0000ADF5 Stack Size: 00001000 Mem: 20001070 SP: 20002030
+Wait Threads:
+State: 00000083 EntryFn: 0000AA1D Stack Size: 00000300 Mem: 20000548 SP: 200007D8
+Delay Threads:
+Idle Thread:
+State: 00000001 EntryFn: 00009F59 Stack Size: 00000200 Mem: 20000348 SP: 20000508
+
+-- MbedOS Fault Handler --
+
+
+To generate more information copy and save this crash information to a text file and run the crash_log_parser.py tool as below.
+NOTE: Make sure you copy the section with text "MbedOS Fault Handler" as the this tool looks for that header.
+
+## Running the Crash Log Parser
+crash_log_parser.py <Path to Crash log> <Path to Elf/Axf file of the build> <Path to Map file of the build>
+For example:
+crashlogparse.py crash.log C:\MyProject\BUILD\k64f\arm\mbed-os-hf-handler.elf C:\MyProject\BUILD\k64f\arm\mbed-os-hf-handler.map
+
+An example output from running crash_log_parser is shown below.
+
+Parsed Crash Info:
+        Crash location = zero_div_test() [0000693E]
+        Caller location = $Super$$main [00009E99]
+        Stack Pointer at the time of crash = [20001CC0]
+        Target/Fault Info:
+                Processor Arch: ARM-V7M or above
+                Processor Variant: C24
+                Forced exception, a fault with configurable priority has been escalated to HardFault
+                Divide by zero error has occurred
+
+Done parsing...
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/debug_tools/crash_log_parser/crash_log_parser.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,213 @@
+#!/usr/bin/env python
+"""
+mbed SDK
+Copyright (c) 2017-2019 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+LIBRARIES BUILD
+"""
+
+from __future__ import print_function
+from os import path
+import re
+import bisect
+from subprocess import check_output
+import sys
+
+#arm-none-eabi-nm -nl <elf file>
+_NM_EXEC = "arm-none-eabi-nm"
+_OPT = "-nlC"
+_PTN = re.compile("([0-9a-f]*) ([Tt]) ([^\t\n]*)(?:\t(.*):([0-9]*))?")
+
+class ElfHelper(object):
+    def __init__(self, elf_file, map_file):
+    
+        op = check_output([_NM_EXEC, _OPT, elf_file.name])
+        self.maplines = map_file.readlines()
+        self.matches = _PTN.findall(op)
+        self.addrs = [int(x[0], 16) for x in self.matches]
+                
+    def function_addrs(self):
+        return self.addrs
+    
+    def function_name_for_addr(self, addr):
+        i = bisect.bisect_right(self.addrs, addr)
+        funcname = self.matches[i-1][2]
+        return funcname
+
+def print_HFSR_info(hfsr):
+    if int(hfsr, 16) & 0x80000000:
+        print("\t\tDebug Event Occurred")
+    if int(hfsr, 16) & 0x40000000:
+        print("\t\tForced exception, a fault with configurable priority has been escalated to HardFault")    
+    if int(hfsr, 16) & 0x2:
+        print("\t\tVector table read fault has occurred")        
+
+def print_MMFSR_info(mmfsr, mmfar):            
+    if int(mmfsr, 16) & 0x20:
+        print("\t\tA MemManage fault occurred during FP lazy state preservation")
+    if int(mmfsr, 16) & 0x10:
+        print("\t\tA derived MemManage fault occurred on exception entry")            
+    if int(mmfsr, 16) & 0x8:
+        print("\t\tA derived MemManage fault occurred on exception return")                
+    if int(mmfsr, 16) & 0x2:
+        if int(mmfsr, 16) & 0x80:
+            print("\t\tData access violation. Faulting address: %s"%(str(mmfar)))                    
+        else:     
+            print("\t\tData access violation. WARNING: Fault address in MMFAR is NOT valid")                    
+    if int(mmfsr, 16) & 0x1:
+        print("\t\tMPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred")                        
+    
+def print_BFSR_info(bfsr, bfar):
+    if int(bfsr, 16) & 0x20:
+        print("\t\tA bus fault occurred during FP lazy state preservation")
+    if int(bfsr, 16) & 0x10:
+        print("\t\tA derived bus fault has occurred on exception entry")  
+    if int(bfsr, 16) & 0x8:
+        print("\t\tA derived bus fault has occurred on exception return") 
+    if int(bfsr, 16) & 0x4:
+        print("\t\tImprecise data access error has occurred")               
+    if int(bfsr, 16) & 0x2:
+        if int(bfsr,16) & 0x80:
+            print("\t\tA precise data access error has occurred. Faulting address: %s"%(str(bfar)))                    
+        else:     
+            print("\t\tA precise data access error has occurred. WARNING: Fault address in BFAR is NOT valid")             
+    if int(bfsr, 16) & 0x1:
+        print("\t\tA bus fault on an instruction prefetch has occurred")                           
+
+def print_UFSR_info(ufsr):            
+    if int(ufsr, 16) & 0x200:
+        print("\t\tDivide by zero error has occurred")
+    if int(ufsr, 16) & 0x100:
+        print("\t\tUnaligned access error has occurred")
+    if int(ufsr, 16) & 0x8:
+        print("\t\tA coprocessor access error has occurred. This shows that the coprocessor is disabled or not present")
+    if int(ufsr, 16) & 0x4:
+        print("\t\tAn integrity check error has occurred on EXC_RETURN")
+    if int(ufsr, 16) & 0x2:
+        print("\t\tInstruction executed with invalid EPSR.T or EPSR.IT field( This may be caused by Thumb bit not being set in branching instruction )")    
+    if int(ufsr, 16) & 0x1:
+        print("\t\tThe processor has attempted to execute an undefined instruction")        
+    
+def print_CPUID_info(cpuid):            
+    if (int(cpuid, 16) & 0xF0000) == 0xC0000:
+        print("\t\tProcessor Arch: ARM-V6M")
+    else:        
+        print("\t\tProcessor Arch: ARM-V7M or above")
+    
+    print("\t\tProcessor Variant: %X" % ((int(cpuid,16) & 0xFFF0 ) >> 4))    
+
+def parse_line_for_register(line):
+    _, register_val = line.split(":")
+    return register_val.strip()    
+
+def main(crash_log, elfhelper):
+    mmfar_val = 0
+    bfar_val = 0
+    lines = iter(crash_log.read().splitlines())
+    
+    for eachline in lines:
+        if "++ MbedOS Fault Handler ++" in eachline:
+            break
+    else:
+        print("ERROR: Unable to find \"MbedOS Fault Handler\" header")
+        return
+    
+    for eachline in lines:
+        if "-- MbedOS Fault Handler --" in eachline:
+            break
+        
+        elif eachline.startswith("PC"):
+            pc_val = parse_line_for_register(eachline)
+            if elfhelper:
+                pc_name = elfhelper.function_name_for_addr(int(pc_val, 16))
+            else:
+                pc_name = "<unknown-symbol>"
+                        
+        elif eachline.startswith("LR"):
+            lr_val = parse_line_for_register(eachline)
+            if elfhelper:
+                lr_name = elfhelper.function_name_for_addr(int(lr_val, 16))
+            else:
+                lr_name = "<unknown-symbol>"
+            
+        elif eachline.startswith("SP"):
+            sp_val = parse_line_for_register(eachline)
+                        
+        elif eachline.startswith("HFSR"):
+            hfsr_val = parse_line_for_register(eachline)
+            
+        elif eachline.startswith("MMFSR"):
+            mmfsr_val = parse_line_for_register(eachline)
+            
+        elif eachline.startswith("BFSR"):
+            bfsr_val = parse_line_for_register(eachline)
+            
+        elif eachline.startswith("UFSR"):
+            ufsr_val = parse_line_for_register(eachline)
+            
+        elif eachline.startswith("CPUID"):
+            cpuid_val = parse_line_for_register(eachline)
+            
+        elif eachline.startswith("MMFAR"):
+            mmfar_val = parse_line_for_register(eachline)
+            
+        elif eachline.startswith("BFAR"):
+            bfar_val = parse_line_for_register(eachline)    
+    
+    print("\nCrash Info:")        
+    print("\tCrash location = %s [0x%s] (based on PC value)" % (pc_name.strip(), str(pc_val)))
+    print("\tCaller location = %s [0x%s] (based on LR value)" % (lr_name.strip(), str(lr_val)))        
+    print("\tStack Pointer at the time of crash = [%s]" % (str(sp_val)))
+    
+    print("\tTarget and Fault Info:")
+    print_CPUID_info(cpuid_val)
+    print_HFSR_info(hfsr_val)
+    print_MMFSR_info(mmfsr_val, mmfar_val)
+    print_BFSR_info(bfsr_val, bfar_val)
+    print_UFSR_info(ufsr_val)
+        
+                            
+if __name__ == '__main__':
+    import argparse
+    
+    parser = argparse.ArgumentParser(description='Analyse mbed-os crash log. This tool requires arm-gcc binary utilities to be available in current path as it uses \'nm\' command')
+    # specify arguments
+    parser.add_argument(metavar='CRASH LOG', type=argparse.FileType('rb', 0),
+                        dest='crashlog',help='path to crash log file')      
+    parser.add_argument(metavar='ELF FILE', type=argparse.FileType('rb', 0),
+                        nargs='?',const=None,dest='elffile',help='path to elf file')             
+    parser.add_argument(metavar='MAP FILE', type=argparse.FileType('rb', 0),
+                        nargs='?',const=None,dest='mapfile',help='path to map file')                                    
+
+    # get and validate arguments
+    args = parser.parse_args()
+
+    # if both the ELF and MAP files are present, the addresses can be converted to symbol names
+    if args.elffile and args.mapfile:
+        elfhelper = ElfHelper(args.elffile, args.mapfile)
+    else:
+        print("ELF or MAP file missing, logging raw values.")
+        elfhelper = None
+    
+    # parse input and write to output
+    main(args.crashlog, elfhelper)
+    
+    #close all files
+    if args.elffile:
+        args.elffile.close()
+    if args.mapfile:
+        args.mapfile.close()
+    args.crashlog.close()
+
--- a/default_settings.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/default_settings.py	Tue Sep 25 13:43:09 2018 -0500
@@ -43,3 +43,6 @@
 
 # mbed.org username
 #MBED_ORG_USER = ""
+
+# Print compiler warnings and errors as link format
+#PRINT_COMPILER_OUTPUT_AS_LINK = False
--- a/detect_targets.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/detect_targets.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,6 +15,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 import sys
 import os
 import re
@@ -67,8 +68,8 @@
 
         # Only prints matrix of supported toolchains
         if options.supported_toolchains:
-            print mcu_toolchain_matrix(
-                platform_filter=options.general_filter_regex)
+            print(mcu_toolchain_matrix(
+                platform_filter=options.general_filter_regex))
             exit(0)
 
         # If auto_detect attribute is present, we assume other auto-detection
@@ -79,25 +80,25 @@
 
         count = 0
         for mut in muts.values():
-            if re.match(mcu_filter, mut['mcu']):
+            if re.match(mcu_filter, mut['mcu'] or "Unknown"):
                 interface_version = get_interface_version(mut['disk'])
-                print ""
-                print "[mbed] Detected %s, port %s, mounted %s, interface version %s:" % \
-                        (mut['mcu'], mut['port'], mut['disk'], interface_version)
-                                    
-                print "[mbed] Supported toolchains for %s" % mut['mcu']
-                print mcu_toolchain_matrix(platform_filter=mut['mcu'])
+                print("")
+                print("[mbed] Detected %s, port %s, mounted %s, interface "
+                      "version %s:" %
+                      (mut['mcu'], mut['port'], mut['disk'], interface_version))
+                print("[mbed] Supported toolchains for %s" % mut['mcu'])
+                print(mcu_toolchain_matrix(platform_filter=mut['mcu']))
                 count += 1
 
         if count == 0:
-            print "[mbed] No mbed targets were detected on your system."
+            print("[mbed] No mbed targets were detected on your system.")
 
     except KeyboardInterrupt:
-        print "\n[CTRL+c] exit"
+        print("\n[CTRL+c] exit")
     except Exception as exc:
         import traceback
         traceback.print_exc(file=sys.stdout)
-        print "[ERROR] %s" % str(exc)
+        print("[ERROR] %s" % str(exc))
         sys.exit(1)
         
 def get_interface_version(mount_point):
@@ -112,15 +113,14 @@
     """
     if get_module_avail('mbed_lstools'):
         try :
-            mbeds = mbed_lstools.create()
-            details_txt = mbeds.get_details_txt(mount_point)
+            mbedls = mbed_lstools.create()
+            mbeds = mbedls.list_mbeds(unique_names=True, read_details_txt=True)
             
-            if 'Interface Version' in details_txt:
-                return details_txt['Interface Version']
+            for mbed in mbeds:
+                if mbed['mount_point'] == mount_point:
             
-            elif 'Version' in details_txt:
-                return details_txt['Version']
-            
+                    if 'daplink_version' in mbed:
+                        return mbed['daplink_version']           
         except :
             return 'unknown'
         
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/device_management.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,167 @@
+#! /usr/bin/env python2
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+device-management, dev-mgmt, and dm sub command
+"""
+from __future__ import print_function, absolute_import
+import logging
+import sys
+import argparse
+from os.path import join, abspath, dirname, basename
+from os import getenv
+
+from manifesttool import create, parse, verify, cert, init, update
+from manifesttool.argparser import MainArgumentParser
+from mbed_cloud import AccountManagementAPI, CertificatesAPI
+import colorama
+colorama.init()
+
+
+LOG = logging.getLogger(__name__)
+LOG_FORMAT = '[%(levelname)s] %(asctime)s - %(name)s - %(message)s'
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.config import Config
+from tools.options import extract_mcus
+
+
+class MbedExtendedArgs(MainArgumentParser):
+    def _addCreateArgs(self, parser, exclusions=[]):
+        if 'payload' not in exclusions:
+            parser.add_argument(
+                '-p', '--payload',
+                help='Supply a local copy of the payload file.'
+                     'This option overrides any payload file supplied in a '
+                     '`-i` argument.',
+                metavar='FILE',
+                type=argparse.FileType('rb')
+            )
+            parser.add_argument('-m', '--mcu')
+            parser.add_argument('-t', '--toolchain')
+            parser.add_argument('--source', nargs='+', dest='source_dir')
+            parser.add_argument('--build')
+            exclusions.append('payload')
+        super(MbedExtendedArgs, self)._addCreateArgs(parser, exclusions)
+
+
+def wrap_payload(func):
+    def inner(options):
+        if not options.payload and options.mcu and options.build:
+            mcus = extract_mcus(MbedExtendedArgs(), options)
+            sources = options.source_dir or ['.']
+            config = Config(mcus[0], sources)
+            app_name = config.name or basename(abspath(sources[0]))
+            output_ext = getattr(config.target, "OUTPUT_EXT", "bin")
+            payload_name = join(options.build, "{}_application.{}".format(
+                app_name, output_ext
+            ))
+            options.payload = open(payload_name, "rb")
+        return func(options)
+    return inner
+
+
+def wrap_init(func):
+    def inner(options):
+        if getattr(options, 'api_key', None):
+            api_key = options.api_key
+        else:
+            api_key = getenv("MBED_CLOUD_SDK_API_KEY")
+        if getattr(options, 'server_address', None):
+            host_addr = options.server_address
+        else:
+            host_addr = getenv("MBED_CLOUD_SDK_HOST",
+                               "https://api.us-east-1.mbedcloud.com/")
+        config = {
+            "api_key": api_key,
+            "host": host_addr,
+        }
+        accounts = AccountManagementAPI(config)
+        certs = CertificatesAPI(config)
+        api_key = accounts.list_api_keys(filter={
+            'key': api_key
+        }).next()
+        certificates_owned = list(certs.list_certificates())
+        dev_cert_info = None
+        for certif in certificates_owned:
+            if certif.type == "developer" and (certif.owner_id == api_key.owner_id or
+                                               certif.owner_id == api_key.id):
+                dev_cert_info = certs.get_certificate(certif.id)
+                LOG.info("Found developer certificate named %s",
+                         dev_cert_info.name)
+                break
+        else:
+            LOG.warning(
+                "Could not find developer certificate for this account."
+                " Generting a new developer certificate."
+            )
+            dev_cert_info = CertificatesAPI().add_developer_certificate(
+                "mbed-cli-auto {}".format(api_key.name),
+                description="cetificate auto-generated by Mbed CLI"
+            )
+        LOG.info("Writing developer certificate %s into c file "
+                 "mbed_cloud_dev_credentials.c", dev_cert_info.name)
+        with open("mbed_cloud_dev_credentials.c", "w") as fout:
+            fout.write(dev_cert_info.header_file)
+        return func(options)
+    return inner
+
+
+def main():
+    options = MbedExtendedArgs().parse_args().options
+
+    log_level = {
+        'debug': logging.DEBUG,
+        'info': logging.INFO,
+        'warning': logging.WARNING,
+        'exception': logging.CRITICAL,
+    }[options.log_level]
+    logging.basicConfig(
+        level=log_level,
+        format=LOG_FORMAT,
+        datefmt='%Y-%m-%d %H:%M:%S',
+    )
+    logging.addLevelName(
+        logging.INFO,
+        "\033[1;32m%s\033[1;0m" % logging.getLevelName(logging.INFO)
+    )
+    logging.addLevelName(
+        logging.WARNING,
+        "\033[1;93m%s\033[1;0m" % logging.getLevelName(logging.WARNING)
+    )
+    logging.addLevelName(
+        logging.CRITICAL,
+        "\033[1;31m%s\033[1;0m" % logging.getLevelName(logging.CRITICAL)
+    )
+    LOG.debug('CLIDriver created. Arguments parsed and logging setup.')
+
+    rc = {
+        "create": wrap_payload(create.main),
+        "parse": parse.main,
+        "verify": verify.main,
+        "cert": cert.main,
+        "init": wrap_init(init.main),
+        "update": wrap_payload(update.main),
+    }[options.action](options) or 0
+
+    sys.exit(rc)
+
+if __name__ == "__main__":
+    main()
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/.gitignore	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,1 @@
+!.mbed
\ No newline at end of file
--- a/export/GettingStarted.html	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/GettingStarted.html	Tue Sep 25 13:43:09 2018 -0500
@@ -3,14 +3,14 @@
     <head>
         <meta charset="UTF-8">
         <meta http-equiv="refresh"
-              content="1;url="https://developer.mbed.org/handbook/Getting-Started-mbed-Exporters>
+              content="1;url="https://os.mbed.com/docs/latest/tools/exporting.html>
         <script type="text/javascript">
-            window.location.href = "https://developer.mbed.org/handbook/Getting-Started-mbed-Exporters"
+            window.location.href = "https://os.mbed.com/docs/latest/tools/exporting.html"
         </script>
         <title>Page Redirection</title>
     </head>
     <body>
         If you are not redirected automatically, please follow the
-        <a href='https://developer.mbed.org/handbook/Getting-Started-mbed-Exporters'>link to the online exporter documentation</a>
+        <a href='https://os.mbed.com/docs/v5.6/tools/exporting.html/'>link to the online exporter documentation</a>
     </body>
 </html>
--- a/export/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,53 +15,49 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+from __future__ import print_function, division, absolute_import
+
 import sys
-from os.path import join, abspath, dirname, exists
+from os.path import join, abspath, dirname, exists, isfile
 from os.path import basename, relpath, normpath, splitext
 from os import makedirs, walk
 import copy
 from shutil import rmtree, copyfile
 import zipfile
-ROOT = abspath(join(dirname(__file__), ".."))
-sys.path.insert(0, ROOT)
 
-from tools.build_api import prepare_toolchain
-from tools.build_api import scan_resources
-from tools.toolchains import Resources
-from tools.export import lpcxpresso, ds5_5, iar, makefile
-from tools.export import embitz, coide, kds, simplicity, atmelstudio, mcuxpresso
-from tools.export import sw4stm32, e2studio, zip, cmsis, uvision, cdt, vscode
-from tools.export import gnuarmeclipse
-from tools.export import qtcreator
-from tools.targets import TARGET_NAMES
+from ..resources import Resources, FileType, FileRef
+from ..config import ALLOWED_FEATURES
+from ..build_api import prepare_toolchain
+from ..targets import TARGET_NAMES
+from . import (lpcxpresso, ds5_5, iar, makefile, embitz, coide, kds, simplicity,
+               atmelstudio, mcuxpresso, sw4stm32, e2studio, zip, cmsis, uvision,
+               cdt, vscode, gnuarmeclipse, qtcreator, cmake, nb, cces, codeblocks)
 
 EXPORTERS = {
-    'uvision5': uvision.Uvision,
-    'uvision': uvision.Uvision,
-    'lpcxpresso': lpcxpresso.LPCXpresso,
-    'gcc_arm': makefile.GccArm,
-    'make_gcc_arm': makefile.GccArm,
-    'make_armc5': makefile.Armc5,
-    'make_armc6': makefile.Armc6,
-    'make_iar': makefile.IAR,
-    'ds5_5': ds5_5.DS5_5,
-    'iar': iar.IAR,
-    'embitz' : embitz.EmBitz,
-    'coide' : coide.CoIDE,
-    'kds' : kds.KDS,
-    'simplicityv3' : simplicity.SimplicityV3,
-    'atmelstudio' : atmelstudio.AtmelStudio,
-    'sw4stm32'    : sw4stm32.Sw4STM32,
-    'e2studio' : e2studio.E2Studio,
-    'eclipse_gcc_arm'  : cdt.EclipseGcc,
-    'eclipse_iar'      : cdt.EclipseIAR,
-    'eclipse_armc5'    : cdt.EclipseArmc5,
-    'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse,
-    'mcuxpresso': mcuxpresso.MCUXpresso,
-    'qtcreator': qtcreator.QtCreator,
-    'vscode_gcc_arm' : vscode.VSCodeGcc,
-    'vscode_iar' : vscode.VSCodeIAR,
-    'vscode_armc5' : vscode.VSCodeArmc5
+    u'uvision6': uvision.UvisionArmc6,
+    u'uvision5': uvision.UvisionArmc5,
+    u'make_gcc_arm': makefile.GccArm,
+    u'make_armc5': makefile.Armc5,
+    u'make_armc6': makefile.Armc6,
+    u'make_iar': makefile.IAR,
+    u'ds5_5': ds5_5.DS5_5,
+    u'iar': iar.IAR,
+    u'embitz' : embitz.EmBitz,
+    u'sw4stm32'    : sw4stm32.Sw4STM32,
+    u'e2studio' : e2studio.E2Studio,
+    u'eclipse_gcc_arm'  : cdt.EclipseGcc,
+    u'eclipse_iar'      : cdt.EclipseIAR,
+    u'eclipse_armc5'    : cdt.EclipseArmc5,
+    u'gnuarmeclipse': gnuarmeclipse.GNUARMEclipse,
+    u'mcuxpresso': mcuxpresso.MCUXpresso,
+    u'netbeans':     nb.GNUARMNetbeans,
+    u'qtcreator': qtcreator.QtCreator,
+    u'vscode_gcc_arm' : vscode.VSCodeGcc,
+    u'vscode_iar' : vscode.VSCodeIAR,
+    u'vscode_armc5' : vscode.VSCodeArmc5,
+    u'cmake_gcc_arm': cmake.GccArm,
+    u'cces' : cces.CCES,
+    u'codeblocks': codeblocks.CodeBlocks
 }
 
 ERROR_MESSAGE_UNSUPPORTED_TOOLCHAIN = """
@@ -142,48 +138,6 @@
     return EXPORTERS[ide], EXPORTERS[ide].TOOLCHAIN
 
 
-def rewrite_basepath(file_name, resources, export_path, loc):
-    """ Replace the basepath of filename with export_path
-
-    Positional arguments:
-    file_name - the absolute path to a file
-    resources - the resources object that the file came from
-    export_path - the final destination of the file after export
-    """
-    new_f = join(loc, relpath(file_name, resources.file_basepath[file_name]))
-    resources.file_basepath[new_f] = export_path
-    return new_f
-
-
-def subtract_basepath(resources, export_path, loc=""):
-    """ Rewrite all of the basepaths with the export_path
-
-    Positional arguments:
-    resources - the resource object to rewrite the basepaths of
-    export_path - the final destination of the resources with respect to the
-      generated project files
-    """
-    keys = ['s_sources', 'c_sources', 'cpp_sources', 'hex_files',
-            'objects', 'libraries', 'inc_dirs', 'headers', 'linker_script',
-            'lib_dirs']
-    for key in keys:
-        vals = getattr(resources, key)
-        if isinstance(vals, set):
-            vals = list(vals)
-        if isinstance(vals, list):
-            new_vals = []
-            for val in vals:
-                new_vals.append(rewrite_basepath(val, resources, export_path,
-                                                 loc))
-            if isinstance(getattr(resources, key), set):
-                setattr(resources, key, set(new_vals))
-            else:
-                setattr(resources, key, new_vals)
-        elif vals:
-            setattr(resources, key, rewrite_basepath(vals, resources,
-                                                     export_path, loc))
-
-
 def generate_project_files(resources, export_path, target, name, toolchain, ide,
                            macros=None):
     """Generate the project files for a project
@@ -209,7 +163,25 @@
     return files, exporter
 
 
-def zip_export(file_name, prefix, resources, project_files, inc_repos):
+def _inner_zip_export(resources, prj_files, inc_repos):
+    to_zip = sum((resources.get_file_refs(ftype) for ftype
+                  in Resources.ALL_FILE_TYPES),
+                 [])
+    to_zip.extend(FileRef(basename(pfile), pfile) for pfile in prj_files)
+    for dest, source in resources.get_file_refs(FileType.BLD_REF):
+        target_dir, _ = splitext(dest)
+        dest = join(target_dir, ".bld", "bldrc")
+        to_zip.append(FileRef(dest, source))
+    if inc_repos:
+        for dest, source in resources.get_file_refs(FileType.REPO_DIRS):
+            for root, _, files in walk(source):
+                for repo_file in files:
+                    file_source = join(root, repo_file)
+                    file_dest = join(dest, relpath(file_source, source))
+                    to_zip.append(FileRef(file_dest, file_source))
+    return to_zip
+
+def zip_export(file_name, prefix, resources, project_files, inc_repos, notify):
     """Create a zip file from an exported project.
 
     Positional Parameters:
@@ -219,43 +191,26 @@
     project_files - a list of extra files to be added to the root of the prefix
       directory
     """
+    to_zip_list = sorted(set(_inner_zip_export(
+        resources, project_files, inc_repos)))
+    total_files = len(to_zip_list)
+    zipped = 0
     with zipfile.ZipFile(file_name, "w") as zip_file:
-        for prj_file in project_files:
-            zip_file.write(prj_file, join(prefix, basename(prj_file)))
-        for loc, res in resources.iteritems():
-            to_zip = (
-                res.headers + res.s_sources + res.c_sources +\
-                res.cpp_sources + res.libraries + res.hex_files + \
-                [res.linker_script] + res.bin_files + res.objects + \
-                res.json_files + res.lib_refs + res.lib_builds)
-            if inc_repos:
-                for directory in res.repo_dirs:
-                    for root, _, files in walk(directory):
-                        for repo_file in files:
-                            source = join(root, repo_file)
-                            to_zip.append(source)
-                            res.file_basepath[source] = res.base_path
-                to_zip += res.repo_files
-            for source in to_zip:
-                if source:
-                    zip_file.write(
-                        source,
-                        join(prefix, loc,
-                             relpath(source, res.file_basepath[source])))
-            for source in res.lib_builds:
-                target_dir, _ = splitext(source)
-                dest = join(prefix, loc,
-                            relpath(target_dir, res.file_basepath[source]),
-                            ".bld", "bldrc")
-                zip_file.write(source, dest)
-
+        for dest, source in to_zip_list:
+            if source and isfile(source):
+                zip_file.write(source, join(prefix, dest))
+                zipped += 1
+                notify.progress("Zipping", source,
+                                100 * (zipped / total_files))
+            else:
+                zipped += 1
 
 
 def export_project(src_paths, export_path, target, ide, libraries_paths=None,
-                   linker_script=None, notify=None, verbose=False, name=None,
-                   inc_dirs=None, jobs=1, silent=False, extra_verbose=False,
-                   config=None, macros=None, zip_proj=None, inc_repos=False,
-                   build_profile=None, app_config=None):
+                   linker_script=None, notify=None, name=None, inc_dirs=None,
+                   jobs=1, config=None, macros=None, zip_proj=None,
+                   inc_repos=False, build_profile=None, app_config=None,
+                   ignore=None):
     """Generates a project file and creates a zip archive if specified
 
     Positional Arguments:
@@ -269,17 +224,14 @@
     linker_script - path to the linker script for the specified target
     notify - function is passed all events, and expected to handle notification
       of the user, emit the events to a log, etc.
-    verbose - assigns the notify function to toolchains print_notify_verbose
     name - project name
     inc_dirs - additional include directories
     jobs - number of threads
-    silent - silent build - no output
-    extra_verbose - assigns the notify function to toolchains
-      print_notify_verbose
     config - toolchain's config object
     macros - User-defined macros
     zip_proj - string name of the zip archive you wish to creat (exclude arg
      if you do not wish to create an archive
+    ignore - list of paths to add to mbedignore
     """
 
     # Convert src_path to a list if needed
@@ -306,32 +258,23 @@
     # Pass all params to the unified prepare_resources()
     toolchain = prepare_toolchain(
         paths, "", target, toolchain_name, macros=macros, jobs=jobs,
-        notify=notify, silent=silent, verbose=verbose,
-        extra_verbose=extra_verbose, config=config, build_profile=build_profile,
-        app_config=app_config)
-    # The first path will give the name to the library
+        notify=notify, config=config, build_profile=build_profile,
+        app_config=app_config, ignore=ignore)
+
     toolchain.RESPONSE_FILES = False
     if name is None:
         name = basename(normpath(abspath(src_paths[0])))
 
-    # Call unified scan_resources
-    resource_dict = {loc: scan_resources(path, toolchain, inc_dirs=inc_dirs, collect_ignores=True)
-                     for loc, path in src_paths.iteritems()}
-    resources = Resources()
+    resources = Resources(notify, collect_ignores=True)
+    resources.add_toolchain_labels(toolchain)
+    for loc, path in src_paths.items():
+        for p in path:
+            resources.add_directory(p, into_path=loc)
     toolchain.build_dir = export_path
+    toolchain.config.load_resources(resources)
+    toolchain.set_config_data(toolchain.config.get_config_data())
     config_header = toolchain.get_config_header()
-    resources.headers.append(config_header)
-    resources.file_basepath[config_header] = dirname(config_header)
-
-    if zip_proj:
-        subtract_basepath(resources, ".")
-        for loc, res in resource_dict.iteritems():
-            temp = copy.deepcopy(res)
-            subtract_basepath(temp, ".", loc)
-            resources.add(temp)
-    else:
-        for _, res in resource_dict.iteritems():
-            resources.add(res)
+    resources.add_file_ref(FileType.HEADER, basename(config_header), config_header)
 
     # Change linker script if specified
     if linker_script is not None:
@@ -340,18 +283,14 @@
     files, exporter = generate_project_files(resources, export_path,
                                              target, name, toolchain, ide,
                                              macros=macros)
-    files.append(config_header)
     if zip_proj:
-        for resource in resource_dict.values():
-            for label, res in resource.features.iteritems():
-                if label not in toolchain.target.features:
-                    resource.add(res)
+        resources.add_features(ALLOWED_FEATURES)
         if isinstance(zip_proj, basestring):
-            zip_export(join(export_path, zip_proj), name, resource_dict,
-                       files + list(exporter.static_files), inc_repos)
+            zip_export(join(export_path, zip_proj), name, resources,
+                       files + list(exporter.static_files), inc_repos, notify)
         else:
-            zip_export(zip_proj, name, resource_dict,
-                       files + list(exporter.static_files), inc_repos)
+            zip_export(zip_proj, name, resources,
+                       files + list(exporter.static_files), inc_repos, notify)
     else:
         for static_file in exporter.static_files:
             if not exists(join(export_path, basename(static_file))):
--- a/export/atmelstudio/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/atmelstudio/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -16,6 +16,7 @@
 """
 import uuid
 from os.path import splitext, basename, dirname
+from os import remove
 
 from tools.export.exporters import Exporter, deprecated_exporter
 
@@ -58,7 +59,7 @@
                 source_folders.append(e)
 
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
             libraries.append(l[3:])
 		
@@ -83,3 +84,8 @@
         target = self.target.lower()
         self.gen_file('atmelstudio/atsln.tmpl', ctx, '%s.atsln' % self.project_name)
         self.gen_file('atmelstudio/cppproj.tmpl', ctx, '%s.cppproj' % self.project_name)
+
+    @staticmethod
+    def clean(project_name):
+        remove('%s.atsln' % project_name)
+        remove('%s.cppproj' % project_name)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/cces/README.md.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,25 @@
+# Create and build CrossCore Embedded Studio projects
+CrossCore Embedded Studio (CCES) can generate and build IDE projects from the command line using .json input files.
+
+## Create a new project
+
+Run the following headless tools command to create your CrossCore Embedded Studio project using the .json file generated by the ARM mbed exporter:
+{% for operating_system, command in commands['create'].items() %}
+### {{ operating_system }}
+> {{ command }}
+
+{% endfor %}
+where "CCES_HOME" is an environment variable pointing to the root CCES installation directory and "WORKSPACE" is the path to the desired CCES workspace directory.
+
+Once the CrossCore Embedded Studio project is generated, you can import the project into the IDE for development and debugging.
+
+## Build a project
+Once created, you can use headless tools to build the project with the following command:
+{% for operating_system, command in commands['build'].items() %}
+### {{ operating_system }}
+> {{ command }}
+
+{% endfor %}
+where "CCES_HOME" is an environment variable pointing to the root CCES installation directory and "WORKSPACE" is the path to the desired CCES workspace directory.
+
+For more information on how to use CrossCore Embedded Studio and headless tools, please see the CrossCore Embedded Studio Help.
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/cces/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,486 @@
+"""
+mbed SDK
+Copyright (c) 2011-2017 ARM Limited
+Portions Copyright (c) 2017-2018 Analog Devices, Inc.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import copy
+import os
+import sys
+import shutil
+import tempfile
+
+from subprocess import Popen, PIPE
+
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter
+
+from collections import namedtuple
+
+
+# Container for CCES option type and value
+Option = namedtuple('Option', ['type', 'value'])
+
+"""
+Tuple of supported device names
+"""
+SUPPORTED_DEVICES = ("ADuCM3027", "ADuCM3029", "ADuCM360", "ADuCM4050")
+
+class CCES(Exporter):
+    """
+    mbed exporter for Analog Devices' CrossCore Embedded Studio(TM)
+    """
+    NAME = 'CrossCore Embedded Studio'
+    TOOLCHAIN = 'GCC_ARM'
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        """Query support for a particular target
+
+        Positional Arguments:
+        target_name - the name of the target.
+        """
+        target = TARGET_MAP[target_name]
+        return (cls.TOOLCHAIN in target.supported_toolchains) \
+            and hasattr(target, "device_name") \
+            and (target.device_name in SUPPORTED_DEVICES)
+
+    @property
+    def flags(self):
+        """Returns a dictionary of toolchain flags.
+        Keys of the dictionary are:
+        cxx_flags    - c++ flags
+        c_flags      - c flags
+        ld_flags     - linker flags
+        asm_flags    - assembler flags
+        common_flags - common options
+
+        Skip macros because headless tools handles them separately
+        """
+        flags = {key + "_flags": copy.deepcopy(value) for key, value \
+                    in self.toolchain.flags.iteritems()}
+        config_header = self.config_header_ref
+        if config_header:
+            config_header = "\\\"" + self.format_inc_path(config_header.name) \
+                                + "\\\""
+            header_options = self.toolchain.get_config_option(config_header)
+            flags['c_flags'] += header_options
+            flags['cxx_flags'] += header_options
+        return flags
+
+    @staticmethod
+    def format_path(path, prefix):
+        """
+        Formats the given source path relative to the project directory
+        using the prefix
+        """
+        new_path = path
+        if new_path.startswith("./"):
+            new_path = new_path[2:]
+        return prefix + new_path.replace("\\", "\\\\")
+
+    @staticmethod
+    def format_inc_path(path):
+        """
+        Formats the given include path relative to the project directory
+        """
+        return CCES.format_path(path, "${ProjDirPath}/../")
+
+    @staticmethod
+    def format_src_path(path):
+        """
+        Formats the given source path relative to the project directory
+        """
+        return CCES.format_path(path, "PARENT-1-PROJECT_LOC/")
+
+    @staticmethod
+    def clean_flags(container, flags_to_remove):
+        """
+        Some flags are handled by CCES already, so there's no need
+        to include them twice.
+        """
+        for flag in flags_to_remove:
+            if flag in container:
+                container.remove(flag)
+
+    @staticmethod
+    def parse_flags(flags, options, booleans):
+        """
+        Parse the values in `booleans`, insert them into the
+        `options` dictionary and remove them from `flags`
+        """
+        for flag, flag_id in booleans.items():
+            value = "false"
+            if flag in flags:
+                value = "true"
+                flags.remove(flag)
+            options[flag_id] = Option("baseId", value)
+
+    @staticmethod
+    def convert_common_options(prefix, options, flags):
+        """
+        Converts the common flags into CCES options and removes them
+        from the flags list
+        """
+        # remove these flags without converting to option
+        # since they are added by CCES
+        remove = ["-c"]
+        CCES.clean_flags(flags, remove)
+
+        value = prefix + "option.dwarfversion.enumerated.v2"
+        for flag in flags:
+            if flag.startswith("-gdwarf"):
+                value = prefix + "option.dwarfversion.enumerated.v" + flag[-1]
+                flags.remove(flag)
+                break
+        option = Option("baseId", value)
+        options[prefix + "option.dwarfversion"] = option
+
+    @staticmethod
+    def convert_assembler_options(flags):
+        """
+        Converts the assembler flags into CCES options and removes them
+        from the flags list
+        """
+        options = {}
+
+        # remove these flags without converting to option
+        # since they are added by CCES
+        remove = ["-x", "assembler-with-cpp"]
+        CCES.clean_flags(flags, remove)
+
+        booleans = {"-v": "arm.assembler.option.verbose",
+                    "-g": "arm.assembler.option.debuginfo"}
+
+        CCES.parse_flags(flags, options, booleans)
+
+        CCES.convert_common_options("arm.assembler.", options, flags)
+
+        return options
+
+    @staticmethod
+    def convert_compiler_options(flags):
+        """
+        Converts the compiler flags into CCES options and removes them
+        from the flags list
+        """
+        options = {}
+
+        enable_optimization = "true"
+        value = "arm.base.compiler.option.optimization.og"
+        for flag in flags:
+            if flag.startswith("-O"):
+                value = "arm.base.compiler.option.optimization.o" + flag[2:]
+                if flag[2:] == "0":
+                    enable_optimization = "false"
+                flags.remove(flag)
+                break
+        option = Option("baseId", value)
+        options["arm.base.compiler.option.optimization"] = option
+
+        option = Option("baseId", enable_optimization)
+        options["arm.base.compiler.option.optimization.enable"] = option
+
+        booleans = {"-g": "arm.base.compiler.option.debug",
+                    "-save-temps": \
+                        "arm.base.compiler.option.savetemps",
+                    "-ffunction-sections": \
+                        "arm.c.compiler.option.elimination.code",
+                    "-fdata-sections": \
+                        "arm.c.compiler.option.elimination.data",
+                    "-pedantic": "arm.base.compiler.option.pedantic",
+                    "-pedantic-errors": \
+                        "arm.base.compiler.option.pedanticerrors",
+                    "-w": "arm.base.compiler.option.inhibitallwarnings",
+                    "-Wall": "arm.base.compiler.option.allwarnings",
+                    "-Wextra": "arm.base.compiler.option.extrawarnings",
+                    "-Werror": "arm.base.compiler.option.warningaserror",
+                    "-Wconversion": \
+                        "arm.base.compiler.option.conversionwarning"}
+
+        CCES.parse_flags(flags, options, booleans)
+
+        CCES.convert_common_options("arm.base.compiler.", options, flags)
+
+        return options
+
+    @staticmethod
+    def convert_linker_options(flags):
+        """
+        Converts the linker flags into CCES options and removes them
+        from the flags list
+        """
+        options = {}
+
+        booleans = {"-nostartfiles": "arm.linker.option.nostart",
+                    "-nodefaultlibs": "arm.linker.option.nodeflibs",
+                    "-nostdlib": "arm.linker.option.nostdlibs",
+                    "-s": "arm.linker.option.strip",
+                    "-Wl,--gc-sections": "arm.linker.option.elimination"}
+
+        CCES.parse_flags(flags, options, booleans)
+
+        return options
+
+    @staticmethod
+    def get_cces_path(root):
+        """
+        Returns the path to the CCES executable
+        """
+        cces_path = None
+
+        if sys.platform == 'win32' or sys.platform == 'cygwin':
+            cces_path = os.path.join(root, "Eclipse", "ccesc.exe")
+        elif sys.platform.startswith('linux'):
+            cces_path = os.path.join(root, "Eclipse", "cces")
+        elif sys.platform == 'darwin':
+            cces_path = os.path.join(root, "MacOS", "cces")
+        else:
+            print("Unsupported operating system '%s'" % sys.platform)
+            return None
+
+        return cces_path
+
+    @staticmethod
+    def get_project_create_command(cces_path, workspace, project_name):
+        """
+        Generate the headless tools projectcreate command string
+        with the given parameters
+        """
+        cmd = [
+            "\"%s\"" % cces_path,
+            "-nosplash",
+            "-consoleLog",
+            "-application com.analog.crosscore.headlesstools",
+            "-data", workspace,
+            "-project", project_name,
+            "-command projectcreate",
+            "-input-file", "cces.json"
+        ]
+        return ' '.join(cmd)
+
+    @staticmethod
+    def get_project_build_command(cces_path, workspace, project_name):
+        """
+        Generate the headless tools build command string
+        with the given parameters
+        """
+        cmd = [
+            "\"%s\"" % cces_path,
+            "-nosplash",
+            "-consoleLog",
+            "-application com.analog.crosscore.headlesstools",
+            "-data", workspace,
+            "-project", project_name,
+            "-cleanBuild all"
+        ]
+        return ' '.join(cmd)
+
+    # override
+    def generate(self):
+        """
+        Generate the CCES project files using headless builder.
+        """
+
+        self.resources.win_to_unix()
+
+        asm_defines = self.toolchain.get_symbols(True)
+        c_defines = self.toolchain.get_symbols()
+
+        include_dirs = [self.format_inc_path(d) for d \
+                        in self.resources.inc_dirs if d]
+
+        srcs = self.resources.s_sources + \
+                self.resources.c_sources + \
+                self.resources.cpp_sources + \
+                self.resources.headers
+
+        srcs_dict = {}
+        for src in srcs:
+            srcs_dict[src] = self.format_src_path(src)
+
+        ld_script = self.format_inc_path(self.resources.linker_script)
+
+        asm_flags = self.flags['asm_flags']
+        c_flags = self.flags['c_flags'] + self.flags['common_flags']
+        cxx_flags = self.flags['cxx_flags'] + self.flags['common_flags']
+
+        libs = []
+        for libpath in self.libraries:
+            lib = os.path.splitext(os.path.basename(libpath))[0]
+            libs.append(lib[3:]) # skip 'lib' prefix
+
+        ld_flags = self.flags['ld_flags'] + ["-l" + lib for lib \
+                    in self.toolchain.sys_libs]
+
+        proc = self.toolchain.target.device_name
+        cpu = self.toolchain.target.core.lower()
+        fpu = None
+        float_abi = None
+
+        # parse toolchain CPU flags
+        for flag in self.toolchain.cpu:
+            if flag.startswith("-mcpu="):
+                cpu = flag[len("-mcpu="):]
+            elif flag.startswith("-mfpu="):
+                fpu = flag[len("-mfpu="):]
+            elif flag.startswith("-mfloat-abi="):
+                float_abi = flag[len("-mfloat-abi="):]
+
+        # remove toolchain CPU flags. We'll handle them separately
+        # in the generated .json file
+        self.clean_flags(c_flags, self.toolchain.cpu)
+        self.clean_flags(cxx_flags, self.toolchain.cpu)
+        self.clean_flags(ld_flags, self.toolchain.cpu)
+
+        ld_opts = self.convert_linker_options(ld_flags)
+        asm_opts = self.convert_assembler_options(asm_flags)
+        c_opts = self.convert_compiler_options(c_flags)
+        cxx_opts = self.convert_compiler_options(cxx_flags)
+
+        project = "cces"
+        json = "cces.json"
+        local_location = project
+
+        jinja_ctx = {
+            'project' : self.project_name,
+            'cpu' : cpu,
+            'proc' : proc,
+            'family' : "ARM",
+            'asm_defines' : asm_defines,
+            'c_defines' : c_defines,
+            'fpu' : fpu,
+            'float_abi' : float_abi,
+            'ld_script' : ld_script,
+            'local_location' : local_location,
+            'srcs': srcs_dict,
+            'include_dirs' : include_dirs,
+            'ld_opts' : ld_opts,
+            'ld_flags' : ld_flags,
+            'asm_opts' : asm_opts,
+            'asm_flags' : asm_flags,
+            'c_opts' : c_opts,
+            'c_flags' : c_flags,
+            'cxx_opts' : cxx_opts,
+            'cxx_flags' : cxx_flags,
+        }
+
+        self.gen_file('cces/cces.json.tmpl', jinja_ctx,
+                      json, trim_blocks=True, lstrip_blocks=True)
+
+        # generate a readme on how to create the CCES project
+        # using the generated .json file
+
+        cces_paths = {
+            "Windows" : "%CCES_HOME%\\Eclipse\\ccesc.exe",
+            "Linux" : "${CCES_HOME}/Eclipse/cces",
+            "MacOS" : "${CCES_HOME}/MacOS/cces"
+        }
+
+        commands = {"create":{}, "build":{}}
+        for operating_system, path in cces_paths.items():
+            commands["create"][operating_system] = \
+                                CCES.get_project_create_command(path, \
+                                "WORKSPACE", project)
+            commands["build"][operating_system] = \
+                                CCES.get_project_build_command(path, \
+                                "WORKSPACE", project)
+
+        jinja_ctx = {
+            'commands' : commands
+        }
+
+        self.gen_file('cces/README.md.tmpl', jinja_ctx, "README.md")
+
+        print("CCES files generated.")
+
+
+    @staticmethod
+    def clean(_):
+        os.remove('cces.json')
+        os.remove('README.md')
+
+    @staticmethod
+    def build(project_name, log_name='build_log.txt', cleanup=True):
+        """
+        Build the generated CCES project using headless builder.
+        """
+        # create the project by importing .json file using CCES headless builder
+        cces_home = os.getenv("CCES_HOME")
+        if cces_home is None:
+            print("Failed to build project: " + \
+                "'CCES_HOME' environment variable not defined.")
+            return -1
+
+        cces_path = CCES.get_cces_path(cces_home)
+        if cces_path is None:
+            return -1
+
+        workspace = tempfile.mkdtemp()
+
+        cmd = CCES.get_project_create_command(cces_path, workspace, \
+                project_name)
+        print(cmd)
+        process = Popen(cmd, shell=True, stdout=PIPE, stderr=PIPE)
+        out, err = process.communicate()
+        ret_code = process.returncode
+
+        # cleanup workspace
+        if os.path.exists(workspace):
+            shutil.rmtree(workspace, True)
+            CCES.clean(project_name)
+
+        # check return code for failure
+        if ret_code != 0:
+            for line in out.split("\n"):
+                print(line)
+            for line in err.split("\n"):
+                print(line)
+
+            print("Failed to create project. Return code: %d" % ret_code)
+            return -1
+
+        # build the project
+        workspace = tempfile.mkdtemp()
+
+        cmd = CCES.get_project_build_command(cces_path, workspace, project_name)
+        print(cmd)
+        process = Popen(cmd, shell=True, stdout=PIPE, stderr=PIPE)
+        out, err = process.communicate()
+        ret_code = process.returncode
+
+        if log_name:
+            with open(log_name, 'w+') as log_file:
+                log_file.write(out)
+                log_file.write(err)
+                if ret_code != 0:
+                    log_file.write("Failed to build project. Return code: %d"\
+                                    % ret_code)
+
+        # cleanup workspace
+        if os.path.exists(workspace):
+            shutil.rmtree(workspace)
+
+        # check return code for failure
+        if ret_code == 0:
+            return 0
+
+        for line in out.split("\n"):
+            print(line)
+        for line in err.split("\n"):
+            print(line)
+
+        print("Failed to build project. Return code: %d" % ret_code)
+        return -1
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/cces/cces.json.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,313 @@
+{
+   "project" : {
+      "schema" : "1.1",
+      "configuration" : {
+         {% for config in ["arm.toolchain.gcc.target.exe.release", "arm.toolchain.gcc.target.exe.debug"] %}
+         "{{ config }}" : {
+            "buildSteps" : {
+               "postbuild" : "",
+               "prebuild" : "",
+               "prebuilddes" : "",
+               "postbuilddes" : ""
+            },
+            "tools" : {
+               "arm.toolchain.gcc.assembler" : {
+                  {% for opt in asm_opts %}
+                  "{{ opt }}" : {
+                     "type" : "{{ asm_opts[opt].type }}",
+                     "value": "{{ asm_opts[opt].value }}"
+                  },
+                  {% endfor %}
+                  "arm.toolchain.gcc.assembler.option.instructionset" : {
+                     "type" : "baseId",
+                     "value" : "-mthumb"
+                  },
+                  {% if float_abi %}
+                  "-mfloat-abi=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ float_abi }}"
+                  },
+                  {% endif %}
+                  "-mcpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ cpu }}"
+                  },
+                  "arm.assembler.option.assemblerswitch" : {
+                     "type" : "baseId",
+                     "value" : "true"
+                  },
+                  "arm.assembler.option.additionaloptions" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for flag in asm_flags %}
+                        "{{ flag }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  "-mproc=${value}" : {
+                     "type" : "command",
+                     "value" : " {{ proc }}"
+                  },
+                  "-D" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for def in asm_defines %}
+                        "{{ def }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  {% if fpu %}
+                  "-mfpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ fpu }}"
+                  },
+                  {% endif %}
+                  "-I" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for dir in include_dirs %}
+                        "\"{{ dir }}\""{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  }
+               },
+               "arm.toolchain.gcc.cpp.linker" : {
+                  {% for opt in ld_opts %}
+                  "{{ opt }}" : {
+                     "type" : "{{ ld_opts[opt].type }}",
+                     "value": "{{ ld_opts[opt].value }}"
+                  },
+                  {% endfor %}
+                  "arm.toolchain.gcc.cpp.linker.option.instructionset" : {
+                     "type" : "baseId",
+                     "value" : "-mthumb"
+                  },
+                  "arm.linker.option.additionaloptions" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for flag in ld_flags %}
+                        "{{ flag }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  {% if float_abi %}
+                  "arm.toolchain.gcc.cpp.linker.option.fpu.abi" : {
+                     "type" : "baseId",
+                     "value" : "arm.toolchain.gcc.c.linker.option.fpu.abi.{{ float_abi }}"
+                  },
+                  {% endif %}
+                  "-T" : {
+                     "type" : "command",
+                     "value" : "{{ ld_script }}"
+                  },
+                  "-mcpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ cpu }}"
+                  },
+                  "arm.linker.option.userlibs" : {
+                     "type" : "baseId",
+                     "value" : [ ]
+                  },
+                  "arm.cpp.linker.option.shared" : {
+                     "type" : "baseId",
+                     "value" : "false"
+                  },
+                  "arm.toolchain.gcc.cpp.linker.option.specs" : {
+                     "type" : "baseId",
+                     "value" : "arm.toolchain.gcc.c.linker.option.specs.nosys"
+                  },
+                  "-mproc=${value}" : {
+                     "type" : "command",
+                     "value" : " {{ proc }}"
+                  },
+                  "arm.c.linker.mathslib" : {
+                     "type" : "baseId",
+                     "value" : "true"
+                  },
+                  {% if fpu %}
+                  "-mfpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ fpu }}"
+                  },
+                  {% endif %}
+                  "-L" : {
+                     "type" : "command",
+                     "value" : [ ]
+                  },
+                  "-l" : {
+                     "type" : "command",
+                     "value" : [ ]
+                  }
+               },
+               "arm.toolchain.gcc.c.compiler" : {
+                  {% for opt in c_opts %}
+                  "{{ opt }}" : {
+                     "type" : "{{ c_opts[opt].type }}",
+                     "value": "{{ c_opts[opt].value }}"
+                  },
+                  {% endfor %}
+                  "-U" : {
+                     "type" : "command",
+                     "value" : [ ]
+                  },
+                  "arm.base.compiler.option.additionaloptions" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for flag in c_flags %}
+                        "{{ flag }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  "arm.toolchain.gcc.c.compiler.option.instructionset" : {
+                     "type" : "baseId",
+                     "value" : "-mthumb"
+                  },
+                  "arm.base.compiler.option.compilerswitch.hide" : {
+                     "type" : "baseId",
+                     "value" : "-c"
+                  },
+                  "arm.toolchain.cpp.compiler.option.coreid" : {
+                     "type" : "baseId",
+                     "value" : "0"
+                  },
+                  {% if float_abi %}
+                  "-mfloat-abi=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ float_abi }}"
+                  },
+                  {% endif %}
+                  "-mcpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ cpu }}"
+                  },
+                  "-mproc=${value}" : {
+                     "type" : "command",
+                     "value" : " {{ proc }}"
+                  },
+                  "-D" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for def in c_defines %}
+                        "{{ def }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  "arm.base.compiler.option.noadiinclude" : {
+                     "type" : "baseId",
+                     "value" : "false"
+                  },
+                  {% if fpu %}
+                  "-mfpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ fpu }}"
+                  },
+                  {% endif %}
+                  "-I" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for dir in include_dirs %}
+                        "\"{{ dir }}\""{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  }
+               },
+               "arm.toolchain.gcc.cpp.compiler" : {
+                  {% for opt in cxx_opts %}
+                  "{{ opt }}" : {
+                     "type" : "{{ cxx_opts[opt].type }}",
+                     "value": "{{ cxx_opts[opt].value }}"
+                  },
+                  {% endfor %}
+                  "-U" : {
+                     "type" : "command",
+                     "value" : [ ]
+                  },
+                  "arm.base.compiler.option.additionaloptions" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for flag in cxx_flags %}
+                        "{{ flag }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  "arm.toolchain.gcc.cpp.compiler.option.instructionset" : {
+                     "type" : "baseId",
+                     "value" : "-mthumb"
+                  },
+                  "arm.base.compiler.option.compilerswitch.hide" : {
+                     "type" : "baseId",
+                     "value" : "-c"
+                  },
+                  "arm.toolchain.cpp.compiler.option.coreid" : {
+                     "type" : "baseId",
+                     "value" : "0"
+                  },
+                  {% if float_abi %}
+                  "-mfloat-abi=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ float_abi }}"
+                  },
+                  {% endif %}
+                  "-mcpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ cpu }}"
+                  },
+                  "-mproc=${value}" : {
+                     "type" : "command",
+                     "value" : " {{ proc }}"
+                  },
+                  "-D" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for def in c_defines %}
+                        "{{ def }}"{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  },
+                  "arm.base.compiler.option.noadiinclude" : {
+                     "type" : "baseId",
+                     "value" : "false"
+                  },
+                  {% if fpu %}
+                  "-mfpu=${value}" : {
+                     "type" : "command",
+                     "value" : "{{ fpu }}"
+                  },
+                  {% endif %}
+                  "-I" : {
+                     "type" : "command",
+                     "value" : [
+                        {% for dir in include_dirs %}
+                        "\"{{ dir }}\""{{ "," if not loop.last else "" }}
+                        {% endfor %}
+                     ]
+                  }
+               }
+            }
+         }{{ "," if not loop.last else "" }}
+         {% endfor %}
+      },
+      "srcFiles" : [
+         {% for src in srcs %}
+         {
+            "path" : "{{ srcs[src] }}",
+            "location" : "{{ src }}",
+            "linked" : true
+         }{{ "," if not loop.last else "" }}
+         {% endfor %}
+      ],
+      "basicInfo" : {
+         "artifact" : "",
+         "name" : "{{ project }}",
+         "projectType" : "Executable",
+         "localLocation" : "{{ local_location }}",
+         "family" : "{{ family }}",
+         "toolChain" : "arm.gcc.toolchain",
+         "activecfg" : "Debug",
+         "language" : "C++",
+         {% if not fpu %}
+         "fpu" : "NO_FPU"
+         {% endif %}
+      }
+   }
+}
--- a/export/cdt/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/cdt/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,7 +1,8 @@
 import re
 
 from os.path import join, exists
-from os import makedirs
+from os import makedirs, remove
+import shutil
 
 from tools.export.makefile import Makefile, GccArm, Armc5, IAR
 
@@ -39,6 +40,12 @@
         self.gen_file('cdt/.cproject.tmpl', ctx, '.cproject')
         self.gen_file('cdt/.project.tmpl', ctx, '.project')
 
+    @staticmethod
+    def clean(project_name):
+        shutil.rmtree("eclipse-extras")
+        remove(".cproject")
+        remove(".project")
+
 
 class EclipseGcc(Eclipse, GccArm):
     LOAD_EXE = True
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/cmake/CMakeLists.txt.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,119 @@
+# This file was automagically generated by mbed.org.
+# If you would like to add your own targets, create a
+# project.cmake file locally in your project directory.
+
+CMAKE_MINIMUM_REQUIRED(VERSION 3.9)
+SET(CMAKE_SYSTEM_NAME Generic)
+#SET(CMAKE_SYSTEM_PROCESSOR arm)
+SET(CMAKE_CROSSCOMPILING TRUE)
+
+# force compiler settings
+SET(CMAKE_C_COMPILER_WORKS TRUE)
+SET(CMAKE_CXX_COMPILER_WORKS TRUE)
+
+# force cmake compilers
+SET(CMAKE_ASM_COMPILER    "{{asm}}")
+SET(CMAKE_C_COMPILER      "{{cc}}")
+SET(CMAKE_CXX_COMPILER    "{{cxx}}")
+SET(ELF2BIN               "{{elf2bin}}")
+{% if hex_files %}
+SET(SREC_CAT "srec_cat")
+{%- endif %}
+
+# if the environment does not specify build type, set to Debug
+IF(NOT CMAKE_BUILD_TYPE)
+  set(CMAKE_BUILD_TYPE "Debug"
+        CACHE STRING "Choose the type of build, options are: Debug Release RelWithDebInfo MinSizeRel."
+        FORCE)
+ENDIF()
+
+# here starts the project
+PROJECT({{name}} C CXX ASM)
+
+# uncomment below to have a verbose build process
+#SET(CMAKE_VERBOSE_MAKEFILE ON)
+
+SET(LD_SYS_LIBS "{%- block sys_libs -%} -Wl,--start-group {{ld_sys_libs|join(" ")}} {{libraries|join(" ")}} -Wl,--end-group {%- endblock -%}")
+
+SET(CMAKE_C_FLAGS "{{cc_flags}} -include mbed_config.h")
+SET(CMAKE_CXX_FLAGS "{{cxx_flags}}  -include mbed_config.h")
+SET(CMAKE_ASM_FLAGS "{{asm_flags}}  -include mbed_config.h")
+SET(CMAKE_CXX_LINK_FLAGS "{{ld_flags}} {% for p in library_paths %} {{user_library_flag}}${CMAKE_CURRENT_SOURCE_DIR}/{{p}} {% endfor %}")
+{% if pp -%}
+SET(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} ${LD_SYS_LIBS} {{link_script_option}} ${CMAKE_BINARY_DIR}/{{name}}_pp.link_script.ld")
+{%- endif %}
+
+ADD_DEFINITIONS(
+  {% for d in symbols %}-D{{d}}
+  {% endfor %})
+INCLUDE_DIRECTORIES(
+  {% for p in include_paths %}{{p}}
+  {% endfor %})
+
+# executable {{name}}
+ADD_EXECUTABLE({{name}}
+  {% for src in sources %}{{src}}
+  {% endfor %})
+SET_TARGET_PROPERTIES({{name}} PROPERTIES ENABLE_EXPORTS 1)
+# add syslibs dependencies to create the correct linker order
+TARGET_LINK_LIBRARIES({{name}} {{ld_sys_libs|join(" ")}})
+
+{% if pp -%}
+add_custom_command(TARGET {{name}} PRE_LINK
+                   COMMAND "{{pp}}" {{pp_flags}} {{linker_script}} -o ${CMAKE_CURRENT_BINARY_DIR}/{{name}}_pp.link_script.ld
+                   WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+                   BYPRODUCTS "${CMAKE_CURRENT_BINARY_DIR}/{{name}}_pp.link_script.ld"
+                   )
+{%- endif %}
+
+add_custom_command(TARGET {{name}} POST_BUILD
+                   COMMAND ${ELF2BIN} -O ihex $<TARGET_FILE:{{name}}> $<TARGET_FILE:{{name}}>.hex
+                   COMMAND ${CMAKE_COMMAND} -E echo "-- built: $<TARGET_FILE:{{name}}>.hex"
+                  )
+
+{% if hex_files %}
+add_custom_command(TARGET {{name}} POST_BUILD
+                   COMMAND ${SREC_CAT}
+                        {% for f in hex_files %}${CMAKE_CURRENT_SOURCE_DIR}/{{f}} {% endfor %}
+                        -intel $<TARGET_FILE:{{name}}>.hex
+                        -intel -o $<TARGET_FILE:{{name}}>-combined.hex -intel --line-length=44
+                   COMMAND ${CMAKE_COMMAND} -E echo "-- built: $<TARGET_FILE:{{name}}>-combined.hex"
+                   )
+{% endif %}
+
+
+##########################################################################
+# mbed-cli specific targets
+##########################################################################
+
+# detect the build type and select the corresponding cli profile
+SET(MBED_BUILD_PROFILE "")
+STRING(TOLOWER ${CMAKE_BUILD_TYPE} LOWERCASE_CMAKE_BUILD_TYPE)
+IF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES debug)
+    SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/debug.json")
+ELSEIF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES relwithdebinfo)
+    SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/develop.json")
+ELSEIF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES release)
+    SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/release.json")
+ELSEIF(LOWERCASE_CMAKE_BUILD_TYPE MATCHES minsizerel)
+    SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/release.json")
+ELSE()
+  MESSAGE(WARNING "Build type '${CMAKE_BUILD_TYPE}' is unknown, using debug profile")
+  SET(MBED_BUILD_PROFILE "mbed-os/tools/profiles/debug.json")
+ENDIF()
+
+# optional custom target to build via mbed-cli
+ADD_CUSTOM_TARGET(mbed-cli-build
+        COMMAND ${CMAKE_COMMAND} -E echo "mbed compile --build BUILD/${CMAKE_BUILD_TYPE} --profile ${MBED_BUILD_PROFILE}"
+        COMMAND mbed compile --build BUILD/${CMAKE_BUILD_TYPE} --profile ${MBED_BUILD_PROFILE}
+        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+        SOURCES ${SOURCE_FILES} ${SYS_SOURCE_FILES})
+
+IF(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/project.cmake)
+  INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/project.cmake)
+ELSE()
+  MESSAGE(STATUS "Add a local project.cmake file to add your own targets.")
+ENDIF()
+
+# this will take care of binary directories generated by cmake/clion not to confuse the cli build
+FILE(GENERATE OUTPUT "${CMAKE_BINARY_DIR}/.mbedignore" CONTENT "*")
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/cmake/README.md	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,15 @@
+# CLion CMakeLists.txt Generator
+
+This exporter generates a CMakeLists.txt file that can be used to
+develop mbed using [IntelliJ CLion](https://www.jetbrains.com/clion/).
+
+It will not create a functional CMake build system that mimics the
+mbed build system, but rather uses the mbed-cli itself to compile
+the targets. The generated files help CLion to understand the
+includes and dependencies of your code.
+
+Run the following command to create/overwrite your CMakeLists.txt.
+```
+mbed export -i cmake_gcc_arm
+```
+> Run the command again if files or libraries have been added or removed.
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/cmake/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,257 @@
+"""
+mbed SDK
+Copyright (c) 2011-2016 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+from __future__ import print_function, absolute_import
+from builtins import str
+
+import re
+import shutil
+from os import remove, getcwd, chdir, mkdir
+from os.path import basename, exists
+from subprocess import Popen, PIPE
+
+from jinja2.exceptions import TemplateNotFound
+
+from tools.export.exporters import Exporter, apply_supported_whitelist
+from tools.targets import TARGET_MAP
+
+
+class CMake(Exporter):
+    """Generic CMake template that mimics the behavior of the python build
+    system
+    """
+
+    TEMPLATE = 'CMakeLists.txt'
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    PREPROCESS_ASM = False
+
+    POST_BINARY_WHITELIST = set([
+        "MCU_NRF51Code.binary_hook",
+        "TEENSY3_1Code.binary_hook",
+        "LPCTargetCode.lpc_patch",
+        "LPC4088Code.binary_hook"
+    ])
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return apply_supported_whitelist(
+            cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target)
+
+    def generate(self):
+        """Generate the CMakefiles.txt
+        """
+        self.resources.win_to_unix()
+
+        # get all source files including headers, adding headers allows IDEs to detect which files
+        # belong to the project, otherwise headers may be greyed out and not work with inspection
+        # (that is true for CLion and definitely for Visual Code)
+        srcs = set(self.resources.c_sources +
+                   self.resources.cpp_sources +
+                   self.resources.s_sources +
+                   self.resources.headers)
+        srcs = [re.sub(r'^[.]/', '', f) for f in srcs]
+
+        # additional libraries
+        libraries = [self.prepare_lib(basename(lib)) for lib in self.libraries]
+        sys_libs = [self.prepare_sys_lib(lib) for lib in self.toolchain.sys_libs]
+
+        # sort includes reverse, so the deepest dir comes first (ensures short includes)
+        includes = sorted([re.sub(r'^[.]/', '', l) for l in self.resources.inc_dirs], reverse=True)
+
+        ctx = {
+            'name': self.project_name,
+            'target': self.target,
+            'sources': sorted(srcs),
+            'libraries': libraries,
+            'ld_sys_libs': sys_libs,
+            'include_paths': includes,
+            'library_paths': sorted([re.sub(r'^[.]/', '', l) for l in self.resources.lib_dirs]),
+            'linker_script': self.resources.linker_script,
+            'hex_files': self.resources.hex_files,
+            'ar': basename(self.toolchain.ar),
+            'cc': basename(self.toolchain.cc[0]),
+            'cc_flags': " ".join(flag for flag in self.toolchain.cc[1:] if not flag == "-c"),
+            'cxx': basename(self.toolchain.cppc[0]),
+            'cxx_flags': " ".join(flag for flag in self.toolchain.cppc[1:] if not flag == "-c"),
+            'asm': basename(self.toolchain.asm[0]),
+            'asm_flags': " ".join(flag for flag in self.toolchain.asm[1:] if not flag == "-c"),
+            'symbols': sorted(self.toolchain.get_symbols()),
+            'ld': basename(self.toolchain.ld[0]),
+            # fix the missing underscore '_' (see
+            'ld_flags': re.sub("--wrap,_(?!_)", "--wrap,__", " ".join(self.toolchain.ld[1:])),
+            'elf2bin': basename(self.toolchain.elf2bin),
+            'link_script_ext': self.toolchain.LINKER_EXT,
+            'link_script_option': self.LINK_SCRIPT_OPTION,
+            'user_library_flag': self.USER_LIBRARY_FLAG,
+            'needs_asm_preproc': self.PREPROCESS_ASM,
+        }
+
+        if hasattr(self.toolchain, "preproc"):
+            ctx['pp'] = basename(self.toolchain.preproc[0])
+            ctx['pp_flags'] = " ".join(self.toolchain.preproc[1:] +
+                                       self.toolchain.ld[1:])
+        else:
+            ctx['pp'] = None
+            ctx['pp_flags'] = None
+
+        try:
+            self.gen_file('cmake/%s.tmpl' % self.TEMPLATE, ctx, 'CMakeLists.txt')
+        except TemplateNotFound:
+            pass
+
+    @staticmethod
+    def clean(_):
+        remove("CMakeLists.txt")
+        # legacy .build directory cleaned if exists
+        if exists('.build'):
+            shutil.rmtree('.build')
+        if exists('BUILD'):
+            shutil.rmtree('BUILD')
+
+    @staticmethod
+    def build(project_name, log_name="build_log.txt", cleanup=True):
+        """ Build Make project """
+
+        # change into our build directory
+        current_dir = getcwd()
+        if not exists("BUILD"):
+            mkdir("BUILD")
+        chdir("BUILD")
+
+        # > run cmake initial command
+        cmd = ["cmake", ".."]
+
+        # Build the project
+        p = Popen(cmd, stdout=PIPE, stderr=PIPE)
+        out, err = p.communicate()
+        ret_code = p.returncode
+
+        if ret_code == 0:
+            # we create the cmake files inside BUILD, change into and run cmake
+
+            # > run make -j
+            cmd = ["make", "-j"]
+
+            p = Popen(cmd, stdout=PIPE, stderr=PIPE)
+            out, err = p.communicate()
+            ret_code = p.returncode
+
+        # go back to the original directory
+        chdir(current_dir)
+
+        out_string = "=" * 10 + "STDOUT" + "=" * 10 + "\n"
+        out_string += out
+        out_string += "=" * 10 + "STDERR" + "=" * 10 + "\n"
+        out_string += err
+
+        if ret_code == 0:
+            out_string += "SUCCESS"
+        else:
+            out_string += "FAILURE"
+
+        print(out_string)
+
+        if log_name:
+            # Write the output to the log file
+            with open(log_name, 'w+') as f:
+                f.write(out_string)
+
+        # Cleanup the exported and built files
+        if cleanup:
+            remove(log_name)
+            CMake.clean(project_name)
+
+        if ret_code != 0:
+            # Seems like something went wrong.
+            return -1
+        else:
+            return 0
+
+
+class GccArm(CMake):
+    """GCC ARM specific cmake target"""
+    NAME = 'CMake-GCC-ARM'
+    TOOLCHAIN = "GCC_ARM"
+    LINK_SCRIPT_OPTION = "-T"
+    USER_LIBRARY_FLAG = "-L"
+
+    @staticmethod
+    def prepare_lib(libname):
+        if "lib" == libname[:3]:
+            libname = libname[3:-2]
+        return "-l" + libname
+
+    @staticmethod
+    def prepare_sys_lib(libname):
+        return "-l" + libname
+
+# class Arm(CMake):
+#     """ARM Compiler generic cmake target"""
+#     LINK_SCRIPT_OPTION = "--scatter"
+#     USER_LIBRARY_FLAG = "--userlibpath "
+#
+#     @staticmethod
+#     def prepare_lib(libname):
+#         return libname
+#
+#     @staticmethod
+#     def prepare_sys_lib(libname):
+#         return libname
+#
+#     def generate(self):
+#         if self.resources.linker_script:
+#             new_script = self.toolchain.correct_scatter_shebang(
+#                 self.resources.linker_script)
+#             if new_script is not self.resources.linker_script:
+#                 self.resources.linker_script = new_script
+#                 self.generated_files.append(new_script)
+#         return super(Arm, self).generate()
+#
+#
+# class Armc5(Arm):
+#     """ARM Compiler 5 (armcc) specific makefile target"""
+#     NAME = 'CMake-ARMc5'
+#     TOOLCHAIN = "ARM"
+#     PREPROCESS_ASM = True
+#
+#
+# class Armc6(Arm):
+#     """ARM Compiler 6 (armclang) specific generic makefile target"""
+#     NAME = 'CMake-ARMc6'
+#     TOOLCHAIN = "ARMC6"
+#
+#
+# class IAR(CMake):
+#     """IAR specific cmake target"""
+#     NAME = 'CMake-IAR'
+#     TOOLCHAIN = "IAR"
+#     LINK_SCRIPT_OPTION = "--config"
+#     USER_LIBRARY_FLAG = "-L"
+#
+#     @staticmethod
+#     def prepare_lib(libname):
+#         if "lib" == libname[:3]:
+#             libname = libname[3:]
+#         return "-l" + splitext(libname)[0]
+#
+#     @staticmethod
+#     def prepare_sys_lib(libname):
+#         if "lib" == libname[:3]:
+#             libname = libname[3:]
+#         return "-l" + splitext(libname)[0]
--- a/export/cmsis/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/cmsis/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -2,13 +2,13 @@
 from os.path import sep, join, exists
 from itertools import groupby
 from xml.etree.ElementTree import Element, tostring
-import ntpath
 import re
 import json
 
 from tools.arm_pack_manager import Cache
 from tools.targets import TARGET_MAP
 from tools.export.exporters import Exporter, TargetNotSupportedException
+from tools.utils import split_path
 
 class fileCMSIS():
     """CMSIS file class.
@@ -37,7 +37,8 @@
         if not target_info:
             raise TargetNotSupportedException("Target not supported in CMSIS pack")
         self.url = target_info['pdsc_file']
-        self.pack_url, self.pack_id = ntpath.split(self.url)
+        self.pdsc_url, self.pdsc_id, _ = split_path(self.url)
+        self.pack_url, self.pack_id, _ = split_path(target_info['pack_file'])
         self.dname = target_info["_cpu_name"]
         self.core = target_info["_core"]
         self.dfpu = target_info['processor']['fpu']
@@ -97,6 +98,7 @@
         cpu = cpu.replace("Cortex-","ARMC")
         cpu = cpu.replace("+","P")
         cpu = cpu.replace("F","_FP")
+        cpu = cpu.replace("-NS", "")
         return cpu
 
 
@@ -142,7 +144,7 @@
     def generate(self):
         srcs = self.resources.headers + self.resources.s_sources + \
                self.resources.c_sources + self.resources.cpp_sources + \
-               self.resources.objects + self.resources.libraries + \
+               self.resources.objects + self.libraries + \
                [self.resources.linker_script]
         srcs = [fileCMSIS(src, src) for src in srcs if src]
         ctx = {
@@ -152,3 +154,8 @@
             'date': ''
         }
         self.gen_file('cmsis/cpdsc.tmpl', ctx, 'project.cpdsc')
+
+
+    @staticmethod
+    def clean(_):
+        os.remove('project.cpdsc')
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/codeblocks/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,177 @@
+"""
+mbed SDK
+Copyright (c) 2014-2017 ARM Limited
+Copyright (c) 2018 ON Semiconductor
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+import copy
+import stat
+import os
+from os.path import splitext, basename, dirname, abspath, isdir
+from os import remove, mkdir
+from shutil import rmtree, copyfile
+from tools.targets import TARGET_MAP
+from tools.export.exporters import Exporter
+from tools.export.makefile import GccArm
+
+class CodeBlocks(GccArm):
+    NAME = 'Code::Blocks'
+
+    DOT_IN_RELATIVE_PATH = True
+
+    MBED_CONFIG_HEADER_SUPPORTED = True
+
+    PREPROCESS_ASM = False
+
+    POST_BINARY_WHITELIST = set([
+        "NCS36510TargetCode.ncs36510_addfib"
+    ])
+
+    @staticmethod
+    def filter_dot(str_in):
+        """
+        Remove the './' prefix, if present.
+        This function assumes that resources.win_to_unix()
+        replaced all windows backslashes with slashes.
+        """
+        if str_in is None:
+            return None
+        if str_in[:2] == './':
+            return str_in[2:]
+        return str_in
+
+    @staticmethod
+    def prepare_lib(libname):
+        if "lib" == libname[:3]:
+            libname = libname[3:-2]
+        return "-l" + libname
+
+    @staticmethod
+    def prepare_sys_lib(libname):
+        return "-l" + libname
+
+    def generate(self):
+        self.resources.win_to_unix()
+
+        comp_flags = []
+        debug_flags = []
+        release_flags = [ '-Os', '-g1' ]
+        next_is_include = False
+        for f in self.flags['c_flags'] + self.flags['cxx_flags'] + self.flags['common_flags']:
+            f = f.strip()
+            if f == "-include":
+                next_is_include = True
+                continue
+            if f == '-c':
+                continue
+            if next_is_include:
+                f = '-include ' + f
+            next_is_include = False
+            if f.startswith('-O') or f.startswith('-g'):
+                debug_flags.append(f)
+            else:
+                comp_flags.append(f)
+        comp_flags = sorted(list(set(comp_flags)))
+        inc_dirs = [self.filter_dot(s) for s in self.resources.inc_dirs];
+        inc_dirs = [x for x in inc_dirs if (x is not None and
+                                            x != '' and x != '.' and
+                                            not x.startswith('bin') and
+                                            not x.startswith('obj'))];
+
+        c_sources = sorted([self.filter_dot(s) for s in self.resources.c_sources])
+        libraries = [self.prepare_lib(basename(lib)) for lib in self.libraries]
+        sys_libs = [self.prepare_sys_lib(lib) for lib
+                    in self.toolchain.sys_libs]
+        ncs36510fib = (hasattr(self.toolchain.target, 'post_binary_hook') and
+                       self.toolchain.target.post_binary_hook['function'] == 'NCS36510TargetCode.ncs36510_addfib')
+        if ncs36510fib:
+            c_sources.append('ncs36510fib.c')
+            c_sources.append('ncs36510trim.c')
+
+        ctx = {
+            'project_name': self.project_name,
+            'debug_flags': debug_flags,
+            'release_flags': release_flags,
+            'comp_flags': comp_flags,
+            'ld_flags': self.flags['ld_flags'],
+            'headers': sorted(list(set([self.filter_dot(s) for s in self.resources.headers]))),
+            'c_sources': c_sources,
+            's_sources': sorted([self.filter_dot(s) for s in self.resources.s_sources]),
+            'cpp_sources': sorted([self.filter_dot(s) for s in self.resources.cpp_sources]),
+            'include_paths': inc_dirs,
+            'linker_script': self.filter_dot(self.resources.linker_script),
+            'libraries': libraries,
+            'sys_libs': sys_libs,
+            'ncs36510addfib': ncs36510fib,
+            'openocdboard': ''
+            }
+
+        openocd_board = {
+            'NCS36510': 'board/ncs36510_axdbg.cfg',
+            'DISCO_F429ZI': 'board/stm32f429discovery.cfg',
+            'DISCO_F469NI': 'board/stm32f469discovery.cfg',
+            'DISCO_L053C8': 'board/stm32l0discovery.cfg',
+            'DISCO_L072CZ_LRWAN1': 'board/stm32l0discovery.cfg',
+            'DISCO_F769NI': 'board/stm32f7discovery.cfg',
+            'DISCO_L475VG_IOT01A': 'board/stm32l4discovery.cfg',
+            'DISCO_L476VG': 'board/stm32l4discovery.cfg',
+            'NRF51822': 'board/nordic_nrf51822_mkit.cfg',
+            'NRF51822_BOOT': 'board/nordic_nrf51822_mkit.cfg',
+            'NRF51822_OTA': 'board/nordic_nrf51822_mkit.cfg',
+            'NRF51_DK_LEGACY': 'board/nordic_nrf51_dk.cfg',
+            'NRF51_DK_BOOT': 'board/nordic_nrf51_dk.cfg',
+            'NRF51_DK_OTA': 'board/nordic_nrf51_dk.cfg',
+            'NRF51_DK': 'board/nordic_nrf51_dk.cfg'
+            }
+
+        if self.target in openocd_board:
+            ctx['openocdboard'] = openocd_board[self.target]
+
+        self.gen_file('codeblocks/cbp.tmpl', ctx, "%s.%s" % (self.project_name, 'cbp'))
+        for f in [ 'obj', 'bin' ]:
+            if not isdir(f):
+                mkdir(f)
+            self.gen_file_nonoverwrite('codeblocks/mbedignore.tmpl',
+                                       ctx, f + '/.mbedignore')
+
+        if ncs36510fib:
+            genaddfiles = [ 'ncs36510fib.c', 'ncs36510trim.c' ]
+            for f in genaddfiles:
+                copyfile(os.path.join(dirname(abspath(__file__)), f),
+                         self.gen_file_dest(f))
+            ignorefiles = genaddfiles
+            try:
+                with open(self.gen_file_dest('.mbedignore'), 'r') as f:
+                    l = set(map(lambda x: x.strip(), f.readlines()))
+                    ignorefiles = [x for x in genaddfiles if x not in l]
+            except IOError as e:
+                pass
+            except:
+                raise
+            if ignorefiles:
+                with open(self.gen_file_dest('.mbedignore'), 'a') as f:
+                    for fi in ignorefiles:
+                        f.write("%s\n" % fi)                
+
+        # finally, generate the project file
+        super(CodeBlocks, self).generate()
+
+    @staticmethod
+    def clean(project_name):
+        for ext in ['cbp', 'depend', 'layout']:
+            remove("%s.%s" % (project_name, ext))
+        for f in ['openocd.log', 'ncs36510fib.c', 'ncs36510trim.c']:
+            remove(f)
+        for d in ['bin', 'obj']:
+            rmtree(d, ignore_errors=True)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/codeblocks/cbp.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<CodeBlocks_project_file>
+	<FileVersion major="1" minor="6" />
+	<Project>
+		<Option title="{{project_name}}" />
+		<Option pch_mode="2" />
+		<Option compiler="arm-elf-gcc" />
+		<Build>
+			<Target title="Debug">
+				<Option output="bin/Debug/{{project_name}}.elf" prefix_auto="1" extension_auto="0" />
+				<Option object_output="obj/Debug/" />
+				<Option type="1" />
+				<Option compiler="arm-elf-gcc" />
+				<Option use_console_runner="0" />
+				<Compiler>
+					{%  for f in debug_flags -%}
+					<Add option="{{f}}" />
+					{%  endfor -%}
+				</Compiler>
+				<Linker>
+					<Add option='-Wl,-Map,&quot;bin/Debug/{{project_name}}.map&quot;' />
+				</Linker>
+				{% if ncs36510addfib -%}
+				<ExtraCommands>
+					<Add after="ncs36510updatefib -u bin/Debug/{{project_name}}.elf" />
+				</ExtraCommands>
+				{% endif -%}
+			</Target>
+			<Target title="Release">
+				<Option output="bin/Release/{{project_name}}.elf" prefix_auto="1" extension_auto="0" />
+				<Option object_output="obj/Release/" />
+				<Option type="1" />
+				<Option compiler="arm-elf-gcc" />
+				<Option use_console_runner="0" />
+				<Compiler>
+                                        <Add option="-DNDEBUG" />
+					{%  for f in release_flags -%}
+					<Add option="{{f}}" />
+					{%  endfor -%}
+				</Compiler>
+				<Linker>
+					<Add option='-Wl,-Map,&quot;bin/Release/{{project_name}}.map&quot;' />
+				</Linker>
+				{% if ncs36510addfib -%}
+				<ExtraCommands>
+					<Add after="ncs36510updatefib -u bin/Release/{{project_name}}.elf" />
+				</ExtraCommands>
+				{% endif -%}
+			</Target>
+		</Build>
+		<Compiler>
+			{%  for f in comp_flags -%}
+			<Add option="{{f}}" />
+			{%  endfor -%}
+			{%  for f in include_paths -%}
+			<Add directory="{{f}}" />
+			{%  endfor -%}
+		</Compiler>
+		<Linker>
+			{%  for f in ld_flags -%}
+			<Add option="{{f}}" />
+			{%  endfor -%}
+			<Add option="-T {{linker_script}}" />
+			<Add option="-Wl,--start-group {{sys_libs|join(" ")}} {{libraries|join(" ")}} -Wl,--end-group" />
+			{%  for f in sys_libs -%}
+			<Add option="{{f}}" />
+			{%  endfor -%}
+			{%  for f in libraries -%}
+			<Add option="{{f}}" />
+			{%  endfor -%}
+		</Linker>
+		{%  for f in headers -%}
+		<Unit filename="{{f}}"/>
+		{%  endfor -%}
+		{%  for f in c_sources -%}
+		<Unit filename="{{f}}">
+			<Option compilerVar="CC" />
+		</Unit>
+		{%  endfor -%}
+		{%  for f in s_sources -%}
+		<Unit filename="{{f}}">
+			<Option compilerVar="CPP" />
+		</Unit>
+		{%  endfor -%}
+		{%  for f in cpp_sources -%}
+		<Unit filename="{{f}}">
+			<Option compilerVar="CPP" />
+		</Unit>
+		{%  endfor -%}
+		<Extensions>
+		        {% if openocdboard != '' -%}
+			<debugger>
+				<remote_debugging target="Release">
+					<options conn_type="3" serial_baud="115200" pipe_command="openocd -p -l openocd.log -f {{openocdboard}}" additional_cmds='monitor reset halt&#x0A;monitor flash write_image erase &quot;bin/Release/{{project_name}}.elf&quot;&#x0A;file &quot;bin/Release/{{project_name}}.elf&quot;&#x0A;monitor reset halt&#x0A;' extended_remote="1" />
+				</remote_debugging>
+				<remote_debugging target="Debug">
+					<options conn_type="3" serial_baud="115200" pipe_command="openocd -p -l openocd.log -f {{openocdboard}}" additional_cmds='monitor reset halt&#x0A;monitor flash write_image erase &quot;bin/Debug/{{project_name}}.elf&quot;&#x0A;file &quot;bin/Debug/{{project_name}}.elf&quot;&#x0A;monitor reset halt&#x0A;' extended_remote="1" />
+				</remote_debugging>
+			</debugger>
+			{% endif -%}
+		</Extensions>
+	</Project>
+</CodeBlocks_project_file>
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/codeblocks/mbedignore.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,1 @@
+*
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/codeblocks/ncs36510fib.c	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,93 @@
+#include <stdint.h>
+
+struct ncs36510fib {
+	uint32_t dummy_sp;
+	uint32_t dummy_reset_vector;
+	uint32_t dummy_nmi_handler;
+	uint32_t dummy_hardfault_handler;
+	uint32_t dummy_blank;
+	uint32_t start;
+	uint32_t size;
+	uint32_t crc32;
+	uint32_t fw_rev;
+	uint32_t checksum;
+	uint32_t fill[502];
+};
+
+static struct ncs36510fib __attribute__((section(".fib,\"a\",%progbits@"), used)) ncs36510fib = {
+	0x3FFFFC00,
+	0x00003625,
+	0x00003761,
+	0x00003691,
+	0x00000000,
+	0,
+	0,
+	0,
+	0x01000100,
+	0,
+	{
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+	}
+};
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/codeblocks/ncs36510trim.c	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,87 @@
+#include <stdint.h>
+#include "mbed_config.h"
+
+struct ncs36510fib {
+	uint32_t mac_addr_low;
+	uint32_t mac_addr_high;
+	uint32_t clk_32k_trim;
+	uint32_t clk_32m_trim;
+	uint32_t rssi;
+	uint32_t txtune;
+	uint32_t fill[506];
+};
+
+static struct ncs36510fib __attribute__((section(".trim,\"a\",%progbits@"), used)) ncs36510fib = {
+	MBED_CONF_TARGET_MAC_ADDR_LOW,
+	MBED_CONF_TARGET_MAC_ADDR_HIGH,
+	MBED_CONF_TARGET_32KHZ_CLK_TRIM,
+	MBED_CONF_TARGET_32MHZ_CLK_TRIM,
+	MBED_CONF_TARGET_RSSI_TRIM,
+	MBED_CONF_TARGET_TXTUNE_TRIM,
+	{
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+		0xffffffff, 0xffffffff
+	}
+};
--- a/export/coide/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/coide/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,6 +15,7 @@
 limitations under the License.
 """
 from os.path import splitext, basename
+from os import remove
 
 from tools.export.exporters import Exporter, deprecated_exporter
 
@@ -74,20 +75,20 @@
     def generate(self):
         self.resources.win_to_unix()
         source_files = []
-        for r_type, n in CoIDE.FILE_TYPES.iteritems():
+        for r_type, n in CoIDE.FILE_TYPES.items():
             for file in getattr(self.resources, r_type):
                 source_files.append({
                     'name': basename(file), 'type': n, 'path': file
                 })
         header_files = []
-        for r_type, n in CoIDE.FILE_TYPES2.iteritems():
+        for r_type, n in CoIDE.FILE_TYPES2.items():
             for file in getattr(self.resources, r_type):
                 header_files.append({
                     'name': basename(file), 'type': n, 'path': file
                 })
 
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
             libraries.append(l[3:])
 
@@ -109,3 +110,7 @@
 
         # Project file
         self.gen_file('coide/%s.coproj.tmpl' % target, ctx, '%s.coproj' % self.project_name)
+
+    @staticmethod
+    def clean(project_name):
+        remove('%s.coproj' % project_name)
--- a/export/ds5_5/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/ds5_5/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -30,6 +30,7 @@
         'ARCH_PRO',
         'RZ_A1H',
         'VK_RZ_A1H',
+        'GR_LYCHEE',
     ]
 
     USING_MICROLIB = [
@@ -49,7 +50,7 @@
 
     def generate(self):
         source_files = []
-        for r_type, n in DS5_5.FILE_TYPES.iteritems():
+        for r_type, n in DS5_5.FILE_TYPES.items():
             for file in getattr(self.resources, r_type):
                 source_files.append({
                     'name': basename(file), 'type': n, 'path': file
@@ -59,7 +60,7 @@
             'name': self.project_name,
             'include_paths': self.resources.inc_dirs,
             'scatter_file': self.resources.linker_script,
-            'object_files': self.resources.objects + self.resources.libraries,
+            'object_files': self.resources.objects + self.libraries,
             'source_files': source_files,
             'symbols': self.toolchain.get_symbols()
         }
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/ds5_5/gr_lychee.cproject.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" moduleId="org.eclipse.cdt.core.settings" name="Build">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576" name="Build" parent="com.arm.eclipse.build.config.baremetal.exe.debug" postbuildStep="fromelf --bin &quot;${ProjDirPath}/Build/${ProjName}.axf&quot; -o &quot;../${ProjName}.bin&quot;">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.debug.1293445387" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.debug">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576..2093450286" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/ds5_gr_lychee/Build}" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.2019880438" incrementalBuildTarget="all" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.debug.518028859" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.debug"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.debug">
+								<option id="com.arm.tool.c.compiler.option.incpath.337015821" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath">
+									{% for path in include_paths %}
+										<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1479931161" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-A9" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.defmac.278202630" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+                                {% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+								{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.982666453" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1990808204" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1188306347" name="ARM Assembler" superClass="com.arm.tool.assembler">
+								<option id="com.arm.tool.assembler.option.cpu.1673465082" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A9" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.2036393580" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<option id="com.arm.tool.c.linker.option.cpu.419580654" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A9" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.scatter.1235987457" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${ProjDirPath}/{{ scatter_file }}" valueType="string"/>
+								<option id="com.arm.tool.c.linker.userobjs.1389137013" name="Other object files" superClass="com.arm.tool.c.linker.userobjs" valueType="userObjs">
+    								{% for path in object_files %}
+                                        <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
+                                    {% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.linker.input.806269116" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinputdependency" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.731120140" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.arm.eclipse.build.config.baremetal.exe.release.751106089">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="com.arm.eclipse.build.artefact.baremetal.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=com.arm.eclipse.build.artefact.baremetal.exe" cleanCommand="$(if $(findstring Windows_NT,$(OS)),clean,/bin/rm -f)" description="" id="com.arm.eclipse.build.config.baremetal.exe.release.751106089" name="Release" parent="com.arm.eclipse.build.config.baremetal.exe.release">
+					<folderInfo id="com.arm.eclipse.build.config.baremetal.exe.release.751106089." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.exe.release.531116686" name="ARM Compiler" superClass="com.arm.toolchain.baremetal.exe.release">
+							<targetPlatform id="com.arm.eclipse.build.config.baremetal.exe.release.751106089..723232367" name=""/>
+							<builder buildPath="${workspace_loc:/ds5_gr_lychee/Release}" id="com.arm.toolchain.baremetal.builder.2017314066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.toolchain.baremetal.builder"/>
+							<tool id="com.arm.tool.c.compiler.baremetal.exe.release.920331842" name="ARM C Compiler" superClass="com.arm.tool.c.compiler.baremetal.exe.release"/>
+							<tool id="com.arm.tool.cpp.compiler.baremetal.exe.release.487140164" name="ARM C++ Compiler" superClass="com.arm.tool.cpp.compiler.baremetal.exe.release">
+								<option id="com.arm.tool.c.compiler.option.defmac.813110551" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols">
+									{% for s in symbols %}
+									<listOptionValue builtIn="false" value="{{s}}"/>
+									{% endfor %}
+								</option>
+								<inputType id="com.arm.tool.c.compiler.input.79502875" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.192669519" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.assembler.1423278729" name="ARM Assembler" superClass="com.arm.tool.assembler"/>
+							<tool id="com.arm.tool.c.linker.1149702455" name="ARM Linker" superClass="com.arm.tool.c.linker">
+								<inputType id="com.arm.tool.c.linker.input.2130902749" superClass="com.arm.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.arm.tool.librarian.710017326" name="ARM Librarian" superClass="com.arm.tool.librarian"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="ds5_gr_lychee.com.arm.eclipse.build.project.baremetal.exe.579849103" name="Bare-metal Executable" projectType="com.arm.eclipse.build.project.baremetal.exe"/>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="1">
+		<resource resourceType="PROJECT" workspacePath="/ds5_gr_lychee"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.cpp.compiler.input.1990808204">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.arm.eclipse.build.config.baremetal.exe.debug.1910477576;com.arm.eclipse.build.config.baremetal.exe.debug.1910477576.;com.arm.tool.cpp.compiler.baremetal.exe.debug.773836201;com.arm.tool.c.compiler.input.982666453">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.arm.eclipse.builder.armcc.ARMCompilerDiscoveryProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/ds5_5/gr_lychee.launch.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.arm.debugger.launcher2">
+<stringAttribute key="ANDROID_ACTIVITY_NAME" value=""/>
+<stringAttribute key="ANDROID_APPLICATION" value=""/>
+<stringAttribute key="ANDROID_APP_DIR" value=""/>
+<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
+<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
+<booleanAttribute key="EVENT_VIEWER_ENABLED" value="false"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH" value="1Mb"/>
+<stringAttribute key="EVENT_VIEWER_MAX_DEPTH_NUMBER" value="1048576"/>
+<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
+<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
+<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
+<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
+<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
+<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
+<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
+<listAttribute key="FILES.ICE_DEBUG">
+<listEntry value="ON_DEMAND_LOAD"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value=""/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.TYPE" value="SYMBOLS_FILE"/>
+<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.1.VALUE" value="${workspace_loc:/ds5_gr_lychee/Build/ds5_gr_lychee.axf}"/>
+<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="2"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
+<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
+<listEntry value="ON_DEMAND_LOAD"/>
+<listEntry value="ALSO_LOAD_SYMBOLS"/>
+</listAttribute>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
+<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
+<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
+<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
+<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
+<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
+<listAttribute key="ITM_CHANNEL_LIST">
+<listEntry value="ITM_CHANNEL_port0"/>
+</listAttribute>
+<booleanAttribute key="ITM_CHANNEL_port0_ENABLED" value="true"/>
+<stringAttribute key="ITM_CHANNEL_port0_FILE" value=""/>
+<stringAttribute key="ITM_CHANNEL_port0_FORMAT" value="raw"/>
+<intAttribute key="ITM_CHANNEL_port0_ID" value="0"/>
+<intAttribute key="ITM_CHANNEL_port0_OUTPUT" value="0"/>
+<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="true"/>
+<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value="interrupt&#13;&#10;set $PC=Reset_Handler&#13;&#10;"/>
+<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
+<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
+<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
+<booleanAttribute key="VFS_ENABLED" value="true"/>
+<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
+<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
+<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#13;&#10;&lt;/breakpoints&gt;&#13;&#10;"/>
+<stringAttribute key="config_db_activity_name" value="Debug Cortex-A9 via VSTREAM"/>
+<stringAttribute key="config_db_connection_keys" value="rvi_address config_file TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
+<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_platform_name" value="MBED - LPC1768"/>
+<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
+<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
+<stringAttribute key="config_file" value="CDB://mbed_dap.rvc"/>
+<booleanAttribute key="connectOnly" value="true"/>
+<stringAttribute key="dtsl_options_file" value="default"/>
+<booleanAttribute key="linuxOS" value="false"/>
+<stringAttribute key="rddi_type" value="rddi-debug-rvi"/>
+<booleanAttribute key="runAfterConnect" value="false"/>
+<stringAttribute key="rvi_address" value="TCP:E106295"/>
+<stringAttribute key="watchpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;US-ASCII&quot; ?&gt;&#13;&#10;&lt;watchpoint&gt;&#13;&#10;&lt;/watchpoint&gt;&#13;&#10;"/>
+</launchConfiguration>
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/ds5_5/gr_lychee.project.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>{{name}}_ds5_gr_lychee</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/ds5_gr_lychee/Build}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
--- a/export/e2studio/.cproject.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/e2studio/.cproject.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -326,10 +326,10 @@
 									{% endfor %}
 								</option>
 								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
-									{% for lib in opts['ld']['user_libraries'] %}
+									{% for lib in opts['ld']['system_libraries'] %}
 									<listOptionValue builtIn="false" value="{{lib}}"/>
 									{% endfor %}
-									{% for lib in opts['ld']['system_libraries'] %}
+									{% for lib in opts['ld']['user_libraries'] %}
 									<listOptionValue builtIn="false" value="{{lib}}"/>
 									{% endfor %}
 								</option>
@@ -337,6 +337,9 @@
 									{% for path in opts['ld']['object_files'] %}
 									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
 									{% endfor %}
+									{% for path in opts['ld']['user_library_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
 								</option>
 								{% if opts['ld']['gcsections'] %}
 								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.{{u.id}}" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
--- a/export/e2studio/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/e2studio/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from os import remove
 from tools.export.gnuarmeclipse import GNUARMEclipse
 
 class E2Studio(GNUARMEclipse):
@@ -23,26 +24,24 @@
     TARGETS = [
         'RZ_A1H',
         'VK_RZ_A1H',
+        'GR_LYCHEE',
     ]
 
     # override
     def generate(self):
 
-        jinja_ctx = self.collect_tmpl_vars()
-            
-        print
-        print 'Create a e2 studio C++ managed project'
-        print 'Project name: {0}'.format(self.project_name)
-        print 'Target: {0}'.format(self.toolchain.target.name)
-        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
+        jinja_ctx = self.create_jinja_ctx()
 
         self.gen_file('e2studio/.cproject.tmpl', jinja_ctx, '.cproject', trim_blocks=True, lstrip_blocks=True)
         self.gen_file('e2studio/.gdbinit.tmpl', jinja_ctx, '.gdbinit')
+        self.gen_file('e2studio/launch5x.tmpl', jinja_ctx, '%s OpenOCD 5x.launch' % self.project_name, trim_blocks=True, lstrip_blocks=True)
         self.gen_file('e2studio/launch.tmpl', jinja_ctx, '%s OpenOCD.launch' % self.project_name, trim_blocks=True, lstrip_blocks=True)
 
         self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx, '.project', trim_blocks=True, lstrip_blocks=True)
-        self.gen_file('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+        self.gen_file_nonoverwrite('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore')
         self.gen_file('gnuarmeclipse/makefile.targets.tmpl', jinja_ctx, 'makefile.targets', trim_blocks=True, lstrip_blocks=True)
 
-        print
-        print 'Done. Import the project located at \'{0}\' in e2 studio.'.format(self.project_name)
+    @staticmethod
+    def clean(project_name):
+        remove('%s OpenOCD 5x.launch' % project_name)
+        remove('%s OpenOCD.launch' % project_name)
--- a/export/e2studio/launch.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/e2studio/launch.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -1,29 +1,29 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value=""/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f board/renesas_gr-peach.cfg"/>
-<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f board/renesas_gr-peach.cfg"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/e2studio/launch5x.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f board/renesas_gr-peach.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\{{name}}.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="{{name}}"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.renesas.cdt.managedbuild.gnuarm.toolchain.base.264627759"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/{{name}}"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
--- a/export/embitz/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/embitz/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,6 +15,7 @@
 limitations under the License.
 """
 from os.path import splitext, basename
+from os import remove
 from tools.targets import TARGET_MAP
 from tools.export.exporters import Exporter, apply_supported_whitelist
 
@@ -52,14 +53,14 @@
     def generate(self):
         self.resources.win_to_unix()
         source_files = []
-        for r_type, n in self.FILE_TYPES.iteritems():
+        for r_type, n in self.FILE_TYPES.items():
             for file in getattr(self.resources, r_type):
                 source_files.append({
                     'name': file, 'type': n
                 })
 
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
             libraries.append(l[3:])
 
@@ -87,3 +88,7 @@
         }
 
         self.gen_file('embitz/eix.tmpl', ctx, '%s.eix' % self.project_name)
+
+    @staticmethod
+    def clean(project_name):
+        remove("%s.eix" % project_name)
--- a/export/exporters.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/exporters.py	Tue Sep 25 13:43:09 2018 -0500
@@ -2,13 +2,15 @@
 import os
 from abc import abstractmethod, ABCMeta
 import logging
-from os.path import join, dirname, relpath, basename, realpath, normpath
+from os.path import join, dirname, relpath, basename, realpath, normpath, exists
 from itertools import groupby
 from jinja2 import FileSystemLoader, StrictUndefined
 from jinja2.environment import Environment
 import copy
 
 from tools.targets import TARGET_MAP
+from tools.utils import mkdir
+from tools.resources import FileType
 
 
 class TargetNotSupportedException(Exception):
@@ -50,6 +52,7 @@
     NAME = None
     TARGETS = set()
     TOOLCHAIN = None
+    CLEAN_FILES = ("GettingStarted.html",)
 
 
     def __init__(self, target, export_dir, project_name, toolchain,
@@ -85,12 +88,8 @@
         return self.TOOLCHAIN
 
     def add_config(self):
-        """Add the containgin directory of mbed_config.h to include dirs"""
-        config = self.toolchain.get_config_header()
-        if config:
-            self.resources.inc_dirs.append(
-                dirname(relpath(config,
-                                self.resources.file_basepath[config])))
+        """Add the containing directory of mbed_config.h to include dirs"""
+        pass
 
     @property
     def flags(self):
@@ -102,9 +101,7 @@
         asm_flags    - assembler flags
         common_flags - common options
         """
-        config_header = self.toolchain.get_config_header()
-        flags = {key + "_flags": copy.deepcopy(value) for key, value
-                 in self.toolchain.flags.iteritems()}
+        flags = self.toolchain_flags(self.toolchain)
         asm_defines = self.toolchain.get_compile_options(
             self.toolchain.get_symbols(for_asm=True),
             filter(None, self.resources.inc_dirs),
@@ -113,14 +110,52 @@
         flags['asm_flags'] += asm_defines
         flags['c_flags'] += c_defines
         flags['cxx_flags'] += c_defines
+        config_header = self.config_header_ref
         if config_header:
-            config_header = relpath(config_header,
-                                    self.resources.file_basepath[config_header])
-            flags['c_flags'] += self.toolchain.get_config_option(config_header)
-            flags['cxx_flags'] += self.toolchain.get_config_option(
-                config_header)
+            config_option = self.toolchain.get_config_option(
+                config_header.name)
+            flags['c_flags'] += config_option
+            flags['cxx_flags'] += config_option
         return flags
 
+    @property
+    def libraries(self):
+        return [l for l in self.resources.get_file_names(FileType.LIB)
+                if l.endswith(self.toolchain.LIBRARY_EXT)]
+
+    def toolchain_flags(self, toolchain):
+        """Returns a dictionary of toolchain flags.
+        Keys of the dictionary are:
+        cxx_flags    - c++ flags
+        c_flags      - c flags
+        ld_flags     - linker flags
+        asm_flags    - assembler flags
+        common_flags - common options
+
+        The difference from the above is that it takes a parameter.
+        """
+        flags = {key + "_flags": copy.deepcopy(value) for key, value
+                 in toolchain.flags.items()}
+        config_header = self.config_header_ref
+        if config_header:
+            header_options = self.toolchain.get_config_option(
+                config_header.name)
+            flags['c_flags'] += header_options
+            flags['cxx_flags'] += header_options
+        return flags
+
+    @property
+    def config_header_ref(self):
+        config_header = self.toolchain.get_config_header()
+        if config_header:
+            def is_config_header(f):
+                return f.path == config_header
+            return list(filter(
+                is_config_header, self.resources.get_file_refs(FileType.HEADER)
+            ))[0]
+        else:
+            return None
+
     def get_source_paths(self):
         """Returns a list of the directories where source files are contained"""
         source_keys = ['s_sources', 'c_sources', 'cpp_sources', 'hex_files',
@@ -130,8 +165,36 @@
             source_files.extend(getattr(self.resources, key))
         return list(set([os.path.dirname(src) for src in source_files]))
 
+    def gen_file_dest(self, target_file):
+        """Generate the project file location in an exported project"""
+        return join(self.export_dir, target_file)
+
     def gen_file(self, template_file, data, target_file, **kwargs):
         """Generates a project file from a template using jinja"""
+        target_text = self._gen_file_inner(template_file, data, target_file, **kwargs)
+        target_path = self.gen_file_dest(target_file)
+        mkdir(dirname(target_path))
+        logging.debug("Generating: %s", target_path)
+        open(target_path, "w").write(target_text)
+        self.generated_files += [target_path]
+
+    def gen_file_nonoverwrite(self, template_file, data, target_file, **kwargs):
+        """Generates a project file from a template using jinja"""
+        target_text = self._gen_file_inner(template_file, data, target_file, **kwargs)
+        target_path = self.gen_file_dest(target_file)
+        if exists(target_path):
+            with open(target_path) as fdin:
+                old_text = fdin.read()
+            if target_text not in old_text:
+                with open(target_path, "a") as fdout:
+                    fdout.write(target_text)
+        else:
+            logging.debug("Generating: %s", target_path)
+            open(target_path, "w").write(target_text)
+        self.generated_files += [target_path]
+
+    def _gen_file_inner(self, template_file, data, target_file, **kwargs):
+        """Generates a project file from a template using jinja"""
         jinja_loader = FileSystemLoader(
             os.path.dirname(os.path.abspath(__file__)))
         jinja_environment = Environment(loader=jinja_loader,
@@ -139,6 +202,7 @@
 
         template = jinja_environment.get_template(template_file)
         target_text = template.render(data)
+        return target_text
 
         target_path = join(self.export_dir, target_file)
         logging.debug("Generating: %s", target_path)
@@ -150,8 +214,7 @@
         Positional Arguments:
         src - the src's location
         """
-        rel_path = relpath(src, self.resources.file_basepath[src])
-        path_list = os.path.normpath(rel_path).split(os.sep)
+        path_list = os.path.normpath(src).split(os.sep)
         assert len(path_list) >= 1
         if len(path_list) == 1:
             key = self.project_name
@@ -189,12 +252,28 @@
 
         Returns -1 on failure and 0 on success
         """
-        raise NotImplemented("Implement in derived Exporter class.")
+        raise NotImplementedError("Implement in derived Exporter class.")
+
+    @staticmethod
+    def clean(project_name):
+        """Clean a previously exported project
+        This method is assumed to be executed at the same level as exporter
+        project files and project source code.
+        See uvision/__init__.py, iar/__init__.py, and makefile/__init__.py for
+        example implemenation.
+
+        Positional Arguments:
+        project_name - the name of the project to build; often required by
+        exporter's build command.
+
+        Returns nothing. May raise exceptions
+        """
+        raise NotImplementedError("Implement in derived Exporter class.")
 
     @abstractmethod
     def generate(self):
         """Generate an IDE/tool specific project file"""
-        raise NotImplemented("Implement a generate function in Exporter child class")
+        raise NotImplementedError("Implement a generate function in Exporter child class")
 
     @classmethod
     def is_target_supported(cls, target_name):
@@ -214,6 +293,20 @@
     def all_supported_targets(cls):
         return [t for t in TARGET_MAP.keys() if cls.is_target_supported(t)]
 
+    @staticmethod
+    def filter_dot(str):
+        """
+        Remove the './' or '.\\' prefix, if present.
+        """
+        if str == None:
+            return None
+        if str[:2] == './':
+            return str[2:]
+        if str[:2] == '.\\':
+            return str[2:]
+        return str
+
+
 
 def apply_supported_whitelist(compiler, whitelist, target):
     """Generate a list of supported targets for a given compiler and post-binary hook
--- a/export/gnuarmeclipse/.cproject.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/gnuarmeclipse/.cproject.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -326,10 +326,10 @@
 									{% endfor %}
 								</option>
 								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
-									{% for lib in opts['ld']['user_libraries'] %}
+									{% for lib in opts['ld']['system_libraries'] %}
 									<listOptionValue builtIn="false" value="{{lib}}"/>
 									{% endfor %}
-									{% for lib in opts['ld']['system_libraries'] %}
+									{% for lib in opts['ld']['user_libraries'] %}
 									<listOptionValue builtIn="false" value="{{lib}}"/>
 									{% endfor %}
 								</option>
@@ -337,6 +337,9 @@
 									{% for path in opts['ld']['object_files'] %}
 									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
 									{% endfor %}
+									{% for path in opts['ld']['user_library_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
 								</option>
 								{% if opts['ld']['gcsections'] %}
 								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.{{u.id}}" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
--- a/export/gnuarmeclipse/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/gnuarmeclipse/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -21,6 +21,8 @@
 
 Author: Liviu Ionescu <ilg@livius.net>
 """
+from __future__ import print_function, absolute_import
+from builtins import str
 
 import os
 import copy
@@ -75,57 +77,6 @@
         return apply_supported_whitelist(
             cls.TOOLCHAIN, POST_BINARY_WHITELIST, target)
 
-    # override
-    @property
-    def flags(self):
-        """Returns a dictionary of toolchain flags.
-        Keys of the dictionary are:
-        cxx_flags    - c++ flags
-        c_flags      - c flags
-        ld_flags     - linker flags
-        asm_flags    - assembler flags
-        common_flags - common options
-
-        The difference from the parent function is that it does not
-        add macro definitions, since they are passed separately.
-        """
-
-        config_header = self.toolchain.get_config_header()
-        flags = {key + "_flags": copy.deepcopy(value) for key, value
-                 in self.toolchain.flags.iteritems()}
-        if config_header:
-            config_header = relpath(config_header,
-                                    self.resources.file_basepath[config_header])
-            flags['c_flags'] += self.toolchain.get_config_option(config_header)
-            flags['cxx_flags'] += self.toolchain.get_config_option(
-                config_header)
-        return flags
-
-    def toolchain_flags(self, toolchain):
-        """Returns a dictionary of toolchain flags.
-        Keys of the dictionary are:
-        cxx_flags    - c++ flags
-        c_flags      - c flags
-        ld_flags     - linker flags
-        asm_flags    - assembler flags
-        common_flags - common options
-
-        The difference from the above is that it takes a parameter.
-        """
-
-        # Note: use the config options from the currently selected toolchain.
-        config_header = self.toolchain.get_config_header()
-
-        flags = {key + "_flags": copy.deepcopy(value) for key, value
-                 in toolchain.flags.iteritems()}
-        if config_header:
-            config_header = relpath(config_header,
-                                    self.resources.file_basepath[config_header])
-            header_options = self.toolchain.get_config_option(config_header)
-            flags['c_flags'] += header_options
-            flags['cxx_flags'] += header_options
-        return flags
-
     def validate_resources(self):
         if not self.resources.linker_script:
             raise NotSupportedException("No linker script found.")
@@ -139,9 +90,9 @@
         # TODO: use some logger to display additional info if verbose
 
         libraries = []
-        # print 'libraries'
-        # print self.resources.libraries
-        for lib in self.resources.libraries:
+        library_files = []
+        for lib in self.libraries:
+            library_files.append(self.filter_dot(lib))
             l, _ = splitext(basename(lib))
             libraries.append(l[3:])
 
@@ -158,28 +109,22 @@
         # TODO: get the list from existing .cproject
         build_folders = [s.capitalize() for s in profile_ids]
         build_folders.append('BUILD')
-        # print build_folders
 
         objects = [self.filter_dot(s) for s in self.resources.objects]
         for bf in build_folders:
             objects = [o for o in objects if not o.startswith(bf + '/')]
-        # print 'objects'
-        # print objects
 
         self.compute_exclusions()
 
         self.include_path = [
             self.filter_dot(s) for s in self.resources.inc_dirs]
-        print 'Include folders: {0}'.format(len(self.include_path))
 
         self.as_defines = self.toolchain.get_symbols(True)
         self.c_defines = self.toolchain.get_symbols()
         self.cpp_defines = self.c_defines
-        print 'Symbols: {0}'.format(len(self.c_defines))
 
         self.ld_script = self.filter_dot(
             self.resources.linker_script)
-        print 'Linker script: {0}'.format(self.ld_script)
 
         self.options = {}
         for id in profile_ids:
@@ -196,8 +141,6 @@
             opts['id'] = id
             opts['name'] = opts['id'].capitalize()
 
-            print
-            print 'Build configuration: {0}'.format(opts['name'])
 
             profile = profiles[id]
 
@@ -210,15 +153,11 @@
 
             # Hack to fill in build_dir
             toolchain.build_dir = self.toolchain.build_dir
+            toolchain.config = self.toolchain.config
+            toolchain.set_config_data(self.toolchain.config.get_config_data())
 
             flags = self.toolchain_flags(toolchain)
 
-            print 'Common flags:', ' '.join(flags['common_flags'])
-            print 'C++ flags:', ' '.join(flags['cxx_flags'])
-            print 'C flags:', ' '.join(flags['c_flags'])
-            print 'ASM flags:', ' '.join(flags['asm_flags'])
-            print 'Linker flags:', ' '.join(flags['ld_flags'])
-
             # Most GNU ARM Eclipse options have a parent,
             # either debug or release.
             if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
@@ -241,6 +180,7 @@
 
             opts['ld']['object_files'] = objects
             opts['ld']['user_libraries'] = libraries
+            opts['ld']['user_library_files'] = library_files
             opts['ld']['system_libraries'] = self.system_libraries
             opts['ld']['script'] = join(id.capitalize(),
                                         "linker-script-%s.ld" % id)
@@ -279,11 +219,6 @@
         """
         jinja_ctx = self.create_jinja_ctx()
 
-        print
-        print 'Create a GNU ARM Eclipse C++ managed project'
-        print 'Project name: {0}'.format(self.project_name)
-        print 'Target: {0}'.format(self.toolchain.target.name)
-        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
 
         self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx,
                       '.project', trim_blocks=True, lstrip_blocks=True)
@@ -291,10 +226,21 @@
                       '.cproject', trim_blocks=True, lstrip_blocks=True)
         self.gen_file('gnuarmeclipse/makefile.targets.tmpl', jinja_ctx,
                       'makefile.targets', trim_blocks=True, lstrip_blocks=True)
-        self.gen_file('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+        self.gen_file_nonoverwrite('gnuarmeclipse/mbedignore.tmpl', jinja_ctx,
+                                   '.mbedignore')
+
+        print('Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name))
 
-        print
-        print 'Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name)
+    @staticmethod
+    def clean(_):
+        os.remove('.project')
+        os.remove('.cproject')
+        if exists('Debug'):
+            shutil.rmtree('Debug')
+        if exists('Release'):
+            shutil.rmtree('Release')
+        if exists('makefile.targets'):
+            os.remove('makefile.targets')
 
     # override
     @staticmethod
@@ -349,7 +295,7 @@
         if ret_code != 0:
             ret_string += "FAILURE\n"
 
-        print "%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string)
+        print("%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string))
 
         if log_name:
             # Write the output to the log file
@@ -363,14 +309,6 @@
         if cleanup:
             if exists(log_name):
                 os.remove(log_name)
-            os.remove('.project')
-            os.remove('.cproject')
-            if exists('Debug'):
-                shutil.rmtree('Debug')
-            if exists('Release'):
-                shutil.rmtree('Release')
-            if exists('makefile.targets'):
-                os.remove('makefile.targets')
 
         # Always remove the temporary folder.
         if exists(tmp_folder):
@@ -391,11 +329,9 @@
         file_names = [join(tools_path, "profiles", fn) for fn in os.listdir(
             join(tools_path, "profiles")) if fn.endswith(".json")]
 
-        # print file_names
 
         profile_names = [basename(fn).replace(".json", "")
                          for fn in file_names]
-        # print profile_names
 
         profiles = {}
 
@@ -429,32 +365,15 @@
             src) for src in self.resources.c_sources + self.resources.cpp_sources + self.resources.s_sources)]
 
         self.excluded_folders = set(self.resources.ignored_dirs) - set(self.resources.inc_dirs)
-        print 'Source folders: {0}, with {1} exclusions'.format(len(source_folders), len(self.excluded_folders))
 
 
     # -------------------------------------------------------------------------
 
-    @staticmethod
-    def filter_dot(str):
-        """
-        Remove the './' prefix, if present.
-        This function assumes that resources.win_to_unix()
-        replaced all windows backslashes with slashes.
-        """
-        if str == None:
-            return None
-        if str[:2] == './':
-            return str[2:]
-        return str
-
-    # -------------------------------------------------------------------------
-
     def dump_tree(self, nodes, depth=0):
         for k in nodes.keys():
             node = nodes[k]
             parent_name = node['parent'][
                 'name'] if 'parent' in node.keys() else ''
-            print '  ' * depth, node['name'], node['is_used'], parent_name
             if len(node['children'].keys()) != 0:
                 self.dump_tree(node['children'], depth + 1)
 
@@ -468,7 +387,6 @@
                     break
                 node = node['parent']
             path = '/'.join(parts)
-            print path, nodes[k]['is_used']
             self.dump_paths(nodes[k]['children'], depth + 1)
 
     # -------------------------------------------------------------------------
@@ -498,14 +416,6 @@
         # Make a copy of the flags, to be one by one removed after processing.
         flags = copy.deepcopy(flags_in)
 
-        if False:
-            print
-            print 'common_flags', flags['common_flags']
-            print 'asm_flags', flags['asm_flags']
-            print 'c_flags', flags['c_flags']
-            print 'cxx_flags', flags['cxx_flags']
-            print 'ld_flags', flags['ld_flags']
-
         # Initialise the 'last resort' options where all unrecognised
         # options will be collected.
         opts['as']['other'] = ''
@@ -938,17 +848,6 @@
         opts['cpp']['other'] = opts['cpp']['other'].strip()
         opts['ld']['other'] = opts['ld']['other'].strip()
 
-        if False:
-            print
-            print opts
-
-            print
-            print 'common_flags', flags['common_flags']
-            print 'asm_flags', flags['asm_flags']
-            print 'c_flags', flags['c_flags']
-            print 'cxx_flags', flags['cxx_flags']
-            print 'ld_flags', flags['ld_flags']
-
     @staticmethod
     def find_options(lst, option):
         tmp = [str for str in lst if str.startswith(option)]
--- a/export/gnuarmeclipse/makefile.targets.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/gnuarmeclipse/makefile.targets.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -1,4 +1,4 @@
-# DO NOT REMOVE! Generated by the GNU ARM Eclipse exporter from an mBed project.
+# DO NOT REMOVE! Generated by the GNU ARM Eclipse exporter from an Mbed project.
 
 mbedclean:
 	$(RM) $(OBJS)
@@ -6,7 +6,7 @@
 	$(RM) $(SECONDARY_FLASH)$(SECONDARY_SIZE) {{name}}.* linker-script-*.ld
 	-@echo ' '
 
-{% for config, data in options.iteritems() %}
+{% for config, data in options.items() %}
 linker-script-{{config}}.ld: ../{{ld_script}}
 	{{data.cpp_cmd}} {{data.ld.other}} $< -o $@
 {{name}}.elf: linker-script-{{config}}.ld
--- a/export/iar/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/iar/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,3 +1,6 @@
+from __future__ import print_function, absolute_import
+from builtins import str
+
 import os
 from os.path import sep, join, exists
 from collections import namedtuple
@@ -106,11 +109,11 @@
             raise NotSupportedException("No linker script found.")
         srcs = self.resources.headers + self.resources.s_sources + \
                self.resources.c_sources + self.resources.cpp_sources + \
-               self.resources.objects + self.resources.libraries
+               self.resources.objects + self.libraries
         flags = self.flags
         c_flags = list(set(flags['common_flags']
-                                    + flags['c_flags']
-                                    + flags['cxx_flags']))
+                           + flags['c_flags']
+                           + flags['cxx_flags']))
         # Flags set in template to be set by user in IDE
         template = ["--vla", "--no_static_destruction"]
         # Flag invalid if set in template
@@ -130,7 +133,7 @@
             'include_paths': [self.format_file(src) for src in self.resources.inc_dirs],
             'device': self.iar_device(),
             'ewp': sep+self.project_name + ".ewp",
-            'debugger': debugger
+            'debugger': debugger,
         }
         ctx.update(flags)
 
@@ -139,6 +142,17 @@
         self.gen_file('iar/ewp.tmpl', ctx, self.project_name + ".ewp")
 
     @staticmethod
+    def clean(project_name):
+        os.remove(project_name + ".ewp")
+        os.remove(project_name + ".ewd")
+        os.remove(project_name + ".eww")
+        # legacy output file location
+        if exists('.build'):
+            shutil.rmtree('.build')
+        if exists('BUILD'):
+            shutil.rmtree('BUILD')
+
+    @staticmethod
     def build(project_name, log_name="build_log.txt", cleanup=True):
         """ Build IAR project """
         # > IarBuild [project_path] -build [project_name]
@@ -170,7 +184,7 @@
         else:
             out_string += "FAILURE"
 
-        print out_string
+        print(out_string)
 
         if log_name:
             # Write the output to the log file
@@ -179,19 +193,10 @@
 
         # Cleanup the exported and built files
         if cleanup:
-            os.remove(project_name + ".ewp")
-            os.remove(project_name + ".ewd")
-            os.remove(project_name + ".eww")
-            # legacy output file location
-            if exists('.build'):
-                shutil.rmtree('.build')
-            if exists('BUILD'):
-                shutil.rmtree('BUILD')
+            IAR.clean(project_name)
 
         if ret_code !=0:
             # Seems like something went wrong.
             return -1
         else:
             return 0
-
-
--- a/export/iar/ewp.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/iar/ewp.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -10,166 +10,166 @@
 		<settings>
 			<name>General</name>
 			<archiveVersion>3</archiveVersion>
-      <data>
-        <version>24</version>
-        <wantNonLocal>1</wantNonLocal>
-        <debug>1</debug>
-        <option>
-          <name>GRuntimeLibThreads</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>ExePath</name>
-          <state>$PROJ_DIR$\BUILD\Exe</state>
-        </option>
-        <option>
-          <name>ObjPath</name>
-          <state>$PROJ_DIR$\BUILD\Obj</state>
-        </option>
-        <option>
-          <name>ListPath</name>
-          <state>$PROJ_DIR$\BUILD\List</state>
-        </option>
-        <option>
-          <name>GEndianMode</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>Input variant</name>
-          <version>3</version>
-          <state>1</state>
-        </option>
-        <option>
-          <name>Input description</name>
-          <state>Full formatting.</state>
-        </option>
-        <option>
-          <name>Output variant</name>
-          <version>2</version>
-          <state>3</state>
-        </option>
-        <option>
-          <name>Output description</name>
-          <state>No specifier a, A.</state>
-        </option>
-        <option>
-          <name>GOutputBinary</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGCoreOrChip</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelect</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>GRuntimeLibSelectSlave</name>
-          <version>0</version>
-          <state>2</state>
-        </option>
-        <option>
-          <name>RTDescription</name>
-          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-        </option>
-        <option>
-          <name>OGProductVersion</name>
-          <state>5.10.0.159</state>
-        </option>
-        <option>
-          <name>OGLastSavedByProductVersion</name>
-          <state>7.80.2.11970</state>
-        </option>
-        <option>
-          <name>GeneralEnableMisra</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraVerbose</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGChipSelectEditMenu</name>
-          <state>{{device.OGChipSelectEditMenu}}</state>
-        </option>
-        <option>
-          <name>GenLowLevelInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GEndianModeBE</name>
-          <state>1</state>
-        </option>
-        <option>
-          <name>OGBufferedTerminalOutput</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GenStdoutInterface</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules98</name>
-          <version>0</version>
-          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
-        </option>
-        <option>
-          <name>GeneralMisraVer</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>GeneralMisraRules04</name>
-          <version>0</version>
-          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
-        </option>
-        <option>
-          <name>RTConfigPath2</name>
-          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-        </option>
-        <option>
-          <name>GBECoreSlave</name>
-          <version>24</version>
-          <state>{{device.GBECoreSlave}}</state>
-        </option>
-        <option>
-          <name>OGUseCmsis</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>OGUseCmsisDspLib</name>
-          <state>0</state>
-        </option>
-        <option>
-          <name>CoreVariant</name>
-          <version>24</version>
-          <state>{{device.CoreVariant}}</state>
-        </option>
-        <option>
-          <name>GFPUDeviceSlave</name>
-          <state></state>
-        </option>
-        <option>
-          <name>FPU2</name>
-          <version>0</version>
-          <state>{{device.FPU2}}</state>
-        </option>
-        <option>
-          <name>NrRegs</name>
-          <version>0</version>
-          <state>{{device.NrRegs}}</state>
-        </option>
-        <option>
-          <name>NEON</name>
-          <state>{{device.NEON}}</state>
-        </option>
-        <option>
-          <name>GFPUCoreSlave2</name>
-          <version>24</version>
-          <state>{{device.GFPUCoreSlave2}}</state>
-        </option>
-      </data>
+            <data>
+                <version>24</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                  <name>ExePath</name>
+                  <state>$PROJ_DIR$\BUILD\Exe</state>
+                </option>
+                <option>
+                  <name>ObjPath</name>
+                  <state>$PROJ_DIR$\BUILD\Obj</state>
+                </option>
+                <option>
+                  <name>ListPath</name>
+                  <state>$PROJ_DIR$\BUILD\List</state>
+                </option>
+                <option>
+                  <name>GEndianMode</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>Input variant</name>
+                  <version>3</version>
+                  <state>1</state>
+                </option>
+                <option>
+                  <name>Input description</name>
+                  <state>Full formatting.</state>
+                </option>
+                <option>
+                  <name>Output variant</name>
+                  <version>2</version>
+                  <state>3</state>
+                </option>
+                <option>
+                  <name>Output description</name>
+                  <state>No specifier a, A.</state>
+                </option>
+                <option>
+                  <name>GOutputBinary</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>OGCoreOrChip</name>
+                  <state>1</state>
+                </option>
+                <option>
+                  <name>GRuntimeLibSelect</name>
+                  <version>0</version>
+                  <state>2</state>
+                </option>
+                <option>
+                  <name>GRuntimeLibSelectSlave</name>
+                  <version>0</version>
+                  <state>2</state>
+                </option>
+                <option>
+                  <name>RTDescription</name>
+                  <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+                </option>
+                <option>
+                  <name>OGProductVersion</name>
+                  <state>5.10.0.159</state>
+                </option>
+                <option>
+                  <name>OGLastSavedByProductVersion</name>
+                  <state>7.80.2.11970</state>
+                </option>
+                <option>
+                  <name>GeneralEnableMisra</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>GeneralMisraVerbose</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>OGChipSelectEditMenu</name>
+                  <state>{{device.OGChipSelectEditMenu}}</state>
+                </option>
+                <option>
+                  <name>GenLowLevelInterface</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>GEndianModeBE</name>
+                  <state>1</state>
+                </option>
+                <option>
+                  <name>OGBufferedTerminalOutput</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>GenStdoutInterface</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>GeneralMisraRules98</name>
+                  <version>0</version>
+                  <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                  <name>GeneralMisraVer</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>GeneralMisraRules04</name>
+                  <version>0</version>
+                  <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                  <name>RTConfigPath2</name>
+                  <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+                </option>
+                <option>
+                  <name>GBECoreSlave</name>
+                  <version>24</version>
+                  <state>{{device.GBECoreSlave}}</state>
+                </option>
+                <option>
+                  <name>OGUseCmsis</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>OGUseCmsisDspLib</name>
+                  <state>0</state>
+                </option>
+                <option>
+                  <name>CoreVariant</name>
+                  <version>24</version>
+                  <state>{{device.CoreVariant}}</state>
+                </option>
+                <option>
+                  <name>GFPUDeviceSlave</name>
+                  <state></state>
+                </option>
+                <option>
+                  <name>FPU2</name>
+                  <version>0</version>
+                  <state>{{device.FPU2}}</state>
+                </option>
+                <option>
+                  <name>NrRegs</name>
+                  <version>0</version>
+                  <state>{{device.NrRegs}}</state>
+                </option>
+                <option>
+                  <name>NEON</name>
+                  <state>{{device.NEON}}</state>
+                </option>
+                <option>
+                  <name>GFPUCoreSlave2</name>
+                  <version>24</version>
+                  <state>{{device.GFPUCoreSlave2}}</state>
+                </option>
+            </data>
 		</settings>
 		<settings>
 			<name>ICCARM</name>
@@ -265,9 +265,9 @@
 				</option>
 				<option>
 					<name>IExtraOptions</name>
-					{% for flag in c_flags %}
+					{% for flag in c_flags -%}
 					<state>{{flag}}</state>
-					{% endfor %}
+					{% endfor -%}
 				</option>
 				<option>
 					<name>CCLangConformance</name>
@@ -315,9 +315,9 @@
 				</option>
 				<option>
 					<name>CCIncludePath2</name>
-					{% for file in include_paths %}
+					{% for file in include_paths -%}
 					<state>{{file}}</state>
-					{% endfor %}
+					{% endfor -%}
 				</option>
 				<option>
 					<name>CCStdIncCheck</name>
@@ -583,9 +583,9 @@
 				</option>
 				<option>
 					<name>AExtraOptionsV2</name>
-					{% for flag in asm_flags %}
-					<state>{{flag}}</state>
-					{% endfor %}
+					{% for flag in asm_flags -%}
+					<state>{{flag|escape}}</state>
+					{% endfor -%}
 				</option>
 				<option>
 					<name>AsmNoLiteralPool</name>
@@ -765,9 +765,9 @@
 				</option>
 				<option>
 					<name>IlinkExtraOptions</name>
-					{% for flag in ld_flags %}
+					{% for flag in ld_flags -%}
 					<state>{{flag}}</state>
-					{% endfor %}
+					{% endfor -%}
 				</option>
 				<option>
 					<name>IlinkLowLevelInterfaceSlave</name>
@@ -963,14 +963,12 @@
 			<data></data>
 		</settings>
 	</configuration>
-	{% for group in groups %}
-	<group>
-	    <name>{{group.name}}</name>
-	    {% for file in group.files %}
-	    <file>
-	        <name>{{file}}</name>
-	    </file>
-	    {% endfor %}
-	</group>
-	{% endfor %}
+	{% for group in groups -%}
+        <group>
+            <name>{{group.name}}</name>
+            {% for file in group.files -%}
+            <file> <name>{{file}}</name> </file>
+            {% endfor -%}
+        </group>
+	{% endfor -%}
 </project>
--- a/export/iar/iar_definitions.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/iar/iar_definitions.json	Tue Sep 25 13:43:09 2018 -0500
@@ -1,10 +1,22 @@
 {
+    "STM32L443RC": {
+        "OGChipSelectEditMenu": "STM32L443RC\tST STM32L443RC"
+    },
+    "STM32L433RC": {
+        "OGChipSelectEditMenu": "STM32L433RC\tST STM32L433RC"
+    },
+    "STM32L496AG": {
+        "OGChipSelectEditMenu": "STM32L496AG\tST STM32L496AG"
+    },
     "STM32L496ZG": {
         "OGChipSelectEditMenu": "STM32L496ZG\tST STM32L496ZG"
     },
     "STM32L476VG": {
         "OGChipSelectEditMenu": "STM32L476VG\tST STM32L476VG"
     },
+    "STM32L475VG": {
+        "OGChipSelectEditMenu": "STM32L475VG\tST STM32L475VG"
+    },
     "LPC11U24FBD48/401": {
         "OGChipSelectEditMenu": "LPC11U24FBD64_401\tNXP LPC11U24FBD64_401"
     },
@@ -45,8 +57,9 @@
         "OGChipSelectEditMenu": "STM32F070RB\tST STM32F070RB"
     },
     "MK22DN512xxx5": {
-        "OGChipSelectEditMenu": "MK22DN512xxx5\tNXP MK22DN512xxx5"
+        "OGChipSelectEditMenu": "MK22FN512xxx12\tFreescale MK22FN512xxx12"
     },
+
     "MK24FN1M0xxx12": {
         "OGChipSelectEditMenu": "MK24FN1M0xxx12\tNXP MK24FN1M0xxx12"
     },
@@ -77,7 +90,7 @@
     "LPC54114J256BD64": {
         "OGChipSelectEditMenu": "LPC54114J256_M4\tNXP LPC54114J256_M4"
     },
-    "LPC54618J512ET180": {
+    "LPC54628J512ET180": {
         "OGChipSelectEditMenu": "LPC54618J512\tNXP LPC54618J512"
     },
     "STM32F072RB": {
@@ -104,6 +117,9 @@
     "STM32F303RE": {
         "OGChipSelectEditMenu": "STM32F303xE\tST STM32F303xE"
     },
+    "STM32L151CC": {
+        "OGChipSelectEditMenu": "STM32L151CC\tST STM32L151CC"
+    },
     "STM32L152RE": {
         "OGChipSelectEditMenu": "STM32L152xE\tST STM32L152xE"
     },
@@ -139,9 +155,6 @@
         "FPU2": 7,
         "NrRegs": 1
     },
-    "MKL43Z256xxx4": {
-        "OGChipSelectEditMenu": "MKL43Z256xxx4\tFreescale MKL43Z256xxx4"
-    },
     "LPC812M101JDH20": {
         "OGChipSelectEditMenu": "LPC812M101\tNXP LPC812M101"
     },
@@ -170,9 +183,6 @@
     "STM32F446ZE": {
         "OGChipSelectEditMenu": "STM32F446ZE\tST STM32F446ZE"
     },
-    "MK22DN512xxx5": {
-        "OGChipSelectEditMenu": "MK22FN512xxx12\tFreescale MK22FN512xxx12"
-    },
     "STM32F303K8": {
         "OGChipSelectEditMenu": "STM32F303x8\tST STM32F303x8"
     },
@@ -194,7 +204,7 @@
     "STM32F091RC": {
         "OGChipSelectEditMenu": "STM32F091RC\tST STM32F091RC"
     },
-    "RZ_A1H": {
+    "R7S72100": {
         "OGChipSelectEditMenu": "R7S721001\tRenesas R7S721001",
         "CoreVariant": 37,
         "GFPUCoreSlave": 37,
@@ -208,6 +218,13 @@
         "GBECoreSlave": 37,
         "NEON":1
     },
+    "R7S72103": {
+        "OGChipSelectEditMenu": "R7S721030\tRenesas R7S721030",
+        "CoreVariant": 37,
+        "GFPUCoreSlave": 37,
+        "GBECoreSlave": 37,
+        "NEON":1
+    },
     "MKL05Z32xxx4": {
         "OGChipSelectEditMenu": "MKL05Z32xxx4\tFreescale MKL05Z32xxx4"
     },
@@ -245,5 +262,21 @@
         "OGChipSelectEditMenu": "TMPM066FWUG\tToshiba TMPM066FWUG",
         "GFPUCoreSlave": 21,
         "GBECoreSlave": 21
+    },
+    "ADuCM3029": {
+        "OGChipSelectEditMenu": "ADuCM3029\tAnalogDevices ADuCM3029"
+    },
+    "ADuCM4050": {
+        "OGChipSelectEditMenu": "ADuCM4050\tAnalogDevices ADuCM4050"
+    },
+    "TMPM46BF10FG":{
+        "OGChipSelectEditMenu": "TMPM46BF10FG\tToshiba TMPM46BF10FG",
+        "GFPUCoreSlave": 21,
+        "GBECoreSlave": 21
+    },
+    "TMPM3H6FWFG":{
+        "OGChipSelectEditMenu": "TMPM3H6FWFG\tToshiba TMPM3H6FWFG",
+        "GFPUCoreSlave": 24,
+        "GBECoreSlave": 24
     }
 }
--- a/export/kds/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/kds/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,6 +15,7 @@
 limitations under the License.
 """
 from os.path import splitext, basename
+from os import remove
 
 from tools.export.exporters import Exporter, deprecated_exporter
 
@@ -32,7 +33,7 @@
 
     def generate(self):
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
             libraries.append(l[3:])
 
@@ -47,3 +48,7 @@
         self.gen_file('kds/%s_project.tmpl' % self.target.lower(), ctx, '.project')
         self.gen_file('kds/%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject')
         self.gen_file('kds/launch.tmpl', ctx, '%s.launch' % self.project_name)
+
+    @staticmethod
+    def clean(project_name):
+        remove('%s.launch' % project_name)
--- a/export/lpcxpresso/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/lpcxpresso/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -44,7 +44,7 @@
 
     def generate(self):
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
             libraries.append(l[3:])
 
--- a/export/makefile/Makefile.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/makefile/Makefile.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -75,11 +75,11 @@
 {%- endif %}
 {%- block additional_executables -%}{%- endblock %}
 
-{% for flag in c_flags %}C_FLAGS += {{flag}}
+{% for flag in c_flags %}C_FLAGS += {{shell_escape(flag)}}
 {% endfor %}
-{% for flag in cxx_flags %}CXX_FLAGS += {{flag}}
+{% for flag in cxx_flags %}CXX_FLAGS += {{shell_escape(flag)}}
 {% endfor %}
-{% for flag in asm_flags %}ASM_FLAGS += {{flag}}
+{% for flag in asm_flags %}ASM_FLAGS += {{shell_escape(flag)}}
 {% endfor %}
 
 LD_FLAGS :={%- block ld_flags -%} {{ld_flags|join(" ")}} {% endblock %}
--- a/export/makefile/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/makefile/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,9 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, absolute_import
+from builtins import str
+
 from os.path import splitext, basename, relpath, join, abspath, dirname,\
     exists
 from os import remove
@@ -21,10 +24,20 @@
 from subprocess import check_output, CalledProcessError, Popen, PIPE
 import shutil
 from jinja2.exceptions import TemplateNotFound
+from tools.resources import FileType
 from tools.export.exporters import Exporter, apply_supported_whitelist
 from tools.utils import NotSupportedException
 from tools.targets import TARGET_MAP
 
+SHELL_ESCAPE_TABLE = {
+    "(": "\(",
+    ")": "\)",
+}
+
+
+def shell_escape(string):
+    return "".join(SHELL_ESCAPE_TABLE.get(char, char) for char in string)
+
 
 class Makefile(Exporter):
     """Generic Makefile template that mimics the behavior of the python build
@@ -66,7 +79,7 @@
                           self.resources.cpp_sources]
 
         libraries = [self.prepare_lib(basename(lib)) for lib
-                     in self.resources.libraries]
+                     in self.libraries]
         sys_libs = [self.prepare_sys_lib(lib) for lib
                     in self.toolchain.sys_libs]
 
@@ -84,28 +97,24 @@
                       if (basename(dirname(dirname(self.export_dir)))
                           == "projectfiles")
                       else [".."]),
-            'cc_cmd': " ".join(["\'" + part + "\'" for part
-                                in ([basename(self.toolchain.cc[0])] +
-                                    self.toolchain.cc[1:])]),
-            'cppc_cmd': " ".join(["\'" + part + "\'" for part
-                                  in ([basename(self.toolchain.cppc[0])] +
-                                      self.toolchain.cppc[1:])]),
-            'asm_cmd': " ".join(["\'" + part + "\'" for part
-                                in ([basename(self.toolchain.asm[0])] +
-                                    self.toolchain.asm[1:])]),
-            'ld_cmd': "\'" + basename(self.toolchain.ld[0]) + "\'",
-            'elf2bin_cmd': "\'" + basename(self.toolchain.elf2bin) + "\'",
+            'cc_cmd': basename(self.toolchain.cc[0]),
+            'cppc_cmd': basename(self.toolchain.cppc[0]),
+            'asm_cmd': basename(self.toolchain.asm[0]),
+            'ld_cmd': basename(self.toolchain.ld[0]),
+            'elf2bin_cmd': basename(self.toolchain.elf2bin),
             'link_script_ext': self.toolchain.LINKER_EXT,
             'link_script_option': self.LINK_SCRIPT_OPTION,
             'user_library_flag': self.USER_LIBRARY_FLAG,
             'needs_asm_preproc': self.PREPROCESS_ASM,
+            'shell_escape': shell_escape,
         }
 
         if hasattr(self.toolchain, "preproc"):
-            ctx['pp_cmd'] = " ".join(["\'" + part + "\'" for part
-                                      in ([basename(self.toolchain.preproc[0])] +
-                                          self.toolchain.preproc[1:] + 
-                                          self.toolchain.ld[1:])])
+            ctx['pp_cmd'] = " ".join(
+                [basename(self.toolchain.preproc[0])] +
+                self.toolchain.preproc[1:] +
+                self.toolchain.ld[1:]
+            )
         else:
             ctx['pp_cmd'] = None
 
@@ -121,6 +130,20 @@
                     'to_be_compiled']:
             ctx[key] = sorted(ctx[key])
         ctx.update(self.format_flags())
+        ctx['asm_flags'].extend(self.toolchain.asm[1:])
+        ctx['c_flags'].extend(self.toolchain.cc[1:])
+        ctx['cxx_flags'].extend(self.toolchain.cppc[1:])
+
+        # Add the virtual path the the include option in the ASM flags
+        new_asm_flags = []
+        for flag in ctx['asm_flags']:
+            if flag.startswith('-I'):
+                new_asm_flags.append("-I{}/{}".format(ctx['vpath'][0], flag[2:]))
+            elif flag.startswith('--preinclude='):
+                new_asm_flags.append("--preinclude={}/{}".format(ctx['vpath'][0], flag[13:]))
+            else:
+                new_asm_flags.append(flag)
+        ctx['asm_flags'] = new_asm_flags
 
         for templatefile in \
             ['makefile/%s_%s.tmpl' % (self.TEMPLATE,
@@ -140,8 +163,8 @@
     def format_flags(self):
         """Format toolchain flags for Makefile"""
         flags = {}
-        for k, v in self.flags.iteritems():
-            if k in ['asm_flags', 'c_flags', 'cxx_flags']:
+        for k, v in self.flags.items():
+            if k in ['c_flags', 'cxx_flags']:
                 flags[k] = map(lambda x: x.replace('"', '\\"'), v)
             else:
                 flags[k] = v
@@ -149,6 +172,15 @@
         return flags
 
     @staticmethod
+    def clean(_):
+        remove("Makefile")
+        # legacy .build directory cleaned if exists
+        if exists('.build'):
+            shutil.rmtree('.build')
+        if exists('BUILD'):
+            shutil.rmtree('BUILD')
+
+    @staticmethod
     def build(project_name, log_name="build_log.txt", cleanup=True):
         """ Build Make project """
         # > Make -j
@@ -169,7 +201,7 @@
         else:
             out_string += "FAILURE"
 
-        print out_string
+        print(out_string)
 
         if log_name:
             # Write the output to the log file
@@ -178,13 +210,8 @@
 
         # Cleanup the exported and built files
         if cleanup:
-            remove("Makefile")
             remove(log_name)
-            # legacy .build directory cleaned if exists
-            if exists('.build'):
-                shutil.rmtree('.build')
-            if exists('BUILD'):
-                shutil.rmtree('BUILD')
+            Makefile.clean(project_name)
 
         if ret_code != 0:
             # Seems like something went wrong.
@@ -228,10 +255,12 @@
 
     def generate(self):
         if self.resources.linker_script:
+            sct_file = self.resources.get_file_refs(FileType.LD_SCRIPT)[-1]
             new_script = self.toolchain.correct_scatter_shebang(
-                self.resources.linker_script)
-            if new_script is not self.resources.linker_script:
-                self.resources.linker_script = new_script
+                sct_file.path, join("..", dirname(sct_file.name)))
+            if new_script is not sct_file:
+                self.resources.add_files_to_type(
+                    FileType.LD_SCRIPT, [new_script])
                 self.generated_files.append(new_script)
         return super(Arm, self).generate()
 
--- a/export/mcuxpresso/LPC546XX_cproject.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/mcuxpresso/LPC546XX_cproject.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -2,8 +2,8 @@
 
 {% block cpu_config %}&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
 &lt;TargetConfig&gt;&#13;
-&lt;Properties property_3="NXP" property_4="LPC54608J512" property_count="5" version="70200"/&gt;&#13;
-&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC54608J512" name="LPC54608J512"&gt;&lt;chip&gt;&lt;name&gt;LPC54608J512&lt;/name&gt;&#13;
+&lt;Properties property_3="NXP" property_4="LPC54628J512" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC54628J512" name="LPC54628J512"&gt;&lt;chip&gt;&lt;name&gt;LPC54628J512&lt;/name&gt;&#13;
 &lt;family&gt;LPC546xx&lt;/family&gt;&#13;
 &lt;vendor&gt;NXP&lt;/vendor&gt;&#13;
 &lt;memory can_program="true" id="Flash" is_ro="true" size="512" type="Flash"/&gt;&#13;
@@ -97,10 +97,10 @@
 &lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
 &lt;family&gt;Cortex-M&lt;/family&gt;&#13;
 &lt;/processor&gt;&#13;
-&lt;link href="LPC54608_internal_peripheral.xml" show="embed" type="simple"/&gt;&#13;
+&lt;link href="LPC54628_internal_peripheral.xml" show="embed" type="simple"/&gt;&#13;
 &lt;/info&gt;&#13;
 &lt;/infoList&gt;&#13;
 &lt;/TargetConfig&gt;{% endblock %}
 
-{% block sdk_name %}SDK_2.x_LPCXpresso54608{% endblock %}
-{% block sdk_version %}2.2.0{% endblock %}
+{% block sdk_name %}SDK_2.x_LPCXpresso54628{% endblock %}
+{% block sdk_version %}2.3.0{% endblock %}
--- a/export/mcuxpresso/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/mcuxpresso/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -22,6 +22,8 @@
 Based on GNU ARM Eclipse Exporter from Liviu Ionescu <ilg@livius.net>
 modified for MCUXpresso by Johannes Stratmann <jojos62@online.de>
 """
+from __future__ import print_function, absolute_import
+from builtins import str
 
 import copy
 import tempfile
@@ -39,9 +41,6 @@
 from tools.build_api import prepare_toolchain
 
 
-# =============================================================================
-
-
 POST_BINARY_WHITELIST = set([
     "TEENSY3_1Code.binary_hook",
     "MCU_NRF51Code.binary_hook",
@@ -73,22 +72,17 @@
         if not self.resources.linker_script:
             raise NotSupportedException("No linker script found.")
 
-        print
-        print 'Create a GNU ARM Eclipse C++ managed project'
-        print 'Project name: {0}'.format(self.project_name)
-        print 'Target: {0}'.format(self.toolchain.target.name)
-        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
-
         self.resources.win_to_unix()
 
         # TODO: use some logger to display additional info if verbose
 
-        self.libraries = []
+        libraries = []
         # print 'libraries'
         # print self.resources.libraries
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
-            self.libraries.append(l[3:])
+            libraries.append(l[3:])
+        self.libraries = libraries
 
         self.system_libraries = [
             'stdc++', 'supc++', 'm', 'c', 'gcc', 'nosys'
@@ -115,16 +109,13 @@
 
         self.include_path = [
             self.filter_dot(s) for s in self.resources.inc_dirs]
-        print 'Include folders: {0}'.format(len(self.include_path))
 
         self.as_defines = self.toolchain.get_symbols(True)
         self.c_defines = self.toolchain.get_symbols()
         self.cpp_defines = self.c_defines
-        print 'Symbols: {0}'.format(len(self.c_defines))
 
         self.ld_script = self.filter_dot(
             self.resources.linker_script)
-        print 'Linker script: {0}'.format(self.ld_script)
 
         self.options = {}
         profile_ids.remove('develop')
@@ -143,7 +134,6 @@
             opts['name'] = opts['id'].capitalize()
 
             print
-            print 'Build configuration: {0}'.format(opts['name'])
 
             profile = profiles[id]
 
@@ -159,12 +149,6 @@
 
             flags = self.toolchain_flags(toolchain)
 
-            print 'Common flags:', ' '.join(flags['common_flags'])
-            print 'C++ flags:', ' '.join(flags['cxx_flags'])
-            print 'C flags:', ' '.join(flags['c_flags'])
-            print 'ASM flags:', ' '.join(flags['asm_flags'])
-            print 'Linker flags:', ' '.join(flags['ld_flags'])
-
             # Most GNU ARM Eclipse options have a parent,
             # either debug or release.
             if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
@@ -224,10 +208,22 @@
                       '.cproject', trim_blocks=True, lstrip_blocks=True)
         self.gen_file('mcuxpresso/makefile.targets.tmpl', jinja_ctx,
                       'makefile.targets', trim_blocks=True, lstrip_blocks=True)
-        self.gen_file('mcuxpresso/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+        self.gen_file_nonoverwrite('mcuxpresso/mbedignore.tmpl', jinja_ctx,
+                                   '.mbedignore')
+
+        print('Done. Import the \'{0}\' project in MCUXpresso.'.format(
+            self.project_name))
 
-        print
-        print 'Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name)
+    @staticmethod
+    def clean(_):
+        remove('.project')
+        remove('.cproject')
+        if exists('Debug'):
+            shutil.rmtree('Debug')
+        if exists('Release'):
+            shutil.rmtree('Release')
+        if exists('makefile.targets'):
+            remove('makefile.targets')
 
     # override
     @staticmethod
@@ -284,7 +280,7 @@
         else:
             ret_string = "FAILURE: build returned %s \n" % ret_code
 
-        print "%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string)
+        print("%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string))
 
         if log_name:
             # Write the output to the log file
@@ -298,14 +294,7 @@
         if cleanup:
             if exists(log_name):
                 remove(log_name)
-            remove('.project')
-            remove('.cproject')
-            if exists('Debug'):
-                shutil.rmtree('Debug')
-            if exists('Release'):
-                shutil.rmtree('Release')
-            if exists('makefile.targets'):
-                remove('makefile.targets')
+            MCUXpresso.clean(project_name)
 
         # Always remove the temporary folder.
         if exists(tmp_folder):
@@ -341,14 +330,6 @@
         # Make a copy of the flags, to be one by one removed after processing.
         flags = copy.deepcopy(flags_in)
 
-        if False:
-            print
-            print 'common_flags', flags['common_flags']
-            print 'asm_flags', flags['asm_flags']
-            print 'c_flags', flags['c_flags']
-            print 'cxx_flags', flags['cxx_flags']
-            print 'ld_flags', flags['ld_flags']
-
         # Initialise the 'last resort' options where all unrecognised
         # options will be collected.
         opts['as']['other'] = ''
@@ -728,15 +709,3 @@
         opts['c']['other'] = opts['c']['other'].strip()
         opts['cpp']['other'] = opts['cpp']['other'].strip()
         opts['ld']['other'] = opts['ld']['other'].strip()
-
-        if False:
-            print
-            print opts
-
-            print
-            print 'common_flags', flags['common_flags']
-            print 'asm_flags', flags['asm_flags']
-            print 'c_flags', flags['c_flags']
-            print 'cxx_flags', flags['cxx_flags']
-            print 'ld_flags', flags['ld_flags']
-
--- a/export/mcuxpresso/makefile.targets.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/mcuxpresso/makefile.targets.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -6,7 +6,7 @@
 	$(RM) $(EXECUTABLES) {{name}}.* linker-script-*.ld
 	-@echo ' '
 
-{% for config, data in options.iteritems() %}
+{% for config, data in options.items() %}
 linker-script-{{config}}.ld: ../{{ld_script}}
 	{{data.cpp_cmd}} {{data.ld.other}} $< -o $@
 {{name}}.elf: linker-script-{{config}}.ld
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/nb/Makefile.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,139 @@
+#
+#  There exist several targets which are by default empty and which can be 
+#  used for execution of your targets. These targets are usually executed 
+#  before and after some main targets. They are: 
+#
+#     .build-pre:              called before 'build' target
+#     .build-post:             called after 'build' target
+#     .clean-pre:              called before 'clean' target
+#     .clean-post:             called after 'clean' target
+#     .clobber-pre:            called before 'clobber' target
+#     .clobber-post:           called after 'clobber' target
+#     .all-pre:                called before 'all' target
+#     .all-post:               called after 'all' target
+#     .help-pre:               called before 'help' target
+#     .help-post:              called after 'help' target
+#
+#  Targets beginning with '.' are not intended to be called on their own.
+#
+#  Main targets can be executed directly, and they are:
+#  
+#     build                    build a specific configuration
+#     clean                    remove built files from a configuration
+#     clobber                  remove all built files
+#     all                      build all configurations
+#     help                     print help mesage
+#  
+#  Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and
+#  .help-impl are implemented in nbproject/makefile-impl.mk.
+#
+#  Available make variables:
+#
+#     CND_BASEDIR                base directory for relative paths
+#     CND_DISTDIR                default top distribution directory (build artifacts)
+#     CND_BUILDDIR               default top build directory (object files, ...)
+#     CONF                       name of current configuration
+#     CND_PLATFORM_${CONF}       platform name (current configuration)
+#     CND_ARTIFACT_DIR_${CONF}   directory of build artifact (current configuration)
+#     CND_ARTIFACT_NAME_${CONF}  name of build artifact (current configuration)
+#     CND_ARTIFACT_PATH_${CONF}  path to build artifact (current configuration)
+#     CND_PACKAGE_DIR_${CONF}    directory of package (current configuration)
+#     CND_PACKAGE_NAME_${CONF}   name of package (current configuration)
+#     CND_PACKAGE_PATH_${CONF}   path to package (current configuration)
+#
+# NOCDDL
+
+
+# Environment 
+MKDIR=mkdir
+CP=cp
+CCADMIN=CCadmin
+
+BUILDDIR = BUILD
+PLATFORM = {{target}}
+ELF2BIN = '{{elf2bin_cmd}}'
+TARGET = ${CND_DISTDIR}/${CONF}/${CND_PLATFORM}/{{name}}
+
+
+# build
+build: .build-post
+
+.build-pre:
+# Add your pre 'build' code here...
+
+.build-post: .build-impl
+# Add your post 'build' code here...
+	$(ELF2BIN) -O binary ${TARGET}.elf ${TARGET}.bin
+	+@echo "===== bin file ready to flash: $(TARGET).bin ====="
+	$(ELF2BIN) -O ihex ${TARGET}.elf ${TARGET}.hex
+	cp ${TARGET}.* ${CND_BUILDDIR}/${CONF}/${CND_PLATFORM}
+
+# clean
+clean: .clean-post
+
+.clean-pre:
+# Add your pre 'clean' code here...
+
+.clean-post: .clean-impl
+# Add your post 'clean' code here...
+
+
+# clobber
+clobber: .clobber-post
+
+.clobber-pre:
+# Add your pre 'clobber' code here...
+
+.clobber-post: .clobber-impl
+# Add your post 'clobber' code here...
+
+
+# all
+all: .all-post
+
+.all-pre:
+# Add your pre 'all' code here...
+
+.all-post: .all-impl
+# Add your post 'all' code here...
+
+
+# build tests
+build-tests: .build-tests-post
+
+.build-tests-pre:
+# Add your pre 'build-tests' code here...
+
+.build-tests-post: .build-tests-impl
+# Add your post 'build-tests' code here...
+
+
+# run tests
+test: .test-post
+
+.test-pre: build-tests
+# Add your pre 'test' code here...
+
+.test-post: .test-impl
+# Add your post 'test' code here...
+
+
+# help
+help: .help-post
+
+.help-pre:
+# Add your pre 'help' code here...
+
+.help-post: .help-impl
+# Add your post 'help' code here...
+
+
+
+# include project implementation makefile
+include nbproject/Makefile-impl.mk
+
+# include project make variables
+include nbproject/Makefile-variables.mk
+
+CND_BUILDDIR = ${BUILDDIR}
+CND_PLATFORM = ${PLATFORM}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/nb/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,358 @@
+from __future__ import print_function, absolute_import
+from builtins import str
+
+import os
+import copy
+import shutil
+
+from os.path import relpath, join, exists, dirname, basename
+from os import makedirs, remove
+from json import load
+
+from tools.export.exporters import Exporter, apply_supported_whitelist
+from tools.targets import TARGET_MAP
+from tools.utils import NotSupportedException
+from tools.build_api import prepare_toolchain
+
+POST_BINARY_WHITELIST = set([
+    "TEENSY3_1Code.binary_hook",
+    "MCU_NRF51Code.binary_hook",
+    "LPCTargetCode.lpc_patch",
+    "LPC4088Code.binary_hook"
+])
+
+
+class GNUARMNetbeans(Exporter):
+    NAME = 'GNU ARM Netbeans'
+    TOOLCHAIN = 'GCC_ARM'
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        return apply_supported_whitelist(
+            cls.TOOLCHAIN, POST_BINARY_WHITELIST, target)
+
+    @staticmethod
+    def prepare_sys_lib(libname):
+        return "-l" + libname
+
+    @staticmethod
+    def get_defines_and_remove_from_flags(flags_in, str_key):
+        defines = []
+        flags_temp = copy.deepcopy(flags_in)
+        for f in flags_temp[str_key]:
+            f = f.strip()
+            if f.startswith('-D'):
+                defines.append(f[2:])
+                flags_in[str_key].remove(f)
+
+        return defines
+
+    @staticmethod
+    def get_includes_and_remove_from_flags(flags_in, str_key):
+        includes = []
+        flags_temp = copy.deepcopy(flags_in)
+        next_is_include = False
+        for f in flags_temp[str_key]:
+            f = f.strip()
+            if next_is_include:
+                includes.append(f)
+                flags_in[str_key].remove(f)
+                next_is_include = False
+                continue
+            if f == "-include":
+                flags_in[str_key].remove(f)
+                next_is_include = True
+
+        return includes
+
+    @staticmethod
+    def get_c_std_and_remove_from_flag(flags_in, str_key):
+        comp_std = ''
+        c_std = {
+            'c90': 'c90', 'c89': 'c90', 'gnu90': 'gnu90', 'gnu89': 'gnu90',
+            'c99': 'c99', 'c9x': 'c99', 'gnu99': 'gnu99', 'gnu9x': 'gnu98',
+            'c11': 'c11', 'c1x': 'c11', 'gnu11': 'gnu11', 'gnu1x': 'gnu11'
+        }
+        cpp_std = {
+            'c++98': 'cpp98', 'c++03': 'cpp98',
+            'gnu++98': 'gnucpp98', 'gnu++03': 'gnucpp98',
+            'c++0x': 'cpp0x', 'gnu++0x': 'gnucpp0x',
+            'c++11': 'cpp11', 'gnu++11': 'gnucpp11',
+            'c++1y': 'cpp1y', 'gnu++1y': 'gnucpp1y',
+            'c++14': 'cpp14', 'gnu++14': 'gnucpp14',
+            'c++1z': 'cpp1z', 'gnu++1z': 'gnucpp1z',
+        }
+
+        flags_temp = copy.deepcopy(flags_in)
+        for f in flags_temp[str_key]:
+            f = f.strip()
+            if f.startswith('-std='):
+                comp_std = f[len('-std='):]
+                flags_in[str_key].remove(f)
+            elif f.startswith('-'):
+                std = f[len('-'):]
+                if std in c_std or std in cpp_std:
+                    comp_std = std
+                    flags_in[str_key].remove(f)
+        return comp_std
+
+    def validate_resources(self):
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+
+    def create_jinja_ctx(self):
+        self.options = {}
+        flags = {}
+        self.validate_resources()
+        # Convert all Backslashes to Forward Slashes
+        self.resources.win_to_unix()
+
+        self.ld_script = self.filter_dot(
+            self.resources.linker_script)
+
+        # Read in all profiles, we'll extract compiler options.
+        profiles = self.get_all_profiles()
+
+        profile_ids = [s.lower() for s in profiles]
+        profile_ids.sort()
+        for prof_id in profile_ids:
+            # There are 4 categories of options, a category common too
+            # all tools and a specific category for each of the tools.
+            opts = {}
+            opts['defines'] = {}
+            opts['common'] = {}
+            opts['as'] = {}
+            opts['c'] = {}
+            opts['cpp'] = {}
+            opts['ld'] = {}
+
+            opts['id'] = prof_id
+            opts['name'] = opts['id'].capitalize()
+
+            profile = profiles[prof_id]
+
+            # A small hack, do not bother with src_path again,
+            # pass an empty string to avoid crashing.
+            src_paths = ['']
+            target_name = self.toolchain.target.name
+
+            toolchain = prepare_toolchain(
+                src_paths, "", target_name, self.TOOLCHAIN, build_profile=[profile])
+
+            flags = self.toolchain_flags(toolchain)
+
+            opts['defines'] = self.get_defines_and_remove_from_flags(flags, 'common_flags')
+            opts['forced_includes'] = self.get_includes_and_remove_from_flags(flags, 'common_flags')
+            opts['common'] = flags['common_flags']
+            opts['as'] = flags['asm_flags']
+            opts['c'] = flags['c_flags']
+            opts['cpp'] = flags['cxx_flags']
+            opts['ld'] = flags['ld_flags']
+
+            self.options[prof_id] = opts
+
+        sources = []  # list of strings
+
+        forced_includes = self.get_includes_and_remove_from_flags(flags, 'c_flags')
+        forced_includes += self.get_includes_and_remove_from_flags(flags, 'cxx_flags')
+
+        # Remove Duplicates
+        forced_includes = list(set(forced_includes))
+
+        c_std = self.get_c_std_and_remove_from_flag(flags, 'c_flags')
+        cpp_std = self.get_c_std_and_remove_from_flag(flags, 'cxx_flags')
+
+        # Make one list of all resources
+        for r_type in ['c_sources', 's_sources', 'cpp_sources']:
+            sources.extend(getattr(self.resources, r_type))
+
+        # Remove all leading './'
+        c_sources = [self.filter_dot(field) for field in self.resources.c_sources]
+        cpp_sources = [self.filter_dot(field) for field in self.resources.cpp_sources]
+        s_sources = [self.filter_dot(field) for field in self.resources.s_sources]
+        headers = [self.filter_dot(field) for field in self.resources.headers]
+        sources = [self.filter_dot(field) for field in sources]
+        include_paths = [self.filter_dot(field) for field in self.resources.inc_dirs]
+
+        sys_libs = [self.prepare_sys_lib(lib) for lib
+                    in self.toolchain.sys_libs]
+        preproc = " ".join([basename(self.toolchain.preproc[0])] +
+                           self.toolchain.preproc[1:] +
+                           self.toolchain.ld[1:])
+
+        if 'nbproject' in include_paths:
+            include_paths.remove('nbproject')
+
+        jinja_ctx = {
+            'name': self.project_name,
+            'target': self.toolchain.target.name,
+            'elf_location': join('BUILD', self.project_name) + '.elf',
+            'c_symbols': self.toolchain.get_symbols(),
+            'asm_symbols': self.toolchain.get_symbols(True),
+            'c_flags': flags['c_flags'],
+            'cxx_flags': flags['cxx_flags'],
+            'ld_flags': self.flags['ld_flags'],
+            'asm_flags': self.flags['asm_flags'],
+            'common_flags': self.flags['common_flags'],
+            'include_paths': include_paths,
+            'forced_includes': forced_includes,
+            'c_sources': c_sources,
+            'cpp_sources': cpp_sources,
+            's_sources': s_sources,
+            'headers': headers,
+            'headers_folder': self.get_netbeans_file_list(sorted(headers)),
+            'sources_folder': self.get_netbeans_file_list(sorted(sources)),
+            'options': self.options,
+            'c_std': self.get_netbeans_c_std(c_std),
+            'cpp_std': self.get_netbeans_cpp_std(cpp_std),
+            'linker_script': self.ld_script,
+            'linker_libs': sys_libs,
+            'pp_cmd': preproc,
+            'cc_cmd': self.toolchain.cc[0],
+            'cppc_cmd': self.toolchain.cppc[0],
+            'asm_cmd': self.toolchain.asm[0],
+            'ld_cmd': self.toolchain.ld[0],
+            'elf2bin_cmd': self.toolchain.elf2bin
+        }
+        return jinja_ctx
+
+    def generate(self):
+        """Generate Makefile, configurations.xml & project.xml Netbeans project file
+        """
+        jinja_ctx = self.create_jinja_ctx()
+
+        if not exists(join(self.export_dir, 'nbproject')):
+            makedirs(join(self.export_dir, 'nbproject'))
+
+        self.gen_file('nb/configurations.tmpl', jinja_ctx, 'nbproject/configurations.xml')
+        self.gen_file('nb/project.tmpl', jinja_ctx, 'nbproject/project.xml')
+        self.gen_file_nonoverwrite('nb/mbedignore.tmpl', jinja_ctx,
+                                   '.mbedignore')
+        self.gen_file('nb/Makefile.tmpl', jinja_ctx, 'Makefile')
+
+        print('Done. Import the \'{0}\' project in Netbeans.'.format(self.project_name))
+
+    @staticmethod
+    def clean(_):
+        shutil.rmtree("nbproject")
+        remove("Makefile")
+
+    # -------------------------------------------------------------------------
+
+    @staticmethod
+    def filter_dot(str_in):
+        """
+        Remove the './' prefix, if present.
+        This function assumes that resources.win_to_unix()
+        replaced all windows backslashes with slashes.
+        """
+        if str_in is None:
+            return None
+        if str_in[:2] == './':
+            return str_in[2:]
+        return str_in
+
+    # -------------------------------------------------------------------------
+
+    @staticmethod
+    def get_all_profiles():
+        tools_path = dirname(dirname(dirname(__file__)))
+        file_names = [join(tools_path, "profiles", fn) for fn in os.listdir(
+            join(tools_path, "profiles")) if fn.endswith(".json")]
+
+        profiles = {}
+
+        for fn in file_names:
+            content = load(open(fn))
+            profile_name = basename(fn).replace(".json", "")
+            profiles[profile_name] = content
+
+        return profiles
+
+    @staticmethod
+    def get_netbeans_file_list(file_list):
+        cur_dir = ''
+        prev_dir = ''
+        output = []
+        folder_count = 1
+        dir_depth = 0
+        for item in file_list:
+            cur_dir = os.path.dirname(item)
+            dir_temp = os.path.normpath(cur_dir)
+            prev_dir_temp = os.path.normpath(prev_dir)
+            dir_list = dir_temp.split(os.sep)
+            prev_dir_list = prev_dir_temp.split(os.sep)
+            dir_depth = len(dir_list)
+
+            # Current File is in Directory: Compare the given dir with previous Dir
+            if cur_dir and prev_dir != cur_dir:
+                # evaluate all matched items (from current and previous list)
+                matched = []
+                # Compare the Element in Previous Dir with the Elements in Current Dir
+                # and add the equal Elements to the match-List
+                for elem_prev_dir, elem_cur_dir in zip(prev_dir_list, dir_list):
+                    if elem_prev_dir == elem_cur_dir:
+                        matched.append(elem_cur_dir)
+
+                # calculate difference between matched and length
+                diff = dir_depth - len(matched)
+
+                # if previous dir was not root
+                if prev_dir != '':
+                    # if the elements count is not equal we calculate the difference
+                    if len(dir_list) != len(prev_dir_list):
+                        dir_depth_prev = len(prev_dir_list)
+                        delta = dir_depth_prev - len(matched)
+
+                        for i in range(dir_depth_prev - delta, dir_depth_prev):
+                            output.append('</logicalFolder>')
+
+                    # if the elements count is equal, we subtract the matched length from the total length
+                    else:
+                        for i in range(len(matched), len(dir_list)):
+                            output.append('</logicalFolder>')
+
+                for i in range(dir_depth - diff, dir_depth):
+                    output.append('<logicalFolder name="f' + str(folder_count) + '" displayName="' + str(
+                        dir_list[i]) + '" projectFiles="true">')
+                    folder_count += 1
+
+            # Current File is in root
+            else:
+                # Close Tag if we are in root and the previous dir wasn't
+                if cur_dir == '' and prev_dir != '':
+                    for i in range(0, len(prev_dir_list)):
+                        output.append('</logicalFolder>')
+
+            # Save the Current Dir
+            prev_dir = cur_dir
+            output.append('<itemPath>' + str(item) + '</itemPath>')
+
+        if cur_dir != '':
+            # close all open tags
+            output.append('</logicalFolder>' * dir_depth)
+
+        return output
+
+    @staticmethod
+    def get_netbeans_c_std(c_std):
+        c_std_netbeans = 0
+        if '89' in c_std:
+            c_std_netbeans = 2
+        elif '99' in c_std:
+            c_std_netbeans = 3
+        elif '11' in c_std:
+            c_std_netbeans = 10
+        return c_std_netbeans
+
+    @staticmethod
+    def get_netbeans_cpp_std(cpp_std):
+        cpp_std_netbeans = 0
+        if '98' in cpp_std:
+            cpp_std_netbeans = 4
+        elif '11' in cpp_std:
+            cpp_std_netbeans = 8
+        elif '14' in cpp_std:
+            cpp_std_netbeans = 11
+        return cpp_std_netbeans
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/nb/configurations.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<configurationDescriptor version="100">
+    <logicalFolder name="root" displayName="root" projectFiles="true" kind="ROOT">
+        <logicalFolder name="HeaderFiles"
+                       displayName="Header Files"
+                       projectFiles="true">
+            {% for header in headers_folder -%}
+            {{ header }}
+            {% endfor %}
+        </logicalFolder>
+        <logicalFolder name="LinkerScript"
+                       displayName="Linker Files"
+                       projectFiles="true">
+            <itemPath>{{ linker_script }}</itemPath>
+        </logicalFolder>
+        <logicalFolder name="ResourceFiles"
+                       displayName="Resource Files"
+                       projectFiles="true">
+        </logicalFolder>
+        <logicalFolder name="SourceFiles"
+                       displayName="Source Files"
+                       projectFiles="true">
+            {% for source in sources_folder -%}
+            {{ source }}
+            {% endfor %}
+        </logicalFolder>
+        <logicalFolder name="OtherFiles"
+                       displayName="Other Files"
+                       projectFiles="true">
+        </logicalFolder>
+        <logicalFolder name="TestFiles"
+                       displayName="Test Files"
+                       projectFiles="false"
+                       kind="TEST_LOGICAL_FOLDER">
+        </logicalFolder>
+        <logicalFolder name="ExternalFiles"
+                       displayName="Important Files"
+                       projectFiles="false"
+                       kind="IMPORTANT_FILES_FOLDER">
+            <itemPath>Makefile</itemPath>
+        </logicalFolder>
+    </logicalFolder>
+    <sourceFolderFilter>^(nbproject)$</sourceFolderFilter>
+    <sourceRootList>
+        <Elem>.</Elem>
+    </sourceRootList>
+    <projectmakefile>Makefile</projectmakefile>
+    <confs>
+        {% for id in options -%}
+        {% set opts = options[id] %}
+        <conf name="{{opts['id']}}" type="1">
+            <toolsSet>
+                <compilerSet>default</compilerSet>
+                <dependencyChecking>true</dependencyChecking>
+                <rebuildPropChanged>false</rebuildPropChanged>
+            </toolsSet>
+            <compileType>
+                <cTool>
+                    <standard>{{ c_std }}</standard>
+                    <incDir>
+                        {% for inc_dir in include_paths -%}{% if inc_dir -%}
+                        <pElem>{{ inc_dir }}</pElem>
+                        {% endif -%}
+                        {% endfor -%}
+                    </incDir>
+                    <incFile>
+                        {% for inc_file in forced_includes -%}
+                        <pElem>{{ inc_file }}</pElem>
+                        {% endfor -%}
+                    </incFile>
+                    <commandLine>{%- for flag in c_flags -%}{{ flag+" "}}{%- endfor -%}
+                        {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%}
+                    </commandLine>
+                    <preprocessorList>
+                        {% for item in opts['defines'] -%}
+                        <Elem>{{ item }}</Elem>
+                        {% endfor -%}
+                        {% for symbol in c_symbols -%}
+                        <Elem>{{ symbol }}</Elem>
+                        {% endfor -%}
+                    </preprocessorList>
+                    <commandlineTool>{{cc_cmd}}</commandlineTool>
+                </cTool>
+                <ccTool>
+                    <standard>{{ cpp_std }}</standard>
+                    <incDir>
+                        {% for inc_dir in include_paths -%}{% if inc_dir -%}
+                        <pElem>{{ inc_dir }}</pElem>
+                        {% endif -%}
+                        {% endfor -%}
+                    </incDir>
+                    <incFile>
+                        {% for inc_file in forced_includes -%}
+                        <pElem>{{ inc_file }}</pElem>
+                        {% endfor -%}
+                    </incFile>
+                    <commandLine>{%- for flag in cxx_flags -%}{{ flag+" "}}{%- endfor -%}
+                        {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%}
+                    </commandLine>
+                    <preprocessorList>
+                        {% for item in opts['defines'] -%}
+                        <Elem>{{ item }}</Elem>
+                        {% endfor -%}
+                        {% for symbol in c_symbols -%}
+                        <Elem>{{ symbol }}</Elem>
+                        {% endfor -%}
+                    </preprocessorList>
+                    <commandlineTool>{{cppc_cmd}}</commandlineTool>
+                </ccTool>
+                <fortranCompilerTool>
+                    <developmentMode>5</developmentMode>
+                </fortranCompilerTool>
+                <asmTool>
+                    <developmentMode>5</developmentMode>
+                    <incDir>
+                        {% for inc_dir in include_paths -%}{% if inc_dir -%}
+                        <pElem>{{ inc_dir }}</pElem>
+                        {% endif -%}
+                        {% endfor -%}
+                    </incDir>
+                    <incFile>
+                        {% for inc_file in forced_includes -%}
+                        <pElem>{{ inc_file }}</pElem>
+                        {% endfor -%}
+                    </incFile>
+                    <commandLine>{%- for flag in asm_flags -%}{{ flag+" "}}{%- endfor -%}
+                        {%- for item in opts['common'] -%}{{ item+" "}}{%- endfor -%}
+                    </commandLine>
+                    <preprocessorList>
+                        {% for symbol in asm_symbols -%}
+                        <Elem>{{ symbol }}</Elem>
+                        {% endfor -%}
+                    </preprocessorList>
+                    <commandlineTool>{{asm_cmd}}</commandlineTool>
+                </asmTool>
+                <linkerTool>
+                    <output>${CND_DISTDIR}/${CND_CONF}/{{target}}/{{name}}.elf</output>
+                    <additionalDep>${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld</additionalDep>
+                    <commandlineTool>{{ld_cmd}}</commandlineTool>
+                    <commandLine>-T ${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld {%- for symbol in opts['ld'] -%}{{" "+symbol}}{%- endfor -%} {%- for item in linker_libs -%}{{" "+item}}{%- endfor -%} </commandLine>
+                </linkerTool>
+            </compileType>
+            {% for h in headers -%}
+            <item path="{{h}}" ex="false" tool="3" flavor2="0">
+            </item>
+            {% endfor -%}
+            {% for s in c_sources -%}
+            <item path="{{s}}" ex="false" tool="0" flavor2="3">
+                <cTool flags="1">
+                </cTool>
+            </item>
+            {% endfor -%}
+            {% for s in cpp_sources -%}
+            <item path="{{s}}" ex="false" tool="1" flavor2="0">
+                <ccTool flags="0">
+                </ccTool>
+            </item>
+            {% endfor -%}
+            {% for s in s_sources -%}
+            <item path="{{s}}" ex="false" tool="0" flavor2="0">
+            </item>
+            {% endfor -%}
+            <item path="{{linker_script }}" ex="false" tool="3" flavor2="0">
+                <customTool>
+                    <customToolCommandline>{{pp_cmd}} -o $@ $&lt;</customToolCommandline>
+                    <customToolDescription>Create ELF File using Link Script</customToolDescription>
+                    <customToolOutputs>${CND_BUILDDIR}/${CND_CONF}/{{target}}/.link_script.ld</customToolOutputs>
+                </customTool>
+            </item>
+            <item path="/nbproject/private/c_standard_headers_indexer.c" ex="true" tool="0" flavor2="0">
+            </item>
+            <item path="/nbproject/private/c_standard_headers_indexer.cpp" ex="true" tool="1" flavor2="0">
+            </item>
+        </conf>
+        {% endfor -%}
+    </confs>
+</configurationDescriptor>
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/nb/mbedignore.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,2 @@
+nbproject/private/*.cpp
+nbproject/private/*.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/nb/project.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project xmlns="http://www.netbeans.org/ns/project/1">
+    <type>org.netbeans.modules.cnd.makeproject</type>
+    <configuration>
+        <data xmlns="http://www.netbeans.org/ns/make-project/1">
+            <name>{{name}}</name>
+            <c-extensions>c</c-extensions>
+            <cpp-extensions>cpp</cpp-extensions>
+            <header-extensions>h</header-extensions>
+            <sourceEncoding>UTF-8</sourceEncoding>
+            <make-dep-projects/>
+            <sourceRootList/>
+            <confList>
+                <confElem>
+                    <name>Debug</name>
+                    <type>1</type>
+                </confElem>
+                <confElem>
+                    <name>Release</name>
+                    <type>1</type>
+                </confElem>
+            </confList>
+            <formatting>
+                <project-formatting-style>false</project-formatting-style>
+            </formatting>
+        </data>
+    </configuration>
+</project>
--- a/export/qtcreator/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/qtcreator/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,6 +15,7 @@
 limitations under the License.
 """
 from os.path import splitext, basename
+from os import remove
 from tools.targets import TARGET_MAP
 from tools.export.exporters import Exporter
 from tools.export.makefile import GccArm
@@ -63,3 +64,8 @@
 
         # finally, generate the Makefile
         super(QtCreator, self).generate()
+
+    @staticmethod
+    def clean(project_name):
+        for ext in ['creator', 'files', 'includes', 'config']:
+            remove("%s.%s" % (project_name, ext))
--- a/export/simplicity/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/simplicity/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,6 +15,7 @@
 limitations under the License.
 """
 from os.path import split,splitext, basename
+from os import remove
 
 from tools.export.exporters import Exporter, deprecated_exporter
 
@@ -143,7 +144,7 @@
                         main_files.append(source)
 
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             l, _ = splitext(basename(lib))
             if l[3:] not in EXCLUDED_LIBS:
                 libraries.append(l[3:])
@@ -194,3 +195,7 @@
         '''
 
         self.gen_file('simplicity/slsproj.tmpl', ctx, '%s.slsproj' % self.project_name)
+
+    @staticmethod
+    def clean(project_name):
+        remove('%s.slsproj' % project_name)
--- a/export/sw4stm32/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/sw4stm32/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,12 +14,16 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, absolute_import
+from builtins import str
 
-from os.path import splitext, basename, join
+from os.path import splitext, basename, relpath, join
+import shutil
 from tools.utils import mkdir
 from tools.export.gnuarmeclipse import GNUARMEclipse
 from tools.export.gnuarmeclipse import UID
 from tools.build_api import prepare_toolchain
+from tools.targets import TARGET_MAP
 from sys import flags, platform
 
 # Global random number generator instance.
@@ -99,6 +103,11 @@
             'name': 'DISCO-L072CZ-LRWAN1',
             'mcuId': 'STM32L072CZTx'
         },
+        'MTB_MURATA_ABZ':
+        {
+            'name': 'MTB-MURATA-ABZ',
+            'mcuId': 'STM32L0x2xZ'
+        },
         'DISCO_L475VG_IOT01A':
         {
             'name': 'STM32L475G-DISCO',
@@ -189,6 +198,11 @@
             'name': 'NUCLEO-F411RE',
             'mcuId': 'STM32F411RETx'
         },
+        'NUCLEO_F413ZH':
+        {
+            'name': 'NUCLEO-F413ZH',
+            'mcuId': 'STM32F413ZHTx'
+        },
         'NUCLEO_F429ZI':
         {
             'name': 'NUCLEO-F429ZI',
@@ -234,6 +248,11 @@
             'name': 'NUCLEO-L073RZ',
             'mcuId': 'STM32L073RZTx'
         },
+        'MTB_RAK811':
+        {
+            'name': 'MTB-RAK-811',
+            'mcuId': 'STM32L151CBUxA'
+        },
         'NUCLEO_L152RE':
         {
             'name': 'NUCLEO-L152RE',
@@ -244,6 +263,11 @@
             'name': 'NUCLEO-L432KC',
             'mcuId': 'STM32L432KCUx'
         },
+        'MTB_ADV_WISE_1510':
+        {
+            'name': 'MTB-ADV-WISE-1510',
+            'mcuId': 'STM32L443xC'
+        },
         'NUCLEO_L476RG':
         {
             'name': 'NUCLEO-L476RG',
@@ -258,10 +282,21 @@
         {
             'name': 'NUCLEO-L496ZG',
             'mcuId': 'STM32L496ZGTx'
-        },        
+        },
+        'NUCLEO_L496ZG_P':
+        {
+            'name': 'NUCLEO-L496ZG',
+            'mcuId': 'STM32L496ZGTx'
+        },
     }
 
-    TARGETS = BOARDS.keys()
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        target_supported = bool(set(target.resolution_order_names)
+                                .intersection(set(cls.BOARDS.keys())))
+        toolchain_supported = cls.TOOLCHAIN in target.supported_toolchains
+        return target_supported and toolchain_supported
 
     def __gen_dir(self, dir_name):
         """
@@ -391,17 +426,15 @@
         if not self.resources.linker_script:
             raise NotSupportedException("No linker script found.")
 
-        print ('\nCreate a System Workbench for STM32 managed project')
-        print ('Project name: {0}'.format(self.project_name))
-        print ('Target:       {0}'.format(self.toolchain.target.name))
-        print ('Toolchain:    {0}'.format(self.TOOLCHAIN) + '\n')
+        print('\nCreate a System Workbench for STM32 managed project')
+        print('Project name: {0}'.format(self.project_name))
+        print('Target:       {0}'.format(self.toolchain.target.name))
+        print('Toolchain:    {0}'.format(self.TOOLCHAIN) + '\n')
 
         self.resources.win_to_unix()
 
-        config_header = self.filter_dot(self.toolchain.get_config_header())
-
         libraries = []
-        for lib in self.resources.libraries:
+        for lib in self.libraries:
             library, _ = splitext(basename(lib))
             libraries.append(library[3:])
 
@@ -415,19 +448,18 @@
         self.c_defines = [s.replace('"', '&quot;')
                           for s in self.toolchain.get_symbols()]
         self.cpp_defines = self.c_defines
-        print 'Symbols: {0}'.format(len(self.c_defines))
 
         self.include_path = []
         for s in self.resources.inc_dirs:
             self.include_path.append("../" + self.filter_dot(s))
-        print ('Include folders: {0}'.format(len(self.include_path)))
+        print('Include folders: {0}'.format(len(self.include_path)))
 
         self.compute_exclusions()
 
-        print ('Exclude folders: {0}'.format(len(self.excluded_folders)))
+        print('Exclude folders: {0}'.format(len(self.excluded_folders)))
 
         ld_script = self.filter_dot(self.resources.linker_script)
-        print ('Linker script:   {0}'.format(ld_script))
+        print('Linker script:   {0}'.format(ld_script))
 
         lib_dirs = [self.filter_dot(s) for s in self.resources.lib_dirs]
 
@@ -444,9 +476,6 @@
             opts['id'] = id
             opts['name'] = opts['id'].capitalize()
 
-            # TODO: Add prints to log or console in verbose mode.
-            #print ('\nBuild configuration: {0}'.format(opts['name']))
-
             profile = profiles[id]
 
             # A small hack, do not bother with src_path again,
@@ -460,13 +489,6 @@
 
             flags = self.toolchain_flags(toolchain)
 
-            # TODO: Add prints to log or console in verbose mode.
-            # print 'Common flags:', ' '.join(flags['common_flags'])
-            # print 'C++ flags:', ' '.join(flags['cxx_flags'])
-            # print 'C flags:', ' '.join(flags['c_flags'])
-            # print 'ASM flags:', ' '.join(flags['asm_flags'])
-            # print 'Linker flags:', ' '.join(flags['ld_flags'])
-
             # Most GNU ARM Eclipse options have a parent,
             # either debug or release.
             if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
@@ -505,7 +527,7 @@
             'name': self.project_name,
             'platform': platform,
             'include_paths': self.include_path,
-            'config_header': config_header,
+            'config_header': self.config_header_ref.name,
             'exclude_paths': '|'.join(self.excluded_folders),
             'ld_script': ld_script,
             'library_paths': lib_dirs,
@@ -529,3 +551,7 @@
                       'makefile.targets', trim_blocks=True, lstrip_blocks=True)
         self.gen_file('sw4stm32/launch.tmpl', ctx, self.project_name +
                       ' ' + options['debug']['name'] + '.launch')
+
+    @staticmethod
+    def clean(_):
+        shutil.rmtree(".settings")
--- a/export/sw4stm32/cproject_common.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/sw4stm32/cproject_common.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -28,7 +28,7 @@
 							<option id="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{u.id}}" name="Floating-point ABI" superClass="fr.ac6.managedbuild.option.gnu.cross.floatabi" value="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{opts['common']['arm.target.fpu.abi']}}" valueType="enumerated"/>
 							{% endif %}
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross.{{u.id}}" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
-							<builder buildPath="${workspace_loc:/{{name}}}/{{opts['name']}}" id="fr.ac6.managedbuild.builder.gnu.cross.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="fr.ac6.managedbuild.builder.gnu.cross"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/{{opts['name']}}" id="fr.ac6.managedbuild.builder.gnu.cross.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="fr.ac6.managedbuild.builder.gnu.cross"/>
 							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{opts['uid']['tool_c_compiler']}}" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler">
 								{% if cfg_id == 'debug' %}
 								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.more" valueType="enumerated"/>
--- a/export/sw4stm32/makefile.targets.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/sw4stm32/makefile.targets.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -3,11 +3,11 @@
 PREPROC_CMD ?= {{cpp_cmd}}
 
 ldclean:
-{% for config, opts in options.iteritems() %}
+{% for config, opts in options.items() %}
 	$(RM) {{opts['ld']['script']}}
 {% endfor %}
 
-{% for config, opts in options.iteritems() %}
+{% for config, opts in options.items() %}
 {{opts['ld']['script']}}: ../{{ld_script}}
 	$(PREPROC_CMD) {{opts.ld.other}} $< -o $@
 
--- a/export/uvision/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/uvision/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,5 +1,8 @@
+from __future__ import print_function, absolute_import
+from builtins import str
+
 import os
-from os.path import sep, normpath, join, exists
+from os.path import normpath, exists, dirname
 import ntpath
 import copy
 from collections import namedtuple
@@ -7,13 +10,11 @@
 from subprocess import Popen, PIPE
 import re
 
-from tools.arm_pack_manager import Cache
+from tools.resources import FileType
 from tools.targets import TARGET_MAP
-from tools.export.exporters import Exporter, apply_supported_whitelist
+from tools.export.exporters import Exporter
 from tools.export.cmsis import DeviceCMSIS
 
-cache_d = False
-
 
 class DeviceUvision(DeviceCMSIS):
     """Uvision Device class, inherits CMSIS Device class
@@ -31,19 +32,23 @@
 
     def uv_debug(self):
         """Return a namedtuple of information about uvision debug settings"""
-        UVDebug = namedtuple('UVDebug',['bin_loc','core_flag', 'key'])
+        UVDebug = namedtuple('UVDebug', ['bin_loc', 'core_flag', 'key'])
 
         # CortexMXn => pCMX
         cpu = self.core.replace("Cortex-", "C")
         cpu = cpu.replace("+", "")
         cpu = cpu.replace("F", "")
+        cpu = cpu.replace("-NS", "")
         cpu_flag = "p"+cpu
 
         # Locations found in Keil_v5/TOOLS.INI
-        debuggers = {"st-link": ('STLink\\ST-LINKIII-KEIL_SWO.dll', 'ST-LINKIII-KEIL_SWO'),
-                     "j-link":('Segger\\JL2CM3.dll', 'JL2CM3'),
-                     "cmsis-dap":('BIN\\CMSIS_AGDI.dll', 'CMSIS_AGDI'),
-                     "nulink":('NULink\\Nu_Link.dll','Nu_Link')}
+        debuggers = {
+            "st-link": ('STLink\\ST-LINKIII-KEIL_SWO.dll',
+                        'ST-LINKIII-KEIL_SWO'),
+            "j-link": ('Segger\\JL2CM3.dll', 'JL2CM3'),
+            "cmsis-dap": ('BIN\\CMSIS_AGDI.dll', 'CMSIS_AGDI'),
+            "nulink": ('NULink\\Nu_Link.dll', 'Nu_Link')
+        }
         res = debuggers[self.debug.lower()]
         binary = res[0]
         key = res[1]
@@ -55,7 +60,7 @@
         S = SW/JTAG Clock ID
         C = CPU index in JTAG chain
         P = Access Port
-        For the Options for Target -> Debug tab -> settings -> "Flash" tab in the dialog:
+        For the Options for Target -> Debug -> settings -> "Flash" dialog:
         FD = RAM Start for Flash Functions
         FC = RAM Size for Flash Functions
         FN = Number of Flash types
@@ -64,44 +69,55 @@
         FL = Size of the Flash Device
         FP = Full path to the Device algorithm (RTE)
 
-        Necessary to flash some targets. Info gathered from algorithms field of pdsc file.
+        Necessary to flash some targets.
         '''
         fl_count = 0
+
         def get_mem_no_x(mem_str):
             mem_reg = "\dx(\w+)"
             m = re.search(mem_reg, mem_str)
             return m.group(1) if m else None
 
-        RAMS = [(get_mem_no_x(info["start"]), get_mem_no_x(info["size"]))
-                for mem, info in self.target_info["memory"].items() if "RAM" in mem]
-        format_str = "UL2CM3(-S0 -C0 -P0 -FD{ramstart}"+" -FC{ramsize} "+"-FN{num_algos} {extra_flags})"
+        RAMS = [
+            (get_mem_no_x(info["start"]), get_mem_no_x(info["size"]))
+            for mem, info in self.target_info["memory"].items() if "RAM" in mem
+        ]
+        format_str = (
+            "UL2CM3(-S0 -C0 -P0 -FD{ramstart}"
+            " -FC{ramsize} -FN{num_algos} {extra_flags})"
+        )
         ramstart = ''
-        #Default according to Keil developer
+        # Default according to Keil developer
         ramsize = '1000'
-        if len(RAMS)>=1:
+        if len(RAMS) >= 1:
             ramstart = RAMS[0][0]
         extra_flags = []
         for name, info in self.target_info["algorithm"].items():
             if not name or not info:
                 continue
-            if int(info["default"])==0:
+            if int(info["default"]) == 0:
                 continue
             name_reg = "\w*/([\w_]+)\.flm"
             m = re.search(name_reg, name.lower())
             fl_name = m.group(1) if m else None
             name_flag = "-FF" + str(fl_count) + fl_name
 
-            start, size = get_mem_no_x(info["start"]), get_mem_no_x(info["size"])
-            rom_start_flag = "-FS"+str(fl_count)+str(start)
+            start = get_mem_no_x(info["start"])
+            size = get_mem_no_x(info["size"])
+            rom_start_flag = "-FS" + str(fl_count) + str(start)
             rom_size_flag = "-FL" + str(fl_count) + str(size)
 
             if info["ramstart"] is not None and info["ramsize"] is not None:
                 ramstart = get_mem_no_x(info["ramstart"])
                 ramsize = get_mem_no_x(info["ramsize"])
 
-            path_flag = "-FP" + str(fl_count) + "($$Device:"+self.dname+"$"+name+")"
+            path_flag = "-FP{}($$Device:{}${})".format(
+                str(fl_count), self.dname, name
+            )
 
-            extra_flags.extend([name_flag, rom_start_flag, rom_size_flag, path_flag])
+            extra_flags.extend([
+                name_flag, rom_start_flag, rom_size_flag, path_flag
+            ])
             fl_count += 1
 
         extra = " ".join(extra_flags)
@@ -117,8 +133,6 @@
     project file (.uvprojx).
     The needed information can be viewed in uvision.tmpl
     """
-    NAME = 'uvision5'
-    TOOLCHAIN = 'ARM'
 
     POST_BINARY_WHITELIST = set([
         "MCU_NRF51Code.binary_hook",
@@ -130,14 +144,7 @@
         "NCS36510TargetCode.ncs36510_addfib"
     ])
 
-    @classmethod
-    def is_target_supported(cls, target_name):
-        target = TARGET_MAP[target_name]
-        return apply_supported_whitelist(
-            cls.TOOLCHAIN, cls.POST_BINARY_WHITELIST, target) and\
-            DeviceCMSIS.check_supported(target_name)
-
-    #File associations within .uvprojx file
+    # File associations within .uvprojx file
     file_types = {'.cpp': 8, '.c': 1, '.s': 2,
                   '.obj': 3, '.o': 3, '.lib': 4,
                   '.ar': 4, '.h': 5, '.hpp': 5, '.sct': 4}
@@ -155,8 +162,8 @@
         </File>
         """
         for loc in files:
-            #Encapsulates the information necessary for template entry above
-            UVFile = namedtuple('UVFile', ['type','loc','name'])
+            # Encapsulates the information necessary for template entry above
+            UVFile = namedtuple('UVFile', ['type', 'loc', 'name'])
             _, ext = os.path.splitext(loc)
             if ext.lower() in self.file_types:
                 type = self.file_types[ext.lower()]
@@ -166,22 +173,40 @@
     def format_flags(self):
         """Format toolchain flags for Uvision"""
         flags = copy.deepcopy(self.flags)
-        # to be preprocessed with armcc
         asm_flag_string = (
             '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' +
-            ",".join(filter(lambda f: f.startswith("-D"), flags['asm_flags'])))
+            ",".join("-D{}".format(s) for s in
+                     self.toolchain.get_symbols(for_asm=True)))
         flags['asm_flags'] = asm_flag_string
-        # All non-asm flags are in one template field
-        c_flags = list(set(flags['c_flags'] + flags['cxx_flags'] +flags['common_flags']))
-        ld_flags = list(set(flags['ld_flags'] ))
-        # These flags are in template to be set by user i n IDE
-        template = ["--no_vla", "--cpp", "--c99"]
-        # Flag is invalid if set in template
-        # Optimizations are also set in the template
-        invalid_flag = lambda x: x in template or re.match("-O(\d|time)", x) 
-        flags['c_flags'] = [flag.replace('"','\\"') for flag in c_flags if not invalid_flag(flag)]
-        flags['c_flags'] = " ".join(flags['c_flags'])
-        flags['ld_flags'] = " ".join(flags['ld_flags'])
+
+        config_header = self.config_header_ref
+        config_option = self.toolchain.get_config_option(config_header.name)
+        c_flags = set(
+            flags['c_flags'] + flags['cxx_flags'] + flags['common_flags']
+        )
+        in_template = set(
+            ["--no_vla", "--cpp", "--c99", "-MMD"] + config_option
+        )
+
+        def valid_flag(x):
+            return (
+                x not in in_template and
+                not x.startswith("-O") and
+                not x.startswith("-std") and
+                not x.startswith("-D")
+            )
+
+        def is_define(s):
+            return s.startswith("-D") and "(" not in s
+
+        flags['c_flags'] = " ".join(
+            f.replace('"', '\\"') for f in c_flags if valid_flag(f)
+        )
+        flags['c_flags'] += " "
+        flags['c_flags'] += " ".join(config_option)
+        flags['c_defines'] = " ".join(f[2:].replace('"', '\\"')
+                                      for f in c_flags if is_define(f))
+        flags['ld_flags'] = " ".join(set(flags['ld_flags']))
         return flags
 
     def format_src(self, srcs):
@@ -189,7 +214,7 @@
         grouped = self.group_project_files(srcs)
         for group, files in grouped.items():
             grouped[group] = sorted(list(self.uv_files(files)),
-                                    key=lambda (_, __, name): name.lower())
+                                    key=lambda tuple: tuple[2].lower())
         return grouped
 
     @staticmethod
@@ -204,38 +229,54 @@
 
     def generate(self):
         """Generate the .uvproj file"""
-        cache = Cache(True, False)
-        if cache_d:
-            cache.cache_descriptors()
-
-        srcs = self.resources.headers + self.resources.s_sources + \
-               self.resources.c_sources + self.resources.cpp_sources + \
-               self.resources.objects + self.resources.libraries
+        srcs = (
+            self.resources.headers + self.resources.s_sources +
+            self.resources.c_sources + self.resources.cpp_sources +
+            self.resources.objects + self.libraries
+        )
         ctx = {
             'name': self.project_name,
             # project_files => dict of generators - file group to generator of
             # UVFile tuples defined above
-            'project_files': sorted(list(self.format_src(srcs).iteritems()),
-                                    key=lambda (group, _): group.lower()),
-            'linker_script':self.toolchain.correct_scatter_shebang(
-                self.resources.linker_script),
-            'include_paths': '; '.join(self.resources.inc_dirs).encode('utf-8'),
+            'project_files': sorted(list(self.format_src(srcs).items()),
+                                    key=lambda tuple: tuple[0].lower()),
+            'include_paths': ';'.join(self.filter_dot(d) for d in
+                                      self.resources.inc_dirs).encode('utf-8'),
             'device': DeviceUvision(self.target),
         }
-        if ctx['linker_script'] is not self.resources.linker_script:
+        sct_name, sct_path = self.resources.get_file_refs(
+            FileType.LD_SCRIPT)[0]
+        ctx['linker_script'] = self.toolchain.correct_scatter_shebang(
+            sct_path, dirname(sct_name))
+        if ctx['linker_script'] != sct_path:
             self.generated_files.append(ctx['linker_script'])
-        core = ctx['device'].core
-        ctx['cputype'] = core.rstrip("FD")
-        if core.endswith("FD"):
+        ctx['cputype'] = ctx['device'].core.rstrip("FD").replace("-NS", "")
+        if ctx['device'].core.endswith("FD"):
             ctx['fpu_setting'] = 3
-        elif core.endswith("F"):
+        elif ctx['device'].core.endswith("F"):
             ctx['fpu_setting'] = 2
         else:
             ctx['fpu_setting'] = 1
-        ctx['fputype'] = self.format_fpu(core)
+        ctx['fputype'] = self.format_fpu(ctx['device'].core)
+        ctx['armc6'] = int(self.TOOLCHAIN is 'ARMC6')
+        ctx['toolchain_name'] = self.TOOLCHAIN_NAME
         ctx.update(self.format_flags())
-        self.gen_file('uvision/uvision.tmpl', ctx, self.project_name+".uvprojx")
-        self.gen_file('uvision/uvision_debug.tmpl', ctx, self.project_name + ".uvoptx")
+        self.gen_file(
+            'uvision/uvision.tmpl', ctx, self.project_name + ".uvprojx"
+        )
+        self.gen_file(
+            'uvision/uvision_debug.tmpl', ctx, self.project_name + ".uvoptx"
+        )
+
+    @staticmethod
+    def clean(project_name):
+        os.remove(project_name + ".uvprojx")
+        os.remove(project_name + ".uvoptx")
+        # legacy .build directory cleaned if exists
+        if exists('.build'):
+            shutil.rmtree('.build')
+        if exists('BUILD'):
+            shutil.rmtree('BUILD')
 
     @staticmethod
     def build(project_name, log_name='build_log.txt', cleanup=True):
@@ -251,18 +292,12 @@
 
         # Print the log file to stdout
         with open(log_name, 'r') as f:
-            print f.read()
+            print(f.read())
 
         # Cleanup the exported and built files
         if cleanup:
             os.remove(log_name)
-            os.remove(project_name+".uvprojx")
-            os.remove(project_name+".uvoptx")
-            # legacy .build directory cleaned if exists
-            if exists('.build'):
-                shutil.rmtree('.build')
-            if exists('BUILD'):
-                shutil.rmtree('BUILD')
+            Uvision.clean(project_name)
 
         # Returns 0 upon success, 1 upon a warning, and neither upon an error
         if ret_code != 0 and ret_code != 1:
@@ -270,3 +305,49 @@
             return -1
         else:
             return 0
+
+
+class UvisionArmc5(Uvision):
+    NAME = 'uvision5-armc5'
+    TOOLCHAIN = 'ARM'
+    TOOLCHAIN_NAME = ''
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        if not (set(target.supported_toolchains).intersection(
+                set(["ARM", "uARM"]))):
+            return False
+        if not DeviceCMSIS.check_supported(target_name):
+            return False
+        if "Cortex-A" in target.core:
+            return False
+        if not hasattr(target, "post_binary_hook"):
+            return True
+        if target.post_binary_hook['function'] in cls.POST_BINARY_WHITELIST:
+            return True
+        else:
+            return False
+
+
+class UvisionArmc6(Uvision):
+    NAME = 'uvision5-armc6'
+    TOOLCHAIN = 'ARMC6'
+    TOOLCHAIN_NAME = '6070000::V6.7::.\ARMCLANG'
+
+    @classmethod
+    def is_target_supported(cls, target_name):
+        target = TARGET_MAP[target_name]
+        if not (set(target.supported_toolchains).intersection(
+                set(["ARMC6"]))):
+            return False
+        if not DeviceCMSIS.check_supported(target_name):
+            return False
+        if "Cortex-A" in target.core:
+            return False
+        if not hasattr(target, "post_binary_hook"):
+            return True
+        if target.post_binary_hook['function'] in cls.POST_BINARY_WHITELIST:
+            return True
+        else:
+            return False
--- a/export/uvision/uvision.tmpl	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/uvision/uvision.tmpl	Tue Sep 25 13:43:09 2018 -0500
@@ -10,6 +10,10 @@
       <TargetName>{{name}}</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
+      {% if toolchain_name %}
+      <pCCUsed>{{toolchain_name}}</pCCUsed>
+      {% endif %}
+      <uAC6>{{armc6}}</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>{{device.dname}}</Device>
@@ -213,7 +217,7 @@
             <AdsLsxf>1</AdsLsxf>
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"{{device.core.replace("D","").replace("F","")}}"</AdsCpuType>
+            <AdsCpuType>"{{cputype}}"</AdsCpuType>
             <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
@@ -354,7 +358,7 @@
             <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
+            <OneElfS>1</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
@@ -365,8 +369,8 @@
             <uSurpInc>0</uSurpInc>
             <uC99>1</uC99>
             <useXO>0</useXO>
-            <v6Lang>1</v6Lang>
-            <v6LangP>1</v6LangP>
+            <v6Lang>4</v6Lang>
+            <v6LangP>2</v6LangP>
             <vShortEn>1</vShortEn>
             <vShortWch>1</vShortWch>
             <v6Lto>0</v6Lto>
@@ -374,7 +378,7 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>{{c_flags}}</MiscControls>
-              <Define></Define>
+              <Define>{{c_defines}}</Define>
               <Undefine></Undefine>
               <IncludePath>{{include_paths}}</IncludePath>
             </VariousControls>
@@ -394,7 +398,7 @@
               <MiscControls>{{asm_flags}}</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath>{{include_paths}}</IncludePath>
+              <IncludePath></IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -434,5 +438,4 @@
       </Groups>
     </Target>
   </Targets>
-
 </Project>
--- a/export/vscode/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/export/vscode/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -12,9 +12,12 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
+from __future__ import print_function, absolute_import
+from builtins import str
+
 
 from os.path import join, exists, realpath, relpath, basename, isfile, splitext
-from os import makedirs, listdir
+from os import makedirs, listdir, remove, rmdir
 import json
 
 from tools.export.makefile import Makefile, GccArm, Armc5, IAR
@@ -40,12 +43,13 @@
         if not exists(join(self.export_dir, '.vscode')):
             makedirs(join(self.export_dir, '.vscode'))
 
-        self.gen_file('vscode/tasks.tmpl', ctx,
-                      join('.vscode', 'tasks.json'))
-        self.gen_file('vscode/launch.tmpl', ctx,
-                      join('.vscode', 'launch.json'))
-        self.gen_file('vscode/settings.tmpl', ctx,
-                      join('.vscode', 'settings.json'))
+        config_files = ['launch', 'settings', 'tasks']
+        for file in config_files:
+            if not exists('.vscode/%s.json' % file):
+                self.gen_file('vscode/%s.tmpl' % file, ctx,
+                              '.vscode/%s.json' % file)
+            else:
+                print('Keeping existing %s.json' % file)
 
         # So.... I want all .h and .hpp files in self.resources.inc_dirs
         all_directories = []
@@ -82,6 +86,11 @@
         with open(join(self.export_dir, '.vscode', 'c_cpp_properties.json'), 'w') as outfile:
             json.dump(cpp_props, outfile, indent=4, separators=(',', ': '))
 
+    @staticmethod
+    def clean(_):
+        for f in ['launch', 'settings', 'tasts', 'c_cpp_properties']:
+            remove(".vscode/%s.json" % f)
+        rmdir(".vscode")
 
 class VSCodeGcc(VSCode, GccArm):
     LOAD_EXE = True
--- a/get_config.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/get_config.py	Tue Sep 25 13:43:09 2018 -0500
@@ -16,9 +16,9 @@
 limitations under the License.
 
 """
+from __future__ import print_function
 import sys
-from os.path import isdir, abspath, dirname, join
-from os import _exit
+from os.path import abspath, dirname, join
 
 # Be sure that the tools directory is in the search path
 ROOT = abspath(join(dirname(__file__), ".."))
@@ -28,22 +28,23 @@
 from tools.options import get_default_options_parser
 from tools.options import extract_mcus
 from tools.build_api import get_config
-from config import Config
-from utils import argparse_filestring_type
-try:
-    import tools.private_settings as ps
-except:
-    ps = object()
+from tools.config import Config
+from tools.utils import argparse_filestring_type
 
 if __name__ == '__main__':
     # Parse Options
-    parser = get_default_options_parser(add_clean=False, add_options=False)
-    parser.add_argument("--source", dest="source_dir", type=argparse_filestring_type, required=True,
-                        default=[], help="The source (input) directory", action="append")
-    parser.add_argument("--prefix", dest="prefix", action="append",
-                      default=[], help="Restrict listing to parameters that have this prefix")
-    parser.add_argument("-v", "--verbose", action="store_true", dest="verbose",
-                      default=False, help="Verbose diagnostic output")
+    parser = get_default_options_parser(add_clean=False, add_options=False,
+                                        add_app_config=True)
+    parser.add_argument(
+        "--source", dest="source_dir", type=argparse_filestring_type,
+        required=True, default=[], help="The source (input) directory",
+        action="append")
+    parser.add_argument(
+        "--prefix", dest="prefix", action="append", default=[],
+        help="Restrict listing to parameters that have this prefix")
+    parser.add_argument(
+        "-v", "--verbose", action="store_true", dest="verbose", default=False,
+        help="Verbose diagnostic output")
 
     options = parser.parse_args()
 
@@ -52,41 +53,42 @@
         args_error(parser, "argument -m/--mcu is required")
     target = extract_mcus(parser, options)[0]
 
-    # Toolchain
-    if options.tool is None:
-        args_error(parser, "argument -t/--toolchain is required")
-    toolchain = options.tool[0]
-
     options.prefix = options.prefix or [""]
 
     try:
-        params, macros, features = get_config(options.source_dir, target, toolchain)
+        params, macros, features = get_config(
+            options.source_dir,
+            target,
+            options.tool[0] if options.tool else None,
+            app_config=options.app_config
+        )
         if not params and not macros:
-            print "No configuration data available."
-            _exit(0)
+            print("No configuration data available.")
+            sys.exit(0)
         if params:
-            print "Configuration parameters"
-            print "------------------------"
-            for p in sorted(params):
-                for s in options.prefix:
-                    if p.startswith(s):
-                        print(str(params[p]) if not options.verbose else params[p].get_verbose_description())
-                        break
-            print ""
+            print("Configuration parameters")
+            print("------------------------")
+            for p in sorted(list(params.keys())):
+                if any(p.startswith(s) for s in options.prefix):
+                    if options.verbose:
+                        print(params[p].get_verbose_description())
+                    else:
+                        print(str(params[p]))
+            print("")
 
-        print "Macros"
-        print "------"
-        if macros:
-            print 'Defined with "macros":', Config.config_macros_to_macros(macros)
-        print "Generated from configuration parameters:", Config.parameters_to_macros(params)
+        print("Macros")
+        print("------")
+        for m in Config.config_macros_to_macros(macros):
+            if any(m.startswith(s) for s in options.prefix):
+                print(m)
 
-    except KeyboardInterrupt, e:
-        print "\n[CTRL+c] exit"
-    except Exception,e:
+    except KeyboardInterrupt as e:
+        print("\n[CTRL+c] exit")
+    except Exception as e:
         if options.verbose:
             import traceback
             traceback.print_exc(file=sys.stdout)
         else:
-            print "[ERROR] %s" % str(e)
+            print("[ERROR] %s" % str(e))
 
         sys.exit(1)
--- a/hooks.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/hooks.py	Tue Sep 25 13:43:09 2018 -0500
@@ -30,14 +30,14 @@
             return function(t_self, *args, **kwargs)
         _RUNNING_HOOKS[tool] = True
         # If this tool isn't hooked, return original function
-        if not _HOOKS.has_key(tool):
+        if tool not in _HOOKS:
             res = function(t_self, *args, **kwargs)
             _RUNNING_HOOKS[tool] = False
             return res
         tooldesc = _HOOKS[tool]
         setattr(t_self, tool_flag, False)
         # If there is a replace hook, execute the replacement instead
-        if tooldesc.has_key("replace"):
+        if "replace" in tooldesc:
             res = tooldesc["replace"](t_self, *args, **kwargs)
         # If the replacement has set the "done" flag, exit now
         # Otherwise continue as usual
@@ -45,12 +45,12 @@
             _RUNNING_HOOKS[tool] = False
             return res
         # Execute pre-function before main function if specified
-        if tooldesc.has_key("pre"):
+        if "pre" in tooldesc:
             tooldesc["pre"](t_self, *args, **kwargs)
         # Execute the main function now
         res = function(t_self, *args, **kwargs)
         # Execute post-function after main function if specified
-        if tooldesc.has_key("post"):
+        if "post" in tooldesc:
             post_res = tooldesc["post"](t_self, *args, **kwargs)
             _RUNNING_HOOKS[tool] = False
             return post_res or res
@@ -173,7 +173,7 @@
         hook_type - one of the _HOOK_TYPES
         cmdline - the initial command line
         """
-        if self._cmdline_hooks.has_key(hook_type):
+        if hook_type in  self._cmdline_hooks:
             cmdline = self._cmdline_hooks[hook_type](
                 self.toolchain.__class__.__name__, cmdline)
         return cmdline
--- a/host_tests/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,25 +15,25 @@
 limitations under the License.
 """
 
-from host_registry import HostRegistry
+from .host_registry import HostRegistry
 
 # Host test supervisors
-from echo import EchoTest
-from rtc_auto import RTCTest
-from stdio_auto import StdioTest
-from hello_auto import HelloTest
-from detect_auto import DetectPlatformTest
-from default_auto import DefaultAuto
-from dev_null_auto import DevNullTest
-from wait_us_auto import WaitusTest
-from tcpecho_server_auto import TCPEchoServerTest
-from udpecho_server_auto import UDPEchoServerTest
-from tcpecho_client_auto import TCPEchoClientTest
-from udpecho_client_auto import UDPEchoClientTest
-from wfi_auto import WFITest
-from serial_nc_rx_auto import SerialNCRXTest
-from serial_nc_tx_auto import SerialNCTXTest
-from serial_complete_auto import SerialCompleteTest
+from .echo import EchoTest
+from .rtc_auto import RTCTest
+from .stdio_auto import StdioTest
+from .hello_auto import HelloTest
+from .detect_auto import DetectPlatformTest
+from .default_auto import DefaultAuto
+from .dev_null_auto import DevNullTest
+from .wait_us_auto import WaitusTest
+from .tcpecho_server_auto import TCPEchoServerTest
+from .udpecho_server_auto import UDPEchoServerTest
+from .tcpecho_client_auto import TCPEchoClientTest
+from .udpecho_client_auto import UDPEchoClientTest
+from .wfi_auto import WFITest
+from .serial_nc_rx_auto import SerialNCRXTest
+from .serial_nc_tx_auto import SerialNCTXTest
+from .serial_complete_auto import SerialCompleteTest
 
 # Populate registry with supervising objects
 HOSTREGISTRY = HostRegistry()
--- a/host_tests/default_auto.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/default_auto.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 from sys import stdout
 
@@ -30,7 +31,7 @@
                     return selftest.RESULT_IO_SERIAL
                 stdout.write(c)
                 stdout.flush()
-        except KeyboardInterrupt, _:
+        except KeyboardInterrupt:
             selftest.notify("\r\n[CTRL+C] exit")
             result = selftest.RESULT_ERROR
         return result
--- a/host_tests/host_tests_plugins/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,26 +14,27 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
-import host_test_registry
+from . import host_test_registry
 
 # This plugins provide 'flashing' methods to host test scripts
-import module_copy_mbed
-import module_copy_shell
-import module_copy_silabs
+from . import module_copy_mbed
+from . import module_copy_shell
+from . import module_copy_silabs
 
 try:
-    import module_copy_smart
+    from . import module_copy_smart
 except:
     pass
 
 #import module_copy_firefox
-import module_copy_mps2
+from . import module_copy_mps2
 
 # Plugins used to reset certain platform
-import module_reset_mbed
-import module_reset_silabs
-import module_reset_mps2
+from . import module_reset_mbed
+from . import module_reset_silabs
+from . import module_reset_mps2
 
 
 # Plugin registry instance
@@ -77,4 +78,4 @@
 def print_plugin_info():
     """ Prints plugins' information in user friendly way
     """
-    print HOST_TEST_PLUGIN_REGISTRY
+    print(HOST_TEST_PLUGIN_REGISTRY)
--- a/host_tests/host_tests_plugins/host_test_plugins.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/host_test_plugins.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 from os import access, F_OK
 from sys import stdout
@@ -58,16 +59,13 @@
     def print_plugin_error(self, text):
         """ Function prints error in console and exits always with False
         """
-        print "Plugin error: %s::%s: %s"% (self.name, self.type, text)
+        print("Plugin error: %s::%s: %s" % (self.name, self.type, text))
         return False
 
     def print_plugin_info(self, text, NL=True):
         """ Function prints notification in console and exits always with True
         """
-        if NL:
-            print "Plugin info: %s::%s: %s"% (self.name, self.type, text)
-        else:
-            print "Plugin info: %s::%s: %s"% (self.name, self.type, text),
+        print("Plugin info: %s::%s: %s"% (self.name, self.type, text))
         return True
 
     def print_plugin_char(self, char):
--- a/host_tests/host_tests_plugins/host_test_registry.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/host_test_registry.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 class HostTestRegistry:
     """ Simple class used to register and store
@@ -23,7 +24,7 @@
     PLUGINS = {}    # 'Plugin Name' : Plugin Object
 
     def print_error(self, text):
-        print "Plugin load failed. Reason: %s"% text
+        print("Plugin load failed. Reason: %s" % text)
 
     def register_plugin(self, plugin):
         """ Registers and stores plugin inside registry for further use.
--- a/host_tests/host_tests_plugins/module_copy_mbed.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_copy_mbed.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,9 +14,10 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 from shutil import copy
-from host_test_plugins import HostTestPluginBase
+from .host_test_plugins import HostTestPluginBase
 from time import sleep
 
 
@@ -32,7 +33,7 @@
             destination_disk += '/'
         try:
             copy(image_path, destination_disk)
-        except Exception, e:
+        except Exception as e:
             self.print_plugin_error("shutil.copy('%s', '%s')"% (image_path, destination_disk))
             self.print_plugin_error("Error: %s"% str(e))
             result = False
--- a/host_tests/host_tests_plugins/module_copy_mps2.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_copy_mps2.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,12 +14,13 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import re
 import os, shutil
 from os.path import join
-from host_test_plugins import HostTestPluginBase
 from time import sleep
+from .host_test_plugins import HostTestPluginBase
 
 
 class HostTestPluginCopyMethod_MPS2(HostTestPluginBase):
--- a/host_tests/host_tests_plugins/module_copy_shell.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_copy_shell.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,12 +14,13 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import os
 from os.path import join, basename
-from host_test_plugins import HostTestPluginBase
 from time import sleep
 
+from .host_test_plugins import HostTestPluginBase
 
 class HostTestPluginCopyMethod_Shell(HostTestPluginBase):
 
--- a/host_tests/host_tests_plugins/module_copy_silabs.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_copy_silabs.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,9 +14,10 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
-from host_test_plugins import HostTestPluginBase
 from time import sleep
+from .host_test_plugins import HostTestPluginBase
 
 
 class HostTestPluginCopyMethod_Silabs(HostTestPluginBase):
--- a/host_tests/host_tests_plugins/module_reset_mbed.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_reset_mbed.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,8 +14,9 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
-from host_test_plugins import HostTestPluginBase
+from .host_test_plugins import HostTestPluginBase
 
 
 class HostTestPluginResetMethod_Mbed(HostTestPluginBase):
--- a/host_tests/host_tests_plugins/module_reset_mps2.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_reset_mps2.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,10 +14,11 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import os
-from host_test_plugins import HostTestPluginBase
 from time import sleep
+from .host_test_plugins import HostTestPluginBase
 
 # Note: This plugin is not fully functional, needs improvements
 
--- a/host_tests/host_tests_plugins/module_reset_silabs.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/host_tests_plugins/module_reset_silabs.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,8 +14,9 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
-from host_test_plugins import HostTestPluginBase
+from .host_test_plugins import HostTestPluginBase
 
 
 class HostTestPluginResetMethod_SiLabs(HostTestPluginBase):
--- a/host_tests/tcpecho_client_auto.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/tcpecho_client_auto.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,17 +14,21 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import sys
 import socket
 from sys import stdout
-from SocketServer import BaseRequestHandler, TCPServer
+try:
+    from SocketServer import BaseRequestHandler, TCPServer
+except ImportError:
+    from socketserver import BaseRequestHandler, TCPServer
 
 class TCPEchoClient_Handler(BaseRequestHandler):
     def handle(self):
         """ One handle per connection
         """
-        print "HOST: Connection received...",
+        print("HOST: Connection received...")
         count = 1;
         while True:
             data = self.request.recv(1024)
@@ -32,7 +36,7 @@
             self.request.sendall(data)
             if '{{end}}' in str(data):
                 print
-                print str(data)
+                print(str(data))
             else:
                 if not count % 10:
                     sys.stdout.write('.')
@@ -82,6 +86,7 @@
 
         # Returning none will suppress host test from printing success code
         server = TCPServer((SERVER_IP, SERVER_PORT), TCPEchoClient_Handler)
-        print "HOST: Listening for TCP connections: " + SERVER_IP + ":" + str(SERVER_PORT)
+        print("HOST: Listening for TCP connections: %s:%s" %
+              (SERVER_IP, str(SERVER_PORT)))
         self.send_server_ip_port(selftest, SERVER_IP, SERVER_PORT)
         server.serve_forever()
--- a/host_tests/tcpecho_server_auto.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/tcpecho_server_auto.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import re
 import sys
@@ -47,18 +48,18 @@
             try:
                 self.s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
                 self.s.connect((self.ECHO_SERVER_ADDRESS, self.ECHO_PORT))
-            except Exception, e:
+            except Exception as e:
                 self.s = None
                 selftest.notify("HOST: Socket error: %s"% e)
                 return selftest.RESULT_ERROR
 
-            print 'HOST: Sending %d echo strings...'% self.ECHO_LOOPs,
+            print('HOST: Sending %d echo strings...'% self.ECHO_LOOPs,)
             for i in range(0, self.ECHO_LOOPs):
                 TEST_STRING = str(uuid.uuid4())
                 try:
                     self.s.sendall(TEST_STRING)
                     data = self.s.recv(128)
-                except Exception, e:
+                except Exception as e:
                     self.s = None
                     selftest.notify("HOST: Socket error: %s"% e)
                     return selftest.RESULT_ERROR
@@ -69,10 +70,10 @@
                     stdout.flush()
                     result = True
                 else:
-                    print "Expected: "
-                    print "'%s'"% TEST_STRING
-                    print "received: "
-                    print "'%s'"% received_str
+                    print("Expected: ")
+                    print("'%s'"% TEST_STRING)
+                    print("received: ")
+                    print("'%s'"% received_str)
                     result = False
                     break
 
--- a/host_tests/udpecho_client_auto.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/udpecho_client_auto.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,11 +14,15 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import sys
 import socket
 from sys import stdout
-from SocketServer import BaseRequestHandler, UDPServer
+try:
+    from SocketServer import BaseRequestHandler, UDPServer
+except ImportError:
+    from socketserver import BaseRequestHandler, UDPServer
 
 class UDPEchoClient_Handler(BaseRequestHandler):
     def handle(self):
@@ -27,8 +31,7 @@
         data, socket = self.request
         socket.sendto(data, self.client_address)
         if '{{end}}' in data:
-            print
-            print data
+            print("\n%s" % data)
         else:
             sys.stdout.write('.')
         stdout.flush()
@@ -72,6 +75,6 @@
 
         # Returning none will suppress host test from printing success code
         server = UDPServer((SERVER_IP, SERVER_PORT), UDPEchoClient_Handler)
-        print "HOST: Listening for UDP connections..."
+        print("HOST: Listening for UDP connections...")
         self.send_server_ip_port(selftest, SERVER_IP, SERVER_PORT)
         server.serve_forever()
--- a/host_tests/udpecho_server_auto.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/host_tests/udpecho_server_auto.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import re
 import sys
@@ -45,7 +46,7 @@
             # We assume this test fails so can't send 'error' message to server
             try:
                 self.s = socket(AF_INET, SOCK_DGRAM)
-            except Exception, e:
+            except Exception as e:
                 self.s = None
                 selftest.notify("HOST: Socket error: %s"% e)
                 return selftest.RESULT_ERROR
--- a/latest_targets.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/latest_targets.json	Tue Sep 25 13:43:09 2018 -0500
@@ -11,13 +11,17 @@
         "detect_code": [],
         "public": false,
         "default_lib": "std",
-        "bootloader_supported": false
-    },
-    "Super_Target": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4",
-        "features_add": ["UVISOR", "BLE", "CLIENT", "IPV4", "IPV6"],
-        "supported_toolchains": ["ARM"]
+        "bootloader_supported": false,
+        "config": {
+            "console-uart-flow-control": {
+                "help": "Console hardware flow control. Options: null, RTS, CTS, RTSCTS.",
+                "value": null
+            },
+            "network-default-interface-type": {
+                "help": "Default network interface type. Typical options: null, ETHERNET, WIFI, CELLULAR, MESH",
+                "value": null
+            }
+        }
     },
     "CM4_UARM": {
         "inherits": ["Target"],
@@ -56,6 +60,7 @@
         "inherits": ["LPCTarget"],
         "core": "Cortex-M0",
         "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
+        "OUTPUT_EXT": "hex",
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
@@ -110,7 +115,7 @@
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-	"default_lib": "small",
+        "default_lib": "small",
         "device_name": "LPC11U34FBD48/311"
     },
     "MICRONFCBOARD": {
@@ -205,7 +210,7 @@
         "supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
         "inherits": ["LPCTarget"],
         "detect_code": ["1168"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "SERIAL", "SLEEP", "SPI"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "LPC11U68JBD100"
@@ -227,7 +232,7 @@
         "supported_toolchains": ["uARM", "GCC_CR", "GCC_ARM", "IAR"],
         "inherits": ["LPCTarget"],
         "detect_code": ["1549"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "LPC1549JBD64"
@@ -235,14 +240,16 @@
     "LPC1768": {
         "inherits": ["LPCTarget"],
         "core": "Cortex-M3",
-        "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768"],
+        "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768", "NXP_EMAC"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
         "detect_code": ["1010"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
-        "features": ["LWIP"],
         "device_name": "LPC1768",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "LPC1769": {
         "inherits": ["LPC1768"],
@@ -252,20 +259,22 @@
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
-        "extra_labels": ["NXP", "LPC176X"],
+        "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
         "macros": ["TARGET_LPC1768"],
         "inherits": ["LPCTarget"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
-        "features": ["LWIP"],
         "device_name": "LPC1768",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "UBLOX_C027": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
-        "extra_labels": ["NXP", "LPC176X"],
+        "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
         "config": {
             "modem_is_on_board": {
                 "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
@@ -280,11 +289,13 @@
         },
         "macros": ["TARGET_LPC1768"],
         "inherits": ["LPCTarget"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
-        "features": ["LWIP"],
         "device_name": "LPC1768",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "CELLULAR"
+        }
     },
     "XBED_LPC1768": {
         "inherits": ["LPCTarget"],
@@ -293,7 +304,7 @@
         "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
         "macros": ["TARGET_LPC1768"],
         "detect_code": ["1010"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "device_name": "LPC1768"
     },
     "LPC810": {
@@ -348,15 +359,17 @@
     "MCU_LPC4088": {
         "inherits": ["LPCTarget"],
         "core": "Cortex-M4F",
-        "extra_labels": ["NXP", "LPC408X"],
+        "extra_labels": ["NXP", "LPC408X", "NXP_EMAC"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "GCC_CR", "GCC_ARM", "IAR"],
         "post_binary_hook": {
             "function": "LPC4088Code.binary_hook"
         },
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "features": ["LWIP"],
-        "device_name": "LPC4088FBD144"
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "EMAC", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_name": "LPC4088FBD144",
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "LPC4088": {
         "inherits": ["MCU_LPC4088"],
@@ -371,7 +384,7 @@
         "core": "Cortex-M4F",
         "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
         "supported_toolchains": ["ARM", "GCC_CR", "IAR", "GCC_ARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "device_name": "LPC4330"
     },
     "LPC4330_M0": {
@@ -379,14 +392,14 @@
         "core": "Cortex-M0",
         "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
         "supported_toolchains": ["ARM", "GCC_CR", "IAR"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
+        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"]
     },
     "LPC4337": {
         "inherits": ["LPCTarget"],
         "core": "Cortex-M4F",
         "extra_labels": ["NXP", "LPC43XX", "LPC4337"],
         "supported_toolchains": ["ARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2"],
         "device_name": "LPC4337"
     },
@@ -429,7 +442,7 @@
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "MKL05Z32xxx4"
@@ -442,7 +455,7 @@
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
         "detect_code": ["0200"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "MKL25Z128xxx4"
     },
@@ -453,7 +466,7 @@
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "device_name": "MKL26Z128xxx4"
     },
     "KL46Z": {
@@ -464,7 +477,7 @@
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "inherits": ["Target"],
         "detect_code": ["0220"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "MKL46Z256xxx4",
         "bootloader_supported": true
@@ -476,7 +489,7 @@
         "is_disk_virtual": true,
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "detect_code": ["0230"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2"],
         "device_name": "MK20DX128xxx5"
     },
@@ -492,7 +505,7 @@
             "toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
         },
         "detect_code": ["0230"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2"],
         "device_name": "MK20DX256xxx7"
     },
@@ -505,7 +518,7 @@
         "macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0231"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "device_name": "MK22DN512xxx5"
     },
     "K22F": {
@@ -524,7 +537,7 @@
         "is_disk_virtual": true,
         "default_toolchain": "ARM",
         "detect_code": ["0261"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "default_lib": "std",
         "release_versions": ["2"],
         "device_name": "MKL27Z64xxx4"
@@ -538,7 +551,7 @@
         "is_disk_virtual": true,
         "inherits": ["Target"],
         "detect_code": ["0262"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "MKL43Z256xxx4"
     },
@@ -551,13 +564,12 @@
         "is_disk_virtual": true,
         "inherits": ["Target"],
         "detect_code": ["0218"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
         "release_versions": ["2", "5"],
         "device_name": "MKL82Z128xxx7"
     },
     "USENSE": {
         "inherits": ["KL82Z"],
-        "device_has_add": ["LOWPOWERTIMER"],
         "extra_labels_remove": ["FRDM"],
         "supported_form_factors": []
     },
@@ -570,10 +582,13 @@
         "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0250"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH", "802_15_4_PHY"],
         "release_versions": ["2", "5"],
         "device_name": "MKW24D512xxx5",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "MESH"
+        }
     },
     "KW41Z": {
         "supported_form_factors": ["ARDUINO"],
@@ -584,7 +599,7 @@
         "macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0201"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "TRNG", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
         "device_name": "MKW41Z512xxx4"
     },
@@ -596,7 +611,7 @@
         "public": false,
         "macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "device_name": "MK24FN1M0xxx12"
     },
     "RO359B": {
@@ -607,17 +622,53 @@
     },
     "K64F": {
         "supported_form_factors": ["ARDUINO"],
+        "components": ["SD"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F", "Freescale_EMAC"],
         "is_disk_virtual": true,
         "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0240"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
-        "features": ["LWIP", "STORAGE"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "CRC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "STORAGE", "TRNG", "FLASH"],
+        "features": ["STORAGE"],
         "release_versions": ["2", "5"],
         "device_name": "MK64FN1M0xxx12",
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
+    },
+    "SDT64B": {
+        "inherits": ["K64F"],
+        "extra_labels_add": ["K64F"],
+        "extra_labels_remove": ["FRDM"],
+        "components_remove": ["SD"],
+        "supported_form_factors": [],
+        "detect_code": ["3105"]
+    },
+    "EV_COG_AD4050LZ": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
+        "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"],
+        "device_has": ["FLASH", "USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
+        "device_name": "ADuCM4050",
+        "detect_code": ["0603"],
+        "release_versions": ["5"],
+        "bootloader_supported": true
+    },
+    "EV_COG_AD3029LZ": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"],
+        "extra_labels": ["Analog_Devices", "ADUCM302X", "ADUCM3029", "EV_COG_AD3029LZ", "FLASH_CMSIS_ALGO"],
+        "device_has": ["FLASH", "USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
+        "device_name": "ADuCM3029",
+        "detect_code": ["0602"],
+        "release_versions": ["5"],
         "bootloader_supported": true
     },
     "MTS_GAMBIT": {
@@ -627,7 +678,7 @@
         "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "KPSDK_MCUS", "KPSDK_CODE", "MCU_K64F"],
         "is_disk_virtual": true,
         "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
-        "device_has": ["I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "device_name": "MK64FN1M0xxx12"
     },
     "HEXIWEAR": {
@@ -639,28 +690,32 @@
         "is_disk_virtual": true,
         "default_toolchain": "ARM",
         "detect_code": ["0214"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "default_lib": "std",
         "release_versions": ["2", "5"],
-        "device_name": "MK64FN1M0xxx12"
+        "device_name": "MK64FN1M0xxx12",
+        "bootloader_supported": true
     },
     "K66F": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
+        "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "Freescale_EMAC"],
         "is_disk_virtual": true,
         "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0311"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "MK66FN2M0xxx18",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "K82F": {
         "supported_form_factors": ["ARDUINO"],
+        "components": ["SPIF"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
@@ -668,13 +723,14 @@
         "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0217"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "MK82FN256xxx15"
     },
     "UBRIDGE": {
         "inherits": ["K82F"],
         "extra_labels_remove": ["FRDM"],
+        "components_remove": ["SPIF"],
         "supported_form_factors": []
     },
     "FAMILY_STM32": {
@@ -683,33 +739,74 @@
         "extra_labels": ["STM"],
         "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
         "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
+        "config": {
+            "lse_available": {
+                "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used",
+                "value": "1"
+            },
+            "lpuart_clock_source": {
+                "help": "Define the LPUART clock source. Mask values: USE_LPUART_CLK_LSE, USE_LPUART_CLK_PCLK1, USE_LPUART_CLK_HSI",
+                "value": "USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1"
+            },
+            "stdio_uart_tx": {
+                "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden"
+            },
+            "stdio_uart_rx": {
+                "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden"
+            }
+        },
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
+    },
+    "MIMXRT1050_EVK": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M7FD",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "EVK", "MIMXRT1050", "IMX"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_MIMXRT1052DVL6B", "FSL_RTOS_MBED", "XIP_BOOT_HEADER_ENABLE=1", "XIP_EXTERNAL_FLASH=1", "XIP_BOOT_HEADER_DCD_ENABLE=1", "SKIP_SYSCLK_INIT"],
+        "inherits": ["Target"],
+        "detect_code": ["0227"],
+        "device_has": ["SLEEP", "USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2CSLAVE", "ERROR_RED", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "release_versions": ["2", "5"],
+        "device_name": "MIMXRT1052"
     },
     "LPC54114": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
-        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54114_M4", "LPCXpresso"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54114_M4", "LPCXpresso", "LPC"],
         "is_disk_virtual": true,
         "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["1054"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["USTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name" : "LPC54114J256BD64"
     },
+    "MCU_LPC546XX": {
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso", "LPC", "LPC546XX", "NXP_EMAC"],
+        "is_disk_virtual": true,
+        "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
+        "inherits": ["Target"],
+        "device_has": ["USTICKER", "RTC", "ANALOGIN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH", "TRNG"],
+        "device_name" : "LPC54628J512ET180",
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
+    },
     "LPC546XX": {
         "supported_form_factors": ["ARDUINO"],
-        "core": "Cortex-M4F",
-        "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
-        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso"],
-        "is_disk_virtual": true,
-        "macros": ["CPU_LPC54618J512ET180", "FSL_RTOS_MBED"],
-        "inherits": ["Target"],
+        "inherits": ["MCU_LPC546XX"],
         "detect_code": ["1056"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"],
-        "device_name" : "LPC54618J512ET180"
+        "release_versions": ["2", "5"]
+    },
+    "FF_LPC546XX": {
+        "inherits": ["MCU_LPC546XX"],
+        "extra_labels_remove" : ["LPCXpresso"],
+        "detect_code": ["8081"],
+        "release_versions": ["2", "5"]
     },
     "NUCLEO_F030R8": {
         "inherits": ["FAMILY_STM32"],
@@ -725,7 +822,8 @@
         },
         "detect_code": ["0725"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["SERIAL_FC"],
+        "device_has_add": ["CRC", "SERIAL_FC"],
+        "device_has_remove": ["LPTICKER"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F030R8"
@@ -744,8 +842,10 @@
             }
         },
         "detect_code": ["0791"],
-        "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["SERIAL_FC"],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["CRC", "SERIAL_FC"],
+        "device_has_remove": ["LPTICKER"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F031K6"
@@ -764,8 +864,10 @@
             }
         },
         "detect_code": ["0785"],
-        "macros_add": ["RTC_LSI=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["CAN", "SERIAL_FC"],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has_add": ["CAN", "CRC", "SERIAL_FC"],
+        "device_has_remove": ["LPTICKER"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F042K6"
@@ -780,11 +882,16 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_delay_ticks": {
+                "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+                "value": 1,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0755"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F070RB"
     },
@@ -798,11 +905,16 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_delay_ticks": {
+                "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+                "value": 1,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0730"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F072RB"
     },
@@ -816,11 +928,16 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_delay_ticks": {
+                "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+                "value": 1,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0750"],
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F091RC"
     },
@@ -842,7 +959,8 @@
             }
         },
         "detect_code": ["0700"],
-        "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH"],
+        "device_has_add": ["CAN", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+        "device_has_remove": ["LPTICKER"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F103RB"
     },
@@ -850,7 +968,7 @@
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
         "core": "Cortex-M3",
-        "extra_labels_add": ["STM32F2", "STM32F207ZG"],
+        "extra_labels_add": ["STM32F2", "STM32F207ZG", "STM_EMAC"],
         "config": {
             "d11_configuration": {
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
@@ -865,10 +983,14 @@
         },
         "detect_code": ["0835"],
         "macros_add": ["USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC"],
-        "features": ["LWIP"],
+        "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_remove": ["LPTICKER"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F207ZG"
+        "device_name": "STM32F207ZG",
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NUCLEO_F302R8": {
         "inherits": ["FAMILY_STM32"],
@@ -883,7 +1005,7 @@
             }
         },
         "detect_code": ["0705"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "device_has_add": ["ANALOGOUT", "CAN",  "CRC", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F302R8"
@@ -893,7 +1015,6 @@
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
-        "macros_add": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -901,9 +1022,10 @@
                 "macro_name": "CLOCK_SOURCE"
             }
         },
+        "overrides": {"lse_available": 0},
         "detect_code": ["0775"],
         "default_lib": "small",
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC"],
         "release_versions": ["2"],
         "device_name": "STM32F303K8"
     },
@@ -920,8 +1042,9 @@
             }
         },
         "detect_code": ["0745"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
+        "bootloader_supported": true,
         "device_name": "STM32F303RE"
     },
     "NUCLEO_F303ZE": {
@@ -937,7 +1060,7 @@
             }
         },
         "detect_code": ["0747"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F303ZE"
     },
@@ -954,7 +1077,7 @@
             }
         },
         "detect_code": ["0735"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F334R8"
@@ -977,6 +1100,23 @@
         "release_versions": ["2", "5"],
         "device_name": "STM32F401RE"
     },
+    "STEVAL_3DP001V1": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401VE"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "HSE_VALUE=25000000"],
+        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "overrides": {"lse_available": 0},
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F401VE"
+    },
     "NUCLEO_F410RB": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
@@ -987,10 +1127,19 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0744"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F410RB"
     },
@@ -1013,9 +1162,10 @@
             }
         },
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F411RE"
+        "device_name": "STM32F411RE",
+        "bootloader_supported": true
     },
     "NUCLEO_F412ZG": {
         "inherits": ["FAMILY_STM32"],
@@ -1031,11 +1181,72 @@
         },
         "detect_code": ["0826"],
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F412ZG",
         "bootloader_supported": true
     },
+    "MTB_MXCHIP_EMW3166": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG", "WICED", "CYW43362"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["5"],
+        "device_name": "STM32F412ZG",
+        "bootloader_supported": true,
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "overrides": {
+            "network-default-interface-type": "WIFI"
+        }
+    },
+    "USI_WM_BN_BM_22": {
+        "inherits": ["FAMILY_STM32"],
+        "components": ["SPIF"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG", "WICED", "CYW4343X", "CORDIO"],
+        "features": ["BLE", "STORAGE"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["5"],
+        "device_name": "STM32F412ZG",
+        "bootloader_supported": true,
+        "public": false,
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "overrides": {
+            "network-default-interface-type": "WIFI"
+        }
+    },
+    "MTB_USI_WM_BN_BM_22": {
+        "overrides": {
+            "lse_available": 0
+        },
+        "inherits": ["USI_WM_BN_BM_22"]
+    },
+    "MTB_ADV_WISE_1530": {
+        "inherits": ["USI_WM_BN_BM_22"],
+        "config": {
+            "led1": "PA_4",
+            "led2": "PC_12",
+            "led3": "NC"
+            },
+        "overrides": {
+            "stdio_uart_tx": "PB_10",
+            "stdio_uart_rx": "PC_11"
+        }
+    },
     "DISCO_F413ZH": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
@@ -1046,11 +1257,47 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0743"],
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F413ZH"
+    },
+    "NUCLEO_F413ZH": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F413xx", "STM32F413ZH", "STM32F413xH"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
+            }
+        },
+        "detect_code": ["0743"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F413ZH"
     },
@@ -1088,14 +1335,16 @@
                 "macro_name": "CLOCK_SOURCE_USB"
             }
         },
-        "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI"],
+        "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI", "STM_EMAC"],
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "detect_code": ["0796"],
-        "features": ["LWIP"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F429ZI",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NUCLEO_F439ZI": {
         "inherits": ["FAMILY_STM32"],
@@ -1118,14 +1367,16 @@
                 "macro_name": "CLOCK_SOURCE_USB"
             }
         },
-        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI"],
+        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI", "STM_EMAC"],
         "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_FC", "TRNG", "FLASH"],
         "detect_code": ["0797"],
-        "features": ["LWIP"],
         "release_versions": ["2", "5"],
         "device_name" : "STM32F439ZI",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NUCLEO_F446RE": {
         "inherits": ["FAMILY_STM32"],
@@ -1141,7 +1392,7 @@
         },
         "detect_code": ["0777"],
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F446RE",
         "bootloader_supported": true
@@ -1160,7 +1411,7 @@
         },
         "detect_code": ["0778"],
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F446ZE"
     },
@@ -1170,14 +1421,14 @@
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446VE"],
         "detect_code": ["0840"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name":"STM32F446VE"
     },
     "NUCLEO_F746ZG": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M7F",
-        "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746ZG"],
+        "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746ZG", "STM_EMAC"],
         "config": {
             "d11_configuration": {
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
@@ -1188,20 +1439,32 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "macros_add": ["USBHOST_OTHER"],
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0816"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F746ZG"
+        "device_name": "STM32F746ZG",
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NUCLEO_F756ZG": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M7F",
-        "extra_labels_add": ["STM32F7", "STM32F756", "STM32F756xG", "STM32F756ZG"],
+        "extra_labels_add": ["STM32F7", "STM32F756", "STM32F756xG", "STM32F756ZG", "STM_EMAC"],
         "config": {
             "d11_configuration": {
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
@@ -1212,21 +1475,36 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "macros_add": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0819"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F756ZG"
+        "device_name": "STM32F756ZG",
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NUCLEO_F767ZI": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M7FD",
-        "extra_labels_add": ["STM32F7", "STM32F767", "STM32F767xI", "STM32F767ZI"],
+        "extra_labels_add": ["STM32F7", "STM32F767", "STM32F767xI", "STM32F767ZI", "STM_EMAC"],
         "config": {
+            "flash_dual_bank": {
+                "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
+                "value": "0"
+            },
             "d11_configuration": {
                 "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
                 "value": "PA_7",
@@ -1236,15 +1514,27 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "supported_form_factors": ["ARDUINO"],
         "macros_add": ["USBHOST_OTHER"],
         "detect_code": ["0818"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F767ZI"
+        "device_name": "STM32F767ZI",
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NUCLEO_L011K4": {
         "inherits": ["FAMILY_STM32"],
@@ -1258,10 +1548,19 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0780"],
-        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["CRC", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32L011K4"
@@ -1277,10 +1576,19 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0790"],
-        "device_has_add": ["LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["CRC", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32L031K6"
@@ -1295,10 +1603,19 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0715"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "FLASH"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32L053R8"
@@ -1313,10 +1630,19 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0760"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L073RZ"
     },
@@ -1330,10 +1656,15 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_delay_ticks": {
+                "help": "For targets with low frequency system clock, set lpticker_delay_ticks value to 1",
+                "value": 1,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0710"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L152RE"
     },
@@ -1347,12 +1678,69 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0770"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "CAN", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32L432KC"
+        "device_name": "STM32L432KC",
+        "bootloader_supported": true
+    },
+    "NUCLEO_L433RC_P": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
+            }
+        },
+        "detect_code": ["0779"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L433RC",
+        "bootloader_supported": true
+    },
+    "MTB_ADV_WISE_1510": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L443xC", "STM32L443RC"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "overrides": {"lse_available": 0},
+        "release_versions": ["5"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "SERIAL_ASYNCH", "CAN", "TRNG", "FLASH"],
+        "device_has_remove": ["LPTICKER"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+        "device_name" : "STM32L443RC",
+        "detect_code": ["0458"],
+        "bootloader_supported": true
     },
     "NUCLEO_L476RG": {
         "inherits": ["FAMILY_STM32"],
@@ -1364,11 +1752,20 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0765"],
-        "macros_add": ["USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L476RG",
         "bootloader_supported": true
@@ -1386,8 +1783,8 @@
             }
         },
         "detect_code": ["0766"],
-        "macros_add": ["USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["5"],
         "device_name": "STM32L476JG"
     },
@@ -1401,14 +1798,44 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0827"],
-        "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT", "TWO_RAM_REGIONS"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L486RG"
     },
+    "MTB_ADV_WISE_1570": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG", "WISE_1570"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_HSE_XTAL",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "overrides": {"lpuart_clock_source": "USE_LPUART_CLK_HSI"},
+        "detect_code": ["0460"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570", "TWO_RAM_REGIONS"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_remove": ["LPTICKER"],
+        "release_versions": ["5"],
+        "device_name": "STM32L486RG",
+        "bootloader_supported": true,
+        "OUTPUT_EXT": "hex"
+    },
     "ARCH_MAX": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
@@ -1420,6 +1847,39 @@
         "release_versions": ["2"],
         "device_name": "STM32F407VG"
     },
+    "WIO_3G": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "clock_source_usb": {
+                "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
+                "value": "1",
+                "macro_name": "CLOCK_SOURCE_USB"
+            },
+            "modem_is_on_board": {
+                "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD"
+            },
+            "modem_data_connection_type": {
+                "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD_UART"
+            }
+        },
+        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439VI", "STM32F439xx", "STM32F439xI"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "detect_code": ["9014"],
+        "release_versions": ["2", "5"],
+        "device_name" : "STM32F439VI",
+        "bootloader_supported": true
+    },
     "DISCO_F051R8": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M0",
@@ -1433,7 +1893,8 @@
             }
         },
         "macros_add": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has_add": ["SERIAL_FC"],
+        "device_has_add": ["CRC", "SERIAL_FC"],
+        "device_has_remove": ["LPTICKER"],
         "device_name": "STM32F051R8"
     },
     "DISCO_F100RB": {
@@ -1442,22 +1903,30 @@
         "extra_labels_add": ["STM32F1", "STM32F100RB"],
         "supported_toolchains": ["GCC_ARM"],
         "device_has_add": [],
+        "device_has_remove": ["LPTICKER"],
         "device_name": "STM32F100RB"
     },
     "DISCO_F303VC": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F303", "STM32F303xC", "STM32F303VC"],
-        "macros_add": ["RTC_LSI=1"],
-        "supported_toolchains": ["GCC_ARM"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
+        "overrides": {"lse_available": 0},
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_FC"],
         "device_name": "STM32F303VC"
     },
     "DISCO_F334C8": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F3", "STM32F334x8","STM32F334C8"],
-        "macros_add": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
@@ -1465,8 +1934,9 @@
                 "macro_name": "CLOCK_SOURCE"
             }
         },
+        "overrides": {"lse_available": 0},
         "detect_code": ["0810"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC"],
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_ASYNCH", "SERIAL_FC"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32F334C8"
@@ -1475,9 +1945,18 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"],
-        "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
+        "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
         "macros_add": ["USB_STM_HAL"],
+        "overrides": {"lse_available": 0},
         "device_has_add": ["ANALOGOUT"],
+        "release_versions": ["2", "5"],
         "device_name": "STM32F407VG"
     },
     "DISCO_F429ZI": {
@@ -1496,10 +1975,12 @@
                 "macro_name": "CLOCK_SOURCE_USB"
             }
         },
-        "macros_add": ["RTC_LSI=1", "USBHOST_OTHER"],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F429ZI"
+        "device_name": "STM32F429ZI",
+        "bootloader_supported": true
     },
     "DISCO_F469NI": {
         "inherits": ["FAMILY_STM32"],
@@ -1514,8 +1995,8 @@
             }
         },
         "detect_code": ["0788"],
-        "macros_add": ["USB_STM_HAL"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F469NI"
     },
@@ -1523,15 +2004,25 @@
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M0+",
         "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
-        "macros": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "FLASH"],
+        "overrides": {"lse_available": 0},
+        "device_has_add": ["ANALOGOUT", "CRC", "SERIAL_FC", "FLASH"],
         "default_lib": "small",
         "release_versions": ["2"],
         "device_name": "STM32L053C8"
@@ -1539,56 +2030,106 @@
     "DISCO_L072CZ_LRWAN1": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M0+",
-        "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"],
+        "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xZ", "STM32L072xx"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
-        "macros": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0833"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L072CZ"
     },
+    "MTB_MURATA_ABZ": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M0+",
+        "extra_labels_add": ["STM32L0", "STM32L0x2xZ", "STM32L082CZ", "STM32L082xx"],
+        "detect_code": ["0456"],
+        "device_has_add": ["ANALOGOUT", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
+        "device_has_remove": ["LPTICKER"],
+        "release_versions": ["5"],
+        "device_name": "STM32L082CZ"
+    },
     "DISCO_F746NG": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M7F",
-        "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746NG"],
+        "extra_labels_add": ["STM32F7", "STM32F746", "STM32F746xG", "STM32F746NG", "STM_EMAC"],
         "supported_form_factors": ["ARDUINO"],
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "usb_speed": {
+                "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)",
+                "value": "1"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0815"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH", "QSPI"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F746NG"
+        "device_name": "STM32F746NG",
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "DISCO_F769NI": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M7FD",
-        "extra_labels_add": ["STM32F7", "STM32F769", "STM32F769xI", "STM32F769NI"],
+        "extra_labels_add": ["STM32F7", "STM32F769", "STM32F769xI", "STM32F769NI", "STM_EMAC"],
         "supported_form_factors": ["ARDUINO"],
         "config": {
+            "flash_dual_bank": {
+                "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
+                "value": "0"
+            },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0817"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "EMAC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F769NI"
+        "device_name": "STM32F769NI",
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "DISCO_L475VG_IOT01A": {
         "inherits": ["FAMILY_STM32"],
@@ -1599,14 +2140,24 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0764"],
-        "macros_add": ["USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32L475VG"
+        "device_name": "STM32L475VG",
+        "bootloader_supported": true
     },
     "DISCO_L476VG": {
         "inherits": ["FAMILY_STM32"],
@@ -1617,11 +2168,20 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0820"],
-        "macros_add": ["USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+        "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
+        "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_FC", "TRNG", "FLASH", "QSPI"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L476VG",
         "bootloader_supported": true
@@ -1665,7 +2225,8 @@
                 "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
-        "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000", "RTC_LSI=1"],
+        "overrides": {"lse_available": 0},
+        "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
         "post_binary_hook": {
             "function": "MTSCode.combine_bins_mts_dragonfly",
             "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
@@ -1674,6 +2235,34 @@
         "release_versions": ["2", "5"],
         "device_name": "STM32F411RE"
     },
+    "MTB_MTS_DRAGONFLY": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F411RE"],
+        "config": {
+            "modem_is_on_board": {
+                "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD"
+            },
+            "modem_data_connection_type": {
+                "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
+                "value": 1,
+                "macro_name": "MODEM_ON_BOARD_UART"
+            }
+        },
+        "overrides": {
+                 "lse_available": 0
+        },
+        "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
+        "post_binary_hook": {
+            "function": "MTSCode.combine_bins_mtb_mts_dragonfly",
+            "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
+        },
+        "release_versions": ["2", "5"],
+        "device_name": "STM32F411RE",
+        "bootloader_supported": true
+    },
     "XDOT_L151CC": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M3",
@@ -1696,16 +2285,48 @@
         "inherits": ["XDOT_L151CC"],
         "detect_code": ["8080"]
     },
-    "MOTE_L152RC": {
+    "MTB_MTS_XDOT": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M3",
-        "default_toolchain": "uARM",
+        "default_toolchain": "ARM",
+        "extra_labels_add": ["STM32L1", "STM32L151CC"],
+        "config": {
+            "hse_value": {
+            "value": "24000000",
+            "macro_name": "HSE_VALUE"
+            }
+        },
+        "overrides": {
+            "stdio_uart_tx": "PA_2",
+            "stdio_uart_rx": "PA_3"
+        },
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "device_has_add": ["ANALOGOUT", "FLASH"],
+        "release_versions": ["5"],
+        "device_name": "STM32L151CC",
+        "bootloader_supported": true
+    },
+    "MTB_RAK811": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "default_toolchain": "ARM",
+        "extra_labels_add": ["STM32L1", "STM32L151xBA", "STM32L151CBA"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "device_has_add": ["ANALOGOUT"],
+        "release_versions": ["5"],
+        "device_name": "STM32L151CBxxA",
+        "bootloader_supported": true
+    },
+    "MOTE_L152RC": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M3",
+        "default_toolchain": "ARM",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "extra_labels_add": ["STM32L1", "STM32L152RC"],
-        "macros": ["RTC_LSI=1"],
         "detect_code": ["4100"],
-        "device_has_add": ["ANALOGOUT"],
-        "default_lib": "small",
-        "release_versions": ["2"],
+        "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "FLASH"],
+        "release_versions": ["2", "5"],
         "device_name": "STM32L152RC"
     },
     "DISCO_F401VC": {
@@ -1717,40 +2338,65 @@
         "device_has_add": [],
         "device_name": "STM32F401VC"
     },
-    "UBLOX_EVK_ODIN_W2": {
+    "MODULE_UBLOX_ODIN_W2": {
         "inherits": ["FAMILY_STM32"],
-        "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
-        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI"],
-        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
-        "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH"],
-        "device_has_remove": ["RTC", "SLEEP"],
-        "features": ["LWIP"],
+        "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI", "STM_EMAC"],
+        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","CB_FEATURE_802DOT11W","CB_FEATURE_802DOT11R","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
+        "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH", "WIFI"],
+        "device_has_remove": [],
+        "device_name": "STM32F439ZI",
+        "public": false,
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "WIFI"
+        }
+    },
+    "UBLOX_EVK_ODIN_W2": {
+        "inherits": ["MODULE_UBLOX_ODIN_W2"],
+        "supported_form_factors": ["ARDUINO"],
         "release_versions": ["5"],
-        "device_name": "STM32F439ZI",
-        "bootloader_supported": true,
+        "device_has_remove": [],
         "config": {
-            "usb_tx": {
-                "help": "Value: D8(default) or D1",
-                "value": "D8"
-            },
-            "usb_rx": {
-                "help": "Value: D2(default) or D0",
-                "value": "D2"
+            "stdio_uart_tx_help": {
+                "help": "Value: D8(default) or D1"
             },
-            "stdio_uart": {
-                "help": "Value: UART_1(default) or UART_3",
-                "value": "UART_1",
-                "macro_name": "STDIO_UART"
+            "stdio_uart_rx_help": {
+                "help": "Value: D2(default) or D0"
             }
+        },
+        "overrides": {
+            "stdio_uart_tx": "D8",
+            "stdio_uart_rx": "D2"
         }
     },
+    "MBED_CONNECT_ODIN": {
+        "inherits": ["MODULE_UBLOX_ODIN_W2"],
+        "release_versions": ["5"],
+        "config": {
+            "stdio_uart_tx_help": {
+                "help": "Value: PA_9(default) or PD_8"
+            },
+            "stdio_uart_rx_help": {
+                "help": "Value: PA_10(default) or PD_9"
+            }
+        },
+        "overrides": {
+            "stdio_uart_tx": "PA_9",
+            "stdio_uart_rx": "PA_10"
+        }
+    },
+    "MTB_UBLOX_ODIN_W2": {
+        "inherits": ["MODULE_UBLOX_ODIN_W2"],
+        "device_has_add": [],
+        "release_versions": ["5"]
+     },
     "UBLOX_C030": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
-        "extra_labels_add": ["STM32F4", "STM32F437", "STM32F437VG", "STM32F437xx", "STM32F437xG"],
+        "extra_labels_add": ["STM32F4", "STM32F437", "STM32F437VG", "STM32F437xx", "STM32F437xG", "STM_EMAC"],
         "config": {
             "modem_is_on_board": {
                 "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
@@ -1763,12 +2409,15 @@
                 "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
-        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
-        "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"],
-        "features": ["LWIP"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
+        "overrides": {"lse_available": 0},
+        "device_has_add": ["ANALOGOUT", "EMAC", "SERIAL_FC", "TRNG", "FLASH"],
         "public": false,
         "device_name": "STM32F437VG",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "UBLOX_C030_U201": {
         "inherits": ["UBLOX_C030"],
@@ -1778,13 +2427,17 @@
         "inherits": ["UBLOX_C030"],
         "release_versions": ["5"]
     },
+    "UBLOX_C030_R410M": {
+        "inherits": ["UBLOX_C030"],
+        "release_versions": ["5"]
+    },
     "NZ32_SC151": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M3",
         "default_toolchain": "uARM",
         "program_cycle_s": 1.5,
         "extra_labels_add": ["STM32L1", "STM32L151RC"],
-        "macros": ["RTC_LSI=1"],
+        "overrides": {"lse_available": 0},
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
         "device_has_add": ["ANALOGOUT"],
         "default_lib": "small",
@@ -2042,6 +2695,12 @@
         "extra_labels_add": ["RBLAB_BLENANO"],
         "macros_add": ["TARGET_RBLAB_BLENANO"]
     },
+    "RBLAB_BLENANO2": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
+        "device_name": "nRF52832_xxAA"
+    },
     "NRF51822_Y5_MBUG": {
         "inherits": ["MCU_NRF51_16K"]
     },
@@ -2063,7 +2722,7 @@
         "inherits": ["MCU_NRF51_32K"],
         "program_cycle_s": 10,
         "macros_add": ["TARGET_NRF_LFCLK_RC"],
-        "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
         "release_versions": ["2"],
         "device_name": "nRF51822_xxAA"
     },
@@ -2082,7 +2741,7 @@
     "DELTA_DFCM_NNN50": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "device_name": "nRF51822_xxAC"
     },
     "DELTA_DFCM_NNN50_BOOT": {
@@ -2177,10 +2836,35 @@
         "extra_labels_add": ["MTM_CONNECT04S"],
         "macros_add": ["TARGET_MTM_CONNECT04S"]
     },
+    "MTB_LAIRD_BL600": {
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_name": "nRF51822_xxAA",
+        "release_versions" : ["5"],
+        "extra_labels_add": ["MTB_LAIRD_BL600"],
+        "config": {
+            "usb_tx": {
+                "help": "Value SIO_21",
+                "value": "SIO_21"
+            },
+            "usb_rx": {
+                "help": "Value SIO_22",
+                "value": "SIO_22"
+            },
+            "stdio_uart": {
+                "help": "Value: UART_0",
+                "value": "UART_0",
+                "macro_name": "STDIO_UART"
+             }
+        },
+        "overrides": {
+                "uart_hwfc": 0
+        }
+    },
     "TY51822R3": {
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
         "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "detect_code": ["1019"],
         "release_versions": ["2", "5"],
         "overrides": {"uart_hwfc": 0},
@@ -2219,14 +2903,6 @@
         "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
         "release_versions": ["2"]
     },
-    "ARM_MPS2_M1": {
-        "inherits": ["ARM_MPS2_Target"],
-        "core": "Cortex-M1",
-        "supported_toolchains": ["ARM"],
-        "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M1"],
-        "macros": ["CMSDK_CM1"],
-        "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
-    },
     "ARM_MPS2_M3": {
         "inherits": ["ARM_MPS2_Target"],
         "core": "Cortex-M3",
@@ -2273,8 +2949,9 @@
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
+        "OUTPUT_EXT": "elf",
         "macros": ["CMSDK_CM3DS"],
-        "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
+        "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "copy_method": "mps2",
         "reset_method": "reboot.txt"
@@ -2286,32 +2963,48 @@
         "default_toolchain": "ARM",
         "extra_labels": ["ARM_SSG", "BEETLE"],
         "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"],
-        "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI"],
+        "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI"],
         "features": ["BLE"],
         "release_versions": ["2", "5"]
     },
+    "RZ_A1XX": {
+        "inherits": ["Target"],
+        "core": "Cortex-A9",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "extra_labels": ["RENESAS", "RZ_A1XX"],
+        "device_has": ["SLEEP", "USTICKER", "RTC", "ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "program_cycle_s": 2,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
+    },
     "RZ_A1H": {
+        "inherits": ["RZ_A1XX"],
         "supported_form_factors": ["ARDUINO"],
-        "core": "Cortex-A9",
-        "program_cycle_s": 2,
-        "extra_labels": ["RENESAS", "MBRZA1H"],
-        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
-        "features": ["LWIP"],
-        "release_versions": ["2"]
+        "extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
+        "device_has_add": ["EMAC", "FLASH", "LPTICKER"],
+        "release_versions": ["2", "5"],
+        "device_name": "R7S72100",
+        "bootloader_supported": true
     },
     "VK_RZ_A1H": {
-        "inherits": ["Target"],
-        "core": "Cortex-A9",
-        "extra_labels": ["RENESAS", "VKRZA1H"],
-        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
-        "default_toolchain": "ARM",
-        "program_cycle_s": 2,
-        "device_has": ["ANALOGIN", "CAN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
-        "features": ["LWIP"],
-        "default_lib": "std",
-        "release_versions": ["2"]
+        "inherits": ["RZ_A1XX"],
+        "extra_labels_add": ["RZA1H", "VKRZA1H", "RZ_A1_EMAC"],
+        "device_has_add": ["EMAC"],
+        "release_versions": ["2", "5"]
+    },
+    "GR_LYCHEE": {
+        "inherits": ["RZ_A1XX"],
+        "supported_form_factors": ["ARDUINO"],
+        "extra_labels_add": ["RZA1UL", "MBRZA1LU"],
+        "device_has_add": ["TRNG", "FLASH", "LPTICKER"],
+        "device_has_remove": ["ETHERNET"],
+        "release_versions": ["2", "5"],
+        "device_name": "R7S72103",
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": null
+        }
     },
     "MAXWSNENV": {
         "inherits": ["Target"],
@@ -2319,9 +3012,9 @@
         "macros": ["__SYSTEM_HFX=24000000"],
         "extra_labels": ["Maxim", "MAX32610"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
         "features": ["BLE"],
-        "release_versions": ["2", "5"]
+        "release_versions": []
     },
     "MAX32600MBED": {
         "inherits": ["Target"],
@@ -2329,7 +3022,7 @@
         "macros": ["__SYSTEM_HFX=24000000"],
         "extra_labels": ["Maxim", "MAX32600"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"]
     },
     "MAX32620HSP": {
@@ -2337,27 +3030,56 @@
         "core": "Cortex-M4F",
         "extra_labels": ["Maxim", "MAX32620"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
         "features": ["BLE"],
-        "release_versions": ["2", "5"]
-    },
-    "MAX32625MBED": {
+        "release_versions": []
+    },
+    "MAX32620FTHR": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
-        "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
+        "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32620","TARGET_REV=0x4332","OPEN_DRAIN_LEDS"],
+        "extra_labels": ["Maxim", "MAX32620C"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+        "release_versions": ["2", "5"]
+    },
+    "SDT32620B": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32620","TARGET_REV=0x4332","OPEN_DRAIN_LEDS"],
+        "detect_code": ["3101"],
+        "extra_labels": ["Maxim", "MAX32620C"],
+        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+        "release_versions": ["2", "5"]
+    },
+    "MAX32625_BASE": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["TARGET=MAX32625","TARGET_REV=0x4132", "OPEN_DRAIN_LEDS"],
         "extra_labels": ["Maxim", "MAX32625"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"]
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES", "USTICKER"],
+        "device_name": "MAX32625",
+        "release_versions": ["2", "5"],
+        "public": false
+    },
+    "MAX32625MBED": {
+        "inherits": ["MAX32625_BASE"],
+        "extra_labels_add": ["MAX32625_NO_BOOT"]
+    },
+    "SDT32625B": {
+        "inherits": ["MAX32625_BASE"],
+        "extra_labels_add": ["MAX32625_NO_BOOT"],
+        "detect_code": ["3102"]
+    },
+    "MAX32625PICO": {
+        "inherits": ["MAX32625_BASE"],
+        "extra_labels_add": ["MAX32625_BOOT"],
+        "bootloader_supported": true
     },
     "MAX32625NEXPAQ": {
-        "inherits": ["Target"],
-        "core": "Cortex-M4F",
-        "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
-        "extra_labels": ["Maxim", "MAX32625"],
-        "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
-        "release_versions": ["2", "5"]
+        "inherits": ["MAX32625_BASE"]
     },
     "MAX32630FTHR": {
         "inherits": ["Target"],
@@ -2365,20 +3087,21 @@
         "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132", "BLE_HCI_UART", "OPEN_DRAIN_LEDS"],
         "extra_labels": ["Maxim", "MAX32630"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
-        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
-		"features": ["BLE"],
+        "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "STDIO_MESSAGES", "USTICKER"],
+        "features": ["BLE"],
         "release_versions": ["2", "5"]
     },
     "EFM32": {
         "inherits": ["Target"],
         "extra_labels": ["Silicon_Labs", "EFM32"],
+        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "MBED_TICKLESS", "EM_MSC_RUN_FROM_FLASH"],
         "public": false
     },
     "EFM32GG990F1024": {
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
         "core": "Cortex-M3",
-        "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32GG990F1024",
@@ -2388,7 +3111,7 @@
     "EFM32GG_STK3700": {
         "inherits": ["EFM32GG990F1024"],
         "progen": {"target": "efm32gg-stk"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH", "ITM"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2432,7 +3155,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
         "core": "Cortex-M3",
-        "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32LG990F256",
@@ -2441,7 +3164,7 @@
     },
     "EFM32LG_STK3600": {
         "inherits": ["EFM32LG990F256"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
         "forced_reset_timeout": 2,
         "device_name": "EFM32LG990F256",
         "config": {
@@ -2486,7 +3209,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32WG990F256",
@@ -2496,7 +3219,7 @@
     "EFM32WG_STK3800": {
         "inherits": ["EFM32WG990F256"],
         "progen": {"target": "efm32wg-stk"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2541,7 +3264,7 @@
         "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
         "core": "Cortex-M0+",
         "default_toolchain": "uARM",
-        "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+        "macros_add": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
         "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -2550,7 +3273,7 @@
     },
     "EFM32ZG_STK3200": {
         "inherits": ["EFM32ZG222F32"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2595,7 +3318,7 @@
         "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
         "core": "Cortex-M0+",
         "default_toolchain": "uARM",
-        "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+        "macros_add": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
         "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -2604,7 +3327,7 @@
     },
     "EFM32HG_STK3400": {
         "inherits": ["EFM32HG322F64"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2648,7 +3371,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32PG1B100F256GM32",
@@ -2657,7 +3380,7 @@
     },
     "EFM32PG_STK3401": {
         "inherits": ["EFM32PG1B100F256GM32"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2699,9 +3422,9 @@
     },
     "EFR32MG1P132F256GM48": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
+        "extra_labels_add": ["EFR32MG1", "EFR32_1", "256K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFR32MG1P132F256GM48",
@@ -2710,9 +3433,9 @@
     },
     "EFR32MG1P233F256GM48": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
+        "extra_labels_add": ["EFR32MG1", "EFR32_1", "256K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "public": false,
@@ -2720,7 +3443,7 @@
     },
     "EFR32MG1_BRD4150": {
         "inherits": ["EFR32MG1P132F256GM48"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2763,7 +3486,7 @@
     },
     "TB_SENSE_1": {
         "inherits": ["EFR32MG1P233F256GM48"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "FLASH"],
         "forced_reset_timeout": 5,
         "config": {
             "hf_clock_src": {
@@ -2802,15 +3525,16 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
+        "device_name": "EFM32PG12B500F1024GL125",
         "public": false,
         "bootloader_supported": true
     },
     "EFM32PG12_STK3402": {
         "inherits": ["EFM32PG12B500F1024GL125"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -2850,19 +3574,21 @@
             }
         }
     },
-	"EFR32MG12P332F1024GL125": {
+    "EFR32MG12P332F1024GL125": {
         "inherits": ["EFM32"],
-        "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
+        "extra_labels_add": ["EFR32MG12", "EFR32_12", "1024K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
+        "device_name": "EFR32MG12P332F1024GL125",
         "public": false,
         "bootloader_supported": true
     },
-	"TB_SENSE_12": {
+    "TB_SENSE_12": {
         "inherits": ["EFR32MG12P332F1024GL125"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
+        "device_name": "EFR32MG12P332F1024GL125",
+        "device_has": ["ANALOGIN", "CRC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
         "forced_reset_timeout": 5,
         "config": {
             "hf_clock_src": {
@@ -2897,6 +3623,65 @@
             }
         }
     },
+    "EFM32GG11B820F2048GL192": {
+        "inherits": ["EFM32"],
+        "extra_labels_add": ["EFM32GG11", "2048K", "SL_CRYPTO"],
+        "core": "Cortex-M4F",
+        "macros_add": ["EFM32GG11B820F2048GL192", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
+        "release_versions": ["2", "5"],
+        "device_name": "EFM32GG11B820F2048GL192",
+        "public": false,
+        "bootloader_supported": true
+    },
+    "EFM32GG11_STK3701": {
+        "inherits": ["EFM32GG11B820F2048GL192"],
+        "device_name": "EFM32GG11B820F2048GL192",
+        "device_has": ["ANALOGIN", "CRC", "EMAC", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "QSPI", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "USTICKER", "TRNG", "FLASH"],
+        "forced_reset_timeout": 5,
+        "config": {
+            "hf_clock_src": {
+                "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
+                "value": "HFXO",
+                "macro_name": "CORE_CLOCK_SOURCE"
+            },
+            "hfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "50000000",
+                "macro_name": "HFXO_FREQUENCY"
+            },
+            "lf_clock_src": {
+                "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
+                "value": "LFXO",
+                "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
+            },
+            "lfxo_clock_freq": {
+                "help": "Value: External crystal frequency in hertz",
+                "value": "32768",
+                "macro_name": "LFXO_FREQUENCY"
+            },
+            "hfrco_clock_freq": {
+                "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
+                "value": "32000000",
+                "macro_name": "HFRCO_FREQUENCY"
+            },
+            "hfrco_band_select": {
+                "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
+                "value": "cmuHFRCOFreq_32M0Hz",
+                "macro_name": "HFRCO_FREQUENCY_ENUM"
+            },
+            "board_controller_enable": {
+                "help": "Pin to pull high for enabling the USB serial port",
+                "value": "PE1",
+                "macro_name": "EFM_BC_EN"
+            },
+            "qspi_flash_enable": {
+                "help": "Pin to pull high for enabling the on-board QSPI flash",
+                "value": "PG13",
+                "macro_name": "QSPI_FLASH_EN"
+            }
+        }
+    },
     "WIZWIKI_W7500": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M0",
@@ -2932,7 +3717,7 @@
         "macros": ["__SAMR21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
         "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "release_versions": ["2"],
         "device_name": "ATSAMR21G18A"
     },
@@ -2942,7 +3727,7 @@
         "macros": ["__SAMD21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
         "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "release_versions": ["2"],
         "device_name": "ATSAMD21J18A"
     },
@@ -2952,7 +3737,7 @@
         "macros": ["__SAMD21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
         "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "release_versions": ["2"],
         "device_name": "ATSAMD21G18A"
     },
@@ -2962,7 +3747,7 @@
         "macros": ["__SAML21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
         "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "device_name": "ATSAML21J18A"
     },
     "SAMG55J19": {
@@ -2972,7 +3757,7 @@
         "macros": ["__SAMG55J19__", "BOARD=75", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
         "default_toolchain": "ARM",
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "default_lib": "std",
         "device_name": "ATSAMG55J19"
     },
@@ -2993,7 +3778,14 @@
             "MBED_TICKLESS"
         ],
         "MERGE_BOOTLOADER": false,
-        "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5", "SDK11"],
+        "extra_labels": [
+            "NORDIC",
+            "MCU_NRF51",
+            "MCU_NRF51822_UNIFIED",
+            "NRF5x",
+            "NRF51",
+            "SDK_11"
+        ],
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
@@ -3026,6 +3818,12 @@
         },
         "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
     },
+    "MCU_NRF51_16K_UNIFIED_S130": {
+        "inherits": ["MCU_NRF51_UNIFIED"],
+        "extra_labels_add": ["MCU_NORDIC_16K", "MCU_NRF51_16K_S130", "MCU_NRF51_16K"],
+        "macros_add": ["TARGET_MCU_NORDIC_16K", "TARGET_MCU_NRF51_16K_S130", "TARGET_MCU_NRF51_16K"],
+        "public": false
+    },
     "MCU_NRF51_32K_UNIFIED": {
         "inherits": ["MCU_NRF51_UNIFIED"],
         "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
@@ -3035,142 +3833,203 @@
     "NRF51_DK": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "device_name": "nRF51822_xxAA"
+    },
+    "SDT51822B": {
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "detect_code": ["3103"],
         "release_versions": ["2", "5"],
         "device_name": "nRF51822_xxAA"
     },
     "NRF51_DONGLE": {
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
         "progen": {"target": "nrf51-dongle"},
-        "device_has": ["I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has": ["USTICKER", "LPTICKER", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"]
     },
-    "MCU_NRF52": {
+    "OSHCHIP": {
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+        "device_name": "nRF51822_xxAC"
+    },
+    "MCU_NRF52832": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
-        "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
-        "device_has": ["STCLK_OFF_DURING_SLEEP"],
-        "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"],
+        "macros": [
+            "BOARD_PCA10040",
+            "NRF52",
+            "TARGET_NRF52832",
+            "CMSIS_VECTAB_VIRTUAL",
+            "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+            "MBED_TICKLESS"
+        ],
+        "device_has": [
+            "ANALOGIN",
+            "FLASH",
+            "I2C",
+            "I2C_ASYNCH",
+            "INTERRUPTIN",
+            "ITM",
+            "LPTICKER",
+            "PORTIN",
+            "PORTINOUT",
+            "PORTOUT",
+            "PWMOUT",
+            "SERIAL",
+            "SERIAL_ASYNCH",
+            "SERIAL_FC",
+            "SLEEP",
+            "SPI",
+            "SPI_ASYNCH",
+            "STCLK_OFF_DURING_SLEEP",
+            "TRNG",
+            "USTICKER"
+        ],
+        "extra_labels": [
+            "NORDIC",
+            "NRF5x",
+            "NRF52",
+            "SDK_14_2",
+            "SOFTDEVICE_COMMON",
+            "SOFTDEVICE_S132_FULL"
+        ],
+        "config": {
+            "lf_clock_src": {
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
+                "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
+                "value": "NRF_LF_SRC_XTAL"
+            },
+            "lf_clock_rc_calib_timer_interval": {
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
+                "value": 16
+            },
+            "lf_clock_rc_calib_mode_config": {
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
+                "value": 0
+            }
+        },
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "public": false,
         "detect_code": ["1101"],
         "program_cycle_s": 6,
-        "MERGE_SOFT_DEVICE": true,
-        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
-            {
-                "boot": "",
-                "name": "s132_nrf52_2.0.0_softdevice.hex",
-                "offset": 114688
-            }
-        ],
-        "post_binary_hook": {
-            "function": "MCU_NRF51Code.binary_hook",
-            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
-        },
-        "MERGE_BOOTLOADER": false,
-        "features": ["BLE"],
-        "config": {
-            "lf_clock_src": {
-                "value": "NRF_LF_SRC_XTAL",
-                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
-            },
-            "uart_hwfc": {
-                "help": "Value: 1 for enable, 0 for disable",
-                "value": 1,
-                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
-            }
-        }
+        "bootloader_supported": true
     },
     "NRF52_DK": {
         "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF52"],
-        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2", "5"],
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
+        "device_name": "nRF52832_xxAA"
+    },
+    "SDT52832B": {
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
+        "detect_code": ["3104"],
         "device_name": "nRF52832_xxAA"
     },
     "UBLOX_EVA_NINA": {
-        "inherits": ["MCU_NRF52"],
-        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2", "5"],
-        "overrides": {"uart_hwfc": 0},
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
         "device_name": "nRF52832_xxAA"
     },
     "UBLOX_EVK_NINA_B1": {
         "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF52"],
-        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2", "5"],
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
+        "device_name": "nRF52832_xxAA"
+    },
+    "MTB_UBLOX_NINA_B1": {
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
+        "device_name": "nRF52832_xxAA"
+    },
+    "MTB_LAIRD_BL652": {
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
         "device_name": "nRF52832_xxAA"
     },
     "DELTA_DFBM_NQ620": {
         "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF52"],
-        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2", "5"],
-        "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
-        "config": {
-            "lf_clock_rc_calib_timer_interval": {
-                "value": 16,
-                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL"
-            },
-            "lf_clock_rc_calib_mode_config": {
-                "value": 0,
-                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG"
-            }
-        },
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
         "device_name": "nRF52832_xxAA"
     },
     "MCU_NRF52840": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
-        "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has": ["STCLK_OFF_DURING_SLEEP"],	    
-        "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
+        "macros": [
+            "BOARD_PCA10056",
+            "NRF52840_XXAA",
+            "TARGET_NRF52840",
+            "CMSIS_VECTAB_VIRTUAL",
+            "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
+            "MBED_TICKLESS",
+            "MBEDTLS_CONFIG_HW_SUPPORT"
+        ],
+        "features": ["CRYPTOCELL310"],
+        "device_has": [
+            "ANALOGIN",
+            "FLASH",
+            "I2C",
+            "I2C_ASYNCH",
+            "INTERRUPTIN",
+            "ITM",
+            "LPTICKER",
+            "PORTIN",
+            "PORTINOUT",
+            "PORTOUT",
+            "PWMOUT",
+            "SERIAL",
+            "SERIAL_ASYNCH",
+            "SERIAL_FC",
+            "SLEEP",
+            "SPI",
+            "SPI_ASYNCH",
+            "STCLK_OFF_DURING_SLEEP",
+            "TRNG",
+            "USTICKER",
+            "QSPI"
+        ],
+        "extra_labels": [
+            "NORDIC",
+            "NRF5x",
+            "NRF52",
+            "SDK_14_2",
+            "SOFTDEVICE_COMMON",
+            "SOFTDEVICE_S140_FULL"
+        ],
+        "config": {
+            "lf_clock_src": {
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
+                "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
+                "value": "NRF_LF_SRC_XTAL"
+            },
+            "lf_clock_rc_calib_timer_interval": {
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
+                "value": 16
+            },
+            "lf_clock_rc_calib_mode_config": {
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
+                "value": 0
+            }
+        },
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "public": false,
         "detect_code": ["1101"],
         "program_cycle_s": 6,
-        "MERGE_SOFT_DEVICE": true,
-        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
-            {
-                "boot": "",
-                "name": "s140_nrf52840_5.0.0-1.alpha_softdevice.hex",
-                "offset": 135168
-            }
-        ],
-        "bootloader_select_index": 0,
-        "post_binary_hook": {
-            "function": "MCU_NRF51Code.binary_hook",
-            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
-        },
-        "MERGE_BOOTLOADER": false,
-        "features": ["BLE"],
-        "config": {
-            "lf_clock_src": {
-                "value": "NRF_LF_SRC_XTAL",
-                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
-            },
-            "uart_hwfc": {
-                "help": "Value: 1 for enable, 0 for disable",
-                "value": 1,
-                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
-            }
-        }
+        "bootloader_supported": true
     },
     "NRF52840_DK": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52840"],
-        "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
-        "device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
-        "release_versions": ["2", "5"],
+        "release_versions": ["5"],
         "device_name": "nRF52840_xxAA"
     },
     "BLUEPILL_F103C8": {
@@ -3180,12 +4039,12 @@
         "extra_labels_add": ["STM32F1", "STM32F103C8"],
         "supported_toolchains": ["GCC_ARM"],
         "device_has_add": [],
-        "device_has_remove": ["RTC", "STDIO_MESSAGES"]
+        "device_has_remove": ["STDIO_MESSAGES", "LPTICKER"]
     },
     "NUMAKER_PFM_NUC472": {
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
-        "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO"],
+        "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO", "NUVOTON_EMAC"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "config": {
@@ -3207,12 +4066,14 @@
             }
         },
         "inherits": ["Target"],
-        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH"],
-        "features": ["LWIP"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH", "EMAC"],
         "release_versions": ["5"],
         "device_name": "NUC472HI8AE",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "NCS36510": {
         "inherits": ["Target"],
@@ -3248,7 +4109,7 @@
         "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
         "macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
-        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG", "SPISLAVE"],
+        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "TRNG", "SPISLAVE", "802_15_4_PHY"],
         "release_versions": ["2", "5"]
     },
     "NUMAKER_PFM_M453": {
@@ -3276,8 +4137,9 @@
             }
         },
         "inherits": ["Target"],
+        "macros_add": ["LPTICKER_DELAY_TICKS=3"],
         "progen": {"target": "numaker-pfm-m453"},
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "M453VG6AE",
         "bootloader_supported": true
@@ -3304,11 +4166,16 @@
             "gpio-irq-debounce-sample-rate": {
                 "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
                 "value": "GPIO_DBCLKSEL_16"
+            },
+            "clock-pll": {
+                "help": "Choose clock source to clock PLL: NU_HXT_PLL or NU_HIRC_PLL",
+                "macro_name": "NU_CLOCK_PLL",
+                "value": "NU_HIRC_PLL"
             }
         },
         "inherits": ["Target"],
-        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"","MBED_FAULT_HANDLER_DISABLED", "LPTICKER_DELAY_TICKS=3"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "release_versions": ["5"],
         "device_name": "NANO130KE3BN"
     },
@@ -3325,9 +4192,9 @@
                 "core.stdio-flush-at-exit": false
             }
         },
-        "device_has": ["INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "STDIO_MESSAGES"],
+        "device_has": ["INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "STDIO_MESSAGES"],
         "default_lib": "std",
-        "release_versions": ["5"]
+        "release_versions": []
    },
     "SARA_NBIOT": {
         "inherits": ["HI2110"],
@@ -3344,41 +4211,77 @@
         "default_toolchain": "GCC_ARM",
         "inherits": ["Target"],
         "detect_code": ["4600"],
-        "extra_labels": ["Realtek", "AMEBA", "RTL8195A"],
-        "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS"],
+        "extra_labels": ["Realtek", "AMEBA", "RTL8195A", "RTW_EMAC"],
+        "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS","MBED_FAULT_HANDLER_DISABLED"],
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "TRNG", "EMAC", "FLASH"],
-        "features": ["LWIP"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "TRNG", "FLASH"],
         "post_binary_hook": {
             "function": "RTL8195ACode.binary_hook",
             "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
         },
-        "release_versions": ["5"]
+        "release_versions": ["5"],
+        "overrides": {
+            "network-default-interface-type": "WIFI"
+        }
     },
     "VBLUNO51_LEGACY": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K"],
+        "detect_code": ["C006"],
+        "overrides": {"uart_hwfc": 0},
         "extra_labels_add": ["VBLUNO51"]
     },
     "VBLUNO51_BOOT": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K_BOOT"],
+        "detect_code": ["C006"],
+        "overrides": {"uart_hwfc": 0},
         "extra_labels_add": ["VBLUNO51"],
         "macros_add": ["TARGET_VBLUNO51"]
     },
     "VBLUNO51_OTA": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K_OTA"],
+        "detect_code": ["C006"],
+        "overrides": {"uart_hwfc": 0},
         "extra_labels_add": ["VBLUNO51"],
         "macros_add": ["TARGET_VBLUNO51"]
     },
     "VBLUNO51": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K_UNIFIED"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "detect_code": ["C006"],
+        "overrides": {"uart_hwfc": 0},
+        "device_has": ["USTICKER", "LPTICKER", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2"],
         "device_name": "nRF51822_xxAC"
     },
+    "DISCO_L496AG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
+            }
+        },
+        "detect_code": ["0822"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L496AG"
+    },
     "NUCLEO_L496ZG": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
@@ -3389,25 +4292,36 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
                 "value": "USE_PLL_MSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lpticker_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
+                "value": 1
+            },
+            "lpticker_delay_ticks": {
+                "help": "In case of lpticker_lptim=1, set lpticker_delay_ticks=3",
+                "value": 3,
+                "macro_name": "LPTICKER_DELAY_TICKS"
             }
         },
         "detect_code": ["0823"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "device_has_add": ["ANALOGOUT", "CAN", "CRC", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L496ZG"
     },
+    "NUCLEO_L496ZG_P": {
+        "inherits": ["NUCLEO_L496ZG"],
+        "detect_code": ["0828"]
+        },
     "VBLUNO52": {
         "supported_form_factors": ["ARDUINO"],
-        "inherits": ["MCU_NRF52"],
-        "macros_add": ["BOARD_PCA10040", "BOARD_VBLUNO52", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
-        "release_versions": ["2"],
+        "inherits": ["MCU_NRF52832"],
+        "release_versions": ["5"],
         "device_name": "nRF52832_xxAA"
     },
     "NUMAKER_PFM_M487": {
         "core": "Cortex-M4F",
         "default_toolchain": "ARM",
-        "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO"],
+        "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO","NUVOTON_EMAC"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
         "config": {
@@ -3437,12 +4351,14 @@
             }
         },
         "inherits": ["Target"],
-        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN"],
-        "features": ["LWIP"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH", "CAN", "EMAC"],
         "release_versions": ["5"],
         "device_name": "M487JIDAE",
-        "bootloader_supported": true
+        "bootloader_supported": true,
+        "overrides": {
+            "network-default-interface-type": "ETHERNET"
+        }
     },
     "TMPM066": {
         "inherits": ["Target"],
@@ -3455,5 +4371,123 @@
         "device_name": "TMPM066FWUG",
         "detect_code": ["7011"],
         "release_versions": ["5"]
+    },
+    "SAKURAIO_EVB_01": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": [],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "value": "USE_PLL_HSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
+        "release_versions": ["2"],
+        "device_name": "STM32F411RE"
+    },
+    "TMPM46B": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "is_disk_virtual": true,
+        "extra_labels": ["TOSHIBA"],
+        "macros": ["__TMPM46B__"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "I2C", "STDIO_MESSAGES", "TRNG", "FLASH", "SLEEP"],
+        "device_name": "TMPM46BF10FG",
+        "detect_code": ["7013"],
+        "release_versions": ["5"],
+        "bootloader_supported": true
+    },
+    "ARM_FM": {
+        "inherits": ["Target"],
+        "public": false,
+        "macros": ["__ARM_FM"],
+        "extra_labels": ["ARM_FM"]
+    },
+    "FVP_MPS2": {
+        "inherits": ["ARM_FM"],
+        "public": false,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "OUTPUT_EXT": "elf",
+        "device_has": ["AACI", "ANALOGIN", "CLCD", "FLASH", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC", "USTICKER"],
+        "release_versions": ["5"]
+    },
+    "FVP_MPS2_M0": {
+        "inherits": ["FVP_MPS2"],
+        "core": "Cortex-M0",
+        "macros_add": ["CMSDK_CM0"]
+    },
+    "FVP_MPS2_M0P": {
+        "inherits": ["FVP_MPS2"],
+        "core": "Cortex-M0+",
+        "macros_add": ["CMSDK_CM0plus"]
+    },
+    "FVP_MPS2_M3": {
+        "inherits": ["FVP_MPS2"],
+        "core": "Cortex-M3",
+        "macros_add": ["CMSDK_CM3"]
+    },
+    "FVP_MPS2_M4": {
+        "inherits": ["FVP_MPS2"],
+        "core": "Cortex-M4",
+        "macros_add": ["CMSDK_CM4"]
+    },
+    "FVP_MPS2_M7": {
+        "inherits": ["FVP_MPS2"],
+        "core": "Cortex-M7",
+        "macros_add": ["CMSDK_CM7"]
+    },
+    "NUMAKER_PFM_M2351": {
+        "core": "Cortex-M23-NS",
+        "default_toolchain": "ARMC6",
+        "extra_labels": ["NUVOTON", "M2351", "M2351KIAAEES", "FLASH_CMSIS_ALGO"],
+        "OUTPUT_EXT": "hex",
+        "macros": ["MBED_FAULT_HANDLER_DISABLED", "MBED_TZ_DEFAULT_ACCESS=1", "LPTICKER_DELAY_TICKS=3"],
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARMC6"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
+                "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
+                "value": "GPIO_DBCTL_DBCLKSEL_16"
+            }
+        },
+        "mbed_rom_start":   "0x10040000",
+        "mbed_rom_size":    "0x40000",
+        "mbed_ram_start":   "0x30008000",
+        "mbed_ram_size":    "0x10000",
+        "inherits": ["Target"],
+        "device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "FLASH"],
+        "detect_code": ["1305"],
+        "release_versions": ["5"],
+        "device_name": "M2351KIAAEES",
+        "bootloader_supported": true
+    },
+    "TMPM3H6": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "is_disk_virtual": true,
+        "extra_labels": ["TOSHIBA"],
+        "macros": ["__TMPM3H6__"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "I2C", "I2CSLAVE", "STDIO_MESSAGES"],
+        "device_name": "TMPM3H6FWFG",
+        "detect_code": ["7012"],
+        "release_versions": ["5"]
     }
 }
--- a/make.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/make.py	Tue Sep 25 13:43:09 2018 -0500
@@ -18,6 +18,8 @@
 
 TEST BUILD & RUN
 """
+from __future__ import print_function
+from builtins import str
 import sys
 import json
 from time import sleep
@@ -43,6 +45,7 @@
 from tools.options import get_default_options_parser
 from tools.options import extract_profile
 from tools.options import extract_mcus
+from tools.notifier.term import TerminalNotifier
 from tools.build_api import build_project
 from tools.build_api import mcu_toolchain_matrix
 from tools.build_api import mcu_toolchain_list
@@ -52,7 +55,6 @@
 from utils import argparse_many
 from utils import argparse_dir_not_parent
 from tools.toolchains import mbedToolchain, TOOLCHAIN_CLASSES, TOOLCHAIN_PATHS
-from tools.settings import CLI_COLOR_MAP
 
 if __name__ == '__main__':
     # Parse Options
@@ -138,6 +140,8 @@
                       default=None, help="The build (output) directory")
     parser.add_argument("-N", "--artifact-name", dest="artifact_name",
                       default=None, help="The built project's name")
+    parser.add_argument("--ignore", dest="ignore", type=argparse_many(str),
+                        default=None, help="Comma separated list of patterns to add to mbedignore (eg. ./main.cpp)")
     parser.add_argument("-d", "--disk", dest="disk",
                       default=None, help="The mbed disk")
     parser.add_argument("-s", "--serial", dest="serial",
@@ -186,20 +190,21 @@
     # Only prints matrix of supported toolchains
     if options.supported_toolchains:
         if options.supported_toolchains == "matrix":
-            print mcu_toolchain_matrix(platform_filter=options.general_filter_regex)
+            print(mcu_toolchain_matrix(platform_filter=options.general_filter_regex,
+                                       release_version=None))
         elif options.supported_toolchains == "toolchains":
             toolchain_list = mcu_toolchain_list()
             # Only print the lines that matter
             for line in toolchain_list.split("\n"):
                 if not "mbed" in line:
-                    print line
+                    print(line)
         elif options.supported_toolchains == "targets":
-            print mcu_target_list()
+            print(mcu_target_list())
         exit(0)
 
     # Print available tests in order and exit
     if options.list_tests is True:
-        print '\n'.join(map(str, sorted(TEST_MAP.values())))
+        print('\n'.join(map(str, sorted(TEST_MAP.values()))))
         sys.exit()
 
     # force program to "0" if a source dir is specified
@@ -230,22 +235,13 @@
         args_error(parser, "argument --build is required when argument --source is provided")
 
 
-    if options.color:
-        # This import happens late to prevent initializing colorization when we don't need it
-        import colorize
-        if options.verbose:
-            notify = mbedToolchain.print_notify_verbose
-        else:
-            notify = mbedToolchain.print_notify
-        notify = colorize.print_in_color_notifier(CLI_COLOR_MAP, notify)
-    else:
-        notify = None
+    notify = TerminalNotifier(options.verbose, options.silent, options.color)
 
     if not TOOLCHAIN_CLASSES[toolchain].check_executable():
         search_path = TOOLCHAIN_PATHS[toolchain] or "No path set"
         args_error(parser, "Could not find executable for %s.\n"
                            "Currently set search path: %s"
-                           %(toolchain,search_path))
+                           %(toolchain, search_path))
 
     # Test
     build_data_blob = {} if options.build_data else None
@@ -259,7 +255,7 @@
         if options.extra is not None:        test.extra_files = options.extra
 
         if not test.is_supported(mcu, toolchain):
-            print 'The selected test is not supported on target %s with toolchain %s' % (mcu, toolchain)
+            print('The selected test is not supported on target %s with toolchain %s' % (mcu, toolchain))
             sys.exit()
 
         # Linking with extra libraries
@@ -277,24 +273,28 @@
             build_dir = options.build_dir
 
         try:
-            bin_file = build_project(test.source_dir, build_dir, mcu, toolchain,
-                                     set(test.dependencies),
-                                     linker_script=options.linker_script,
-                                     clean=options.clean,
-                                     verbose=options.verbose,
-                                     notify=notify,
-                                     report=build_data_blob,
-                                     silent=options.silent,
-                                     macros=options.macros,
-                                     jobs=options.jobs,
-                                     name=options.artifact_name,
-                                     app_config=options.app_config,
-                                     inc_dirs=[dirname(MBED_LIBRARIES)],
-                                     build_profile=extract_profile(parser,
-                                                                   options,
-                                                                   toolchain),
-                                     stats_depth=options.stats_depth)
-            print 'Image: %s'% bin_file
+            bin_file, update_file = build_project(
+                test.source_dir,
+                build_dir,
+                mcu,
+                toolchain,
+                set(test.dependencies),
+                linker_script=options.linker_script,
+                clean=options.clean,
+                notify=notify,
+                report=build_data_blob,
+                macros=options.macros,
+                jobs=options.jobs,
+                name=options.artifact_name,
+                app_config=options.app_config,
+                inc_dirs=[dirname(MBED_LIBRARIES)],
+                build_profile=extract_profile(parser, options, toolchain),
+                stats_depth=options.stats_depth,
+                ignore=options.ignore
+            )
+            if update_file:
+                print('Update Image: %s' % update_file)
+            print('Image: %s' % bin_file)
 
             if options.disk:
                 # Simple copy to the mbed disk
@@ -328,16 +328,16 @@
                     sys.stdout.write(c)
                     sys.stdout.flush()
 
-        except KeyboardInterrupt, e:
-            print "\n[CTRL+c] exit"
+        except KeyboardInterrupt as e:
+            print("\n[CTRL+c] exit")
         except NotSupportedException as e:
-            print "\nCould not compile for %s: %s" % (mcu, str(e))
-        except Exception,e:
+            print("\nCould not compile for %s: %s" % (mcu, str(e)))
+        except Exception as e:
             if options.verbose:
                 import traceback
                 traceback.print_exc(file=sys.stdout)
             else:
-                print "[ERROR] %s" % str(e)
+                print("[ERROR] %s" % str(e))
 
             sys.exit(1)
     if options.build_data:
--- a/memap.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/memap.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,90 +1,54 @@
 #!/usr/bin/env python
 
 """Memory Map File Analyser for ARM mbed"""
+from __future__ import print_function, division, absolute_import
 
-import sys
-import os
+from abc import abstractmethod, ABCMeta
+from sys import stdout, exit, argv, path
+from os import sep, rename, remove
+from os.path import (basename, dirname, join, relpath, abspath, commonprefix,
+                     splitext, exists)
+
+# Be sure that the tools directory is in the search path
+ROOT = abspath(join(dirname(__file__), ".."))
+path.insert(0, ROOT)
+
 import re
 import csv
 import json
-import argparse
+from argparse import ArgumentParser
 from copy import deepcopy
-from prettytable import PrettyTable
-
-from utils import argparse_filestring_type, \
-    argparse_lowercase_hyphen_type, argparse_uppercase_type
+from collections import defaultdict
+from prettytable import PrettyTable, HEADER
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
 
-RE_ARMCC = re.compile(
-    r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$')
-RE_IAR = re.compile(
-    r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s'
-    r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$')
-
-RE_CMDLINE_FILE_IAR = re.compile(r'^#\s+(.+\.o)')
-RE_LIBRARY_IAR = re.compile(r'^(.+\.a)\:.+$')
-RE_OBJECT_LIBRARY_IAR = re.compile(r'^\s+(.+\.o)\s.*')
-
-RE_OBJECT_FILE_GCC = re.compile(r'^(.+\/.+\.o)$')
-RE_LIBRARY_OBJECT_GCC = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$')
-RE_STD_SECTION_GCC = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$')
-RE_FILL_SECTION_GCC = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$')
-
-RE_OBJECT_ARMCC = re.compile(r'(.+\.(l|ar))\((.+\.o)\)')
+from tools.utils import (argparse_filestring_type, argparse_lowercase_hyphen_type,
+                         argparse_uppercase_type)
+from tools.settings import COMPARE_FIXED
 
 
-class MemapParser(object):
-    """An object that represents parsed results, parses the memory map files,
-    and writes out different file types of memory results
-    """
-
-    print_sections = ('.text', '.data', '.bss')
-
-    misc_flash_sections = ('.interrupts', '.flash_config')
-
-    other_sections = ('.interrupts_ram', '.init', '.ARM.extab',
+class _Parser(object):
+    """Internal interface for parsing"""
+    __metaclass__ = ABCMeta
+    SECTIONS = ('.text', '.data', '.bss', '.heap', '.stack')
+    MISC_FLASH_SECTIONS = ('.interrupts', '.flash_config')
+    OTHER_SECTIONS = ('.interrupts_ram', '.init', '.ARM.extab',
                       '.ARM.exidx', '.ARM.attributes', '.eh_frame',
                       '.init_array', '.fini_array', '.jcr', '.stab',
                       '.stabstr', '.ARM.exidx', '.ARM')
 
-    # sections to print info (generic for all toolchains)
-    sections = ('.text', '.data', '.bss', '.heap', '.stack')
-
     def __init__(self):
-        """ General initialization
-        """
-
-        # list of all modules and their sections
-        self.modules = dict()       # full list - doesn't change with depth
-        self.short_modules = dict() # short version with specific depth
-
-        # sections must be defined in this order to take irrelevant out
-        self.all_sections = self.sections + self.other_sections + \
-                            self.misc_flash_sections + ('unknown', 'OUTPUT')
-
-        # Memory report (sections + summary)
-        self.mem_report = []
-
-        # Just the memory summary section
-        self.mem_summary = dict()
-
-        self.subtotal = dict()
-
-        self.misc_flash_mem = 0
-
-        # Modules passed to the linker on the command line
-        # this is a dict because modules are looked up by their basename
-        self.cmd_modules = {}
-
+        self.modules = dict()
 
     def module_add(self, object_name, size, section):
-        """ Adds a module / section to the list
+        """ Adds a module or section to the list
 
         Positional arguments:
         object_name - name of the entry to add
         size - the size of the module being added
         section - the section the module contributes to
         """
-
         if not object_name or not size or not section:
             return
 
@@ -93,14 +57,15 @@
             self.modules[object_name][section] += size
             return
 
-        obj_split = os.sep + os.path.basename(object_name)
+        obj_split = sep + basename(object_name)
         for module_path, contents in self.modules.items():
             if module_path.endswith(obj_split) or module_path == object_name:
                 contents.setdefault(section, 0)
                 contents[section] += size
                 return
 
-        new_module = {section: size}
+        new_module = defaultdict(int)
+        new_module[section] = size
         self.modules[object_name] = new_module
 
     def module_replace(self, old_object, new_object):
@@ -110,15 +75,38 @@
             self.modules[new_object] = self.modules[old_object]
             del self.modules[old_object]
 
-    def check_new_section_gcc(self, line):
-        """ Check whether a new section in a map file has been detected (only
-        applies to gcc)
+    @abstractmethod
+    def parse_mapfile(self, mapfile):
+        """Parse a given file object pointing to a map file
+
+        Positional arguments:
+        mapfile - an open file object that reads a map file
+
+        return value - a dict mapping from object names to section dicts,
+                       where a section dict maps from sections to sizes
+        """
+        raise NotImplemented
+
+
+class _GccParser(_Parser):
+    RE_OBJECT_FILE = re.compile(r'^(.+\/.+\.o)$')
+    RE_LIBRARY_OBJECT = re.compile(r'^.+' + r''.format(sep) + r'lib((.+\.a)\((.+\.o)\))$')
+    RE_STD_SECTION = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$')
+    RE_FILL_SECTION = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$')
+
+    ALL_SECTIONS = _Parser.SECTIONS + _Parser.OTHER_SECTIONS + \
+                   _Parser.MISC_FLASH_SECTIONS + ('unknown', 'OUTPUT')
+
+    def check_new_section(self, line):
+        """ Check whether a new section in a map file has been detected
 
         Positional arguments:
         line - the line to check for a new section
+
+        return value - A section name, if a new section was found, False
+                       otherwise
         """
-
-        for i in self.all_sections:
+        for i in self.ALL_SECTIONS:
             if line.startswith(i):
                 # should name of the section (assuming it's a known one)
                 return i
@@ -129,72 +117,65 @@
             return False         # everything else, means no change in section
 
 
-    def parse_object_name_gcc(self, line):
+    def parse_object_name(self, line):
         """ Parse a path to object file
 
         Positional arguments:
-        txt - the path to parse the object and module name from
-        """
+        line - the path to parse the object and module name from
 
-        line = line.replace('\\', '/')
-        test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line)
+        return value - an object file name
+        """
+        test_re_mbed_os_name = re.match(self.RE_OBJECT_FILE, line)
 
         if test_re_mbed_os_name:
-
             object_name = test_re_mbed_os_name.group(1)
 
             # corner case: certain objects are provided by the GCC toolchain
             if 'arm-none-eabi' in line:
-                return '[lib]/misc/' + object_name
+                return join('[lib]', 'misc', basename(object_name))
             return object_name
 
         else:
-
-            test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line)
+            test_re_obj_name = re.match(self.RE_LIBRARY_OBJECT, line)
 
             if test_re_obj_name:
-                object_name = test_re_obj_name.group(1) + '/' + \
-                              test_re_obj_name.group(2)
-
-                return '[lib]/' + object_name
-
+                return join('[lib]', test_re_obj_name.group(2),
+                            test_re_obj_name.group(3))
             else:
-                print "Unknown object name found in GCC map file: %s" % line
+                print("Unknown object name found in GCC map file: %s" % line)
                 return '[misc]'
 
-    def parse_section_gcc(self, line):
+    def parse_section(self, line):
         """ Parse data from a section of gcc map file
 
         examples:
                         0x00004308       0x7c ./BUILD/K64F/GCC_ARM/mbed-os/hal/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.o
-         .text          0x00000608      0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/HAL_CM4.o
+         .text          0x00000608      0x198 ./BUILD/K64F/GCC_ARM/mbed-os/core/mbed-rtos/rtx/TARGET_CORTEX_M/TARGET_RTOS_M4_M7/TOOLCHAIN/HAL_CM4.o
 
         Positional arguments:
         line - the line to parse a section from
         """
-
-        is_fill = re.match(RE_FILL_SECTION_GCC, line)
+        is_fill = re.match(self.RE_FILL_SECTION, line)
         if is_fill:
             o_name = '[fill]'
             o_size = int(is_fill.group(2), 16)
             return [o_name, o_size]
 
-        is_section = re.match(RE_STD_SECTION_GCC, line)
+        is_section = re.match(self.RE_STD_SECTION, line)
         if is_section:
             o_size = int(is_section.group(2), 16)
             if o_size:
-                o_name = self.parse_object_name_gcc(is_section.group(3))
+                o_name = self.parse_object_name(is_section.group(3))
                 return [o_name, o_size]
 
         return ["", 0]
 
-    def parse_map_file_gcc(self, file_desc):
+    def parse_mapfile(self, file_desc):
         """ Main logic to decode gcc map files
 
         Positional arguments:
         file_desc - a stream object to parse as a gcc map file
         """
-
         current_section = 'unknown'
 
         with file_desc as infile:
@@ -204,97 +185,141 @@
                     break
 
             for line in infile:
-                next_section = self.check_new_section_gcc(line)
+                next_section = self.check_new_section(line)
 
                 if next_section == "OUTPUT":
                     break
                 elif next_section:
                     current_section = next_section
 
-                object_name, object_size = self.parse_section_gcc(line)
-
+                object_name, object_size = self.parse_section(line)
                 self.module_add(object_name, object_size, current_section)
 
-        common_prefix = os.path.dirname(os.path.commonprefix([
+        common_prefix = dirname(commonprefix([
             o for o in self.modules.keys() if (o.endswith(".o") and not o.startswith("[lib]"))]))
         new_modules = {}
         for name, stats in self.modules.items():
             if name.startswith("[lib]"):
                 new_modules[name] = stats
             elif name.endswith(".o"):
-                new_modules[os.path.relpath(name, common_prefix)] = stats
+                new_modules[relpath(name, common_prefix)] = stats
             else:
                 new_modules[name] = stats
-        self.modules = new_modules
+        return new_modules
+
 
-    def parse_object_name_armcc(self, line):
+class _ArmccParser(_Parser):
+    RE = re.compile(
+        r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$')
+    RE_OBJECT = re.compile(r'(.+\.(l|ar))\((.+\.o)\)')
+
+    def parse_object_name(self, line):
         """ Parse object file
 
         Positional arguments:
         line - the line containing the object or library
         """
-
-        # simple object (not library)
-        if line[-2] == '.' and line[-1] == 'o':
+        if line.endswith(".o"):
             return line
 
         else:
-            is_obj = re.match(RE_OBJECT_ARMCC, line)
+            is_obj = re.match(self.RE_OBJECT, line)
             if is_obj:
-                object_name = os.path.basename(is_obj.group(1)) + '/' + is_obj.group(3)
-                return '[lib]/' + object_name
+                return join('[lib]', basename(is_obj.group(1)), is_obj.group(3))
             else:
-                print "Malformed input found when parsing ARMCC map: %s" % line
+                print("Malformed input found when parsing ARMCC map: %s" % line)
                 return '[misc]'
 
-
-
-    def parse_section_armcc(self, line):
+    def parse_section(self, line):
         """ Parse data from an armcc map file
 
         Examples of armcc map file:
             Base_Addr    Size         Type   Attr      Idx    E Section Name        Object
-            0x00000000   0x00000400   Data   RO        11222    RESET               startup_MK64F12.o
+            0x00000000   0x00000400   Data   RO        11222    self.RESET               startup_MK64F12.o
             0x00000410   0x00000008   Code   RO        49364  * !!!main             c_w.l(__main.o)
 
         Positional arguments:
         line - the line to parse the section data from
         """
-
-        test_re_armcc = re.match(RE_ARMCC, line)
+        test_re = re.match(self.RE, line)
 
-        if test_re_armcc:
+        if test_re:
+            size = int(test_re.group(2), 16)
 
-            size = int(test_re_armcc.group(2), 16)
-
-            if test_re_armcc.group(4) == 'RO':
+            if test_re.group(4) == 'RO':
                 section = '.text'
             else:
-                if test_re_armcc.group(3) == 'Data':
+                if test_re.group(3) == 'Data':
                     section = '.data'
-                elif test_re_armcc.group(3) == 'Zero':
+                elif test_re.group(3) == 'Zero':
                     section = '.bss'
+                elif test_re.group(3) == 'Code':
+                    section = '.text'
                 else:
-                    print "Malformed input found when parsing armcc map: %s" %\
-                          line
+                    print("Malformed input found when parsing armcc map: %s, %r"
+                          % (line, test_re.groups()))
+
+                    return ["", 0, ""]
 
             # check name of object or library
-            object_name = self.parse_object_name_armcc(\
-                test_re_armcc.group(6))
+            object_name = self.parse_object_name(
+                test_re.group(6))
 
             return [object_name, size, section]
 
         else:
             return ["", 0, ""]
 
-    def parse_object_name_iar(self, object_name):
+    def parse_mapfile(self, file_desc):
+        """ Main logic to decode armc5 map files
+
+        Positional arguments:
+        file_desc - a file like object to parse as an armc5 map file
+        """
+        with file_desc as infile:
+            # Search area to parse
+            for line in infile:
+                if line.startswith('    Base Addr    Size'):
+                    break
+
+            # Start decoding the map file
+            for line in infile:
+                self.module_add(*self.parse_section(line))
+
+        common_prefix = dirname(commonprefix([
+            o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))]))
+        new_modules = {}
+        for name, stats in self.modules.items():
+            if name == "anon$$obj.o" or name.startswith("[lib]"):
+                new_modules[name] = stats
+            elif name.endswith(".o"):
+                new_modules[relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        return new_modules
+
+
+class _IarParser(_Parser):
+    RE = re.compile(
+        r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s'
+        r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$')
+
+    RE_CMDLINE_FILE = re.compile(r'^#\s+(.+\.o)')
+    RE_LIBRARY = re.compile(r'^(.+\.a)\:.+$')
+    RE_OBJECT_LIBRARY = re.compile(r'^\s+(.+\.o)\s.*')
+
+    def __init__(self):
+        _Parser.__init__(self)
+        # Modules passed to the linker on the command line
+        # this is a dict because modules are looked up by their basename
+        self.cmd_modules = {}
+
+    def parse_object_name(self, object_name):
         """ Parse object file
 
         Positional arguments:
         line - the line containing the object or library
         """
-
-        # simple object (not library)
         if object_name.endswith(".o"):
             try:
                 return self.cmd_modules[object_name]
@@ -303,8 +328,7 @@
         else:
             return '[misc]'
 
-
-    def parse_section_iar(self, line):
+    def parse_section(self, line):
         """ Parse data from an IAR map file
 
         Examples of IAR map file:
@@ -321,86 +345,48 @@
         Positional_arguments:
         line - the line to parse section data from
         """
-
-        test_re_iar = re.match(RE_IAR, line)
-
-        if test_re_iar:
-
-            size = int(test_re_iar.group(4), 16)
-
-            if (test_re_iar.group(2) == 'const' or
-                test_re_iar.group(2) == 'ro code'):
+        test_re = re.match(self.RE, line)
+        if test_re:
+            if (test_re.group(2) == 'const' or
+                test_re.group(2) == 'ro code'):
                 section = '.text'
-            elif (test_re_iar.group(2) == 'zero' or
-                  test_re_iar.group(2) == 'uninit'):
-                if test_re_iar.group(1)[0:4] == 'HEAP':
+            elif (test_re.group(2) == 'zero' or
+                  test_re.group(2) == 'uninit'):
+                if test_re.group(1)[0:4] == 'HEAP':
                     section = '.heap'
-                elif test_re_iar.group(1)[0:6] == 'CSTACK':
+                elif test_re.group(1)[0:6] == 'CSTACK':
                     section = '.stack'
                 else:
                     section = '.bss' #  default section
 
-            elif test_re_iar.group(2) == 'inited':
+            elif test_re.group(2) == 'inited':
                 section = '.data'
             else:
-                print "Malformed input found when parsing IAR map: %s" % line
+                print("Malformed input found when parsing IAR map: %s" % line)
+                return ["", 0, ""]
 
             # lookup object in dictionary and return module name
-            object_name = self.parse_object_name_iar(test_re_iar.group(5))
+            object_name = self.parse_object_name(test_re.group(5))
 
+            size = int(test_re.group(4), 16)
             return [object_name, size, section]
 
         else:
-            return ["", 0, ""] # no valid entry
-
-    def parse_map_file_armcc(self, file_desc):
-        """ Main logic to decode armc5 map files
-
-        Positional arguments:
-        file_desc - a file like object to parse as an armc5 map file
-        """
-
-        with file_desc as infile:
-
-            # Search area to parse
-            for line in infile:
-                if line.startswith('    Base Addr    Size'):
-                    break
+            return ["", 0, ""]
 
-            # Start decoding the map file
-            for line in infile:
-                self.module_add(*self.parse_section_armcc(line))
-
-        common_prefix = os.path.dirname(os.path.commonprefix([
-            o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))]))
-        new_modules = {}
-        for name, stats in self.modules.items():
-            if name == "anon$$obj.o" or name.startswith("[lib]"):
-                new_modules[name] = stats
-            elif name.endswith(".o"):
-                new_modules[os.path.relpath(name, common_prefix)] = stats
-            else:
-                new_modules[name] = stats
-        self.modules = new_modules
-
-
-
-    def check_new_library_iar(self, line):
+    def check_new_library(self, line):
         """
         Searches for libraries and returns name. Example:
         m7M_tls.a: [43]
 
         """
-
-
-        test_address_line = re.match(RE_LIBRARY_IAR, line)
-
+        test_address_line = re.match(self.RE_LIBRARY, line)
         if test_address_line:
             return test_address_line.group(1)
         else:
             return ""
 
-    def check_new_object_lib_iar(self, line):
+    def check_new_object_lib(self, line):
         """
         Searches for objects within a library section and returns name. Example:
         rt7M_tl.a: [44]
@@ -411,15 +397,13 @@
             I64DivZer.o                  2
 
         """
-
-        test_address_line = re.match(RE_OBJECT_LIBRARY_IAR, line)
-
+        test_address_line = re.match(self.RE_OBJECT_LIBRARY, line)
         if test_address_line:
             return test_address_line.group(1)
         else:
             return ""
 
-    def parse_iar_command_line(self, lines):
+    def parse_command_line(self, lines):
         """Parse the files passed on the command line to the iar linker
 
         Positional arguments:
@@ -428,51 +412,87 @@
         for line in lines:
             if line.startswith("*"):
                 break
-            is_cmdline_file = RE_CMDLINE_FILE_IAR.match(line)
-            if is_cmdline_file:
-                full_path = is_cmdline_file.group(1)
-                self.cmd_modules[os.path.basename(full_path)] = full_path
+            for arg in line.split(" "):
+                arg = arg.rstrip(" \n")
+                if (not arg.startswith("-")) and arg.endswith(".o"):
+                    self.cmd_modules[basename(arg)] = arg
 
-        common_prefix = os.path.dirname(os.path.commonprefix(self.cmd_modules.values()))
-        self.cmd_modules = {s: os.path.relpath(f, common_prefix)
+        common_prefix = dirname(commonprefix(list(self.cmd_modules.values())))
+        self.cmd_modules = {s: relpath(f, common_prefix)
                             for s, f in self.cmd_modules.items()}
 
-
-    def parse_map_file_iar(self, file_desc):
+    def parse_mapfile(self, file_desc):
         """ Main logic to decode IAR map files
 
         Positional arguments:
         file_desc - a file like object to parse as an IAR map file
         """
-
         with file_desc as infile:
-            self.parse_iar_command_line(infile)
+            self.parse_command_line(infile)
 
             for line in infile:
                 if line.startswith('  Section  '):
                     break
 
             for line in infile:
-                self.module_add(*self.parse_section_iar(line))
+                self.module_add(*self.parse_section(line))
 
                 if line.startswith('*** MODULE SUMMARY'): # finish section
                     break
 
             current_library = ""
             for line in infile:
-
-                library = self.check_new_library_iar(line)
+                library = self.check_new_library(line)
 
                 if library:
                     current_library = library
 
-                object_name = self.check_new_object_lib_iar(line)
+                object_name = self.check_new_object_lib(line)
 
                 if object_name and current_library:
-                    temp = '[lib]' + '/'+ current_library + '/'+ object_name
+                    temp = join('[lib]', current_library, object_name)
                     self.module_replace(object_name, temp)
+        return self.modules
 
 
+class MemapParser(object):
+    """An object that represents parsed results, parses the memory map files,
+    and writes out different file types of memory results
+    """
+
+    print_sections = ('.text', '.data', '.bss')
+    delta_sections = ('.text-delta', '.data-delta', '.bss-delta')
+
+
+    # sections to print info (generic for all toolchains)
+    sections = _Parser.SECTIONS
+    misc_flash_sections = _Parser.MISC_FLASH_SECTIONS
+    other_sections = _Parser.OTHER_SECTIONS
+
+    def __init__(self):
+        # list of all modules and their sections
+        # full list - doesn't change with depth
+        self.modules = dict()
+        self.old_modules = None
+        # short version with specific depth
+        self.short_modules = dict()
+
+
+        # Memory report (sections + summary)
+        self.mem_report = []
+
+        # Memory summary
+        self.mem_summary = dict()
+
+        # Totals of ".text", ".data" and ".bss"
+        self.subtotal = dict()
+
+        # Flash no associated with a module
+        self.misc_flash_mem = 0
+
+        # Name of the toolchain, for better headings
+        self.tc_name = None
+
     def reduce_depth(self, depth):
         """
         populates the short_modules attribute with a truncated module list
@@ -492,17 +512,25 @@
         else:
             self.short_modules = dict()
             for module_name, v in self.modules.items():
-                split_name = module_name.split('/')
+                split_name = module_name.split(sep)
                 if split_name[0] == '':
                     split_name = split_name[1:]
-                new_name = "/".join(split_name[:depth])
-                self.short_modules.setdefault(new_name, {})
+                new_name = join(*split_name[:depth])
+                self.short_modules.setdefault(new_name, defaultdict(int))
                 for section_idx, value in v.items():
-                    self.short_modules[new_name].setdefault(section_idx, 0)
                     self.short_modules[new_name][section_idx] += self.modules[module_name][section_idx]
+                    self.short_modules[new_name][section_idx + '-delta'] += self.modules[module_name][section_idx]
+            if self.old_modules:
+                for module_name, v in self.old_modules.items():
+                    split_name = module_name.split(sep)
+                    if split_name[0] == '':
+                        split_name = split_name[1:]
+                    new_name = join(*split_name[:depth])
+                    self.short_modules.setdefault(new_name, defaultdict(int))
+                    for section_idx, value in v.items():
+                        self.short_modules[new_name][section_idx + '-delta'] -= self.old_modules[module_name][section_idx]
 
-
-    export_formats = ["json", "csv-ci", "table"]
+    export_formats = ["json", "csv-ci", "html", "table"]
 
     def generate_output(self, export_format, depth, file_output=None):
         """ Generates summary of memory map data
@@ -516,29 +544,135 @@
 
         Returns: generated string for the 'table' format, otherwise None
         """
-
-        self.reduce_depth(depth)
+        if depth is None or depth > 0:
+            self.reduce_depth(depth)
         self.compute_report()
-
         try:
             if file_output:
-                file_desc = open(file_output, 'wb')
+                file_desc = open(file_output, 'w')
             else:
-                file_desc = sys.stdout
+                file_desc = stdout
         except IOError as error:
-            print "I/O error({0}): {1}".format(error.errno, error.strerror)
+            print("I/O error({0}): {1}".format(error.errno, error.strerror))
             return False
 
         to_call = {'json': self.generate_json,
+                   'html': self.generate_html,
                    'csv-ci': self.generate_csv,
                    'table': self.generate_table}[export_format]
         output = to_call(file_desc)
 
-        if file_desc is not sys.stdout:
+        if file_desc is not stdout:
             file_desc.close()
 
         return output
 
+    @staticmethod
+    def _move_up_tree(tree, next_module):
+        tree.setdefault("children", [])
+        for child in tree["children"]:
+            if child["name"] == next_module:
+                return child
+        else:
+            new_module = {"name": next_module, "value": 0, "delta": 0}
+            tree["children"].append(new_module)
+            return new_module
+
+    def generate_html(self, file_desc):
+        """Generate a json file from a memory map for D3
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+        tree_text = {"name": ".text", "value": 0, "delta": 0}
+        tree_bss = {"name": ".bss", "value": 0, "delta": 0}
+        tree_data = {"name": ".data", "value": 0, "delta": 0}
+        for name, dct in self.modules.items():
+            cur_text = tree_text
+            cur_bss = tree_bss
+            cur_data = tree_data
+            modules = name.split(sep)
+            while True:
+                try:
+                    cur_text["value"] += dct['.text']
+                    cur_text["delta"] += dct['.text']
+                except KeyError:
+                    pass
+                try:
+                    cur_bss["value"] += dct['.bss']
+                    cur_bss["delta"] += dct['.bss']
+                except KeyError:
+                    pass
+                try:
+                    cur_data["value"] += dct['.data']
+                    cur_data["delta"] += dct['.data']
+                except KeyError:
+                    pass
+                if not modules:
+                    break
+                next_module = modules.pop(0)
+                cur_text = self._move_up_tree(cur_text, next_module)
+                cur_data = self._move_up_tree(cur_data, next_module)
+                cur_bss = self._move_up_tree(cur_bss, next_module)
+        if self.old_modules:
+            for name, dct in self.old_modules.items():
+                cur_text = tree_text
+                cur_bss = tree_bss
+                cur_data = tree_data
+                modules = name.split(sep)
+                while True:
+                    try:
+                        cur_text["delta"] -= dct['.text']
+                    except KeyError:
+                        pass
+                    try:
+                        cur_bss["delta"] -= dct['.bss']
+                    except KeyError:
+                        pass
+                    try:
+                        cur_data["delta"] -= dct['.data']
+                    except KeyError:
+                        pass
+                    if not modules:
+                        break
+                    next_module = modules.pop(0)
+                    if not any(cld['name'] == next_module for cld in cur_text['children']):
+                        break
+                    cur_text = self._move_up_tree(cur_text, next_module)
+                    cur_data = self._move_up_tree(cur_data, next_module)
+                    cur_bss = self._move_up_tree(cur_bss, next_module)
+
+        tree_rom = {
+            "name": "ROM",
+            "value": tree_text["value"] + tree_data["value"],
+            "delta": tree_text["delta"] + tree_data["delta"],
+            "children": [tree_text, tree_data]
+        }
+        tree_ram = {
+            "name": "RAM",
+            "value": tree_bss["value"] + tree_data["value"],
+            "delta": tree_bss["delta"] + tree_data["delta"],
+            "children": [tree_bss, tree_data]
+        }
+
+        jinja_loader = FileSystemLoader(dirname(abspath(__file__)))
+        jinja_environment = Environment(loader=jinja_loader,
+                                        undefined=StrictUndefined)
+
+        template = jinja_environment.get_template("memap_flamegraph.html")
+        name, _ = splitext(basename(file_desc.name))
+        if name.endswith("_map"):
+            name = name[:-4]
+        if self.tc_name:
+            name = "%s %s" % (name, self.tc_name)
+        data = {
+            "name": name,
+            "rom": json.dumps(tree_rom),
+            "ram": json.dumps(tree_ram),
+        }
+        file_desc.write(template.render(data))
+        return None
+
     def generate_json(self, file_desc):
         """Generate a json file from a memory map
 
@@ -547,8 +681,15 @@
         """
         file_desc.write(json.dumps(self.mem_report, indent=4))
         file_desc.write('\n')
+        return None
 
-        return None
+    RAM_FORMAT_STR = (
+        "Total Static RAM memory (data + bss): {}({:+}) bytes\n"
+    )
+
+    ROM_FORMAT_STR = (
+        "Total Flash memory (text + data): {}({:+}) bytes\n"
+    )
 
     def generate_csv(self, file_desc):
         """Generate a CSV file from a memoy map
@@ -556,25 +697,24 @@
         Positional arguments:
         file_desc - the file to write out the final report to
         """
-        csv_writer = csv.writer(file_desc, delimiter=',',
-                                quoting=csv.QUOTE_MINIMAL)
-
-        csv_module_section = []
-        csv_sizes = []
-        for i in sorted(self.short_modules):
-            for k in self.print_sections:
-                csv_module_section += [i+k]
-                csv_sizes += [self.short_modules[i][k]]
+        writer = csv.writer(file_desc, delimiter=',',
+                            quoting=csv.QUOTE_MINIMAL)
 
-        csv_module_section += ['static_ram']
-        csv_sizes += [self.mem_summary['static_ram']]
+        module_section = []
+        sizes = []
+        for i in sorted(self.short_modules):
+            for k in self.print_sections + self.delta_sections:
+                module_section.append((i + k))
+                sizes += [self.short_modules[i][k]]
 
-        csv_module_section += ['total_flash']
-        csv_sizes += [self.mem_summary['total_flash']]
+        module_section.append('static_ram')
+        sizes.append(self.mem_summary['static_ram'])
 
-        csv_writer.writerow(csv_module_section)
-        csv_writer.writerow(csv_sizes)
+        module_section.append('total_flash')
+        sizes.append(self.mem_summary['total_flash'])
 
+        writer.writerow(module_section)
+        writer.writerow(sizes)
         return None
 
     def generate_table(self, file_desc):
@@ -586,7 +726,7 @@
         columns = ['Module']
         columns.extend(self.print_sections)
 
-        table = PrettyTable(columns)
+        table = PrettyTable(columns, junction_char="|", hrules=HEADER)
         table.align["Module"] = "l"
         for col in self.print_sections:
             table.align[col] = 'r'
@@ -598,23 +738,29 @@
             row = [i]
 
             for k in self.print_sections:
-                row.append(self.short_modules[i][k])
+                row.append("{}({:+})".format(self.short_modules[i][k],
+                                             self.short_modules[i][k + "-delta"]))
 
             table.add_row(row)
 
         subtotal_row = ['Subtotals']
         for k in self.print_sections:
-            subtotal_row.append(self.subtotal[k])
+            subtotal_row.append("{}({:+})".format(
+                self.subtotal[k], self.subtotal[k + '-delta']))
 
         table.add_row(subtotal_row)
 
         output = table.get_string()
         output += '\n'
 
-        output += "Total Static RAM memory (data + bss): %s bytes\n" % \
-                        str(self.mem_summary['static_ram'])
-        output += "Total Flash memory (text + data): %s bytes\n" % \
-                        str(self.mem_summary['total_flash'])
+        output += self.RAM_FORMAT_STR.format(
+            self.mem_summary['static_ram'],
+            self.mem_summary['static_ram_delta']
+        )
+        output += self.ROM_FORMAT_STR.format(
+            self.mem_summary['total_flash'],
+            self.mem_summary['total_flash_delta']
+        )
 
         return output
 
@@ -623,27 +769,36 @@
     def compute_report(self):
         """ Generates summary of memory usage for main areas
         """
-        for k in self.sections:
-            self.subtotal[k] = 0
+        self.subtotal = defaultdict(int)
 
-        for i in self.short_modules:
+        for mod in self.modules.values():
             for k in self.sections:
-                self.short_modules[i].setdefault(k, 0)
-                self.subtotal[k] += self.short_modules[i][k]
+                self.subtotal[k] += mod[k]
+                self.subtotal[k + '-delta'] += mod[k]
+        if self.old_modules:
+            for mod in self.old_modules.values():
+                for k in self.sections:
+                    self.subtotal[k + '-delta'] -= mod[k]
 
         self.mem_summary = {
-            'static_ram': (self.subtotal['.data'] + self.subtotal['.bss']),
+            'static_ram': self.subtotal['.data'] + self.subtotal['.bss'],
+            'static_ram_delta':
+            self.subtotal['.data-delta'] + self.subtotal['.bss-delta'],
             'total_flash': (self.subtotal['.text'] + self.subtotal['.data']),
+            'total_flash_delta':
+            self.subtotal['.text-delta'] + self.subtotal['.data-delta'],
         }
 
         self.mem_report = []
-        for i in sorted(self.short_modules):
-            self.mem_report.append({
-                "module":i,
-                "size":{
-                    k: self.short_modules[i][k] for k in self.print_sections
-                }
-            })
+        if self.short_modules:
+            for name, sizes in sorted(self.short_modules.items()):
+                self.mem_report.append({
+                    "module": name,
+                    "size":{
+                        k: sizes.get(k, 0) for k in (self.print_sections +
+                                                     self.delta_sections)
+                    }
+                })
 
         self.mem_report.append({
             'summary': self.mem_summary
@@ -656,31 +811,40 @@
         mapfile - the file name of the memory map file
         toolchain - the toolchain used to create the file
         """
-
-        result = True
+        self.tc_name = toolchain.title()
+        if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"):
+            parser = _ArmccParser
+        elif toolchain == "GCC_ARM" or toolchain == "GCC_CR":
+            parser = _GccParser
+        elif toolchain == "IAR":
+            parser = _IarParser
+        else:
+            return False
         try:
             with open(mapfile, 'r') as file_input:
-                if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"):
-                    self.parse_map_file_armcc(file_input)
-                elif toolchain == "GCC_ARM" or toolchain == "GCC_CR":
-                    self.parse_map_file_gcc(file_input)
-                elif toolchain == "IAR":
-                    self.parse_map_file_iar(file_input)
-                else:
-                    result = False
+                self.modules = parser().parse_mapfile(file_input)
+            try:
+                with open("%s.old" % mapfile, 'r') as old_input:
+                    self.old_modules = parser().parse_mapfile(old_input)
+            except IOError:
+                self.old_modules = None
+            if not COMPARE_FIXED:
+                old_mapfile = "%s.old" % mapfile
+                if exists(old_mapfile):
+                    remove(old_mapfile)
+                rename(mapfile, old_mapfile)
+            return True
 
         except IOError as error:
-            print "I/O error({0}): {1}".format(error.errno, error.strerror)
-            result = False
-        return result
+            print("I/O error({0}): {1}".format(error.errno, error.strerror))
+            return False
 
 def main():
     """Entry Point"""
-
     version = '0.4.0'
 
     # Parser handling
-    parser = argparse.ArgumentParser(
+    parser = ArgumentParser(
         description="Memory Map File Analyser for ARM mbed\nversion %s" %
         version)
 
@@ -711,9 +875,9 @@
     parser.add_argument('-v', '--version', action='version', version=version)
 
     # Parse/run command
-    if len(sys.argv) <= 1:
+    if len(argv) <= 1:
         parser.print_help()
-        sys.exit(1)
+        exit(1)
 
     args = parser.parse_args()
 
@@ -723,7 +887,7 @@
     # Parse and decode a map file
     if args.file and args.toolchain:
         if memap.parse(args.file, args.toolchain) is False:
-            sys.exit(0)
+            exit(0)
 
     if args.depth is None:
         depth = 2  # default depth level
@@ -739,9 +903,9 @@
         returned_string = memap.generate_output(args.export, depth)
 
     if args.export == 'table' and returned_string:
-        print returned_string
+        print(returned_string)
 
-    sys.exit(0)
+    exit(0)
 
 if __name__ == "__main__":
     main()
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/memap_flamegraph.html	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,122 @@
+<!DOCTYPE html>
+<html lang="en">
+  <head>
+    <meta charset="utf-8">
+    <meta http-equiv="X-UA-Compatible" content="IE=edge">
+    <meta name="viewport" content="width=device-width, initial-scale=1">
+    
+    <link rel="stylesheet" type="text/css" 
+      href="https://maxcdn.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css" 
+      integrity="sha256-916EbMg70RQy9LHiGkXzG8hSg9EdNy97GazNG/aiY1w=" 
+      crossorigin="anonymous" 
+    />
+    <link rel="stylesheet" type="text/css" 
+      href="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.css" 
+      integrity="sha256-w762vSe6WGrkVZ7gEOpnn2Y+FSmAGlX77jYj7nhuCyY=" 
+      crossorigin="anonymous" 
+    />
+
+    <style>
+    /* Space out content a bit */
+    body {
+      padding-top: 20px;
+      padding-bottom: 20px;
+    }
+    /* Custom page header */
+    .header {
+      padding-bottom: 20px;
+      padding-right: 15px;
+      padding-left: 15px;
+      border-bottom: 1px solid #e5e5e5;
+    }
+    /* Make the masthead heading the same height as the navigation */
+    .header h3 {
+      margin-top: 0;
+      margin-bottom: 0;
+      line-height: 40px;
+    }
+    </style>
+
+    <title>{{name}} Memory Details</title>
+
+    <!-- HTML5 shim and Respond.js for IE8 support of HTML5 elements and media queries -->
+    <!--[if lt IE 9]>
+      <script src="https://oss.maxcdn.com/html5shiv/3.7.2/html5shiv.min.js" integrity="sha256-4OrICDjBYfKefEbVT7wETRLNFkuq4TJV5WLGvjqpGAk=" crossorigin="anonymous"></script>
+      <script src="https://oss.maxcdn.com/respond/1.4.2/respond.min.js" integrity="sha256-g6iAfvZp+nDQ2TdTR/VVKJf3bGro4ub5fvWSWVRi2NE=" crossorigin="anonymous"></script>
+    <![endif]-->
+  </head>
+  <body>
+    <div class="container">
+      <div class="header clearfix">
+        <h3 class="text-muted">{{name}} Memory Details</h3>
+      </div>
+      <div id="chart-rom">
+      </div>
+      <hr/>
+      <div id="chart-ram">
+      </div>
+      <hr/>
+      <div id="details"></div>
+    </div>
+
+    <script type="text/javascript" 
+      src="https://cdnjs.cloudflare.com/ajax/libs/d3/4.10.0/d3.min.js" 
+      integrity="sha256-r7j1FXNTvPzHR41+V71Jvej6fIq4v4Kzu5ee7J/RitM=" 
+      crossorigin="anonymous">
+    </script>
+    <script type="text/javascript" 
+      src="https://cdnjs.cloudflare.com/ajax/libs/d3-tip/0.7.1/d3-tip.min.js" 
+      integrity="sha256-z0A2CQF8xxCKuOJsn4sJ5HBjxiHHRAfTX8hDF4RSN5s=" 
+      crossorigin="anonymous">
+    </script>
+    <script type="text/javascript" 
+      src="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.js" 
+      integrity="sha256-I1CkrWbmjv+GWjgbulJ4i0vbzdrDGfxqdye2qNlhG3Q=" 
+      crossorigin="anonymous">
+    </script>
+
+    <script type="text/javascript">
+    var tip = d3.tip()
+      .direction("s")
+      .offset([8, 0])
+      .attr('class', 'd3-flame-graph-tip')
+      .html(function(d) { return "module: " + d.data.name + ", bytes: " + d.data.value + ", delta: " + d.data.delta; });
+    var colorizer = function (d) {
+        if (d.data.delta > 0) {
+            ratio = (d.data.value - d.data.delta) / d.data.value;
+            green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+            blue = ("0" + (Number(ratio * 0xEE | 0).toString(16))).slice(-2).toUpperCase();
+            console.log(d.data.name, green, blue);
+            return "#EE" + green + blue
+        } else if (d.data.delta < 0) {
+            ratio = (d.data.value + d.data.delta) / d.data.value;
+            green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+            red = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+            console.log(d.data.name, red, green);
+            return "#" + red + green + "EE";
+        } else {
+            return "#FFFFEE";
+        }
+    }
+    var flameGraph_rom = d3.flameGraph()
+      .transitionDuration(250)
+      .transitionEase(d3.easeCubic)
+      .sort(true)
+      .color(colorizer)
+      .tooltip(tip);
+    var flameGraph_ram = d3.flameGraph()
+      .transitionDuration(250)
+      .transitionEase(d3.easeCubic)
+      .sort(true)
+      .color(colorizer)
+      .tooltip(tip);
+    var rom_elem = d3.select("#chart-rom");
+    flameGraph_rom.width(rom_elem.node().getBoundingClientRect().width);
+    rom_elem.datum({{rom}}).call(flameGraph_rom);
+    var ram_elem = d3.select("#chart-ram");
+    flameGraph_ram.width(ram_elem.node().getBoundingClientRect().width);
+    ram_elem.datum({{ram}}).call(flameGraph_ram);
+    </script>
+  </body>
+</html>
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/notifier/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,106 @@
+# mbed SDK
+# Copyright (c) 2011-2013 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import print_function, division, absolute_import
+
+from abc import ABCMeta, abstractmethod
+
+
+class Notifier(object):
+    """
+    Notifiers send build system events to a front end or may implement a front
+    end themselves, displaying warnings and errors for a user.
+
+    This is different from a logger in a few ways:
+     * The structure of the events are defined by this interface.
+     * A "progress" level is included allowing signaling completion status to
+       users.
+     * It's tailored to providing events from a build system.
+
+    The structure of a message is a dict with a 'type' key. The type key
+    determines the remaining keys as follows:
+      type       | description and remaining keys
+      ---------- | ------------------------------
+      info       | A simple message. The 'message' key contains the message
+      debug      | Another simple message; this one is less useful when compiles
+                 | are working. Again, the 'message' key contains the message
+      progress   | A progress indicator, which may include progress as a
+                 | percentage. The action key includes what action was taken to
+                 | make this progress, the file key what file was used to make
+                 | this progress, and the percent key, when present, indicates
+                 | how far along the build is.
+      tool_error | When a compile fails, this contains the entire output of the
+                 | compiler.
+      var        | Provides a key, in the 'key' key, and a value, in the 'value'
+                 | key, for use in a UI. At the time of writing it's used to
+                 | communicate the binary location to the online IDE.
+    """
+
+    __metaclass__ = ABCMeta
+
+    @abstractmethod
+    def notify(self, event):
+        """
+        Send the user a notification specified in the event.
+        """
+        raise NotImplemented
+
+    def info(self, message):
+        """
+        Send the user a simple message.
+        """
+        self.notify({'type': 'info', 'message': message})
+
+    def debug(self, message):
+        """
+        Send a debug message to the user.
+        """
+        if isinstance(message, list):
+            message = ' '.join(message)
+        self.notify({'type': 'debug', 'message': message})
+
+    def cc_info(self, info=None):
+        if info is not None:
+            info['type'] = 'cc'
+            self.notify(info)
+
+    def cc_verbose(self, message, file=""):
+        self.notify({
+            'type': 'cc',
+            'severity': 'verbose',
+            'file': file,
+            'message': message
+        })
+
+    def progress(self, action, file, percent=None):
+        """
+        Indicate compilation progress to a user.
+        """
+        msg = {'type': 'progress', 'action': action, 'file': file}
+        if percent:
+            msg['percent'] = percent
+        self.notify(msg)
+
+    def tool_error(self, message):
+        """
+        Communicate a full fatal error to a user.
+        """
+        self.notify({'type': 'tool_error', 'message': message})
+
+    def var(self, key, value):
+        """
+        Update a UI with a key, value pair
+        """
+        self.notify({'type': 'var', 'key': key, 'val': value})
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/notifier/mock.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,27 @@
+# mbed SDK
+# Copyright (c) 2011-2013 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import print_function, division, absolute_import
+
+from . import Notifier
+
+class MockNotifier(Notifier):
+    """Collect notifications
+    """
+    def __init__(self):
+        self.messages = []
+
+    def notify(self, message):
+        self.messages.append(message)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/notifier/term.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,146 @@
+# mbed SDK
+# Copyright (c) 2011-2013 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import print_function, division, absolute_import
+from past.builtins import basestring
+
+import re
+import sys
+from os import getcwd
+from os.path import (basename, abspath)
+
+from . import Notifier
+from ..settings import (PRINT_COMPILER_OUTPUT_AS_LINK,
+                        CLI_COLOR_MAP, COLOR)
+
+class TerminalNotifier(Notifier):
+    """
+    Writes notifications to a terminal based on silent, verbose and color flags.
+    """
+
+    def __init__(self, verbose=False, silent=False, color=False):
+        self.verbose = verbose
+        self.silent = silent
+        self.output = ""
+        self.color = color or COLOR
+        if self.color:
+            from colorama import init, Fore, Back, Style
+            init()
+            self.COLORS = {
+                'none' : "",
+                'default' : Style.RESET_ALL,
+
+                'black'   : Fore.BLACK,
+                'red'     : Fore.RED,
+                'green'   : Fore.GREEN,
+                'yellow'  : Fore.YELLOW,
+                'blue'    : Fore.BLUE,
+                'magenta' : Fore.MAGENTA,
+                'cyan'    : Fore.CYAN,
+                'white'   : Fore.WHITE,
+
+                'on_black'   : Back.BLACK,
+                'on_red'     : Back.RED,
+                'on_green'   : Back.GREEN,
+                'on_yellow'  : Back.YELLOW,
+                'on_blue'    : Back.BLUE,
+                'on_magenta' : Back.MAGENTA,
+                'on_cyan'    : Back.CYAN,
+                'on_white'   : Back.WHITE,
+            }
+
+    def get_output(self):
+        return self.output
+
+    def notify(self, event):
+        if self.verbose:
+            msg = self.print_notify_verbose(event)
+        else:
+            msg = self.print_notify(event)
+        if msg:
+            if not self.silent:
+                if self.color:
+                    self.print_in_color(event, msg)
+                else:
+                    print(msg)
+            self.output += msg + "\n"
+
+    def print_notify(self, event):
+        """ Command line notification
+        """
+        if event['type'] in ('tool_error', 'info'):
+            return event['message']
+
+        elif event['type'] == 'cc' and event['severity'] != 'verbose':
+            event['severity'] = event['severity'].title()
+
+            if PRINT_COMPILER_OUTPUT_AS_LINK:
+                event['file'] = abspath(event['file'])
+                return '[{severity}] {file}:{line}:{col}: {message}'.format(
+                    **event)
+            else:
+                event['file'] = basename(event['file'])
+                return '[{severity}] {file}@{line},{col}: {message}'.format(
+                    **event)
+
+        elif event['type'] == 'progress':
+            event['action'] = event['action'].title()
+            event['file'] = basename(event['file'])
+            if 'percent' in event:
+                format_string = '{action} [{percent:>5.1f}%]: {file}'
+            else:
+                format_string = '{action}: {file}'
+            return format_string.format(**event)
+
+    def print_notify_verbose(self, event):
+        """ Command line notification with more verbose mode
+        """
+        if event['type'] == 'info' or (event['type'] == 'cc' and
+                                       event['severity'] == 'verbose'):
+            return event['message']
+        elif event['type'] == 'debug':
+            return "[DEBUG] {message}".format(**event)
+        elif event['type'] in ('progress', 'cc'):
+            return self.print_notify(event)
+
+    COLOR_MATCHER = re.compile(r"(\w+)(\W+on\W+\w+)?")
+    def colorstring_to_escapecode(self, color_string):
+        """ Convert a color string from a string into an ascii escape code that
+        will print that color on the terminal.
+
+        Positional arguments:
+        color_string - the string to parse
+        """
+        match = re.match(self.COLOR_MATCHER, color_string)
+        if match:
+            return self.COLORS[match.group(1)] + \
+                (self.COLORS[match.group(2).strip().replace(" ", "_")]
+                 if match.group(2) else "")
+        else:
+            return self.COLORS['default']
+
+    def print_in_color(self, event, msg):
+        """ Wrap a toolchain notifier in a colorizer. This colorizer will wrap
+        notifications in a color if the severity matches a color in the
+        CLI_COLOR_MAP.
+        """
+        """The notification function inself"""
+        if sys.stdout.isatty() and event.get('severity', None) in CLI_COLOR_MAP:
+            sys.stdout.write(self.colorstring_to_escapecode(
+                CLI_COLOR_MAP[event['severity']]))
+            print(msg)
+            sys.stdout.write(self.colorstring_to_escapecode('default'))
+        else:
+            print(msg)
--- a/options.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/options.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,16 +14,19 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, division, absolute_import
+
 from json import load
 from os.path import join, dirname
 from os import listdir
 from argparse import ArgumentParser, ArgumentTypeError
-from tools.toolchains import TOOLCHAINS
-from tools.targets import TARGET_NAMES, Target, update_target_data
-from tools.utils import argparse_force_uppercase_type, \
-    argparse_lowercase_hyphen_type, argparse_many, \
-    argparse_filestring_type, args_error, argparse_profile_filestring_type,\
-    argparse_deprecate
+
+from .toolchains import TOOLCHAINS
+from .targets import TARGET_NAMES, Target, update_target_data
+from .utils import (argparse_force_uppercase_type, argparse_deprecate,
+                    argparse_lowercase_hyphen_type, argparse_many,
+                    argparse_filestring_type, args_error,
+                    argparse_profile_filestring_type)
 
 FLAGS_DEPRECATION_MESSAGE = "Please use the --profile argument instead.\n"\
                             "Documentation may be found in "\
@@ -117,16 +120,6 @@
         profiles.append(contents)
 
     return profiles
-
-def mcu_is_enabled(parser, mcu):
-    if "Cortex-A" in TARGET_MAP[mcu].core:
-        args_error(
-            parser,
-            ("%s Will be supported in mbed OS 5.6. "
-             "To use the %s, please checkout the mbed OS 5.4 release branch. "
-             "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice "
-             "for more information") % (mcu, mcu))
-    return True
     
 def extract_mcus(parser, options):
     try:
--- a/profiles/debug.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/profiles/debug.json	Tue Sep 25 13:43:09 2018 -0500
@@ -19,12 +19,11 @@
         "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-g", "-O0",
                    "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
                    "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
-                   "-fno-exceptions", "-MMD"],
+                   "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="],
         "asm": [],
         "c": ["-D__ASSERT_MSG", "-std=gnu99"],
         "cxx": ["-fno-rtti", "-std=gnu++98"],
-        "ld": ["--verbose", "--remove", "--legacyalign", "--no_strict_wchar_size",
-               "--no_strict_enum_size"]
+        "ld": ["--verbose", "--remove", "--show_full_path", "--legacyalign"]
     },
     "ARM": {
         "common": ["-c", "--gnu", "-Otime", "--split_sections",
@@ -51,9 +50,9 @@
         "common": [
             "--no_wrap_diagnostics",  "-e",
             "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-On", "-r", "-DMBED_DEBUG",
-            "-DMBED_TRAP_ERRORS_ENABLED=1"],
+            "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict"],
         "asm": [],
-        "c": ["--vla"],
+        "c": ["--vla", "--diag_suppress=Pe546"],
         "cxx": ["--guard_calls", "--no_static_destruction"],
         "ld": ["--skip_dynamic_initialization", "--threaded_lib"]
     }
--- a/profiles/develop.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/profiles/develop.json	Tue Sep 25 13:43:09 2018 -0500
@@ -5,7 +5,7 @@
                    "-fmessage-length=0", "-fno-exceptions", "-fno-builtin",
                    "-ffunction-sections", "-fdata-sections", "-funsigned-char",
                    "-MMD", "-fno-delete-null-pointer-checks",
-                   "-fomit-frame-pointer", "-Os"],
+                   "-fomit-frame-pointer", "-Os", "-g1"],
         "asm": ["-x", "assembler-with-cpp"],
         "c": ["-std=gnu99"],
         "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"],
@@ -18,11 +18,11 @@
         "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Os",
                    "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
                    "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
-                   "-fno-exceptions", "-MMD"],
+                   "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="],
         "asm": [],
         "c": ["-D__ASSERT_MSG", "-std=gnu99"],
         "cxx": ["-fno-rtti", "-std=gnu++98"],
-        "ld": ["--legacyalign", "--no_strict_wchar_size", "--no_strict_enum_size"]
+        "ld": ["--show_full_path", "--legacyalign"]
     },
     "ARM": {
         "common": ["-c", "--gnu", "-Otime", "--split_sections",
@@ -46,9 +46,9 @@
     "IAR": {
         "common": [
             "--no_wrap_diagnostics", "-e",
-            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh"],
+            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict"],
         "asm": [],
-        "c": ["--vla"],
+        "c": ["--vla", "--diag_suppress=Pe546"],
         "cxx": ["--guard_calls", "--no_static_destruction"],
         "ld": ["--skip_dynamic_initialization", "--threaded_lib"]
     }
--- a/profiles/release.json	Mon Nov 06 13:17:14 2017 -0600
+++ b/profiles/release.json	Tue Sep 25 13:43:09 2018 -0500
@@ -5,7 +5,7 @@
                    "-fmessage-length=0", "-fno-exceptions", "-fno-builtin",
                    "-ffunction-sections", "-fdata-sections", "-funsigned-char",
                    "-MMD", "-fno-delete-null-pointer-checks",
-                   "-fomit-frame-pointer", "-Os", "-DNDEBUG"],
+                   "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g1"],
         "asm": ["-x", "assembler-with-cpp"],
         "c": ["-std=gnu99"],
         "cxx": ["-std=gnu++98", "-fno-rtti", "-Wvla"],
@@ -18,11 +18,11 @@
         "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Oz",
                    "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
                    "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
-                   "-fno-exceptions", "-MMD"],
+                   "-fno-exceptions", "-MMD", "-D_LIBCPP_EXTERN_TEMPLATE(...)="],
         "asm": [],
         "c": ["-D__ASSERT_MSG", "-std=gnu99"],
         "cxx": ["-fno-rtti", "-std=gnu++98"],
-        "ld": ["--legacyalign", "--no_strict_wchar_size", "--no_strict_enum_size"]
+        "ld": ["--show_full_path", "--legacyalign"]
     },
     "ARM": {
         "common": ["-c", "--gnu", "-Ospace", "--split_sections",
@@ -46,9 +46,9 @@
     "IAR": {
         "common": [
             "--no_wrap_diagnostics", "-e",
-            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG"],
+            "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG", "--enable_restrict"],
         "asm": [],
-        "c": ["--vla"],
+        "c": ["--vla", "--diag_suppress=Pe546"],
         "cxx": ["--guard_calls", "--no_static_destruction"],
         "ld": ["--skip_dynamic_initialization", "--threaded_lib"]
     }
--- a/project.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/project.py	Tue Sep 25 13:43:09 2018 -0500
@@ -1,31 +1,68 @@
 """ The CLI entry point for exporting projects from the mbed tools to any of the
 supported IDEs or project structures.
 """
+from __future__ import print_function, absolute_import
+from builtins import str
+
 import sys
-from os.path import join, abspath, dirname, exists, basename
+from os.path import (join, abspath, dirname, exists, basename, normpath,
+                     realpath, relpath, basename)
+from os import remove
 ROOT = abspath(join(dirname(__file__), ".."))
 sys.path.insert(0, ROOT)
 
 from shutil import move, rmtree
 from argparse import ArgumentParser
-from os.path import normpath, realpath
 
 from tools.paths import EXPORT_DIR, MBED_HAL, MBED_LIBRARIES, MBED_TARGETS_PATH
 from tools.settings import BUILD_DIR
-from tools.export import EXPORTERS, mcu_ide_matrix, mcu_ide_list, export_project, get_exporter_toolchain
+from tools.export import (
+    EXPORTERS,
+    mcu_ide_matrix,
+    mcu_ide_list,
+    export_project,
+    get_exporter_toolchain,
+)
 from tools.tests import TESTS, TEST_MAP
 from tools.tests import test_known, test_name_known, Test
 from tools.targets import TARGET_NAMES, set_targets_json_location
-from tools.utils import argparse_filestring_type, argparse_profile_filestring_type, argparse_many, args_error
+from tools.utils import (
+    argparse_filestring_type,
+    argparse_profile_filestring_type,
+    argparse_many,
+    args_error,
+)
 from tools.utils import argparse_force_lowercase_type
 from tools.utils import argparse_force_uppercase_type
 from tools.utils import print_large_string
 from tools.utils import NotSupportedException
 from tools.options import extract_profile, list_profiles, extract_mcus
+from tools.notifier.term import TerminalNotifier
 from tools.build_profiles import find_targets_json, find_build_profile, get_toolchain_profile
 from tools.toolchains import mbedToolchain
 
-def setup_project(ide, target, program=None, source_dir=None, build=None, export_path=None):
+EXPORTER_ALIASES = {
+    u'gcc_arm': u'make_gcc_arm',
+    u'uvision': u'uvision5',
+}
+
+
+def resolve_exporter_alias(ide):
+    if ide in EXPORTER_ALIASES:
+        return EXPORTER_ALIASES[ide]
+    else:
+        return ide
+
+
+def setup_project(
+        ide,
+        target,
+        zip,
+        program,
+        source_dir,
+        build,
+        export_path,
+):
     """Generate a name, if not provided, and find dependencies
 
     Positional arguments:
@@ -48,7 +85,10 @@
             project_name = TESTS[program]
         else:
             project_name = basename(normpath(realpath(source_dir[0])))
-        src_paths = source_dir
+        if zip:
+            src_paths = {path.strip(".\\/"): [path] for path in source_dir}
+        else:
+            src_paths = {relpath(path, project_dir): [path] for path in source_dir}
         lib_paths = None
     else:
         test = Test(program)
@@ -59,7 +99,6 @@
                 test.dependencies.append(MBED_HAL)
                 test.dependencies.append(MBED_TARGETS_PATH)
 
-
         src_paths = [test.source_dir]
         lib_paths = test.dependencies
         project_name = "_".join([test.id, ide, target])
@@ -69,8 +108,8 @@
 
 
 def export(target, ide, build=None, src=None, macros=None, project_id=None,
-           zip_proj=False, build_profile=None, export_path=None, silent=False,
-           app_config=None):
+           zip_proj=False, build_profile=None, export_path=None, notify=None,
+           app_config=None, ignore=None):
     """Do an export of a project.
 
     Positional arguments:
@@ -84,14 +123,10 @@
     project_id - the name of the project
     clean - start from a clean state before exporting
     zip_proj - create a zip file or not
+    ignore - list of paths to add to mbedignore
 
     Returns an object of type Exporter (tools/exports/exporters.py)
     """
-    project_dir, name, src, lib = setup_project(ide, target, program=project_id,
-                                                source_dir=src, build=build, export_path=export_path)
-
-    zip_name = name+".zip" if zip_proj else None
-
     ###################################
     # mbed Classic/2.0/libary support #
 
@@ -107,8 +142,7 @@
 
     # Apply targets.json to active targets
     if targets_json:
-        if not silent:
-            print("Using targets from %s" % targets_json)
+        notify.info("Using targets from %s" % targets_json)
         set_targets_json_location(targets_json)
 
     # Apply profile to toolchains
@@ -117,8 +151,7 @@
             profile_data = get_toolchain_profile(self.name, profile)
             if not profile_data:
                 return
-            if not silent:
-                self.info("Using toolchain %s profile %s" % (self.name, profile))
+            notify.info("Using toolchain %s profile %s" % (self.name, profile))
 
             for k,v in profile_data.items():
                 if self.flags.has_key(k):
@@ -131,170 +164,260 @@
     # mbed Classic/2.0/libary support #
     ###################################
 
+    project_dir, name, src, lib = setup_project(
+        ide,
+        target,
+        bool(zip_proj),
+        program=project_id,
+        source_dir=src,
+        build=build,
+        export_path=export_path,
+    )
+
+    zip_name = name+".zip" if zip_proj else None
+
+    return export_project(
+        src,
+        project_dir,
+        target,
+        ide,
+        name=name,
+        macros=macros,
+        libraries_paths=lib,
+        zip_proj=zip_name,
+        build_profile=build_profile,
+        notify=TerminalNotifier(),
+        app_config=app_config,
+        ignore=ignore
+    )
+
+def clean(source_dir):
+    if exists(EXPORT_DIR):
+        rmtree(EXPORT_DIR)
+    for cls in EXPORTERS.values():
+        try:
+            cls.clean(basename(abspath(source_dir[0])))
+        except (NotImplementedError, IOError, OSError):
+            pass
+    for f in list(EXPORTERS.values())[0].CLEAN_FILES:
+        try:
+            remove(f)
+        except (IOError, OSError):
+            pass
+
     return export_project(src, project_dir, target, ide, name=name,
                           macros=macros, libraries_paths=lib, zip_proj=zip_name,
-                          build_profile=build_profile, silent=silent,
-                          app_config=app_config)
+                          build_profile=build_profile, notify=notify,
+                          app_config=app_config, ignore=ignore)
 
 
-def main():
-    """Entry point"""
-    # Parse Options
+def get_args(argv):
     parser = ArgumentParser()
 
     targetnames = TARGET_NAMES
     targetnames.sort()
-    toolchainlist = EXPORTERS.keys()
+    toolchainlist = list(EXPORTERS.keys()) + list(EXPORTER_ALIASES.keys())
     toolchainlist.sort()
 
-    parser.add_argument("-m", "--mcu",
-                        metavar="MCU",
-                        type=str.upper,
-                        help="generate project for the given MCU ({})".format(
-                            ', '.join(targetnames)))
+    parser.add_argument(
+        "-m", "--mcu",
+        metavar="MCU",
+        help="generate project for the given MCU ({})".format(
+            ', '.join(targetnames))
+    )
 
-    parser.add_argument("-i",
-                        dest="ide",
-                        type=argparse_force_lowercase_type(
-                            toolchainlist, "toolchain"),
-                        help="The target IDE: %s"% str(toolchainlist))
+    parser.add_argument(
+        "-i",
+        dest="ide",
+        type=argparse_force_lowercase_type(
+            toolchainlist, "toolchain"),
+        help="The target IDE: %s" % str(toolchainlist)
+    )
 
-    parser.add_argument("-c", "--clean",
-                        action="store_true",
-                        default=False,
-                        help="clean the export directory")
+    parser.add_argument(
+        "-c", "--clean",
+        action="store_true",
+        default=False,
+        help="clean the export directory"
+    )
 
     group = parser.add_mutually_exclusive_group(required=False)
     group.add_argument(
         "-p",
         type=test_known,
         dest="program",
-        help="The index of the desired test program: [0-%s]"% (len(TESTS)-1))
+        help="The index of the desired test program: [0-%s]" % (len(TESTS) - 1)
+    )
 
-    group.add_argument("-n",
-                       type=test_name_known,
-                       dest="program",
-                       help="The name of the desired test program")
+    group.add_argument(
+        "-n",
+        type=test_name_known,
+        dest="program",
+        help="The name of the desired test program"
+    )
 
-    parser.add_argument("-b",
-                      dest="build",
-                      default=False,
-                      action="store_true",
-                      help="use the mbed library build, instead of the sources")
+    parser.add_argument(
+        "-b",
+        dest="build",
+        default=False,
+        action="store_true",
+        help="use the mbed library build, instead of the sources"
+    )
 
-    group.add_argument("-L", "--list-tests",
-                       action="store_true",
-                       dest="list_tests",
-                       default=False,
-                       help="list available programs in order and exit")
+    group.add_argument(
+        "-L", "--list-tests",
+        action="store_true",
+        dest="list_tests",
+        default=False,
+        help="list available programs in order and exit"
+    )
 
-    group.add_argument("-S", "--list-matrix",
-                       dest="supported_ides",
-                       default=False,
-                       const="matrix",
-                       choices=["matrix", "ides"],
-                       nargs="?",
-                       help="displays supported matrix of MCUs and IDEs")
+    group.add_argument(
+        "-S", "--list-matrix",
+        dest="supported_ides",
+        default=False,
+        const="matrix",
+        choices=["matrix", "ides"],
+        nargs="?",
+        help="displays supported matrix of MCUs and IDEs"
+    )
+
+    group.add_argument(
+        "--update-packs",
+        dest="update_packs",
+        action="store_true",
+        default=False
+    )
+
+    parser.add_argument(
+        "-E",
+        action="store_true",
+        dest="supported_ides_html",
+        default=False,
+        help="Generate a markdown version of the results of -S in README.md"
+    )
 
-    parser.add_argument("-E",
-                        action="store_true",
-                        dest="supported_ides_html",
-                        default=False,
-                        help="writes tools/export/README.md")
+    parser.add_argument(
+        "--build",
+        type=argparse_filestring_type,
+        dest="build_dir",
+        default=None,
+        help="Directory for the exported project files"
+    )
 
-    parser.add_argument("--source",
-                        action="append",
-                        type=argparse_filestring_type,
-                        dest="source_dir",
-                        default=[],
-                        help="The source (input) directory")
+    parser.add_argument(
+        "--source",
+        action="append",
+        type=argparse_filestring_type,
+        dest="source_dir",
+        default=[],
+        help="The source (input) directory"
+    )
+
+    parser.add_argument(
+        "-D",
+        action="append",
+        dest="macros",
+        help="Add a macro definition"
+    )
 
-    parser.add_argument("-D",
-                        action="append",
-                        dest="macros",
-                        help="Add a macro definition")
+    parser.add_argument(
+        "--profile",
+        dest="profile",
+        action="append",
+        type=argparse_profile_filestring_type,
+        help=("Build profile to use. Can be either path to json"
+              "file or one of the default one ({})".format(
+                  ", ".join(list_profiles()))),
+        default=[]
+    )
+
+    parser.add_argument(
+        "--app-config",
+        dest="app_config",
+        default=None
+    )
 
-    parser.add_argument("--profile", dest="profile", action="append",
-                        type=argparse_profile_filestring_type,
-                        help="Build profile to use. Can be either path to json" \
-                        "file or one of the default one ({})".format(", ".join(list_profiles())),
-                        default=[])
+    parser.add_argument(
+        "-z",
+        action="store_true",
+        default=None,
+        dest="zip",
+    )
 
-    parser.add_argument("--update-packs",
-                        dest="update_packs",
-                        action="store_true",
-                        default=False)
-    parser.add_argument("--app-config",
-                        dest="app_config",
-                        default=None)
+    parser.add_argument(
+        "--ignore",
+        dest="ignore",
+        type=argparse_many(str),
+        default=None,
+        help=("Comma separated list of patterns to add to mbedignore "
+              "(eg. ./main.cpp)")
+    )
 
-    options = parser.parse_args()
+    return parser.parse_args(argv), parser
+
+
+def main():
+    """Entry point"""
+    # Parse Options
+    options, parser = get_args(sys.argv[1:])
 
     # Print available tests in order and exit
-    if options.list_tests is True:
-        print '\n'.join([str(test) for test in  sorted(TEST_MAP.values())])
-        sys.exit()
-
-    # Only prints matrix of supported IDEs
-    if options.supported_ides:
+    if options.list_tests:
+        print('\n'.join(str(test) for test in sorted(TEST_MAP.values())))
+    elif options.supported_ides:
         if options.supported_ides == "matrix":
             print_large_string(mcu_ide_matrix())
         elif options.supported_ides == "ides":
-            print mcu_ide_list()
-        exit(0)
-
-    # Only prints matrix of supported IDEs
-    if options.supported_ides_html:
+            print(mcu_ide_list())
+    elif options.supported_ides_html:
         html = mcu_ide_matrix(verbose_html=True)
-        try:
-            with open("./export/README.md", "w") as readme:
-                readme.write("Exporter IDE/Platform Support\n")
-                readme.write("-----------------------------------\n")
-                readme.write("\n")
-                readme.write(html)
-        except IOError as exc:
-            print "I/O error({0}): {1}".format(exc.errno, exc.strerror)
-        except:
-            print "Unexpected error:", sys.exc_info()[0]
-            raise
-        exit(0)
-
-    if options.update_packs:
+        with open("README.md", "w") as readme:
+            readme.write("Exporter IDE/Platform Support\n")
+            readme.write("-----------------------------------\n")
+            readme.write("\n")
+            readme.write(html)
+    elif options.update_packs:
         from tools.arm_pack_manager import Cache
         cache = Cache(True, True)
-        cache.cache_descriptors()
-
-    # Target
-    if not options.mcu:
-        args_error(parser, "argument -m/--mcu is required")
+        cache.cache_everything()
+    else:
+        # Check required arguments
+        if not options.mcu:
+            args_error(parser, "argument -m/--mcu is required")
+        if not options.ide:
+            args_error(parser, "argument -i is required")
+        if (options.program is None) and (not options.source_dir):
+            args_error(parser, "one of -p, -n, or --source is required")
 
-    # Toolchain
-    if not options.ide:
-        args_error(parser, "argument -i is required")
-
-    # Clean Export Directory
-    if options.clean:
-        if exists(EXPORT_DIR):
-            rmtree(EXPORT_DIR)
-
-    zip_proj = not bool(options.source_dir)
+        if options.clean:
+            clean(options.source_dir)
 
-    if (options.program is None) and (not options.source_dir):
-        args_error(parser, "one of -p, -n, or --source is required")
-    exporter, toolchain_name = get_exporter_toolchain(options.ide)
-    mcu = extract_mcus(parser, options)[0]
-    if not exporter.is_target_supported(mcu):
-        args_error(parser, "%s not supported by %s"%(mcu,options.ide))
-    profile = extract_profile(parser, options, toolchain_name, fallback="debug")
-    if options.clean:
-        rmtree(BUILD_DIR)
-    try:
-        export(mcu, options.ide, build=options.build,
-               src=options.source_dir, macros=options.macros,
-               project_id=options.program, zip_proj=zip_proj,
-               build_profile=profile, app_config=options.app_config)
-    except NotSupportedException as exc:
-        print "[ERROR] %s" % str(exc)
+        ide = resolve_exporter_alias(options.ide)
+        exporter, toolchain_name = get_exporter_toolchain(ide)
+        profile = extract_profile(parser, options, toolchain_name, fallback="debug")
+        mcu = extract_mcus(parser, options)[0]
+        if not exporter.is_target_supported(mcu):
+            args_error(parser, "%s not supported by %s" % (mcu, ide))
+
+        try:
+            export(
+                mcu,
+                ide,
+                build=options.build,
+                src=options.source_dir,
+                macros=options.macros,
+                project_id=options.program,
+                zip_proj=not bool(options.source_dir) or options.zip,
+                build_profile=profile,
+                app_config=options.app_config,
+                export_path=options.build_dir,
+                ignore=options.ignore
+            )
+        except NotSupportedException as exc:
+            args_error(parser, "%s not supported by %s" % (mcu, ide))
+            print("[Not Supported] %s" % str(exc))
+    exit(0)
 
 if __name__ == "__main__":
     main()
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/resources/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,533 @@
+# mbed SDK
+# Copyright (c) 2011-2013 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+# The scanning rules and Resources object.
+
+A project in Mbed OS contains metadata in the file system as directory names.
+These directory names adhere to a set of rules referred to as scanning rules.
+The following are the English version of the scanning rules:
+
+Directory names starting with "TEST_", "TARGET_", "TOOLCHAIN_" and "FEATURE_"
+are excluded from a build unless one of the following is true:
+ * The suffix after "TARGET_" is a target label (see target.labels).
+ * The suffix after "TOOLCHAIN_" is a toolchain label, defined by the
+   inheritance hierarchy of the toolchain class.
+ * The suffix after "FEATURE_" is a member of `target.features`.
+
+
+"""
+
+from __future__ import print_function, division, absolute_import
+
+import fnmatch
+import re
+from collections import namedtuple, defaultdict
+from copy import copy
+from itertools import chain
+from os import walk, sep
+from os.path import (join, splitext, dirname, relpath, basename, split, normcase,
+                     abspath, exists)
+
+from .ignore import MbedIgnoreSet, IGNORE_FILENAME
+
+# Support legacy build conventions: the original mbed build system did not have
+# standard labels for the "TARGET_" and "TOOLCHAIN_" specific directories, but
+# had the knowledge of a list of these directories to be ignored.
+LEGACY_IGNORE_DIRS = set([
+    # Legacy Targets
+    'LPC11U24',
+    'LPC1768',
+    'LPC2368',
+    'LPC4088',
+    'LPC812',
+    'KL25Z',
+
+    # Legacy Toolchains
+    'ARM',
+    'uARM',
+    'IAR',
+    'GCC_ARM',
+    'GCC_CS',
+    'GCC_CR',
+    'GCC_CW',
+    'GCC_CW_EWL',
+    'GCC_CW_NEWLIB',
+    'ARMC6',
+
+    # Tests, here for simplicity
+    'TESTS',
+    'TEST_APPS',
+])
+LEGACY_TOOLCHAIN_NAMES = {
+    'ARM_STD':'ARM',
+    'ARM_MICRO': 'uARM',
+    'GCC_ARM': 'GCC_ARM',
+    'GCC_CR': 'GCC_CR',
+    'IAR': 'IAR',
+    'ARMC6': 'ARMC6',
+}
+
+
+FileRef = namedtuple("FileRef", "name path")
+
+class FileType(object):
+    C_SRC = "c"
+    CPP_SRC = "c++"
+    ASM_SRC = "s"
+    HEADER = "header"
+    INC_DIR = "inc"
+    LIB_DIR = "libdir"
+    LIB = "lib"
+    OBJECT = "o"
+    HEX = "hex"
+    BIN = "bin"
+    JSON = "json"
+    LD_SCRIPT = "ld"
+    LIB_REF = "libref"
+    BLD_REF = "bldref"
+    REPO_DIR = "repodir"
+
+    def __init__(self):
+        raise NotImplemented
+
+class Resources(object):
+    ALL_FILE_TYPES = [
+        FileType.C_SRC,
+        FileType.CPP_SRC,
+        FileType.ASM_SRC,
+        FileType.HEADER,
+        FileType.INC_DIR,
+        FileType.LIB_DIR,
+        FileType.LIB,
+        FileType.OBJECT,
+        FileType.HEX,
+        FileType.BIN,
+        FileType.JSON,
+        FileType.LD_SCRIPT,
+        FileType.LIB_REF,
+        FileType.BLD_REF,
+        FileType.REPO_DIR,
+    ]
+
+    def __init__(self, notify, collect_ignores=False):
+        # publicly accessible things
+        self.ignored_dirs = []
+
+        # Pre-mbed 2.0 ignore dirs
+        self._legacy_ignore_dirs = (LEGACY_IGNORE_DIRS)
+
+        # Primate parameters
+        self._notify = notify
+        self._collect_ignores = collect_ignores
+
+        # Storage for file references, indexed by file type
+        self._file_refs = defaultdict(set)
+
+        # Incremental scan related
+        self._label_paths = []
+        self._labels = {
+            "TARGET": [], "TOOLCHAIN": [], "FEATURE": [], "COMPONENT": []
+        }
+        self._prefixed_labels = set()
+
+        # Path seperator style (defaults to OS-specific seperator)
+        self._sep = sep
+
+        self._ignoreset = MbedIgnoreSet()
+
+    def ignore_dir(self, directory):
+        if self._collect_ignores:
+            self.ignored_dirs.append(directory)
+
+    def _collect_duplicates(self, dupe_dict, dupe_headers):
+        for filename in self.s_sources + self.c_sources + self.cpp_sources:
+            objname, _ = splitext(basename(filename))
+            dupe_dict.setdefault(objname, set())
+            dupe_dict[objname] |= set([filename])
+        for filename in self.headers:
+            headername = basename(filename)
+            dupe_headers.setdefault(headername, set())
+            dupe_headers[headername] |= set([headername])
+        return dupe_dict, dupe_headers
+
+    def detect_duplicates(self):
+        """Detect all potential ambiguities in filenames and report them with
+        a toolchain notification
+        """
+        count = 0
+        dupe_dict, dupe_headers = self._collect_duplicates(dict(), dict())
+        for objname, filenames in dupe_dict.items():
+            if len(filenames) > 1:
+                count+=1
+                self._notify.tool_error(
+                    "Object file %s.o is not unique! It could be made from: %s"\
+                    % (objname, " ".join(filenames)))
+        for headername, locations in dupe_headers.items():
+            if len(locations) > 1:
+                count+=1
+                self._notify.tool_error(
+                    "Header file %s is not unique! It could be: %s" %\
+                    (headername, " ".join(locations)))
+        return count
+
+    def win_to_unix(self):
+        self._sep = "/"
+        if self._sep != sep:
+            for file_type in self.ALL_FILE_TYPES:
+                v = [f._replace(name=f.name.replace(sep, self._sep)) for
+                     f in self.get_file_refs(file_type)]
+                self._file_refs[file_type] = v
+
+    def __str__(self):
+        s = []
+
+        for (label, file_type) in (
+                ('Include Directories', FileType.INC_DIR),
+                ('Headers', FileType.HEADER),
+
+                ('Assembly sources', FileType.ASM_SRC),
+                ('C sources', FileType.C_SRC),
+                ('C++ sources', FileType.CPP_SRC),
+
+                ('Library directories', FileType.LIB_DIR),
+                ('Objects', FileType.OBJECT),
+                ('Libraries', FileType.LIB),
+
+                ('Hex files', FileType.HEX),
+                ('Bin files', FileType.BIN),
+                ('Linker script', FileType.LD_SCRIPT)
+            ):
+            resources = self.get_file_refs(file_type)
+            if resources:
+                s.append('%s:\n  ' % label + '\n  '.join(
+                    "%s -> %s" % (name, path) for name, path in resources))
+
+        return '\n'.join(s)
+
+
+    def _add_labels(self, prefix, labels):
+        self._labels[prefix].extend(labels)
+        self._prefixed_labels |= set("%s_%s" % (prefix, label) for label in labels)
+        for path, base_path, into_path in self._label_paths:
+            if basename(path) in self._prefixed_labels:
+                self.add_directory(path, base_path, into_path)
+        self._label_paths = [(p, b, i) for p, b, i in self._label_paths
+                             if basename(p) not in self._prefixed_labels]
+
+    def add_target_labels(self, target):
+        self._add_labels("TARGET", target.labels)
+        self._add_labels("COMPONENT", target.components)
+        self.add_features(target.features)
+
+    def add_features(self, features):
+        self._add_labels("FEATURE", features)
+
+    def add_toolchain_labels(self, toolchain):
+        for prefix, value in toolchain.get_labels().items():
+            self._add_labels(prefix, value)
+        self._legacy_ignore_dirs -= set(
+            [toolchain.target.name, LEGACY_TOOLCHAIN_NAMES[toolchain.name]])
+
+    def add_ignore_patterns(self, root, base_path, patterns):
+        real_base = relpath(root, base_path)
+        self._ignoreset.add_ignore_patterns(real_base, patterns)
+
+    def _not_current_label(self, dirname, label_type):
+        return (dirname.startswith(label_type + "_") and
+                dirname[len(label_type) + 1:] not in self._labels[label_type])
+
+    def add_file_ref(self, file_type, file_name, file_path):
+        if sep != self._sep:
+            ref = FileRef(file_name.replace(sep, self._sep), file_path)
+        else:
+            ref = FileRef(file_name, file_path)
+        self._file_refs[file_type].add(ref)
+
+    def get_file_refs(self, file_type):
+        """Return a list of FileRef for every file of the given type"""
+        return list(self._file_refs[file_type])
+
+    def _all_parents(self, files):
+        for name in files:
+            components = name.split(self._sep)
+            start_at = 2 if components[0] in set(['', '.']) else 1
+            for index, directory in reversed(list(enumerate(components))[start_at:]):
+                if directory in self._prefixed_labels:
+                    start_at = index + 1
+                    break
+            for n in range(start_at, len(components)):
+                parent = self._sep.join(components[:n])
+                yield parent
+
+    def _get_from_refs(self, file_type, key):
+        if file_type is FileType.INC_DIR:
+            parents = set(self._all_parents(self._get_from_refs(
+                FileType.HEADER, key)))
+            parents.add(".")
+        else:
+            parents = set()
+        return sorted(
+            list(parents) + [key(f) for f in self.get_file_refs(file_type)]
+        )
+
+
+    def get_file_names(self, file_type):
+        return self._get_from_refs(file_type, lambda f: f.name)
+
+    def get_file_paths(self, file_type):
+        return self._get_from_refs(file_type, lambda f: f.path)
+
+    def add_files_to_type(self, file_type, files):
+        for f in files:
+            self.add_file_ref(file_type, f, f)
+
+    @property
+    def inc_dirs(self):
+        return self.get_file_names(FileType.INC_DIR)
+
+    @property
+    def headers(self):
+        return self.get_file_names(FileType.HEADER)
+
+    @property
+    def s_sources(self):
+        return self.get_file_names(FileType.ASM_SRC)
+
+    @property
+    def c_sources(self):
+        return self.get_file_names(FileType.C_SRC)
+
+    @property
+    def cpp_sources(self):
+        return self.get_file_names(FileType.CPP_SRC)
+
+    @property
+    def lib_dirs(self):
+        return self.get_file_names(FileType.LIB_DIR)
+
+    @property
+    def objects(self):
+        return self.get_file_names(FileType.OBJECT)
+
+    @property
+    def libraries(self):
+        return self.get_file_names(FileType.LIB)
+
+    @property
+    def lib_builds(self):
+        return self.get_file_names(FileType.BLD_REF)
+
+    @property
+    def lib_refs(self):
+        return self.get_file_names(FileType.LIB_REF)
+
+    @property
+    def linker_script(self):
+        options = self.get_file_names(FileType.LD_SCRIPT)
+        if options:
+            return options[0]
+        else:
+            return None
+
+    @property
+    def hex_files(self):
+        return self.get_file_names(FileType.HEX)
+
+    @property
+    def bin_files(self):
+        return self.get_file_names(FileType.BIN)
+
+    @property
+    def json_files(self):
+        return self.get_file_names(FileType.JSON)
+
+    def add_directory(
+            self,
+            path,
+            base_path=None,
+            into_path=None,
+            exclude_paths=None,
+    ):
+        """ Scan a directory and include its resources in this resources obejct
+
+        Positional arguments:
+        path - the path to search for resources
+
+        Keyword arguments
+        base_path - If this is part of an incremental scan, include the origin
+                    directory root of the scan here
+        into_path - Pretend that scanned files are within the specified
+                    directory within a project instead of using their actual path
+        exclude_paths - A list of paths that are to be excluded from a build
+        """
+        self._notify.progress("scan", abspath(path))
+
+        if base_path is None:
+            base_path = path
+        if into_path is None:
+            into_path = path
+        if self._collect_ignores and path in self.ignored_dirs:
+            self.ignored_dirs.remove(path)
+        if exclude_paths:
+            self.add_ignore_patterns(
+                path, base_path, [join(e, "*") for e in exclude_paths])
+
+        for root, dirs, files in walk(path, followlinks=True):
+            # Check if folder contains .mbedignore
+            if IGNORE_FILENAME in files:
+                real_base = relpath(root, base_path)
+                self._ignoreset.add_mbedignore(
+                    real_base, join(root, IGNORE_FILENAME))
+
+            root_path =join(relpath(root, base_path))
+            if self._ignoreset.is_ignored(join(root_path,"")):
+                self.ignore_dir(root_path)
+                dirs[:] = []
+                continue
+
+            for d in copy(dirs):
+                dir_path = join(root, d)
+                if d == '.hg' or d == '.git':
+                    fake_path = join(into_path, relpath(dir_path, base_path))
+                    self.add_file_ref(FileType.REPO_DIR, fake_path, dir_path)
+
+                if (any(self._not_current_label(d, t) for t
+                        in self._labels.keys())):
+                    self._label_paths.append((dir_path, base_path, into_path))
+                    self.ignore_dir(dir_path)
+                    dirs.remove(d)
+                elif (d.startswith('.') or d in self._legacy_ignore_dirs or
+                      self._ignoreset.is_ignored(join(root_path, d, ""))):
+                    self.ignore_dir(dir_path)
+                    dirs.remove(d)
+
+            # Add root to include paths
+            root = root.rstrip("/")
+
+            for file in files:
+                file_path = join(root, file)
+                self._add_file(file_path, base_path, into_path)
+
+    _EXT = {
+        ".c": FileType.C_SRC,
+        ".cc": FileType.CPP_SRC,
+        ".cpp": FileType.CPP_SRC,
+        ".s": FileType.ASM_SRC,
+        ".h": FileType.HEADER,
+        ".hh": FileType.HEADER,
+        ".hpp": FileType.HEADER,
+        ".o": FileType.OBJECT,
+        ".hex": FileType.HEX,
+        ".bin": FileType.BIN,
+        ".json": FileType.JSON,
+        ".a": FileType.LIB,
+        ".ar": FileType.LIB,
+        ".sct": FileType.LD_SCRIPT,
+        ".ld": FileType.LD_SCRIPT,
+        ".icf": FileType.LD_SCRIPT,
+        ".lib": FileType.LIB_REF,
+        ".bld": FileType.BLD_REF,
+    }
+
+    _DIR_EXT = {
+        ".a": FileType.LIB_DIR,
+        ".ar": FileType.LIB_DIR,
+    }
+
+    def _add_file(self, file_path, base_path, into_path):
+        """ Add a single file into the resources object that was found by
+        scanning starting as base_path
+        """
+
+        if  (self._ignoreset.is_ignored(relpath(file_path, base_path)) or
+             basename(file_path).startswith(".")):
+            self.ignore_dir(relpath(file_path, base_path))
+            return
+
+        fake_path = join(into_path, relpath(file_path, base_path))
+        _, ext = splitext(file_path)
+        try:
+            file_type = self._EXT[ext.lower()]
+            self.add_file_ref(file_type, fake_path, file_path)
+        except KeyError:
+            pass
+        try:
+            dir_type = self._DIR_EXT[ext.lower()]
+            self.add_file_ref(dir_type, dirname(fake_path), dirname(file_path))
+        except KeyError:
+            pass
+
+
+    def scan_with_toolchain(self, src_paths, toolchain, dependencies_paths=None,
+                            inc_dirs=None, exclude=True):
+        """ Scan resources using initialized toolcain
+
+        Positional arguments
+        src_paths - the paths to source directories
+        toolchain - valid toolchain object
+
+        Keyword arguments
+        dependencies_paths - dependency paths that we should scan for include dirs
+        inc_dirs - additional include directories which should be added to
+                   the scanner resources
+        exclude - Exclude the toolchain's build directory from the resources
+        """
+        self.add_toolchain_labels(toolchain)
+        for path in src_paths:
+            if exists(path):
+                into_path = relpath(path).strip(".\\/")
+                if exclude:
+                    self.add_directory(
+                        path,
+                        into_path=into_path,
+                        exclude_paths=[toolchain.build_dir]
+                    )
+                else:
+                    self.add_directory(path, into_path=into_path)
+
+        # Scan dependency paths for include dirs
+        if dependencies_paths is not None:
+            toolchain.progress("dep", dependencies_paths)
+            for dep in dependencies_paths:
+                lib_self = self.__class__(self._notify, self._collect_ignores)\
+                               .scan_with_toolchain([dep], toolchain)
+                self.inc_dirs.extend(lib_self.inc_dirs)
+
+        # Add additional include directories if passed
+        if inc_dirs:
+            if isinstance(inc_dirs, list):
+                self.inc_dirs.extend(inc_dirs)
+            else:
+                self.inc_dirs.append(inc_dirs)
+
+        # Load self into the config system which might expand/modify self
+        # based on config data
+        toolchain.config.load_resources(self)
+
+        # Set the toolchain's configuration data
+        toolchain.set_config_data(toolchain.config.get_config_data())
+
+        return self
+
+    def scan_with_config(self, src_paths, config):
+        if config.target:
+            self.add_target_labels(config.target)
+        for path in src_paths:
+            if exists(path):
+                self.add_directory(path)
+        config.load_resources(self)
+        return self
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/resources/ignore.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,69 @@
+# mbed SDK
+# Copyright (c) 2011-2013 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import fnmatch
+import re
+from os.path import normcase, join
+
+
+IGNORE_FILENAME = ".mbedignore"
+
+
+class MbedIgnoreSet(object):
+    """
+    # The mbedignore rules as an object
+
+    A project in Mbed OS contains metadata files that exclude files from a build.
+    These rules are stored as `fnmatch` patterns in text in a files named `.mbedignore`.
+    """
+
+    def __init__(self):
+        self._ignore_patterns = []
+        self._ignore_regex = re.compile("$^")
+
+    def is_ignored(self, file_path):
+        """Check if file path is ignored by any .mbedignore thus far"""
+        return self._ignore_regex.match(normcase(file_path))
+
+    def add_ignore_patterns(self, in_name, patterns):
+        """Ignore all files and directories matching the paterns in 
+        directories named by in_name.
+
+        Positional arguments:
+        in_name - the filename prefix that this ignore will apply to
+        patterns - the list of patterns we will ignore in the future
+        """
+        if in_name == ".":
+            self._ignore_patterns.extend(normcase(p) for p in patterns)
+        else:
+            self._ignore_patterns.extend(
+                normcase(join(in_name, pat)) for pat in patterns)
+        if self._ignore_patterns:
+            self._ignore_regex = re.compile("|".join(
+                fnmatch.translate(p) for p in self._ignore_patterns))
+
+    def add_mbedignore(self, in_name, filepath):
+        """Add a series of patterns to the ignored paths
+
+        Positional arguments:
+        in_name - the filename prefix that this ignore will apply to
+        patterns - the list of patterns we will ignore in the future
+        """
+        with open (filepath) as f:
+            patterns = [l.strip() for l in f
+                        if l.strip() != "" and not l.startswith("#")]
+            self.add_ignore_patterns(in_name, patterns)
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/run_icetea.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,342 @@
+#! /usr/bin/env python2
+"""
+Copyright 2018 ARM Limited
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+from __future__ import print_function, division, absolute_import
+import sys
+import os
+import re
+from os.path import abspath, join, dirname, relpath, sep
+import json
+import traceback
+from fnmatch import translate
+from argparse import ArgumentParser
+
+ROOT = abspath(join(dirname(__file__), '..'))
+sys.path.insert(0, ROOT)
+
+from tools.config import ConfigException
+from tools.utils import cmd, run_cmd
+
+plugins_path = abspath(join(ROOT, 'TEST_APPS', 'icetea_plugins', 'plugins_to_load.py'))
+
+
+def find_build_from_build_data(build_data, id, target, toolchain):
+    if 'builds' not in build_data:
+        raise Exception("build data is in wrong format, does not include builds object")
+
+    for build in build_data['builds']:
+        if 'id' in build.keys() \
+                and id.upper() in build['id'].upper() \
+                and 'target_name' in build.keys() \
+                and target.upper() == build['target_name'].upper() \
+                and 'toolchain_name' in build.keys() \
+                and toolchain.upper() == build['toolchain_name'].upper() \
+                and 'result' in build.keys() \
+                and "OK" == build['result']:
+            return build
+    return None
+
+
+def create_test_suite(target, tool, icetea_json_output, build_data, tests_by_name):
+    """
+    Create test suite content
+    :param target:
+    :param tool:
+    :param icetea_json_output:
+    :param build_data:
+    :return:
+    """
+    test_suite = dict()
+    test_suite['testcases'] = list()
+
+    for test in icetea_json_output:
+        skip = False
+
+        for dut in test['requirements']['duts'].values():
+            # Set binary path based on application name
+            if 'application' in dut.keys() and 'name' in dut['application'].keys():
+                build = find_build_from_build_data(
+                    build_data=build_data,
+                    id=dut['application']['name'],
+                    target=target,
+                    toolchain=tool)
+                if build:
+                    try:
+                        dut['application']['bin'] = build['bin_fullpath']
+                    except KeyError:
+                        raise Exception('Full path is missing from build: {}'.format(build))
+                else:
+                    skip = True
+
+        if not tests_by_name or is_test_in_test_by_name(test['name'], tests_by_name):
+            test_case = {
+                'name': test['name'],
+                'config': {
+                    'requirements': set_allowed_platform(test['requirements'], target)
+                }
+            }
+
+            # Skip test if not binary path
+            if skip:
+                test_case['config']['execution'] = {
+                    'skip': {
+                        'value': True,
+                        'reason': "Test requiring application binary not build"
+                    }
+                }
+
+            test_suite['testcases'].append(test_case)
+
+    return test_suite
+
+
+def set_allowed_platform(requirements, target):
+    """
+    Allowed platform restrict icetea to run tests on specific board
+    This targets tests to the right board in case that user has multiple ones connected same time
+    """
+    if '*' not in requirements['duts'].keys():
+        requirements['duts']['*'] = dict()
+    requirements['duts']['*']['allowed_platforms'] = [target]
+    return requirements
+
+
+def get_applications(test):
+    ret = list()
+    for dut in test['requirements']['duts'].values():
+        if 'application' in dut.keys() and 'name' in dut['application'].keys():
+            ret.append(dut['application']['name'])
+    return ret
+
+
+def filter_test_by_build_data(icetea_json_output, build_data, target, toolchain):
+    if not build_data:
+        return icetea_json_output
+
+    ret = list()
+    for test in icetea_json_output:
+        for dut in test['requirements']['duts'].values():
+            if 'application' in dut.keys() and 'name' in dut['application'].keys():
+                id = dut['application']['name']
+                if find_build_from_build_data(build_data, id, target, toolchain):
+                    # Test requiring build found
+                    ret.append(test)
+    return ret
+
+
+def filter_test_by_name(icetea_json_output, test_by_name):
+    if not test_by_name:
+        return icetea_json_output
+    ret = list()
+    for test_temp in icetea_json_output:
+        if is_test_in_test_by_name(test_temp['name'], test_by_name) and test_temp not in ret:
+            ret.append(test_temp)
+    return ret
+
+
+def get_applications_from_test(test):
+    ret = list()
+    if u'requirements' in test.keys() and u'duts' in test[u'requirements']:
+        for name, dut in test[u'requirements'][u'duts'].items():
+            if u'application' in dut.keys() and u'name' in dut[u'application']:
+                ret.append(dut[u'application'][u'name'])
+    return ret
+
+
+def get_application_list(icetea_json_output, tests_by_name):
+    """ Return comma separated list of application which are used in tests """
+    ret = list()
+    for test in filter_test_by_name(icetea_json_output, tests_by_name):
+        ret.extend(get_applications_from_test(test))
+    # Remove duplicates
+    return list(set(ret))
+
+
+def icetea_tests(target, tcdir, verbose):
+    command = ['icetea', '--tcdir', tcdir, '--list', '--json', '--platform_filter', target] \
+              + (['-v'] if verbose else [])
+
+    stdout, stderr, returncode = run_cmd(command)
+
+    if returncode != 0:
+        raise Exception(
+            "Error when running icetea. \ncwd:{} \nCommand:'{}' \noutput:{}".format(os.getcwd(), ' '.join(command),
+                                                                                    stderr.decode()))
+
+    return json.loads(stdout)
+
+
+def is_test_in_test_by_name(test_name, test_by_name):
+    for tbn_temp in test_by_name:
+        if re.search(translate(tbn_temp), test_name):
+            return True
+    return False
+
+
+def check_tests(icetea_json_output):
+    """
+    Check that all tests have all necessary information
+    :return:
+    """
+    for test in icetea_json_output:
+        if not get_applications_from_test(test):
+            raise Exception('Test {} does not have application with correct name'.format(test['name']))
+
+
+def load_build_data(build_data_path):
+    """
+    :return: build_data.json content as dict and None if build data is not available
+    """
+    if not os.path.isfile(build_data_path):
+        return None
+    return json.load(open(build_data_path))
+
+
+if __name__ == '__main__':
+    try:
+        # Parse Options
+        parser = ArgumentParser()
+
+        parser.add_argument('-m', '--mcu',
+                            dest='target',
+                            default=None,
+                            help='Test target MCU',
+                            required=True)
+
+        parser.add_argument('-t', '--toolchain',
+                            dest='toolchain',
+                            default=None,
+                            help='Toolchain',
+                            required=True)
+
+        parser.add_argument('--build-data',
+                            dest='build_data',
+                            default=None,
+                            help='Detail data from build')
+
+        parser.add_argument('--test-suite',
+                            dest='test_suite',
+                            default=None,
+                            help='Path used for test suite file')
+
+        parser.add_argument('-n', '--tests-by-name',
+                            dest='tests_by_name',
+                            default=None,
+                            help='Limit the tests to a list (ex. test1,test2,test3)')
+
+        parser.add_argument('--tcdir',
+                            dest='tcdir',
+                            default='TEST_APPS',
+                            help='Test case directory',
+                            required=False)
+
+        parser.add_argument('--compile-list',
+                            action='store_true',
+                            dest='compile_list',
+                            default=False,
+                            help='List tests, which applications can be compiled')
+
+        parser.add_argument('--run-list',
+                            action='store_true',
+                            dest='run_list',
+                            default=False,
+                            help='List tests, which applications are compiled and ready for run')
+
+        parser.add_argument('--application-list',
+                            action='store_true',
+                            dest='application_list',
+                            default=False,
+                            help='List applications that need to be build')
+
+        parser.add_argument('--ignore-checks',
+                            action='store_true',
+                            dest='ignore_checks',
+                            default=False,
+                            help='Ignore data validation checks')
+
+        parser.add_argument('-v', '--verbose',
+                            action='store_true',
+                            dest='verbose',
+                            default=False,
+                            help='Verbose diagnostic output')
+
+        options = parser.parse_args()
+
+        icetea_json_output = icetea_tests(options.target, options.tcdir, options.verbose)
+        tests_by_name = options.tests_by_name.split(',') if options.tests_by_name else None
+        build_data = load_build_data(options.build_data) if options.build_data else None
+
+        if not options.ignore_checks:
+            check_tests(icetea_json_output)
+
+        if options.compile_list:
+            print('Available icetea tests for build \'{}-{}\', location \'{}\''.format(
+                options.target, options.toolchain, options.tcdir))
+            for test in icetea_json_output:
+                print(
+                    'Test Case:\n    Name: {name}\n    Path: .{sep}{filepath}\n    Test applications: .{sep}{apps}'.format(
+                        name=test['name'],
+                        sep=sep,
+                        filepath=relpath(test['filepath'], ROOT),
+                        apps=''.join(get_applications(test)).replace('-', os.path.sep)))
+
+        elif options.run_list:
+            print('Available icetea tests for build \'{}-{}\', location \'{}\''.format(
+                options.target, options.toolchain, options.tcdir))
+
+            # Filters
+            tests = filter_test_by_name(icetea_json_output, tests_by_name)
+            if build_data:
+                tests = filter_test_by_build_data(tests, build_data, options.target, options.toolchain)
+
+            for test in tests:
+                print('    test \'{name}\''.format(name=test['name']))
+
+        elif options.application_list:
+            print(','.join(get_application_list(icetea_json_output, tests_by_name)))
+
+        else:
+            if not build_data:
+                raise Exception("Build data file does not exist: {}".format(options.build_data))
+
+            test_suite = create_test_suite(options.target, options.toolchain, icetea_json_output, build_data,
+                                           tests_by_name)
+
+            if not test_suite['testcases']:
+                raise Exception("Test suite is empty. Check that --tcdir and --tests-by-name have correct values")
+
+            if not options.test_suite:
+                raise Exception('--test-suite is required when running tests')
+
+            with open(options.test_suite, 'w') as f:
+                json.dump(test_suite, f, indent=2)
+
+            # List just for debug
+            if options.verbose:
+                cmd(['icetea', '--tcdir', options.tcdir, '--list'] + (['-v'] if options.verbose else []))
+
+            cmd(['icetea', '--tcdir', options.tcdir, '--suite', options.test_suite, '--clean', '--plugin_path',
+                 plugins_path] + (['-v'] if options.verbose else []))
+
+    except KeyboardInterrupt as e:
+        print('\n[CTRL+c] exit')
+    except ConfigException as e:
+        # Catching ConfigException here to prevent a traceback
+        print('[ERROR] {}'.format(e))
+    except Exception as e:
+        traceback.print_exc(file=sys.stdout)
+        print('[ERROR] {}'.format(e))
+        sys.exit(1)
--- a/settings.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/settings.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,7 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
-
+from __future__ import print_function
 from os import getenv
 from os.path import join, abspath, dirname, exists
 import logging
@@ -45,6 +45,7 @@
 # Goanna static analyser. Please overload it in mbed_settings.py
 GOANNA_PATH = ""
 
+
 # cppcheck path (command) and output message format
 CPPCHECK_CMD = ["cppcheck", "--enable=all"]
 CPPCHECK_MSG_FORMAT = ["--template=[{severity}] {file}@{line}: {id}:{message}"]
@@ -54,9 +55,18 @@
 # mbed.org username
 MBED_ORG_USER = ""
 
+# Print compiler warnings and errors as link format
+PRINT_COMPILER_OUTPUT_AS_LINK = False
+
+# Compare against a fixed build of the project for space consumption
+COMPARE_FIXED = False
+
+# Print warnings/errors in color
+COLOR = False
+
 CLI_COLOR_MAP = {
-    "warning": "yellow",
-    "error"  : "red"
+    "Warning": "yellow",
+    "Error"  : "red"
 }
 
 ##############################################################################
@@ -81,7 +91,14 @@
         if exists(getenv('MBED_'+_n)):
             globals()[_n] = getenv('MBED_'+_n)
         else:
-            print "WARNING: MBED_%s set as environment variable but doesn't exist" % _n
+            print("WARNING: MBED_%s set as environment variable but doesn't"
+                  " exist" % _n)
+
+_ENV_VARS = ['PRINT_COMPILER_OUTPUT_AS_LINK', 'COLOR', 'COMPARE_FIXED']
+for _n in _ENV_VARS:
+    value = getenv('MBED_%s' % _n)
+    if value:
+        globals()[_n] = value
 
 
 ##############################################################################
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/synch.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,344 @@
+"""
+mbed SDK
+Copyright (c) 2011-2013 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+One repository to update them all
+On mbed.org the mbed SDK is split up in multiple repositories, this script takes
+care of updating them all.
+"""
+import sys
+from copy import copy
+from os import walk, remove, makedirs, getcwd, rmdir, listdir
+from os.path import join, abspath, dirname, relpath, exists, isfile, normpath, isdir
+from shutil import copyfile
+from optparse import OptionParser
+import re
+import string
+
+ROOT = abspath(join(dirname(__file__), ".."))
+sys.path.insert(0, ROOT)
+
+from tools.settings import MBED_ORG_PATH, MBED_ORG_USER, BUILD_DIR
+from tools.paths import *
+from tools.utils import run_cmd
+
+MBED_URL = "mbed.org"
+MBED_USER = "mbed_official"
+
+changed = []
+push_remote = True
+quiet = False
+commit_msg = ''
+
+# Code that does have a mirror in the mbed SDK
+# Tuple data: (repo_name, list_of_code_dirs, [team])
+# team is optional - if not specified, the code is published under mbed_official
+OFFICIAL_CODE = {"mbed-dev" : ["cmsis", "drivers", "hal", "platform", "targets", "mbed.h"]}
+
+
+# A list of regular expressions that will be checked against each directory
+# name and skipped if they match.
+IGNORE_DIRS = (
+)
+
+IGNORE_FILES = (
+    'COPYING',
+    '\.md',
+    "\.lib",
+    "\.bld"
+)
+
+def ignore_path(name, reg_exps):
+    for r in reg_exps:
+        if re.search(r, name):
+            return True
+    return False
+
+class MbedRepository:
+    @staticmethod
+    def run_and_print(command, cwd):
+        stdout, _, _ = run_cmd(command, work_dir=cwd, redirect=True)
+        print(stdout)
+
+    def __init__(self, name):
+        self.name = name
+        self.path = join(MBED_ORG_PATH, name)
+        self.url = "http://" + MBED_URL + "/users/" + MBED_ORG_USER + "/code/%s/"
+
+        if not exists(self.path):
+            # Checkout code
+            if not exists(MBED_ORG_PATH):
+                makedirs(MBED_ORG_PATH)
+
+            self.run_and_print(['hg', 'clone', self.url % name], cwd=MBED_ORG_PATH)
+
+        else:
+            # Update
+            self.run_and_print(['hg', 'pull'], cwd=self.path)
+            self.run_and_print(['hg', 'update'], cwd=self.path)
+
+    def publish(self):
+        # The maintainer has to evaluate the changes first and explicitly accept them
+        self.run_and_print(['hg', 'addremove'], cwd=self.path)
+        stdout, _, _ = run_cmd(['hg', 'status'], work_dir=self.path)
+        if stdout == '':
+            print "No changes"
+            return False
+        print stdout
+        if quiet:
+            commit = 'Y'
+        else:
+            commit = raw_input(push_remote and "Do you want to commit and push? Y/N: " or "Do you want to commit? Y/N: ")
+        if commit == 'Y':
+            args = ['hg', 'commit', '-u', MBED_ORG_USER]
+            
+            
+            # NOTE commit_msg should always come from the relevant mbed 2 release text
+            if commit_msg:
+                args = args + ['-m', commit_msg]
+            self.run_and_print(args, cwd=self.path)
+            if push_remote:
+                self.run_and_print(['hg', 'push'], cwd=self.path)
+        return True
+
+# Check if a file is a text file or a binary file
+# Taken from http://code.activestate.com/recipes/173220/
+text_characters = "".join(map(chr, range(32, 127)) + list("\n\r\t\b"))
+_null_trans = string.maketrans("", "")
+def is_text_file(filename):
+    block_size = 1024
+    def istext(s):
+        if "\0" in s:
+            return 0
+
+        if not s:  # Empty files are considered text
+            return 1
+
+        # Get the non-text characters (maps a character to itself then
+        # use the 'remove' option to get rid of the text characters.)
+        t = s.translate(_null_trans, text_characters)
+
+        # If more than 30% non-text characters, then
+        # this is considered a binary file
+        if float(len(t))/len(s) > 0.30:
+            return 0
+        return 1
+    with open(filename) as f:
+        res = istext(f.read(block_size))
+    return res
+
+# Return the line ending type for the given file ('cr' or 'crlf')
+def get_line_endings(f):
+  examine_size = 1024
+  try:
+    tf = open(f, "rb")
+    lines, ncrlf = tf.readlines(examine_size), 0
+    tf.close()
+    for l in lines:
+      if l.endswith("\r\n"):
+        ncrlf = ncrlf + 1
+    return 'crlf' if ncrlf > len(lines) >> 1 else 'cr'
+  except:
+    return 'cr'
+
+# Copy file to destination, but preserve destination line endings if possible
+# This prevents very annoying issues with huge diffs that appear because of
+# differences in line endings
+def copy_with_line_endings(sdk_file, repo_file):
+    if not isfile(repo_file):
+        copyfile(sdk_file, repo_file)
+        return
+    is_text = is_text_file(repo_file)
+    if is_text:
+        sdk_le = get_line_endings(sdk_file)
+        repo_le = get_line_endings(repo_file)
+    if not is_text or sdk_le == repo_le:
+        copyfile(sdk_file, repo_file)
+    else:
+        print "Converting line endings in '%s' to '%s'" % (abspath(repo_file), repo_le)
+        f = open(sdk_file, "rb")
+        data = f.read()
+        f.close()
+        f = open(repo_file, "wb")
+        data = data.replace("\r\n", "\n") if repo_le == 'cr' else data.replace('\n','\r\n')
+        f.write(data)
+        f.close()
+
+def visit_files(path, visit):
+    for root, dirs, files in walk(path):    
+        # Ignore hidden directories
+        for d in copy(dirs):
+            full = join(root, d)
+            if d.startswith('.'):
+                dirs.remove(d)
+            if ignore_path(full, IGNORE_DIRS):
+                print "Skipping '%s'" % full
+                dirs.remove(d)
+
+        for file in files:
+            if ignore_path(file, IGNORE_FILES):
+                continue
+
+            visit(join(root, file))
+
+def visit_dirs(path, visit):
+
+    for root, dirs, files in walk(path, topdown=False):            
+        for d in dirs:
+            full = join(root, d)
+            
+            # We don't want to remove the .hg directory
+            if not '.hg' in full:
+                visit(full)
+
+
+def update_repo(repo_name, sdk_paths, lib=False):
+    repo = MbedRepository(repo_name)
+    
+    # copy files from mbed SDK to mbed_official repository
+    def visit_mbed_sdk(sdk_file):
+
+        # Source files structure is different for the compiled binary lib 
+        # compared to the mbed-dev sources
+        if lib:
+            repo_file = join(repo.path, relpath(sdk_file, sdk_path))            
+        else:
+            repo_file = join(repo.path, sdk_file)
+        repo_dir = dirname(repo_file)
+        if not exists(repo_dir):
+            print("CREATING: %s" % repo_dir)
+            makedirs(repo_dir)
+
+        copy_with_line_endings(sdk_file, repo_file)
+
+    # Go through each path specified in the mbed structure 
+    for sdk_path in sdk_paths:
+
+        if isfile(sdk_path):
+            # Single file so just copy directly across
+            visit_mbed_sdk(sdk_path)
+        else:    
+            visit_files(sdk_path, visit_mbed_sdk)
+
+    def sdk_remove(repo_path):
+        
+        print("REMOVING: %s" % repo_path)
+        
+        # Check if this is an empty directory or a file before determining how to 
+        # delete it. As this function should only be called with a directory list
+        # after being called with a file list, the directory should automatically
+        # be either valid or empty .
+        if isfile(repo_path):
+            remove(repo_path)
+        elif isdir(repo_path) and not listdir(repo_path):
+            rmdir(repo_path)
+        else:
+            print("ERROR: %s is not empty, please remove manually." % repo_path)
+            print listdir(repo_path)
+            exit(1)
+
+    # remove repository files that do not exist in the mbed SDK
+    def visit_lib_repo(repo_path):
+        for sdk_path in sdk_paths:
+            sdk_file = join(sdk_path, relpath(repo_path, repo.path))
+            if not exists(sdk_file):
+                sdk_remove(repo_path)
+
+    # remove repository files that do not exist in the mbed SDK source
+    def visit_repo(repo_path):
+
+        # work out equivalent sdk path from repo file
+        sdk_path = join(getcwd(), relpath(repo_path, repo.path))
+
+        if not exists(sdk_path):
+            sdk_remove(repo_path)
+
+    # Go through each path specified in the mbed structure
+    # Check if there are any files in any of those paths that are no longer part of the SDK
+
+    if lib:
+        visit_files(repo.path, visit_lib_repo)
+        # Now do the same for directories that may need to be removed. This needs to be done
+        # bottom up to ensure any lower nested directories can be deleted first
+        visit_dirs(repo.path, visit_lib_repo)
+        
+    else:
+        visit_files(repo.path, visit_repo)
+
+        # Now do the same for directories that may need to be removed. This needs to be done
+        # bottom up to ensure any lower nested directories can be deleted first
+        visit_dirs(repo.path, visit_repo)
+    
+    if repo.publish():
+        changed.append(repo_name)
+
+
+def update_code(repositories):
+    for repo_name in repositories.keys():
+        sdk_dirs = repositories[repo_name]
+        print '\n=== Updating "%s" ===' % repo_name
+        update_repo(repo_name, sdk_dirs)
+
+
+def update_mbed():
+    update_repo("mbed", [join(BUILD_DIR, "mbed")], lib=True)
+
+def do_sync(options):
+    global push_remote, quiet, commit_msg, changed
+
+    push_remote = not options.nopush
+    quiet = options.quiet
+    commit_msg = options.msg
+    changed = []
+
+    if options.code:
+        update_code(OFFICIAL_CODE)
+
+    if options.mbed:
+        update_mbed()
+
+    if changed:
+        print "Repositories with changes:", changed
+
+    return changed
+
+if __name__ == '__main__':
+    parser = OptionParser()
+
+    parser.add_option("-c", "--code",
+                  action="store_true",  default=False,
+                  help="Update the mbed_official code")
+
+    parser.add_option("-m", "--mbed",
+                  action="store_true",  default=False,
+                  help="Release a build of the mbed library")
+
+    parser.add_option("-n", "--nopush",
+                  action="store_true", default=False,
+                  help="Commit the changes locally only, don't push them")
+
+    parser.add_option("", "--commit_message",
+                  action="store", type="string", default='', dest='msg',
+                  help="Commit message to use for all the commits")
+
+    parser.add_option("-q", "--quiet",
+                  action="store_true", default=False,
+                  help="Don't ask for confirmation before commiting or pushing")
+
+    (options, args) = parser.parse_args()
+
+    do_sync(options)
+
--- a/targets/REALTEK_RTL8195AM.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/targets/REALTEK_RTL8195AM.py	Tue Sep 25 13:43:09 2018 -0500
@@ -7,33 +7,47 @@
 import sys, array, struct, os, re, subprocess
 import hashlib
 import shutil
+import time
+import binascii
+import elftools
 
 from tools.paths import TOOLS_BOOTLOADERS
 from tools.toolchains import TOOLCHAIN_PATHS
-from datetime import datetime
 
 # Constant Variables
-RAM2_RSVD = 0x00000000
-RAM2_VER = 0x8195FFFF00000000
-RAM2_TAG = 0x81950001
-RAM2_SHA = '0'
+TAG = 0x81950001
+VER = 0x81950001
+CAMPAIGN = binascii.hexlify('FFFFFFFFFFFFFFFF')
 
-def write_fixed_width_string(value, width, output):
-        # cut string to list & reverse
-        line = [value[i:i+2] for i in range(0, len(value), 2)]
-        output.write("".join([chr(long(b, 16)) for b in line]))
+RAM2_HEADER = {
+    'tag': 0,
+    'ver': 0,
+    'timestamp': 0,
+    'size': 72,
+    'hash': 'FF',
+    'campaign': 'FF',
+    'crc32': 0xFFFFFFFF,
+}
 
-def write_fixed_width_value(value, width, output):
-        # convert to string
-        line = format(value, '0%dx' % (width))
-        if len(line) > width:
-            print "[ERROR] value 0x%s cannot fit width %d" % (line, width)
-            sys.exit(-1)
-        # cut string to list & reverse
-        line = [line[i:i+2] for i in range(0, len(line), 2)]
-        line.reverse()
-        # convert to write buffer
-        output.write("".join([chr(long(b, 16)) for b in line]))
+def format_number(number, width):
+    # convert to string
+    line = format(number, '0%dx' % (width))
+    if len(line) > width:
+        print "[ERROR] 0x%s cannot fit in width %d" % (line, width)
+        sys.exit(-1)
+    # cut string to list & reverse
+    line = [line[i:i+2] for i in range(0, len(line), 2)]
+    line.reverse()
+    return binascii.a2b_hex("".join(line))
+
+def format_string(string):
+    return binascii.a2b_hex(string)
+
+def write_number(value, width, output):
+    output.write(format_number(value, width))
+
+def write_string(value, width, output):
+    output.write(format_string(value))
 
 def append_image_file(image, output):
     input = open(image, "rb")
@@ -50,6 +64,9 @@
     output.write('\377' * padcount)
     output.close()
 
+def crc32_checksum(string):
+    return binascii.crc32(string) & 0xFFFFFFFF
+
 def sha256_checksum(filename, block_size=65536):
     sha256 = hashlib.sha256()
     with open(filename, 'rb') as f:
@@ -57,42 +74,9 @@
             sha256.update(block)
     return sha256.hexdigest()
 
-def get_version_by_time():
-    secs = int((datetime.now()-datetime(2016,11,1)).total_seconds())
-    return RAM2_VER + secs
-
-# ----------------------------
-#       main function
-# ----------------------------
-def prepend(image, entry, segment, image_ram2, image_ota):
-
-    # parse input arguments
-    output = open(image_ram2, "wb")
-
-    write_fixed_width_value(os.stat(image).st_size, 8, output)
-    write_fixed_width_value(int(entry), 8, output)
-    write_fixed_width_value(int(segment), 8, output)
-
-    RAM2_SHA = sha256_checksum(image)
-    write_fixed_width_value(RAM2_TAG, 8, output)
-    write_fixed_width_value(get_version_by_time(), 16, output)
-    write_fixed_width_string(RAM2_SHA, 64, output)
-    write_fixed_width_value(RAM2_RSVD, 8, output)
-
-    append_image_file(image, output)
-    output.close()
-
-    ota = open(image_ota, "wb")
-    write_fixed_width_value(os.stat(image).st_size, 8, ota)
-    write_fixed_width_value(int(entry), 8, ota)
-    write_fixed_width_value(int(segment), 8, ota)
-    write_fixed_width_value(0xFFFFFFFF, 8, ota)
-    write_fixed_width_value(get_version_by_time(), 16, ota)
-    write_fixed_width_string(RAM2_SHA, 64, ota)
-    write_fixed_width_value(RAM2_RSVD, 8, ota)
-
-    append_image_file(image, ota)
-    ota.close()
+def epoch_timestamp():
+    epoch = int(time.time())
+    return epoch
 
 def find_symbol(toolchain, mapfile, symbol):
     ret = None
@@ -117,164 +101,85 @@
 
     return int(ret,16) | 1
 
-def parse_load_segment_gcc(image_elf):
-    # Program Headers:
-    #   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
-    #   LOAD           0x000034 0x10006000 0x10006000 0x026bc 0x026bc RW  0x8
-    #   LOAD           0x0026f0 0x30000000 0x30000000 0x06338 0x06338 RWE 0x4
-    segment_list = []
-    cmd = os.path.join(TOOLCHAIN_PATHS['GCC_ARM'], 'arm-none-eabi-readelf')
-    cmd = '"' + cmd + '"' + ' -l ' + image_elf
-    for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
-        if not line.startswith("  LOAD"):
-            continue
-        segment = line.split()
-        if len(segment) != 8:
-            continue
-        offset = int(segment[1][2:], 16)
-        addr   = int(segment[2][2:], 16)
-        size   = int(segment[4][2:], 16)
-        if addr != 0 and size != 0:
-            segment_list.append((offset, addr, size))
-    return segment_list
-
-def parse_load_segment_armcc(image_elf):
-    # ====================================
-    #
-    # ** Program header #2
-    #
-    #     Type          : PT_LOAD (1)
-    #     File Offset   : 52 (0x34)
-    #     Virtual Addr  : 0x30000000
-    #     Physical Addr : 0x30000000
-    #     Size in file  : 27260 bytes (0x6a7c)
-    #     Size in memory: 42168 bytes (0xa4b8)
-    #     Flags         : PF_X + PF_W + PF_R + PF_ARM_ENTRY (0x80000007)
-    #     Alignment     : 8
-    #
-    (offset, addr, size) = (0, 0, 0)
-    segment_list = []
-    in_segment = False
-    cmd = os.path.join(TOOLCHAIN_PATHS['ARM'], 'bin', 'fromelf')
-    cmd = '"' + cmd + '"' + ' --text -v --only=none ' + image_elf
-    for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
-        if line == "":
-            pass
-        elif line.startswith("** Program header"):
-            in_segment = True
-        elif in_segment == False:
-            pass
-        elif line.startswith("============"):
-            if addr != 0 and size != 0:
-                segment_list.append((offset, addr, size))
-            in_segment = False
-            (offset, addr, size) = (0, 0, 0)
-        elif line.startswith("    Type"):
-            if not re.match(r'\s+Type\s+:\s+PT_LOAD\s.*$', line):
-                in_segment = False
-        elif line.startswith("    File Offset"):
-            match = re.match(r'^\s+File Offset\s+:\s+(?P<offset>\d+).*$', line)
-            if match:
-                offset = int(match.group("offset"))
-        elif line.startswith("    Virtual Addr"):
-            match = re.match(r'^\s+Virtual Addr\s+:\s+0x(?P<addr>[0-9a-f]+).*$', line)
-            if match:
-                addr = int(match.group("addr"), 16)
-        elif line.startswith("    Size in file"):
-            match = re.match(r'^\s+Size in file\s+:.*\(0x(?P<size>[0-9a-f]+)\).*$', line)
-            if match:
-                size = int(match.group("size"), 16)
-    return segment_list
-
-
-def parse_load_segment_iar(image_elf):
-    #   SEGMENTS:
-    #
-    #      Type Offset    Virtual   Physical File Sz Mem Sz Flags   Align
-    #      ---- ------    -------   -------- ------- ------ -----   -----
-    #   0: load   0x34 0x10006000 0x10006000  0x26bc 0x26bc 0x6  WR   0x8
-    #   1: load 0x26f0 0x30000000 0x30000000  0x6338 0x6338 0x7 XWR   0x4
-    #
-    #   SECTIONS:
-    #
-    #       Name            Type     Addr         Offset    Size Aln Lnk Inf  ESz Flags
-    #       ----            ----     ----         ------    ---- --- --- ---  --- -----
-    #    1: .shstrtab       strtab               0xfc4d8    0x60 0x4
-    #    2: .strtab         strtab               0xfc538  0xbb3f 0x4
-
-    segment_list = []
-    in_segment = False
-    cmd = os.path.join(TOOLCHAIN_PATHS['IAR'], 'bin', 'ielfdumparm')
-    cmd = '"' + cmd + '"' + ' ' + image_elf
-    for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
-        if line.startswith("  SEGMENTS:"):
-            in_segment = True
-        elif in_segment == False:
-            pass
-        elif line.startswith("  SECTIONS:"):
-            break
-        elif re.match(r'^\s+\w+:\s+load\s+.*$', line):
-            segment = line.split()
-            offset = int(segment[2][2:], 16)
-            addr   = int(segment[3][2:], 16)
-            size   = int(segment[5][2:], 16)
-            if addr < 0x10007000:
-                continue
-            if addr != 0 and size != 0:
-                segment_list.append((offset, addr, size))
-    return segment_list
+def _parse_load_segment_inner(image_elf):
+    with open(image_elf, "rb") as fd:
+        elffile = elftools.elf.elffile.ELFFile(fd)
+        for segment in elffile.iter_segments():
+            offset = segment['p_offset']
+            addr = segment['p_vaddr']
+            size = segment['p_filesz']
+            if (addr != 0 and size != 0 and segment['p_type'] == 'PT_LOAD'):
+                yield offset, addr, size
 
 def parse_load_segment(toolchain, image_elf):
-    if toolchain == "GCC_ARM":
-        return parse_load_segment_gcc(image_elf)
-    elif toolchain in ["ARM_STD", "ARM", "ARM_MICRO"]:
-        return parse_load_segment_armcc(image_elf)
-    elif toolchain == "IAR":
-        return parse_load_segment_iar(image_elf)
-    else:
-        return []
+    return list(_parse_load_segment_inner(image_elf))
+
+def create_payload(image_elf, ram2_bin, entry, segment):
+    file_elf = open(image_elf, "rb")
+    file_bin = open(ram2_bin, "wb")
 
-def write_load_segment(image_elf, image_bin, segment):
-    file_elf = open(image_elf, "rb")
-    file_bin = open(image_bin, "wb")
+    write_number(int(entry), 8, file_bin)
+    write_number(int(len(segment)), 8, file_bin)
+    write_number(0xFFFFFFFF, 8, file_bin)
+    write_number(0xFFFFFFFF, 8, file_bin)
+
     for (offset, addr, size) in segment:
         file_elf.seek(offset)
         # write image header - size & addr
-        write_fixed_width_value(addr, 8, file_bin)
-        write_fixed_width_value(size, 8, file_bin)
+        write_number(addr, 8, file_bin)
+        write_number(size, 8, file_bin)
         # write load segment
         file_bin.write(file_elf.read(size))
         delta = size % 4
         if delta != 0:
             padding = 4 - delta
-            write_fixed_width_value(0x0, padding * 2, file_bin)
+            write_number(0x0, padding * 2, file_bin)
     file_bin.close()
     file_elf.close()
 
-# ----------------------------
-#       main function
-# ----------------------------
-def rtl8195a_elf2bin(t_self, image_elf, image_bin):
+def create_daplink(image_bin, ram1_bin, ram2_bin):
+
     # remove target binary file/path
     if os.path.isfile(image_bin):
         os.remove(image_bin)
     else:
         shutil.rmtree(image_bin)
 
-    segment = parse_load_segment(t_self.name, image_elf)
-    write_load_segment(image_elf, image_bin, segment)
-
-    image_name = os.path.splitext(image_elf)[0]
-    image_map = image_name + '.map'
+    RAM2_HEADER['tag'] = format_number(TAG, 8)
+    RAM2_HEADER['ver'] = format_number(VER, 8)
+    RAM2_HEADER['timestamp'] = format_number(epoch_timestamp(), 16)
+    RAM2_HEADER['size'] = format_number(os.stat(ram2_bin).st_size + 72, 8)
+    RAM2_HEADER['hash'] = format_string(sha256_checksum(ram2_bin))
+    RAM2_HEADER['campaign'] = format_string(CAMPAIGN)
 
-    ram2_ent = find_symbol(t_self.name, image_map, "PLAT_Start")
-    ram1_bin = os.path.join(TOOLS_BOOTLOADERS, "REALTEK_RTL8195AM", "ram_1.bin")
-    ram2_bin = image_name + '-ram_2.bin'
-    ota_bin = image_name + '-ota.bin'
-    prepend(image_bin, ram2_ent, len(segment), ram2_bin, ota_bin)
-
-    # write output file
     output = open(image_bin, "wb")
     append_image_file(ram1_bin, output)
     append_image_file(ram2_bin, output)
+
+    output.seek(0xb000)
+    line = ""
+    for key in ['tag', 'ver', 'timestamp', 'size', 'hash', 'campaign']:
+        line += RAM2_HEADER[key]
+        output.write(RAM2_HEADER[key])
+
+    RAM2_HEADER['crc32'] = format_number(crc32_checksum(line), 8)
+
+    output.write(RAM2_HEADER['crc32'])
     output.close()
+
+# ----------------------------
+#       main function
+# ----------------------------
+def rtl8195a_elf2bin(t_self, image_elf, image_bin):
+
+    image_name = list(os.path.splitext(image_elf))[:-1]
+    image_map = ".".join(image_name + ['map'])
+
+    ram1_bin = os.path.join(TOOLS_BOOTLOADERS, "REALTEK_RTL8195AM", "ram_1.bin")
+    ram2_bin = ".".join(image_name) + '-payload.bin'
+
+    entry = find_symbol(t_self.name, image_map, "PLAT_Start")
+    segment = parse_load_segment(t_self.name, image_elf)
+
+    create_payload(image_elf, ram2_bin, entry, segment)
+    create_daplink(image_bin, ram1_bin, ram2_bin)
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/STM32_gen_PeripheralPins.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,1223 @@
+"""
+* mbed Microcontroller Library
+* Copyright (c) 2006-2018 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+"""
+
+import argparse
+import datetime
+import fnmatch
+import json
+import os
+import re
+import sys
+import textwrap
+from xml.dom.minidom import parse, Node
+from argparse import RawTextHelpFormatter
+
+GENPINMAP_VERSION = "1.3"
+
+ADD_DEVICE_IFDEF = 0
+ADD_QSPI_FEATURE = 1
+
+mcu_file=""
+mcu_list = []       #'name'
+io_list = []        #'PIN','name'
+adclist = []        #'PIN','name','ADCSignal'
+daclist = []        #'PIN','name','DACSignal'
+i2cscl_list = []    #'PIN','name','I2CSCLSignal'
+i2csda_list = []    #'PIN','name','I2CSDASignal'
+pwm_list = []       #'PIN','name','PWM'
+uarttx_list = []    #'PIN','name','UARTtx'
+uartrx_list = []    #'PIN','name','UARTrx'
+uartcts_list = []   #'PIN','name','UARTcts'
+uartrts_list = []   #'PIN','name','UARTrts'
+spimosi_list = []   #'PIN','name','SPIMOSI'
+spimiso_list = []   #'PIN','name','SPIMISO'
+spissel_list = []   #'PIN','name','SPISSEL'
+spisclk_list = []   #'PIN','name','SPISCLK'
+cantd_list = []     #'PIN','name','CANTD'
+canrd_list = []     #'PIN','name','CANRD'
+eth_list = []       #'PIN','name','ETH'
+quadspidata_list = []      #'PIN','name','QUADSPIDATA'
+quadspisclk_list = []      #'PIN','name','QUADSPISCLK'
+quadspissel_list = []      #'PIN','name','QUADSPISSEL'
+usb_list = []      #'PIN','name','USB'
+osc_list = []      #'PIN','name','OSC'
+sys_list = []      #'PIN','name','SYS'
+
+TIM_MST_LIST = { # Timer used for us ticker is hardcoded in this script
+"NUCLEO_F030R8":"TIM1",
+"NUCLEO_F072RB":"TIM2",
+"NUCLEO_F091RC":"TIM2",
+"NUCLEO_F070RB":"TIM1",
+"NUCLEO_F042K6":"TIM2",
+"NUCLEO_F031K6":"TIM2",
+"NUCLEO_F103RB":"TIM4",
+"NUCLEO_F207ZG":"TIM5",
+"NUCLEO_F302R8":"TIM2",
+"NUCLEO_F334R8":"TIM2",
+"NUCLEO_F303RE":"TIM2",
+"NUCLEO_F303K8":"TIM2",
+"NUCLEO_F303ZE":"TIM2",
+"NUCLEO_F401RE":"TIM5",
+"NUCLEO_F411RE":"TIM5",
+"NUCLEO_F446RE":"TIM5",
+"NUCLEO_F410RB":"TIM5",
+"NUCLEO_F429ZI":"TIM5",
+"NUCLEO_F446ZE":"TIM5",
+"NUCLEO_F412ZG":"TIM5",
+"NUCLEO_F413ZH":"TIM5",
+"NUCLEO_F746ZG":"TIM5",
+"NUCLEO_F767ZI":"TIM5",
+"NUCLEO_F722ZE":"TIM5",
+"NUCLEO_H743ZI":"TIM5",
+"NUCLEO_L053R8":"TIM21",
+"NUCLEO_L073RZ":"TIM21",
+"NUCLEO_L031K6":"TIM21",
+"NUCLEO_L011K4":"TIM21",
+"NUCLEO_L152RE":"TIM5",
+"NUCLEO_L476RG":"TIM5",
+"NUCLEO_L432KC":"TIM2",
+"NUCLEO_L496ZG":"TIM5",
+"NUCLEO_L496ZG_P":"TIM5",
+"NUCLEO_L433RC_P":"TIM2",
+
+"DISCO_F051R8":"TIM1",
+"DISCO_F100RB":"TIM4",
+"DISCO_F303VC":"TIM2",
+"DISCO_F334C8":"TIM2",
+"DISCO_F401VC":"TIM5",
+"DISCO_F407VG":"TIM5",
+"DISCO_F413ZH":"TIM5",
+"DISCO_F429ZI":"TIM5",
+"DISCO_F469NI":"TIM5",
+"DISCO_F769NI":"TIM5",
+"DISCO_F746NG":"TIM5",
+"DISCO_L053C8":"TIM21",
+"DISCO_L072CZ_LRWAN1":"TIM21",
+"DISCO_L475VG_IOT01A":"TIM5",
+"DISCO_L476VG":"TIM5",
+"DISCO_L496AG":"TIM5"
+}
+
+
+def find_gpio_file():
+    res = 'ERROR'
+    itemlist = xml_mcu.getElementsByTagName('IP')
+    for s in itemlist:
+        a = s.attributes['Name'].value
+        if "GPIO" in a:
+            res = s.attributes['Version'].value
+    return res
+
+def get_gpio_af_num(pintofind, iptofind):
+    if 'STM32F10' in mcu_file:
+        return get_gpio_af_numF1(pintofind, iptofind)
+    #DBG print ('pin to find ' + pintofind)
+    i=0
+    mygpioaf = 'NOTFOUND'
+    for n in  xml_gpio.documentElement.childNodes:
+        i += 1
+        j = 0
+        if n.nodeType == Node.ELEMENT_NODE:
+            for firstlevel in n.attributes.items():
+#                if 'PB7' in firstlevel:
+                if pintofind ==  firstlevel[1]:
+                    #DBG print (i , firstlevel)
+                    #n = pin node found
+                    for m in n.childNodes:
+                        j += 1
+                        k = 0
+                        if m.nodeType == Node.ELEMENT_NODE:
+                            for secondlevel in  m.attributes.items():
+                                k += 1
+#                                if 'I2C1_SDA' in secondlevel:
+                                if iptofind in secondlevel:
+                                    #DBG print (i, j,  m.attributes.items())
+                                    # m = IP node found
+                                    for p in m.childNodes:
+                                        if p.nodeType == Node.ELEMENT_NODE:
+                                            #p node of 'Specific parameter'
+                                            #DBG print (i,j,k,p.attributes.items())
+                                            for myc in p.childNodes:
+                                                #DBG print (myc)
+                                                if myc.nodeType == Node.ELEMENT_NODE:
+                                                    #myc = node of ALTERNATE
+                                                    for mygpioaflist in myc.childNodes:
+                                                        mygpioaf += ' ' + mygpioaflist.data
+                                                        #print (mygpioaf)
+    if mygpioaf == 'NOTFOUND':
+        print ('GPIO AF not found in ' + gpiofile + ' for ' + pintofind + ' and the IP ' + iptofind)
+        #quit()
+    return mygpioaf.replace('NOTFOUND ', '')
+
+def get_gpio_af_numF1(pintofind, iptofind):
+    #print ('pin to find ' + pintofind + ' ip to find ' + iptofind)
+    i=0
+    mygpioaf = 'NOTFOUND'
+    for n in  xml_gpio.documentElement.childNodes:
+        i += 1
+        j = 0
+        if n.nodeType == Node.ELEMENT_NODE:
+            for firstlevel in n.attributes.items():
+                #print ('firstlevel ' , firstlevel)
+#                if 'PB7' in firstlevel:
+                if pintofind ==  firstlevel[1]:
+                    #print ('firstlevel ' , i , firstlevel)
+                    #n = pin node found
+                    for m in n.childNodes:
+                        j += 1
+                        k = 0
+                        if m.nodeType == Node.ELEMENT_NODE:
+                            for secondlevel in  m.attributes.items():
+                                #print ('secondlevel ' , i, j, k , secondlevel)
+                                k += 1
+#                                if 'I2C1_SDA' in secondlevel:
+                                if iptofind in secondlevel:
+                                    # m = IP node found
+                                    #print (i, j,  m.attributes.items())
+                                    for p in m.childNodes:
+                                        #p node 'RemapBlock'
+                                        if p.nodeType == Node.ELEMENT_NODE and p.hasChildNodes() == False:
+                                            mygpioaf += ' AFIO_NONE'
+                                        else:
+                                            for s in p.childNodes:
+                                                if s.nodeType == Node.ELEMENT_NODE:
+                                                    #s node 'Specific parameter'
+                                                    #DBG print (i,j,k,p.attributes.items())
+                                                    for myc in s.childNodes:
+                                                        #DBG print (myc)
+                                                        if myc.nodeType == Node.ELEMENT_NODE:
+                                                            #myc = AF value
+                                                            for mygpioaflist in myc.childNodes:
+                                                                mygpioaf += ' ' + mygpioaflist.data.replace("__HAL_", "").replace("_REMAP", "")
+                                                                #print mygpioaf
+    if mygpioaf == 'NOTFOUND':
+        print ('GPIO AF not found in ' + gpiofile + ' for ' + pintofind + ' and the IP ' + iptofind + ' set as AFIO_NONE')
+        mygpioaf = 'AFIO_NONE'
+    return mygpioaf.replace('NOTFOUND ', '')\
+        .replace("AFIO_NONE", "0")\
+        .replace("AFIO_SPI1_ENABLE", "1")\
+        .replace("AFIO_I2C1_ENABLE", "2")\
+        .replace("AFIO_USART1_ENABLE", "3")\
+        .replace("AFIO_USART3_PARTIAL", "5")\
+        .replace("AFIO_TIM1_PARTIAL", "6")\
+        .replace("AFIO_TIM3_PARTIAL", "7")\
+        .replace("AFIO_TIM2_ENABLE", "8")\
+        .replace("AFIO_TIM3_ENABLE", "9")\
+        .replace("AFIO_CAN1_2", "10")
+
+#function to store I/O pin
+def store_pin (pin, name):
+    p = [pin, name]
+    io_list.append(p)
+
+#function to store ADC list
+def store_adc (pin, name, signal):
+    adclist.append([pin,name,signal])
+
+#function to store DAC list
+def store_dac (pin, name, signal):
+    daclist.append([pin,name,signal])
+
+#function to store I2C list
+def store_i2c (pin, name, signal):
+    #is it SDA or SCL ?
+    if "_SCL" in signal:
+        i2cscl_list.append([pin,name,signal])
+    if "_SDA" in signal:
+        i2csda_list.append([pin,name,signal])
+
+#function to store timers
+def store_pwm(pin, name, signal):
+    if "_CH" in signal:
+        pwm_list.append([pin,name,signal])
+
+#function to store Uart pins
+def store_uart(pin, name, signal):
+    if "_TX" in signal:
+        uarttx_list.append([pin,name,signal])
+    if "_RX" in signal:
+        uartrx_list.append([pin,name,signal])
+    if "_CTS" in signal:
+        uartcts_list.append([pin,name,signal])
+    if "_RTS" in signal:
+        uartrts_list.append([pin,name,signal])
+
+#function to store SPI pins
+def store_spi(pin, name, signal):
+    if "_MISO" in signal:
+        spimiso_list.append([pin,name,signal])
+    if "_MOSI" in signal:
+        spimosi_list.append([pin,name,signal])
+    if "_SCK" in signal:
+        spisclk_list.append([pin,name,signal])
+    if "_NSS" in signal:
+        spissel_list.append([pin,name,signal])
+
+#function to store CAN pins
+def store_can(pin, name, signal):
+    if "_RX" in signal:
+        canrd_list.append([pin,name,signal])
+    if "_TX" in signal:
+        cantd_list.append([pin,name,signal])
+
+#function to store ETH list
+def store_eth (pin, name, signal):
+    eth_list.append([pin,name,signal])
+
+#function to store QSPI pins
+def store_qspi (pin, name, signal):
+    if "_BK" in signal:
+        quadspidata_list.append([pin,name,signal])
+    if "_CLK" in signal:
+        quadspisclk_list.append([pin,name,signal])
+    if "_NCS" in signal:
+        quadspissel_list.append([pin,name,signal])
+
+#function to store USB pins
+def store_usb (pin, name, signal):
+    usb_list.append([pin,name,signal])
+
+#function to store OSC pins
+def store_osc (pin, name, signal):
+    osc_list.append([pin,name,signal])
+
+#function to store SYS pins
+def store_sys (pin, name, signal):
+    sys_list.append([pin,name,signal])
+
+def print_header():
+    s =  ("""/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) %i, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ *
+ * Automatically generated from %s
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+//   See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+""" % (datetime.datetime.now().year, os.path.basename(input_file_name)))
+    out_c_file.write( s )
+
+    s =  ("""/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) %i, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ *
+ * Automatically generated from %s
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
+typedef enum {
+
+""" % (datetime.datetime.now().year, os.path.basename(input_file_name)))
+    out_h_file.write( s )
+
+
+def print_footer():
+    s = ("""
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+""")
+    out_h_file.write(s)
+
+
+def print_all_lists():
+    if print_list_header("ADC", "ADC", adclist, "ANALOGIN"):
+        print_adc()
+    if print_list_header("DAC", "DAC", daclist, "ANALOGOUT"):
+        print_dac()
+    if print_list_header("I2C", "I2C_SDA", i2csda_list, "I2C"):
+        print_i2c(i2csda_list)
+    if print_list_header("", "I2C_SCL", i2cscl_list, "I2C"):
+        print_i2c(i2cscl_list)
+    if print_list_header("PWM", "PWM", pwm_list, "PWMOUT"):
+        print_pwm()
+    if print_list_header("SERIAL", "UART_TX", uarttx_list, "SERIAL"):
+        print_uart(uarttx_list)
+    if print_list_header("", "UART_RX", uartrx_list, "SERIAL"):
+        print_uart(uartrx_list)
+    if print_list_header("", "UART_RTS", uartrts_list, "SERIAL"):
+        print_uart(uartrts_list)
+    if print_list_header("", "UART_CTS", uartcts_list, "SERIAL"):
+        print_uart(uartcts_list)
+    if print_list_header("SPI", "SPI_MOSI", spimosi_list, "SPI"):
+        print_spi(spimosi_list)
+    if print_list_header("", "SPI_MISO", spimiso_list, "SPI"):
+        print_spi(spimiso_list)
+    if print_list_header("", "SPI_SCLK", spisclk_list, "SPI"):
+        print_spi(spisclk_list)
+    if print_list_header("", "SPI_SSEL", spissel_list, "SPI"):
+        print_spi(spissel_list)
+    if print_list_header("CAN", "CAN_RD", canrd_list, "CAN"):
+        print_can(canrd_list)
+    if print_list_header("", "CAN_TD", cantd_list, "CAN"):
+        print_can(cantd_list)
+    if ADD_QSPI_FEATURE:
+        if print_list_header("QUADSPI", "QSPI_DATA", quadspidata_list, "QSPI"):
+            print_qspi(quadspidata_list)
+        if print_list_header("", "QSPI_SCLK", quadspisclk_list, "QSPI"):
+            print_qspi(quadspisclk_list)
+        if print_list_header("", "QSPI_SSEL", quadspissel_list, "QSPI"):
+            print_qspi(quadspissel_list)
+    print_h_file(usb_list, "USB")
+    print_h_file(eth_list, "ETHERNET")
+    print_h_file(osc_list, "OSCILLATOR")
+    print_h_file(sys_list, "DEBUG")
+
+def print_list_header(comment, name, l, switch):
+    s = ""
+    if len(l)>0:
+        if comment:
+            s += "\n//*** %s ***\n" % comment
+
+        s += "\n"
+
+        if name == "PWM":
+            if TargetName in TIM_MST_LIST.keys():
+                s += "// %s cannot be used because already used by the us_ticker\n" % TIM_MST_LIST[TargetName]
+            else:
+                s += "// TIM<x> cannot be used because already used by the us_ticker\n"
+                s += "// You have to comment all PWM using TIM_MST defined in hal_tick.h file\n"
+                s += "//  or update python script (check TIM_MST_LIST) and re-run it\n"
+
+        if ADD_DEVICE_IFDEF:
+            s += "#ifdef DEVICE_%s\n" % switch
+
+        s += "MBED_WEAK const PinMap PinMap_%s[] = {\n" % name
+
+    # else:
+    #     if comment:
+    #         s += "\n//*** No %s ***\n" % comment
+
+    out_c_file.write(s)
+    return len(l)
+
+def print_adc():
+    s_pin_data = 'STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, '
+    prev_p = ''
+    alt_index = 0
+    for p in adclist:
+        if "IN" in p[2]:
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "STDIO_UART" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            if CommentedLine != "//":
+                if p[0] == prev_p:
+                    prev_p = p[0]
+                    p[0] += '_ALT%d' % alt_index
+                    alt_index += 1
+                else:
+                    prev_p = p[0]
+                    alt_index = 0
+            s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+            a = p[2].split('_')
+            inst = a[0].replace("ADC", "")
+            if len(inst) == 0:
+                inst = '1' #single ADC for this product
+            s1 += "%-7s" % ('ADC_' + inst + ',')
+            chan = re.sub('IN[N|P]?', '', a[1])
+            s1 += s_pin_data + chan
+            s1 += ', 0)}, // ' + p[2]
+            if p[1] in PinLabel.keys():
+                s1 += ' // Connected to ' + PinLabel[p[1]]
+            s1 += '\n'
+            out_c_file.write(s1)
+    out_c_file.write( """    {NC, NC, 0}
+};
+
+// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+    {ADC_VREF,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VBAT,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_dac():
+    for p in daclist:
+        CommentedLine = "  "
+        if p[1] in PinLabel.keys():
+            if "STDIO_UART" in PinLabel[p[1]]:
+                CommentedLine = "//"
+            if "RCC_OSC" in PinLabel[p[1]]:
+                CommentedLine = "//"
+        s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+        #p[2] : DAC_OUT1 / DAC1_OUT1
+        a = p[2].split('_')
+        inst = a[0].replace("DAC", "")
+        b = a[1].replace("OUT", "")
+        if len(inst) == 0:
+            inst = '1'  # single DAC for this product
+        s1 += "%-7s" % ('DAC_' + inst + ',')
+        s1 += 'STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, ' + b + ', 0)}, // ' + p[2]
+        if p[1] in PinLabel.keys():
+            s1 += ' // Connected to ' + PinLabel[p[1]]
+        s1 += '\n'
+        out_c_file.write(s1)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_i2c(l):
+    prev_p = ''
+    alt_index = 0
+    for p in l:
+        result = get_gpio_af_num(p[1], p[2])
+        if result != 'NOTFOUND':
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "STDIO_UART" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            if CommentedLine != "//":
+                if p[0] == prev_p:
+                    prev_p = p[0]
+                    p[0] += '_ALT%d' % alt_index
+                    alt_index += 1
+                else:
+                    prev_p = p[0]
+                    alt_index = 0
+            s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+            # p[2] : I2C1_SDA / FMPI2C1_SDA
+            if "FMP" in p[2]:
+                inst = p[2].split('_')[0].replace("FMPI2C", "")
+                s1 += "%-10s" % ('FMPI2C_' + inst + ',')
+            else:
+                inst = p[2].split('_')[0].replace("I2C", "")
+                s1 += "%-7s" % ('I2C_' + inst + ',')
+            s1 += 'STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, '
+            r = result.split(' ')
+            for af in r:
+                s2 = s1 + af  + ')},'
+                if p[1] in PinLabel.keys():
+                    s2 += ' // Connected to ' + PinLabel[p[1]]
+                s2 += '\n'
+                out_c_file.write(s2)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_pwm():
+    prev_p = ''
+    alt_index = 0
+    TIM_MST = "NOT_KNOWN"
+    if TargetName in TIM_MST_LIST.keys():
+        TIM_MST = TIM_MST_LIST[TargetName]
+    for p in pwm_list:
+        result = get_gpio_af_num(p[1], p[2])
+        if result != 'NOTFOUND':
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "STDIO_UART" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            if "%s_" % TIM_MST in p[2]:
+                CommentedLine = "//"
+            if CommentedLine != "//":
+                if p[0] == prev_p:
+                    prev_p = p[0]
+                    p[0] += '_ALT%d' % alt_index
+                    alt_index += 1
+                else:
+                    prev_p = p[0]
+                    alt_index = 0
+            s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+            # p[2] : TIM2_CH1 / TIM15_CH1N
+            a = p[2].split('_')
+            inst = a[0].replace("TIM", "PWM_")
+            # if len(inst) == 3:
+            #     inst += '1'
+            s1 += "%-8s" % (inst + ',')
+            chan = a[1].replace("CH", "")
+            if chan.endswith('N'):
+                neg = ', 1'
+                chan = chan.strip('N')
+            else:
+                neg = ', 0'
+            s1 += 'STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, '
+            r = result.split(' ')
+            for af in r:
+                s2 = s1 + af + ', ' + chan + neg + ')}, // ' + p[2]
+                if p[1] in PinLabel.keys():
+                    s2 += ' // Connected to ' + PinLabel[p[1]]
+                s2 += '\n'
+                out_c_file.write(s2)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_uart(l):
+    prev_p = ''
+    alt_index = 0
+    for p in l:
+        result = get_gpio_af_num(p[1], p[2])
+        if result != 'NOTFOUND':
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            if CommentedLine != "//":
+                if p[0] == prev_p:
+                    prev_p = p[0]
+                    p[0] += '_ALT%d' % alt_index
+                    alt_index += 1
+                else:
+                    prev_p = p[0]
+                    alt_index = 0
+            s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+            # p[2] : USART2_RX
+            b=p[2].split('_')[0]
+            b = b.replace("UART", "UART_")
+            b = b.replace("USART", "UART_")
+            s1 += "%-9s" % (b[:len(b)-1] +  b[len(b)-1:] + ',')
+            if 'STM32F10' in mcu_file and l == uartrx_list:
+                s1 += 'STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, '
+            else:
+                s1 += 'STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, '
+            r = result.split(' ')
+            for af in r:
+                s2 = s1 + af  + ')},'
+                if p[1] in PinLabel.keys():
+                    s2 += ' // Connected to ' + PinLabel[p[1]]
+                s2 += '\n'
+                out_c_file.write(s2)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_spi(l):
+    prev_p = ''
+    alt_index = 0
+    for p in l:
+        result = get_gpio_af_num(p[1], p[2])
+        if result != 'NOTFOUND':
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "STDIO_UART" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            if CommentedLine != "//":
+                if p[0] == prev_p:
+                    prev_p = p[0]
+                    p[0] += '_ALT%d' % alt_index
+                    alt_index += 1
+                else:
+                    prev_p = p[0]
+                    alt_index = 0
+            s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+            # p[2] : SPI1_MISO
+            instance=p[2].split('_')[0].replace("SPI", "")
+            s1 += "%-7s" % ('SPI_' + instance + ',')
+            s1 += 'STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, '
+            r = result.split(' ')
+            for af in r:
+                s2 = s1 + af  + ')},'
+                if p[1] in PinLabel.keys():
+                    s2 += ' // Connected to ' + PinLabel[p[1]]
+                s2 += '\n'
+                out_c_file.write(s2)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_can(l):
+    for p in l:
+        result = get_gpio_af_num(p[1], p[2])
+        if result != 'NOTFOUND':
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "STDIO_UART" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            s1 = "%-17s" % (CommentedLine + "  {" + p[0] + ',')
+            # p[2] : CAN_RX / CAN1_RX
+            p[2] = p[2].replace("FD", "")
+            instance = p[2].split('_')[0].replace("CAN", "")
+            if len(instance) == 0:
+                instance = '1'
+            s1 += "%-7s" % ('CAN_' + instance + ',')
+            if 'STM32F10' in mcu_file and l == canrd_list:
+                s1 += 'STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, '
+            else:
+                s1 += 'STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, '
+            r = result.split(' ')
+            for af in r:
+                s2 = s1 + af  + ')},'
+                if p[1] in PinLabel.keys():
+                    s2 += ' // Connected to ' + PinLabel[p[1]]
+                s2 += '\n'
+                out_c_file.write(s2)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_qspi(l):
+    for p in l:
+        result = get_gpio_af_num(p[1], p[2])
+        if result != 'NOTFOUND':
+            CommentedLine = "  "
+            if p[1] in PinLabel.keys():
+                if "STDIO_UART" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+                if "RCC_OSC" in PinLabel[p[1]]:
+                    CommentedLine = "//"
+            s1 = "%-16s" % (CommentedLine + "  {" + p[0] + ',')
+            # p[2] : QUADSPI_BK1_IO3 / QUADSPI_CLK / QUADSPI_NCS
+            s1 += "%-8s" % ('QSPI_1,')
+            result = result.replace("GPIO_AF10_OTG_FS", "GPIO_AF10_QSPI")
+            s1 += 'STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, ' + result +')},'
+            s1 += '  // ' + p[2]
+            if p[1] in PinLabel.keys():
+                s1 += ' // Connected to ' + PinLabel[p[1]]
+            s1 += '\n'
+            out_c_file.write(s1)
+    out_c_file.write( """    {NC, NC, 0}
+};
+""")
+    if ADD_DEVICE_IFDEF:
+        out_c_file.write( "#endif\n" )
+
+def print_h_file(l, comment):
+    if len(l) > 0:
+        s = ("\n/**** %s pins ****/\n" % comment)
+        out_h_file.write(s)
+
+        prev_s = ''
+        alt_index = 0
+        for p in l:
+            if p[2] == prev_s:
+                prev_s = p[2]
+                p[2] += '_ALT%d' % alt_index
+                alt_index += 1
+            else:
+                prev_s = p[2]
+                alt_index = 0
+            s1 = "    %s = %s,\n" % (p[2].replace("-", "_"), p[0])
+            out_h_file.write(s1)
+    # else:
+    #     s = ("\n/**** No %s pins ***/\n" % comment)
+    #     out_h_file.write(s)
+
+
+tokenize = re.compile(r'(\d+)|(\D+)').findall
+
+def natural_sortkey(list_2_elem):
+    return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[0]))
+
+def natural_sortkey2(list_2_elem):
+    return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[2]))
+
+def natural_sortkey_uart(list_2_elem):
+    return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[2].replace("USART", "UART").replace("LPUART", "ZUART")))
+
+def natural_sortkey_i2c(list_2_elem):
+    return tuple(int(num) if num else alpha for num, alpha in tokenize(list_2_elem[2].replace("FMPI2C", "ZFMPI2C")))
+
+def sort_my_lists():
+    adclist.sort(key=natural_sortkey)
+    daclist.sort(key=natural_sortkey)
+    i2cscl_list.sort(key=natural_sortkey_i2c) # first sort on name column
+    i2csda_list.sort(key=natural_sortkey_i2c) # first sort on name column
+    i2cscl_list.sort(key=natural_sortkey)
+    i2csda_list.sort(key=natural_sortkey)
+    pwm_list.sort(key=natural_sortkey2) # first sort on name column
+    pwm_list.sort(key=natural_sortkey)
+    uarttx_list.sort(key=natural_sortkey_uart) # first sort on name column
+    uartrx_list.sort(key=natural_sortkey_uart) # first sort on name column
+    uartcts_list.sort(key=natural_sortkey_uart) # first sort on name column
+    uartrts_list.sort(key=natural_sortkey_uart) # first sort on name column
+    uarttx_list.sort(key=natural_sortkey)
+    uartrx_list.sort(key=natural_sortkey)
+    uartcts_list.sort(key=natural_sortkey)
+    uartrts_list.sort(key=natural_sortkey)
+    spimosi_list.sort(key=natural_sortkey)
+    spimiso_list.sort(key=natural_sortkey)
+    spissel_list.sort(key=natural_sortkey)
+    spisclk_list.sort(key=natural_sortkey)
+    cantd_list.sort(key=natural_sortkey)
+    canrd_list.sort(key=natural_sortkey)
+    eth_list.sort(key=natural_sortkey2)
+    quadspidata_list.sort(key=natural_sortkey)
+    quadspisclk_list.sort(key=natural_sortkey)
+    quadspissel_list.sort(key=natural_sortkey)
+    usb_list.sort(key=natural_sortkey2)
+    osc_list.sort(key=natural_sortkey2)
+    sys_list.sort(key=natural_sortkey2)
+
+def clean_all_lists():
+    del io_list[:]
+    del adclist[:]
+    del daclist[:]
+    del i2cscl_list[:]
+    del i2csda_list[:]
+    del pwm_list[:]
+    del uarttx_list[:]
+    del uartrx_list[:]
+    del uartcts_list[:]
+    del uartrts_list[:]
+    del spimosi_list[:]
+    del spimiso_list[:]
+    del spissel_list[:]
+    del spisclk_list[:]
+    del cantd_list[:]
+    del canrd_list[:]
+    del eth_list[:]
+    del quadspidata_list[:]
+    del quadspisclk_list[:]
+    del quadspissel_list[:]
+    del usb_list[:]
+    del osc_list[:]
+    del sys_list[:]
+
+def parse_pins():
+    # print (" * Getting pins per Ips...")
+    pinregex=r'^(P[A-Z][0-9][0-5]?)'
+    itemlist = xml_mcu.getElementsByTagName('Pin')
+    for s in itemlist:
+        m = re.match(pinregex, s.attributes['Name'].value)
+        if m:
+            pin = m.group(0)[:2] + '_' + m.group(0)[2:] # pin formatted P<port>_<number>: PF_O
+            name = s.attributes['Name'].value.strip()   # full name: "PF0 / OSC_IN"
+            if s.attributes['Type'].value == "I/O":
+                store_pin(pin, name)
+            else:
+                continue
+            siglist = s.getElementsByTagName('Signal')
+            for a in siglist:
+                sig = a.attributes['Name'].value.strip()
+                if "ADC" in sig:
+                    store_adc(pin, name, sig)
+                if all(["DAC" in sig, "_OUT" in sig]):
+                    store_dac(pin, name, sig)
+                if "I2C" in sig:
+                    store_i2c(pin, name, sig)
+                if re.match('^TIM', sig) is not None: #ignore HRTIM
+                    store_pwm(pin, name, sig)
+                if re.match('^(LPU|US|U)ART', sig) is not None:
+                    store_uart(pin, name, sig)
+                if "SPI" in sig:
+                    store_spi(pin, name, sig)
+                if "CAN" in sig:
+                    store_can(pin, name, sig)
+                if "ETH" in sig:
+                    store_eth(pin, name, sig)
+                if "QUADSPI" in sig:
+                    store_qspi(pin, name, sig)
+                if "USB" in sig:
+                    store_usb(pin, name, sig)
+                if "RCC_OSC" in sig:
+                    store_osc(pin, name, sig)
+                if "SYS_" in sig:
+                    store_sys(pin, name, sig)
+
+PinData = {}
+PinLabel = {}
+
+def parse_BoardFile(fileName):
+    print(" * Board file: '%s'" % (fileName))
+    board_file = open(board_file_name, "r")
+    # IOC_PIN_pattern = re.compile(r'(P[A-I][\d]*).*\.([\w]*)=(.*)')
+    IOC_PIN_pattern = re.compile(r'(.*)\.([\w]*)=(.*)')
+    for line in board_file.readlines():
+        IOC_PIN = re.match(IOC_PIN_pattern, line)
+        if IOC_PIN:
+            if IOC_PIN.groups()[0] in PinData.keys():
+                PinData[IOC_PIN.groups()[0]][IOC_PIN.groups()[1]] = IOC_PIN.groups()[2]
+            else:
+                PinData[IOC_PIN.groups()[0]] = {}
+                PinData[IOC_PIN.groups()[0]][IOC_PIN.groups()[1]] = IOC_PIN.groups()[2]
+        # IOC_MCU = re.match(r'Mcu\.UserName=(.*)', line)
+        IOC_MCU = re.match(r'Mcu\.Name=(.*)', line)
+        if IOC_MCU:
+            mcu_list.append("%s.xml" % IOC_MCU.groups()[0])
+
+    board_file.close()
+
+    for EachPin in PinData:
+        try:
+            PinLabel[EachPin] = PinData[EachPin]["Signal"]
+        except:
+            pass
+
+        try:
+            PinLabel[EachPin] = PinData[EachPin]["GPIO_Label"]
+
+            if "STLK_RX" in PinLabel[EachPin] or "STLK_TX" in PinLabel[EachPin]:
+                # Patch waiting for CubeMX correction
+                if "RX" in PinData[EachPin]["Signal"]:
+                    PinLabel[EachPin] = "STDIO_UART_RX"
+                else:
+                    PinLabel[EachPin] = "STDIO_UART_TX"
+            elif "USART_RX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_RX"
+            elif "USART_TX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_TX"
+            elif "VCP_RX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_RX"
+            elif "VCP_TX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_TX"
+            elif "ST_LINK_UART1_RX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_RX"
+            elif "ST_LINK_UART1_TX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_TX"
+            elif "USART2_RX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_RX"
+            elif "USART2_TX" in PinLabel[EachPin]:
+                PinLabel[EachPin] = "STDIO_UART_TX"
+            elif "STLINK_RX" in PinLabel[EachPin] or "STLINK_TX" in PinLabel[EachPin]:
+                # Patch waiting for CubeMX correction
+                if "RX" in PinData[EachPin]["Signal"]:
+                    PinLabel[EachPin] = "STDIO_UART_RX"
+                else:
+                    PinLabel[EachPin] = "STDIO_UART_TX"
+        except:
+            pass
+
+# main
+print ("\nScript version %s" % GENPINMAP_VERSION)
+cur_dir = os.getcwd()
+PeripheralPins_c_filename = 'PeripheralPins.c'
+PinNames_h_filename = 'PinNames.h'
+config_filename = 'cube_path.json'
+
+try:
+    config_file = open(config_filename, "r")
+except IOError:
+    print("Please set your configuration in '%s' file" % config_filename)
+    config_file = open(config_filename, "w")
+    if sys.platform.startswith('win32'):
+        print("Platform is Windows")
+        cubemxdir = 'C:\\Program Files (x86)\\STMicroelectronics\\STM32Cube\\STM32CubeMX'
+    elif sys.platform.startswith('linux'):
+        print("Platform is Linux")
+        cubemxdir = os.getenv("HOME")+'/STM32CubeMX'
+    elif sys.platform.startswith('darwin'):
+        print("Platform is Mac OSX")
+        cubemxdir = '/Applications/STMicroelectronics/STM32CubeMX.app/Contents/Resources'
+    else:
+        print("Platform unknown")
+        cubemxdir = '<Set CubeMX install directory>'
+    config_file.write(json.dumps({"CUBEMX_DIRECTORY":cubemxdir}))
+    config_file.close()
+    exit(1)
+
+config = json.load(config_file)
+config_file.close()
+cubemxdir = config["CUBEMX_DIRECTORY"]
+
+parser = argparse.ArgumentParser(
+    description=textwrap.dedent('''\
+Script will generate %s thanks to the xml files description available in
+STM32CubeMX directory defined in '%s':
+\t%s''' % (PeripheralPins_c_filename, config_filename, cubemxdir)),
+    epilog=textwrap.dedent('''\
+Once generated, you have to check and comment pins that can not be used (specific HW, internal ADC channels, remove PWM using us ticker timer, ...)
+'''),
+    formatter_class=RawTextHelpFormatter)
+group = parser.add_mutually_exclusive_group()
+
+group.add_argument("-l", "--list", help="list available mcu xml files description in STM32CubeMX", action="store_true")
+
+group.add_argument("-b", "--boards", help="list available boards description in STM32CubeMX", action="store_true")
+
+group.add_argument("-m", "--mcu", metavar='xml', help=textwrap.dedent('''\
+specify the mcu xml file description in STM32CubeMX to use (use double quotes).
+   Parameter can be a filter like L496 if you want to parse all L496 chips (-m STM32 to parse all).
+'''))
+
+group.add_argument("-t", "--target", metavar='HW', help=textwrap.dedent('''\
+specify the board file description in STM32CubeMX to use (use double quotes).
+   Parameter can be a filter like L496 (only the first file found will be parsed).
+'''))
+
+args = parser.parse_args()
+
+if not(os.path.isdir(cubemxdir)):
+    print ("\n ! ! ! Cube Mx seems not to be installed or not at the requested location")
+    print ("\n ! ! ! please check the value you set for 'CUBEMX_DIRECTORY' in '%s' file" % config_filename)
+    quit()
+
+cubemxdirMCU = os.path.join(cubemxdir, 'db', 'mcu')
+cubemxdirIP = os.path.join(cubemxdir, 'db', 'mcu', 'IP')
+cubemxdirBOARDS = os.path.join(cubemxdir, 'db', 'plugins', 'boardmanager', 'boards')
+
+version_file = os.path.join(cubemxdir, 'db', 'package.xml')
+try:
+    xml_file = parse(version_file)
+    PackDescription_item = xml_file.getElementsByTagName('PackDescription')
+    for item in PackDescription_item:
+        CUBEMX_DB_VERSION = item.attributes['Release'].value
+except:
+    CUBEMX_DB_VERSION = "NOT_FOUND"
+print ("CubeMX DB version %s\n" % CUBEMX_DB_VERSION)
+
+if args.list:
+    FileCount = 0
+    for f in fnmatch.filter(os.listdir(cubemxdirMCU), 'STM32*.xml'):
+        print(f)
+        FileCount += 1
+    print
+    print("%i available xml files description" % FileCount)
+    quit()
+
+if args.boards:
+    NucleoFileCount = 0
+    DiscoFileCount = 0
+    for f in fnmatch.filter(os.listdir(cubemxdirBOARDS), '*AllConfig.ioc'):
+        print(f)
+        if "Nucleo" in f:
+            NucleoFileCount += 1
+        elif "Discovery" in f:
+            DiscoFileCount += 1
+    print
+    print("%2i available Nucleo files description" % NucleoFileCount)
+    print("%2i available Disco  files description" % DiscoFileCount)
+    quit()
+
+if args.mcu:
+    #check input file exists
+    if os.path.isfile(os.path.join(cubemxdirMCU, args.mcu)):
+        mcu_list.append(args.mcu)
+    else:
+        mcu_list = fnmatch.filter(os.listdir(cubemxdirMCU), '*%s*' % args.mcu)
+        if len(mcu_list) == 0:
+            print (" ! ! ! " + args.mcu + " file not found")
+            print (" ! ! ! Check in " + cubemxdirMCU + " the correct name of this file")
+            print (" ! ! ! You may use double quotes for this file if it contains special characters")
+            quit()
+
+if args.target:
+    board_file_name = os.path.join(cubemxdirBOARDS, args.target)
+    if not(os.path.isfile(board_file_name)):
+        board_list = fnmatch.filter(os.listdir(cubemxdirBOARDS), '*%s*AllConfig.ioc' % args.target)
+        if len(board_list) == 0:
+            print (" ! ! ! No file contains " + args.target)
+            print (" ! ! ! Check in " + cubemxdirBOARDS + " the correct filter to apply")
+            quit()
+        elif len(board_list) > 1:
+            print (" ! ! ! Multiple files contains " + args.target)
+            for board_elem in board_list: print (board_elem)
+            print (" ! ! ! Only the first one will be parsed\n")
+        board_file_name = os.path.join(cubemxdirBOARDS,board_list[0])
+        if not (os.path.isfile(board_file_name)):
+            print (" ! ! ! " + args.target + " file not found")
+            print (" ! ! ! Check in " + cubemxdirBOARDS + " the correct name of this file")
+            print (" ! ! ! You may use double quotes for this file if it contains special characters")
+            quit()
+    parse_BoardFile(board_file_name)
+    TargetName = ""
+    if "Nucleo" in board_file_name:
+        TargetName += "NUCLEO_"
+    elif "Discovery" in board_file_name:
+        TargetName += "DISCO_"
+    elif "Evaluation" in board_file_name:
+        TargetName += "EVAL_"
+    m = re.search(r'STM32([\w][\dR]{3}[\w]{0,2})[\w]*_Board', board_file_name)
+    if m:
+        TargetName += "%s" % m.group(1)
+        # specific case
+        if "-P" in args.target:
+            TargetName += "_P"
+        if TargetName == "DISCO_L072":
+            TargetName += "CZ_LRWAN1"
+        if TargetName == "DISCO_L475V":
+            TargetName += "G_IOT01A"
+    else:
+        quit()
+
+for mcu_file in mcu_list:
+    if args.mcu:
+        TargetName = os.path.splitext(mcu_file)[0]
+    out_path = os.path.join(cur_dir, '%s' % TargetName)
+    print(" * Output directory: %s" % (out_path))
+    print(" * Generating %s and %s with '%s'" % (PeripheralPins_c_filename, PinNames_h_filename, mcu_file))
+    input_file_name = os.path.join(cubemxdirMCU, mcu_file)
+    output_cfilename = os.path.join(out_path, PeripheralPins_c_filename)
+    output_hfilename = os.path.join(out_path, PinNames_h_filename)
+    if not(os.path.isdir(out_path)):
+        os.makedirs(out_path)
+
+    if (os.path.isfile(output_cfilename)):
+        # print (" * Requested %s file already exists and will be overwritten" % PeripheralPins_c_filename)
+        os.remove(output_cfilename)
+    out_c_file = open(output_cfilename, 'w')
+    out_h_file = open(output_hfilename, 'w')
+
+    #open input file
+    try:
+        xml_mcu = parse(input_file_name)
+    except:
+        # Patch waiting for CubeMX correction
+        if "STM32F042K6Tx" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32F042K(4-6)Tx.xml")
+            xml_mcu = parse(input_file_name)
+        elif "STM32F429Z" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32F429ZITx.xml")
+            xml_mcu = parse(input_file_name)
+        elif "STM32F746Z" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32F746ZGTx.xml")
+            xml_mcu = parse(input_file_name)
+        elif "STM32F767Z" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32F767ZGTx.xml")
+            xml_mcu = parse(input_file_name)
+
+        elif "STM32L011K4Tx" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32L011K(3-4)Tx.xml")
+            xml_mcu = parse(input_file_name)
+        elif "STM32L432KCUx" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32L432K(B-C)Ux.xml")
+            xml_mcu = parse(input_file_name)
+        elif "STM32F746N" in input_file_name:
+            input_file_name = os.path.join(cubemxdirMCU, "STM32F746NGHx.xml")
+            xml_mcu = parse(input_file_name)
+        else:
+            print ("\n ! ! ! Error in CubeMX file. File " + input_file_name + " doesn't exist")
+            print (" ! ! ! Check in " + cubemxdirMCU)
+            quit()
+    gpiofile = find_gpio_file()
+    if gpiofile == 'ERROR':
+        print("Could not find GPIO file")
+        quit()
+    xml_gpio = parse(os.path.join(cubemxdirIP, 'GPIO-' + gpiofile + '_Modes.xml'))
+    print (" * GPIO file: " + os.path.join(cubemxdirIP, 'GPIO-' + gpiofile + '_Modes.xml'))
+
+    parse_pins()
+    sort_my_lists()
+    print_header()
+    print_all_lists()
+    print_footer()
+
+    nb_pin = (len(io_list))
+    nb_connected_pin = len(PinLabel)
+    print (" * I/O pins found: %i connected: %i\n" % (nb_pin, nb_connected_pin))
+    clean_all_lists()
+
+    out_c_file.close()
+    out_h_file.close()
--- a/targets/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/targets/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function
 
 import os
 import binascii
@@ -29,24 +30,41 @@
 from tools.utils import json_file_to_dict
 
 __all__ = ["target", "TARGETS", "TARGET_MAP", "TARGET_NAMES", "CORE_LABELS",
-           "HookError", "generate_py_target", "Target",
+           "CORE_ARCH", "HookError", "generate_py_target", "Target",
            "CUMULATIVE_ATTRIBUTES", "get_resolution_order"]
 
 CORE_LABELS = {
-   "Cortex-M0" : ["M0", "CORTEX_M", "LIKE_CORTEX_M0", "CORTEX"],
-   "Cortex-M0+": ["M0P", "CORTEX_M", "LIKE_CORTEX_M0", "CORTEX"],
-   "Cortex-M1" : ["M1", "CORTEX_M", "LIKE_CORTEX_M1", "CORTEX"],
-   "Cortex-M3" : ["M3", "CORTEX_M", "LIKE_CORTEX_M3", "CORTEX"],
-   "Cortex-M4" : ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4", "CORTEX"],
-   "Cortex-M4F" : ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4", "CORTEX"],
-   "Cortex-M7" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
-   "Cortex-M7F" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
-   "Cortex-M7FD" : ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
-   "Cortex-A9" : ["A9", "CORTEX_A", "LIKE_CORTEX_A9", "CORTEX"],
+    "Cortex-M0": ["M0", "CORTEX_M", "LIKE_CORTEX_M0", "CORTEX"],
+    "Cortex-M0+": ["M0P", "CORTEX_M", "LIKE_CORTEX_M0", "CORTEX"],
+    "Cortex-M1": ["M1", "CORTEX_M", "LIKE_CORTEX_M1", "CORTEX"],
+    "Cortex-M3": ["M3", "CORTEX_M", "LIKE_CORTEX_M3", "CORTEX"],
+    "Cortex-M4": ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4", "CORTEX"],
+    "Cortex-M4F": ["M4", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M4", "CORTEX"],
+    "Cortex-M7": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
+    "Cortex-M7F": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
+    "Cortex-M7FD": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
+    "Cortex-A9": ["A9", "CORTEX_A", "LIKE_CORTEX_A9", "CORTEX"],
     "Cortex-M23": ["M23", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
-    "Cortex-M23-NS": ["M23", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
+    "Cortex-M23-NS": ["M23", "M23_NS", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
     "Cortex-M33": ["M33", "CORTEX_M", "LIKE_CORTEX_M33", "CORTEX"],
-    "Cortex-M33-NS": ["M33", "CORTEX_M", "LIKE_CORTEX_M33", "CORTEX"]
+    "Cortex-M33-NS": ["M33", "M33_NS", "CORTEX_M", "LIKE_CORTEX_M33", "CORTEX"]
+}
+
+CORE_ARCH = {
+    "Cortex-M0": 6,
+    "Cortex-M0+": 6,
+    "Cortex-M1": 6,
+    "Cortex-M3": 7,
+    "Cortex-M4": 7,
+    "Cortex-M4F": 7,
+    "Cortex-M7": 7,
+    "Cortex-M7F": 7,
+    "Cortex-M7FD": 7,
+    "Cortex-A9": 7,
+    "Cortex-M23": 8,
+    "Cortex-M23-NS": 8,
+    "Cortex-M33": 8,
+    "Cortex-M33-NS": 8,
 }
 
 ################################################################################
@@ -65,7 +83,7 @@
     """
     def wrapper(*args, **kwargs):
         """The wrapped function itself"""
-        if not CACHES.has_key((func.__name__, args)):
+        if (func.__name__, args) not in CACHES:
             CACHES[(func.__name__, args)] = func(*args, **kwargs)
         return CACHES[(func.__name__, args)]
     return wrapper
@@ -73,7 +91,7 @@
 
 # Cumulative attributes can have values appended to them, so they
 # need to be computed differently than regular attributes
-CUMULATIVE_ATTRIBUTES = ['extra_labels', 'macros', 'device_has', 'features']
+CUMULATIVE_ATTRIBUTES = ['extra_labels', 'macros', 'device_has', 'features', 'components']
 
 
 def get_resolution_order(json_data, target_name, order, level=0):
@@ -141,9 +159,10 @@
                                     Target.__targets_json_location_default)
 
         for extra_target in Target.__extra_target_json_files:
-            for k, v in json_file_to_dict(extra_target).iteritems():
+            for k, v in json_file_to_dict(extra_target).items():
                 if k in targets:
-                    print 'WARNING: Custom target "%s" cannot replace existing target.' % k
+                    print('WARNING: Custom target "%s" cannot replace existing '
+                          'target.' % k)
                 else:
                     targets[k] = v
 
@@ -203,8 +222,7 @@
                 def_idx = idx
                 break
         else:
-            raise AttributeError("Attribute '%s' not found in target '%s'"
-                                 % (attrname, self.name))
+            return []
         # Get the starting value of the attribute
         starting_value = (tdata[self.resolution_order[def_idx][0]][attrname]
                           or [])[:]
@@ -212,16 +230,16 @@
         # inheritance level, left to right order to figure out all the
         # other classes that change the definition by adding or removing
         # elements
-        for idx in xrange(self.resolution_order[def_idx][1] - 1, -1, -1):
+        for idx in range(self.resolution_order[def_idx][1] - 1, -1, -1):
             same_level_targets = [tar[0] for tar in self.resolution_order
                                   if tar[1] == idx]
             for tar in same_level_targets:
                 data = tdata[tar]
                 # Do we have anything to add ?
-                if data.has_key(attrname + "_add"):
+                if (attrname + "_add") in data:
                     starting_value.extend(data[attrname + "_add"])
                 # Do we have anything to remove ?
-                if data.has_key(attrname + "_remove"):
+                if (attrname + "_remove") in data:
                     # Macros can be defined either without a value (MACRO)
                     # or with a value (MACRO=10). When removing, we specify
                     # only the name of the macro, without the value. So we
@@ -258,19 +276,14 @@
             starting_value = None
             for tgt in self.resolution_order:
                 data = tdata[tgt[0]]
-                if data.has_key(attrname):
-                    starting_value = data[attrname]
-                    break
+                try:
+                    return data[attrname]
+                except KeyError:
+                    pass
             else: # Attribute not found
                 raise AttributeError(
                     "Attribute '%s' not found in target '%s'"
                     % (attrname, self.name))
-            # 'progen' needs the full path to the template (the path in JSON is
-            # relative to tools/export)
-            if attrname == "progen":
-                return self.__add_paths_to_progen(starting_value)
-            else:
-                return starting_value
 
     def __getattr__(self, attrname):
         """ Return the value of an attribute. This function only computes the
@@ -305,10 +318,6 @@
         if "Target" in names:
             names.remove("Target")
         labels = (names + CORE_LABELS[self.core] + self.extra_labels)
-        # Automatically define UVISOR_UNSUPPORTED if the target doesn't
-        # specifically define UVISOR_SUPPORTED
-        if "UVISOR_SUPPORTED" not in labels:
-            labels.append("UVISOR_UNSUPPORTED")
         return labels
 
     def init_hooks(self, hook, toolchain):
@@ -338,7 +347,7 @@
         # "class_name" must refer to a class in this file, so check if the
         # class exists
         mdata = self.get_module_data()
-        if not mdata.has_key(class_name) or \
+        if class_name not in mdata or \
            not inspect.isclass(mdata[class_name]):
             raise HookError(
                 ("Class '%s' required by '%s' in target '%s'"
@@ -373,7 +382,7 @@
     @staticmethod
     def lpc_patch(t_self, resources, elf, binf):
         """Patch an elf file"""
-        t_self.debug("LPC Patch: %s" % os.path.split(binf)[1])
+        t_self.notify.debug("LPC Patch: %s" % os.path.split(binf)[1])
         patch(binf)
 
 class LPC4088Code(object):
@@ -407,7 +416,7 @@
         # file to 'binf'
         shutil.rmtree(binf, True)
         os.rename(binf + '.temp', binf)
-        t_self.debug("Generated custom binary file (internal flash + SPIFI)")
+        t_self.notify.debug("Generated custom binary file (internal flash + SPIFI)")
         LPCTargetCode.lpc_patch(t_self, resources, elf, binf)
 
 class TEENSY3_1Code(object):
@@ -427,7 +436,7 @@
         loader = os.path.join(TOOLS_BOOTLOADERS, target_name, "bootloader.bin")
         target = binf + ".tmp"
         if not os.path.exists(loader):
-            print "Can't find bootloader binary: " + loader
+            print("Can't find bootloader binary: " + loader)
             return
         outbin = open(target, 'w+b')
         part = open(loader, 'rb')
@@ -458,6 +467,11 @@
         """A hoof for the MTS Dragonfly"""
         MTSCode._combine_bins_helper("MTS_DRAGONFLY_F411RE", binf)
 
+    @staticmethod
+    def combine_bins_mtb_mts_dragonfly(t_self, resources, elf, binf):
+        """A hook for the MTB MTS Dragonfly"""
+        MTSCode._combine_bins_helper("MTB_MTS_DRAGONFLY", binf)
+
 class MCU_NRF51Code(object):
     """NRF51 Hooks"""
     @staticmethod
@@ -469,8 +483,8 @@
             in t_self.target.EXPECTED_SOFTDEVICES_WITH_OFFSETS:
             for hexf in resources.hex_files:
                 if hexf.find(softdevice_and_offset_entry['name']) != -1:
-                    t_self.debug("SoftDevice file found %s."
-                                 % softdevice_and_offset_entry['name'])
+                    t_self.notify.debug("SoftDevice file found %s."
+                                        % softdevice_and_offset_entry['name'])
                     sdf = hexf
 
                 if sdf is not None:
@@ -479,7 +493,7 @@
                 break
 
         if sdf is None:
-            t_self.debug("Hex file not found. Aborting.")
+            t_self.notify.debug("Hex file not found. Aborting.")
             return
 
         # Look for bootloader file that matches this soft device or bootloader
@@ -488,13 +502,13 @@
         if t_self.target.MERGE_BOOTLOADER is True:
             for hexf in resources.hex_files:
                 if hexf.find(t_self.target.OVERRIDE_BOOTLOADER_FILENAME) != -1:
-                    t_self.debug("Bootloader file found %s."
-                                 % t_self.target.OVERRIDE_BOOTLOADER_FILENAME)
+                    t_self.notify.debug("Bootloader file found %s."
+                                        % t_self.target.OVERRIDE_BOOTLOADER_FILENAME)
                     blf = hexf
                     break
                 elif hexf.find(softdevice_and_offset_entry['boot']) != -1:
-                    t_self.debug("Bootloader file found %s."
-                                 % softdevice_and_offset_entry['boot'])
+                    t_self.notify.debug("Bootloader file found %s."
+                                        % softdevice_and_offset_entry['boot'])
                     blf = hexf
                     break
 
@@ -508,14 +522,16 @@
             binh.loadbin(binf, softdevice_and_offset_entry['offset'])
 
         if t_self.target.MERGE_SOFT_DEVICE is True:
-            t_self.debug("Merge SoftDevice file %s"
-                         % softdevice_and_offset_entry['name'])
+            t_self.notify.debug("Merge SoftDevice file %s"
+                                % softdevice_and_offset_entry['name'])
             sdh = IntelHex(sdf)
+            sdh.start_addr = None
             binh.merge(sdh)
 
         if t_self.target.MERGE_BOOTLOADER is True and blf is not None:
-            t_self.debug("Merge BootLoader file %s" % blf)
+            t_self.notify.debug("Merge BootLoader file %s" % blf)
             blh = IntelHex(blf)
+            blh.start_addr = None
             binh.merge(blh)
 
         with open(binf.replace(".bin", ".hex"), "w") as fileout:
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/lint.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,277 @@
+"""A linting utility for targets.json
+
+This linting utility may be called as follows:
+python <path-to>/lint.py targets TARGET [TARGET ...]
+
+all targets will be linted
+"""
+
+# mbed SDK
+# Copyright (c) 2017 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from os.path import join, abspath, dirname
+if __name__ == "__main__":
+    import sys
+    ROOT = abspath(join(dirname(__file__), "..", ".."))
+    sys.path.insert(0, ROOT)
+from copy import copy
+from yaml import dump_all
+import argparse
+
+from tools.targets import Target, set_targets_json_location, TARGET_MAP
+
+def must_have_keys(keys, dict):
+    """Require keys in an MCU/Board
+
+    is a generator for errors
+    """
+    for key in keys:
+        if key not in dict:
+            yield "%s not found, and is required" % key
+
+def may_have_keys(keys, dict):
+    """Disable all other keys in an MCU/Board
+
+    is a generator for errors
+    """
+    for key in dict.keys():
+        if key not in keys:
+            yield "%s found, and is not allowed" % key
+
+def check_extra_labels(dict):
+    """Check that extra_labels does not contain any Target names
+
+    is a generator for errors
+    """
+    for label in (dict.get("extra_labels", []) +
+                  dict.get("extra_labels_add", [])):
+        if label in Target.get_json_target_data():
+            yield "%s is not allowed in extra_labels" % label
+
+def check_release_version(dict):
+    """Verify that release version 5 is combined with support for all toolcahins
+
+    is a generator for errors
+    """
+    if  ("release_versions" in dict and
+         "5" in dict["release_versions"] and
+         "supported_toolchains" in dict):
+        for toolc in ["GCC_ARM", "ARM", "IAR"]:
+            if toolc not in dict["supported_toolchains"]:
+                yield ("%s not found in supported_toolchains, and is "
+                       "required by mbed OS 5" % toolc)
+
+def check_inherits(dict):
+    if  ("inherits" in dict and len(dict["inherits"]) > 1):
+        yield "multiple inheritance is forbidden"
+
+DEVICE_HAS_ALLOWED = ["ANALOGIN", "ANALOGOUT", "CAN", "ETHERNET", "EMAC",
+                      "FLASH", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN",
+                      "LPTICKER", "PORTIN", "PORTINOUT", "PORTOUT",
+                      "PWMOUT", "RTC", "TRNG","SERIAL", "SERIAL_ASYNCH",
+                      "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE",
+                      "STORAGE", "STCLK_OFF_DURING_SLEEP"]
+def check_device_has(dict):
+    for name in dict.get("device_has", []):
+        if name not in DEVICE_HAS_ALLOWED:
+            yield "%s is not allowed in device_has" % name
+
+MCU_REQUIRED_KEYS = ["release_versions", "supported_toolchains",
+                     "default_lib", "public", "inherits", "device_has"]
+MCU_ALLOWED_KEYS = ["device_has_add", "device_has_remove", "core",
+                    "extra_labels", "features", "features_add",
+                    "features_remove", "bootloader_supported", "device_name",
+                    "post_binary_hook", "default_toolchain", "config",
+                    "extra_labels_add", "extra_labels_remove",
+                    "target_overrides"] + MCU_REQUIRED_KEYS
+def check_mcu(mcu_json, strict=False):
+    """Generate a list of problems with an MCU
+
+    :param: mcu_json the MCU's dict to check
+    :param: strict enforce required keys
+    """
+    errors = list(may_have_keys(MCU_ALLOWED_KEYS, mcu_json))
+    if strict:
+        errors.extend(must_have_keys(MCU_REQUIRED_KEYS, mcu_json))
+    errors.extend(check_extra_labels(mcu_json))
+    errors.extend(check_release_version(mcu_json))
+    errors.extend(check_inherits(mcu_json))
+    errors.extend(check_device_has(mcu_json))
+    if 'public' in mcu_json and mcu_json['public']:
+        errors.append("public must be false")
+    return errors
+
+BOARD_REQUIRED_KEYS = ["inherits"]
+BOARD_ALLOWED_KEYS = ["supported_form_factors", "is_disk_virtual",
+                      "detect_code", "extra_labels", "extra_labels_add",
+                      "extra_labels_remove", "public", "config",
+                      "forced_reset_timeout", "target_overrides"] + BOARD_REQUIRED_KEYS
+def check_board(board_json, strict=False):
+    """Generate a list of problems with an board
+
+    :param: board_json the mcus dict to check
+    :param: strict enforce required keys
+    """
+    errors = list(may_have_keys(BOARD_ALLOWED_KEYS, board_json))
+    if strict:
+        errors.extend(must_have_keys(BOARD_REQUIRED_KEYS, board_json))
+    errors.extend(check_extra_labels(board_json))
+    errors.extend(check_inherits(board_json))
+    return errors
+
+def add_if(dict, key, val):
+    """Add a value to a dict if it's non-empty"""
+    if val:
+        dict[key] = val
+
+def _split_boards(resolution_order, tgt):
+    """Split the resolution order between boards and mcus"""
+    mcus = []
+    boards = []
+    iterable = iter(resolution_order)
+    for name in iterable:
+        mcu_json = tgt.json_data[name]
+        if  (len(list(check_mcu(mcu_json, True))) >
+             len(list(check_board(mcu_json, True)))):
+            boards.append(name)
+        else:
+            mcus.append(name)
+            break
+    mcus.extend(iterable)
+    mcus.reverse()
+    boards.reverse()
+    return mcus, boards
+
+
+MCU_FORMAT_STRING = {1: "MCU (%s) ->",
+                     2: "Family (%s) -> MCU (%s) ->",
+                     3: "Family (%s) -> SubFamily (%s) -> MCU (%s) ->"}
+BOARD_FORMAT_STRING = {1: "Board (%s)",
+                       2: "Module (%s) -> Board (%s)"}
+def _generate_hierarchy_string(mcus, boards):
+    global_errors = []
+    if len(mcus) < 1:
+        global_errors.append("No MCUS found in hierarchy")
+        mcus_string = "??? ->"
+    elif len(mcus) > 3:
+        global_errors.append("No name for targets %s" % ", ".join(mcus[3:]))
+        mcus_string = MCU_FORMAT_STRING[3] % tuple(mcus[:3])
+        for name in mcus[3:]:
+            mcus_string += " ??? (%s) ->" % name
+    else:
+        mcus_string = MCU_FORMAT_STRING[len(mcus)] % tuple(mcus)
+
+    if len(boards) < 1:
+        global_errors.append("no boards found in hierarchy")
+        boards_string = "???"
+    elif len(boards) > 2:
+        global_errors.append("no name for targets %s" % ", ".join(boards[2:]))
+        boards_string = BOARD_FORMAT_STRING[2] % tuple(boards[:2])
+        for name in boards[2:]:
+            boards_string += " -> ??? (%s)" % name
+    else:
+        boards_string = BOARD_FORMAT_STRING[len(boards)] % tuple(boards)
+    return mcus_string + " " + boards_string, global_errors
+
+
+def check_hierarchy(tgt):
+    """Atempts to assign labels to the hierarchy"""
+    resolution_order = copy(tgt.resolution_order_names[:-1])
+    mcus, boards = _split_boards(resolution_order, tgt)
+
+    target_errors = {}
+    hierachy_string, hierachy_errors = _generate_hierarchy_string(mcus, boards)
+    to_ret = {"hierarchy": hierachy_string}
+    add_if(to_ret, "hierarchy errors", hierachy_errors)
+
+    for name in mcus[:-1]:
+        add_if(target_errors, name, list(check_mcu(tgt.json_data[name])))
+    if len(mcus) >= 1:
+        add_if(target_errors, mcus[-1],
+               list(check_mcu(tgt.json_data[mcus[-1]], True)))
+    for name in boards:
+        add_if(target_errors, name, list(check_board(tgt.json_data[name])))
+    if len(boards) >= 1:
+        add_if(target_errors, boards[-1],
+               list(check_board(tgt.json_data[boards[-1]], True)))
+    add_if(to_ret, "target errors", target_errors)
+    return to_ret
+
+PARSER = argparse.ArgumentParser(prog="targets/lint.py")
+SUBPARSERS = PARSER.add_subparsers(title="Commands")
+
+def subcommand(name, *args, **kwargs):
+    def __subcommand(command):
+        kwargs['description'] = command.__doc__
+        subparser = SUBPARSERS.add_parser(name, **kwargs)
+        for arg in args:
+            arg = dict(arg)
+            opt = arg['name']
+            del arg['name']
+
+            if isinstance(opt, basestring):
+                subparser.add_argument(opt, **arg)
+            else:
+                subparser.add_argument(*opt, **arg)
+
+        def _thunk(parsed_args):
+            argv = [arg['dest'] if 'dest' in arg else arg['name']
+                    for arg in args]
+            argv = [(arg if isinstance(arg, basestring)
+                     else arg[-1]).strip('-').replace('-', '_')
+                    for arg in argv]
+            argv = {arg: vars(parsed_args)[arg] for arg in argv
+                    if vars(parsed_args)[arg] is not None}
+
+            return command(**argv)
+
+        subparser.set_defaults(command=_thunk)
+        return command
+    return __subcommand
+
+@subcommand("targets",
+            dict(name="mcus", nargs="+", metavar="MCU",
+                 choices=TARGET_MAP.keys(), type=str.upper))
+def targets_cmd(mcus=[]):
+    """Find and print errors about specific targets"""
+    print dump_all([check_hierarchy(TARGET_MAP[m]) for m in mcus],
+                   default_flow_style=False)
+
+@subcommand("all-targets")
+def all_targets_cmd():
+    """Print all errors about all parts"""
+    print dump_all([check_hierarchy(m) for m in TARGET_MAP.values()],
+                   default_flow_style=False)
+
+@subcommand("orphans")
+def orphans_cmd():
+    """Find and print all orphan targets"""
+    orphans = Target.get_json_target_data().keys()
+    for tgt in TARGET_MAP.values():
+        for name in tgt.resolution_order_names:
+            if name in orphans:
+                orphans.remove(name)
+    if orphans:
+        print dump_all([orphans], default_flow_style=False)
+    return len(orphans)
+
+def main():
+    """entry point"""
+    options = PARSER.parse_args()
+    return options.command(options)
+
+if __name__ == "__main__":
+    sys.exit(main())
+
--- a/test.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/test.py	Tue Sep 25 13:43:09 2018 -0500
@@ -16,28 +16,31 @@
 limitations under the License.
 
 
-TEST BUILD & RUN
+TEST BUILD
 """
+from __future__ import print_function, division, absolute_import
 import sys
 import os
-import json
 import fnmatch
 
 ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
 sys.path.insert(0, ROOT)
 
+from tools.config import ConfigException, Config
+from tools.test_configs import get_default_config
 from tools.config import ConfigException
-from tools.test_api import test_path_to_name, find_tests, get_test_config, print_tests, build_tests, test_spec_from_test_builds
+from tools.test_api import find_tests, get_test_config, print_tests, build_tests, test_spec_from_test_builds
 import tools.test_configs as TestConfig
 from tools.options import get_default_options_parser, extract_profile, extract_mcus
 from tools.build_api import build_project, build_library
 from tools.build_api import print_build_memory_usage
 from tools.build_api import merge_build_data
 from tools.targets import TARGET_MAP
-from tools.utils import mkdir, ToolException, NotSupportedException, args_error
+from tools.notifier.term import TerminalNotifier
+from tools.utils import mkdir, ToolException, NotSupportedException, args_error, write_json_to_file
 from tools.test_exporters import ReportExporter, ResultExporterType
-from utils import argparse_filestring_type, argparse_lowercase_type, argparse_many
-from utils import argparse_dir_not_parent
+from tools.utils import argparse_filestring_type, argparse_lowercase_type, argparse_many
+from tools.utils import argparse_dir_not_parent
 from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS, TOOLCHAIN_CLASSES
 from tools.settings import CLI_COLOR_MAP
 
@@ -109,6 +112,19 @@
                             dest="stats_depth",
                             default=2,
                             help="Depth level for static memory report")
+        parser.add_argument("--ignore", dest="ignore", type=argparse_many(str),
+                          default=None, help="Comma separated list of patterns to add to mbedignore (eg. ./main.cpp)")
+        parser.add_argument("--icetea",
+                            action="store_true",
+                            dest="icetea",
+                            default=False,
+                            help="Only icetea tests")
+
+        parser.add_argument("--greentea",
+                            action="store_true",
+                            dest="greentea",
+                            default=False,
+                            help="Only greentea tests")
 
         options = parser.parse_args()
 
@@ -121,8 +137,13 @@
         all_tests = {}
         tests = {}
 
+        # As default both test tools are enabled
+        if not (options.greentea or options.icetea):
+            options.greentea = True
+            options.icetea = True
+
         # Target
-        if options.mcu is None :
+        if options.mcu is None:
             args_error(parser, "argument -m/--mcu is required")
         mcu = extract_mcus(parser, options)[0]
 
@@ -143,15 +164,24 @@
             config = get_test_config(options.test_config, mcu)
             if not config:
                 args_error(parser, "argument --test-config contains invalid path or identifier")
-        elif not options.app_config:
-            config = TestConfig.get_default_config(mcu)
+        elif options.app_config:
+            config = options.app_config
         else:
-            config = options.app_config
+            config = Config.find_app_config(options.source_dir)
+
+        if not config:
+            config = get_default_config(options.source_dir or ['.'], mcu)
+
 
         # Find all tests in the relevant paths
         for path in all_paths:
-            all_tests.update(find_tests(path, mcu, toolchain,
-                                        app_config=config))
+            all_tests.update(find_tests(
+                base_dir=path,
+                target_name=mcu,
+                toolchain_name=toolchain,
+                icetea=options.icetea,
+                greentea=options.greentea,
+                app_config=config))
 
         # Filter tests by name if specified
         if options.names:
@@ -164,20 +194,11 @@
                         if fnmatch.fnmatch(testname, name):
                             tests[testname] = test
                 else:
-                    print "[Warning] Test with name '%s' was not found in the available tests" % (name)
+                    print("[Warning] Test with name '%s' was not found in the "
+                          "available tests" % (name))
         else:
             tests = all_tests
 
-        if options.color:
-            # This import happens late to prevent initializing colorization when we don't need it
-            import colorize
-            if options.verbose:
-                notify = mbedToolchain.print_notify_verbose
-            else:
-                notify = mbedToolchain.print_notify
-            notify = colorize.print_in_color_notifier(CLI_COLOR_MAP, notify)
-        else:
-            notify = None
 
         if options.list:
             # Print available tests in order and exit
@@ -201,60 +222,57 @@
             profile = extract_profile(parser, options, toolchain)
             try:
                 # Build sources
+                notify = TerminalNotifier(options.verbose)
                 build_library(base_source_paths, options.build_dir, mcu,
                               toolchain, jobs=options.jobs,
                               clean=options.clean, report=build_report,
                               properties=build_properties, name="mbed-build",
-                              macros=options.macros, verbose=options.verbose,
+                              macros=options.macros,
                               notify=notify, archive=False,
                               app_config=config,
-                              build_profile=profile)
+                              build_profile=profile,
+                              ignore=options.ignore)
 
                 library_build_success = True
-            except ToolException, e:
+            except ToolException as e:
                 # ToolException output is handled by the build log
                 pass
-            except NotSupportedException, e:
+            except NotSupportedException as e:
                 # NotSupportedException is handled by the build log
                 pass
-            except Exception, e:
+            except Exception as e:
+                if options.verbose:
+                    import traceback
+                    traceback.print_exc()
                 # Some other exception occurred, print the error message
-                print e
+                print(e)
 
             if not library_build_success:
-                print "Failed to build library"
+                print("Failed to build library")
             else:
                 # Build all the tests
-
-                test_build_success, test_build = build_tests(tests, [options.build_dir], options.build_dir, mcu, toolchain,
-                        clean=options.clean,
-                        report=build_report,
-                        properties=build_properties,
-                        macros=options.macros,
-                        verbose=options.verbose,
-                        notify=notify,
-                        jobs=options.jobs,
-                        continue_on_build_fail=options.continue_on_build_fail,
-                        app_config=config,
-                        build_profile=profile,
-                        stats_depth=options.stats_depth)
+                notify = TerminalNotifier(options.verbose)
+                test_build_success, test_build = build_tests(
+                    tests,
+                    [os.path.relpath(options.build_dir)],
+                    options.build_dir,
+                    mcu,
+                    toolchain,
+                    clean=options.clean,
+                    report=build_report,
+                    properties=build_properties,
+                    macros=options.macros,
+                    notify=notify,
+                    jobs=options.jobs,
+                    continue_on_build_fail=options.continue_on_build_fail,
+                    app_config=config,
+                    build_profile=profile,
+                    stats_depth=options.stats_depth,
+                    ignore=options.ignore)
 
                 # If a path to a test spec is provided, write it to a file
                 if options.test_spec:
-                    test_spec_data = test_spec_from_test_builds(test_build)
-
-                    # Create the target dir for the test spec if necessary
-                    # mkdir will not create the dir if it already exists
-                    test_spec_dir = os.path.dirname(options.test_spec)
-                    if test_spec_dir:
-                        mkdir(test_spec_dir)
-
-                    try:
-                        with open(options.test_spec, 'w') as f:
-                            f.write(json.dumps(test_spec_data, indent=2))
-                    except IOError, e:
-                        print "[ERROR] Error writing test spec to file"
-                        print e
+                    write_json_to_file(test_spec_from_test_builds(test_build), options.test_spec)
 
             # If a path to a JUnit build report spec is provided, write it to a file
             if options.build_report_junit:
@@ -264,7 +282,7 @@
             # Print memory map summary on screen
             if build_report:
                 print
-                print print_build_memory_usage(build_report)
+                print(print_build_memory_usage(build_report))
 
             print_report_exporter = ReportExporter(ResultExporterType.PRINT, package="build")
             status = print_report_exporter.report(build_report)
@@ -276,13 +294,14 @@
             else:
                 sys.exit(1)
 
-    except KeyboardInterrupt, e:
-        print "\n[CTRL+c] exit"
-    except ConfigException, e:
+    except KeyboardInterrupt as e:
+        print("\n[CTRL+c] exit")
+    except ConfigException as e:
         # Catching ConfigException here to prevent a traceback
-        print "[ERROR] %s" % str(e)
-    except Exception,e:
+        print("[ERROR] %s" % str(e))
+    except Exception as e:
         import traceback
         traceback.print_exc(file=sys.stdout)
-        print "[ERROR] %s" % str(e)
+        print("[ERROR] %s" % str(e))
         sys.exit(1)
+
--- a/test_api.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/test_api.py	Tue Sep 25 13:43:09 2018 -0500
@@ -16,6 +16,8 @@
 
 Author: Przemyslaw Wirkus <Przemyslaw.wirkus@arm.com>
 """
+from __future__ import print_function
+import six
 
 import os
 import re
@@ -28,14 +30,17 @@
 import datetime
 import threading
 import ctypes
-from types import ListType
+import functools
 from colorama import Fore, Back, Style
-from prettytable import PrettyTable
-from copy import copy
+from prettytable import PrettyTable, HEADER
+from copy import copy, deepcopy
 
 from time import sleep, time
-from Queue import Queue, Empty
-from os.path import join, exists, basename, relpath
+try:
+    from Queue import Queue, Empty
+except ImportError:
+    from queue import Queue, Empty
+from os.path import join, exists, basename, relpath, isdir, isfile
 from threading import Thread, Lock
 from multiprocessing import Pool, cpu_count
 from subprocess import Popen, PIPE
@@ -49,7 +54,8 @@
 from tools.utils import NotSupportedException
 from tools.utils import construct_enum
 from tools.memap import MemapParser
-from tools.targets import TARGET_MAP
+from tools.targets import TARGET_MAP, Target
+from tools.config import Config
 import tools.test_configs as TestConfig
 from tools.test_db import BaseDBAccess
 from tools.build_api import build_project, build_mbed_libs, build_lib
@@ -60,8 +66,8 @@
 from tools.build_api import create_result
 from tools.build_api import add_result_to_report
 from tools.build_api import prepare_toolchain
-from tools.build_api import scan_resources
 from tools.build_api import get_config
+from tools.resources import Resources, MbedIgnoreSet, IGNORE_FILENAME
 from tools.libraries import LIBRARIES, LIBRARY_MAP
 from tools.options import extract_profile
 from tools.toolchains import TOOLCHAIN_PATHS
@@ -71,7 +77,8 @@
 from tools.utils import argparse_uppercase_type
 from tools.utils import argparse_lowercase_type
 from tools.utils import argparse_many
-from tools.utils import get_path_depth
+from tools.notifier.mock import MockNotifier
+from tools.notifier.term import TerminalNotifier
 
 import tools.host_tests.host_tests_plugins as host_tests_plugins
 
@@ -100,7 +107,7 @@
         self.active = False
         try:
             self.proc.terminate()
-        except Exception, _:
+        except Exception:
             pass
 
 
@@ -120,12 +127,14 @@
         # Human readable summary
         if not self.single_test.opts_suppress_summary:
             # prints well-formed summary with results (SQL table like)
-            print self.single_test.generate_test_summary(test_summary, shuffle_seed)
+            print(self.single_test.generate_test_summary(test_summary,
+                                                         shuffle_seed))
         if self.single_test.opts_test_x_toolchain_summary:
             # prints well-formed summary with results (SQL table like)
             # table shows text x toolchain test result matrix
-            print self.single_test.generate_test_summary_by_target(test_summary, shuffle_seed)
-        print "Completed in %.2f sec"% (elapsed_time)
+            print(self.single_test.generate_test_summary_by_target(
+                test_summary, shuffle_seed))
+        print("Completed in %.2f sec"% (elapsed_time))
 
 
 class SingleTestRunner(object):
@@ -360,31 +369,40 @@
             # print '=== %s::%s ===' % (target, toolchain)
             # Let's build our test
             if target not in TARGET_MAP:
-                print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Target platform not found'% (target))
+                print(self.logger.log_line(
+                    self.logger.LogType.NOTIF,
+                    'Skipped tests for %s target. Target platform not found' %
+                    (target)))
                 continue
 
-            clean_mbed_libs_options = True if self.opts_goanna_for_mbed_sdk or clean or self.opts_clean else None
+            clean_mbed_libs_options = (self.opts_goanna_for_mbed_sdk or
+                                       self.opts_clean or clean)
 
             profile = extract_profile(self.opts_parser, self.opts, toolchain)
             stats_depth = self.opts.stats_depth or 2
 
-
             try:
-                build_mbed_libs_result = build_mbed_libs(T,
-                                                         toolchain,
-                                                         clean=clean_mbed_libs_options,
-                                                         verbose=self.opts_verbose,
-                                                         jobs=self.opts_jobs,
-                                                         report=build_report,
-                                                         properties=build_properties,
-                                                         build_profile=profile)
+                build_mbed_libs_result = build_mbed_libs(
+                    T, toolchain,
+                    clean=clean_mbed_libs_options,
+                    jobs=self.opts_jobs,
+                    report=build_report,
+                    properties=build_properties,
+                    build_profile=profile,
+                    notify=TerminalNotifier())
 
                 if not build_mbed_libs_result:
-                    print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Toolchain %s is not yet supported for this target'% (T.name, toolchain))
+                    print(self.logger.log_line(
+                        self.logger.LogType.NOTIF,
+                        'Skipped tests for %s target. Toolchain %s is not '
+                        'supported for this target'% (T.name, toolchain)))
                     continue
 
             except ToolException:
-                print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building MBED libs for %s using %s'% (target, toolchain))
+                print(self.logger.log_line(
+                    self.logger.LogType.ERROR,
+                    'There were errors while building MBED libs for %s using %s'
+                    % (target, toolchain)))
                 continue
 
             build_dir = join(BUILD_DIR, "test", target, toolchain)
@@ -402,16 +420,22 @@
                 if self.db_logger:
                     self.db_logger.reconnect();
                     if self.db_logger.is_connected():
-                        self.db_logger.update_build_id_info(self.db_logger_build_id, _shuffle_seed=self.shuffle_random_func())
+                        self.db_logger.update_build_id_info(
+                            self.db_logger_build_id,
+                            _shuffle_seed=self.shuffle_random_func())
                         self.db_logger.disconnect();
 
             if self.db_logger:
                 self.db_logger.reconnect();
                 if self.db_logger.is_connected():
                     # Update MUTs and Test Specification in database
-                    self.db_logger.update_build_id_info(self.db_logger_build_id, _muts=self.muts, _test_spec=self.test_spec)
+                    self.db_logger.update_build_id_info(
+                        self.db_logger_build_id,
+                        _muts=self.muts, _test_spec=self.test_spec)
                     # Update Extra information in database (some options passed to test suite)
-                    self.db_logger.update_build_id_info(self.db_logger_build_id, _extra=json.dumps(self.dump_options()))
+                    self.db_logger.update_build_id_info(
+                        self.db_logger_build_id,
+                        _extra=json.dumps(self.dump_options()))
                     self.db_logger.disconnect();
 
             valid_test_map_keys = self.get_valid_tests(test_map_keys, target, toolchain, test_ids, self.opts_include_non_automated)
@@ -441,15 +465,17 @@
                     build_lib(lib_id,
                               T,
                               toolchain,
-                              verbose=self.opts_verbose,
                               clean=clean_mbed_libs_options,
                               jobs=self.opts_jobs,
                               report=build_report,
                               properties=build_properties,
-                              build_profile=profile)
+                              build_profile=profile,
+                              notify=TerminalNotifier())
 
                 except ToolException:
-                    print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id))
+                    print(self.logger.log_line(
+                        self.logger.LogType.ERROR,
+                        'There were errors while building library %s' % lib_id))
                     continue
 
 
@@ -483,31 +509,40 @@
 
                 project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None
                 try:
-                    path = build_project(test.source_dir, join(build_dir, test_id), T,
+                    path = build_project(
+                        test.source_dir, join(build_dir, test_id), T,
                         toolchain, test.dependencies, clean=clean_project_options,
-                        verbose=self.opts_verbose, name=project_name, macros=MACROS,
+                        name=project_name, macros=MACROS,
                         inc_dirs=INC_DIRS, jobs=self.opts_jobs, report=build_report,
                         properties=build_properties, project_id=test_id,
                         project_description=test.get_description(),
-                        build_profile=profile, stats_depth=stats_depth)
+                        build_profile=profile, stats_depth=stats_depth,
+                        notify=TerminalNotifier(),
+                    )
 
-                except Exception, e:
+                except Exception as e:
                     project_name_str = project_name if project_name is not None else test_id
 
 
                     test_result = self.TEST_RESULT_FAIL
 
                     if isinstance(e, ToolException):
-                        print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str))
+                        print(self.logger.log_line(
+                            self.logger.LogType.ERROR,
+                            'There were errors while building project %s' %
+                            project_name_str))
                         test_result = self.TEST_RESULT_BUILD_FAILED
                     elif isinstance(e, NotSupportedException):
-                        print self.logger.log_line(self.logger.LogType.INFO, 'The project %s is not supported'% (project_name_str))
+                        print(self.logger.log_line(
+                            self.logger.LogType.INFO,
+                            'Project %s is not supported' % project_name_str))
                         test_result = self.TEST_RESULT_NOT_SUPPORTED
 
 
                     # Append test results to global test summary
                     self.test_summary.append(
-                        (test_result, target, toolchain, test_id, test.get_description(), 0, 0, '-')
+                        (test_result, target, toolchain, test_id,
+                         test.get_description(), 0, 0, '-')
                     )
 
                     # Add detailed test result to test summary structure
@@ -603,7 +638,7 @@
             # in separate threads do not collide.
             # Inside execute_thread_slice() function function handle() will be called to
             # get information about available MUTs (per target).
-            for target, toolchains in self.test_spec['targets'].iteritems():
+            for target, toolchains in self.test_spec['targets'].items():
                 self.test_suite_properties_ext[target] = {}
                 t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids, self.build_report, self.build_properties))
                 t.daemon = True
@@ -614,7 +649,7 @@
                 q.get() # t.join() would block some threads because we should not wait in any order for thread end
         else:
             # Serialized (not parallel) test execution
-            for target, toolchains in self.test_spec['targets'].iteritems():
+            for target, toolchains in self.test_spec['targets'].items():
                 if target not in self.test_suite_properties_ext:
                     self.test_suite_properties_ext[target] = {}
 
@@ -642,23 +677,33 @@
 
             if self.opts_test_only_peripheral and not test.peripherals:
                 if self.opts_verbose_skipped_tests:
-                    print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target))
+                    print(self.logger.log_line(
+                        self.logger.LogType.INFO,
+                        'Common test skipped for target %s' % target))
                 continue
 
-            if self.opts_peripheral_by_names and test.peripherals and not len([i for i in test.peripherals if i in self.opts_peripheral_by_names]):
+            if (self.opts_peripheral_by_names and test.peripherals and
+                not any((i in self.opts_peripheral_by_names)
+                        for i in test.peripherals)):
                 # We will skip tests not forced with -p option
                 if self.opts_verbose_skipped_tests:
-                    print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target))
+                    print(self.logger.log_line(
+                        self.logger.LogType.INFO,
+                        'Common test skipped for target %s' % target))
                 continue
 
             if self.opts_test_only_common and test.peripherals:
                 if self.opts_verbose_skipped_tests:
-                    print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target))
+                    print(self.logger.log_line(
+                        self.logger.LogType.INFO,
+                        'Peripheral test skipped for target %s' % target))
                 continue
 
             if not include_non_automated and not test.automated:
                 if self.opts_verbose_skipped_tests:
-                    print self.logger.log_line(self.logger.LogType.INFO, 'Non automated test skipped for target %s'% (target))
+                    print(self.logger.log_line(
+                        self.logger.LogType.INFO,
+                        'Non automated test skipped for target %s' % target))
                 continue
 
             if test.is_supported(target, toolchain):
@@ -673,9 +718,15 @@
                 elif not self.is_peripherals_available(target, test.peripherals):
                     if self.opts_verbose_skipped_tests:
                         if test.peripherals:
-                            print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral %s test skipped for target %s'% (",".join(test.peripherals), target))
+                            print(self.logger.log_line(
+                                self.logger.LogType.INFO,
+                                'Peripheral %s test skipped for target %s' %
+                                (",".join(test.peripherals), target)))
                         else:
-                            print self.logger.log_line(self.logger.LogType.INFO, 'Test %s skipped for target %s'% (test_id, target))
+                            print(self.logger.log_line(
+                                self.logger.LogType.INFO,
+                                'Test %s skipped for target %s' %
+                                (test_id, target)))
                     continue
 
                 # The test has made it through all the filters, so add it to the valid tests list
@@ -715,7 +766,7 @@
                     result_dict[test[TEST_INDEX]][test[TOOLCHAIN_INDEX]] = test[RESULT_INDEX]
 
             pt_cols = ["Target", "Test ID", "Test Description"] + unique_target_toolchains
-            pt = PrettyTable(pt_cols)
+            pt = PrettyTable(pt_cols, junction_char="|", hrules=HEADER)
             for col in pt_cols:
                 pt.align[col] = "l"
             pt.padding_width = 1 # One space between column edges and contents (default)
@@ -743,7 +794,7 @@
         result = "Test summary:\n"
         # Pretty table package is used to print results
         pt = PrettyTable(["Result", "Target", "Toolchain", "Test ID", "Test Description",
-                          "Elapsed Time (sec)", "Timeout (sec)", "Loops"])
+                          "Elapsed Time (sec)", "Timeout (sec)", "Loops"], junction_char="|", hrules=HEADER)
         pt.align["Result"] = "l" # Left align
         pt.align["Target"] = "l" # Left align
         pt.align["Toolchain"] = "l" # Left align
@@ -773,7 +824,7 @@
         result += "\n"
 
         # Print result count
-        result += "Result: " + ' / '.join(['%s %s' % (value, key) for (key, value) in {k: v for k, v in result_dict.items() if v != 0}.iteritems()])
+        result += "Result: " + ' / '.join(['%s %s' % (value, key) for (key, value) in {k: v for k, v in result_dict.items() if v != 0}.items()])
         shuffle_seed_text = "Shuffle Seed: %.*f\n"% (self.SHUFFLE_SEED_ROUND,
                                                     shuffle_seed if shuffle_seed else self.shuffle_random_seed)
         result += "\n%s"% (shuffle_seed_text if self.opts_shuffle_test_order else '')
@@ -812,7 +863,7 @@
         resutl_msg = ""
         try:
             os.remove(file_path)
-        except Exception, e:
+        except Exception as e:
             resutl_msg = e
             result = False
         return result, resutl_msg
@@ -828,7 +879,7 @@
         duration = data.get("duration", 10)
 
         if mut is None:
-            print "Error: No Mbed available: MUT[%s]" % data['mcu']
+            print("Error: No Mbed available: MUT[%s]" % data['mcu'])
             return None
 
         mcu = mut['mcu']
@@ -864,7 +915,7 @@
                         break
 
                 if not found:
-                    print "Error: mbed not found with MBEDLS: %s" % data['mcu']
+                    print("Error: mbed not found with MBEDLS: %s" % data['mcu'])
                     return None
                 else:
                     mut = muts_list[1]
@@ -895,7 +946,7 @@
                 single_test_result = self.TEST_RESULT_NO_IMAGE
                 elapsed_time = 0
                 single_test_output = self.logger.log_line(self.logger.LogType.ERROR, 'Image file does not exist: %s'% image_path)
-                print single_test_output
+                print(single_test_output)
             else:
                 # Host test execution
                 start_host_exec_time = time()
@@ -930,8 +981,9 @@
                 'copy_method' : _copy_method,
             }
 
-            print self.print_test_result(single_test_result, target_name_unique, toolchain_name,
-                                         test_id, test_description, elapsed_time, single_timeout)
+            print(self.print_test_result(
+                single_test_result, target_name_unique, toolchain_name, test_id,
+                test_description, elapsed_time, single_timeout))
 
             # Update database entries for ongoing test
             if self.db_logger and self.db_logger.is_connected():
@@ -972,7 +1024,7 @@
 
         # Find a suitable MUT:
         mut = None
-        for id, m in self.muts.iteritems():
+        for id, m in self.muts.items():
             if m['mcu'] == data['mcu']:
                 mut = m
                 handle_result = self.handle_mut(mut, data, target_name, toolchain_name, test_loops=test_loops)
@@ -1027,7 +1079,7 @@
             """
             try:
                 c = obs.queue.get(block=True, timeout=0.5)
-            except Empty, _:
+            except Empty:
                 c = None
             return c
 
@@ -1060,7 +1112,6 @@
                     result = property.groups()[0]
             return result
 
-        # print "{%s} port:%s disk:%s"  % (name, port, disk),
         cmd = ["python",
                '%s.py'% name,
                '-d', disk,
@@ -1083,8 +1134,8 @@
             cmd += ["-R", str(reset_tout)]
 
         if verbose:
-            print Fore.MAGENTA + "Executing '" + " ".join(cmd) + "'" + Fore.RESET
-            print "Test::Output::Start"
+            print(Fore.MAGENTA + "Executing '" + " ".join(cmd) + "'" + Fore.RESET)
+            print("Test::Output::Start")
 
         proc = Popen(cmd, stdout=PIPE, cwd=HOST_TESTS)
         obs = ProcessObserver(proc)
@@ -1138,7 +1189,7 @@
             output.append(c)
 
         if verbose:
-            print "Test::Output::Finish"
+            print("Test::Output::Finish")
         # Stop test process
         obs.stop()
 
@@ -1150,7 +1201,7 @@
         """
         if peripherals is not None:
             peripherals = set(peripherals)
-        for id, mut in self.muts.iteritems():
+        for id, mut in self.muts.items():
             # Target MCU name check
             if mut["mcu"] != target_mcu_name:
                 continue
@@ -1205,9 +1256,10 @@
         line_no = 1
         for json_line in data_file:
             if line_no + 5 >= line: # Print last few lines before error
-                print 'Line %d:\t'%line_no + json_line, # Prints line
+                print('Line %d:\t'%line_no + json_line)
             if line_no == line:
-                print ' ' * len('Line %d:'%line_no) + '\t', '-' * (column-1) + '^'
+                print('%s\t%s^' (' ' * len('Line %d:' % line_no),
+                                 '-' * (column - 1)))
                 break
             line_no += 1
 
@@ -1244,18 +1296,19 @@
                 result = json.load(data_file)
             except ValueError as json_error_msg:
                 result = None
-                print 'JSON file %s parsing failed. Reason: %s' % (json_spec_filename, json_error_msg)
+                print('JSON file %s parsing failed. Reason: %s' %
+                      (json_spec_filename, json_error_msg))
                 # We can print where error occurred inside JSON file if we can parse exception msg
                 json_format_defect_pos = json_format_error_defect_pos(str(json_error_msg))
                 if json_format_defect_pos is not None:
                     line = json_format_defect_pos[0]
                     column = json_format_defect_pos[1]
-                    print
+                    print()
                     show_json_file_format_error(json_spec_filename, line, column)
 
     except IOError as fileopen_error_msg:
-        print 'JSON file %s not opened. Reason: %s'% (json_spec_filename, fileopen_error_msg)
-        print
+        print('JSON file %s not opened. Reason: %s\n'%
+              (json_spec_filename, fileopen_error_msg))
     if verbose and result:
         pp = pprint.PrettyPrinter(indent=4)
         pp.pprint(result)
@@ -1275,7 +1328,7 @@
 
     # Prepare pretty table object to display all MUTs
     pt_cols = ["index"] + muts_info_cols
-    pt = PrettyTable(pt_cols)
+    pt = PrettyTable(pt_cols, junction_char="|", hrules=HEADER)
     for col in pt_cols:
         pt.align[col] = "l"
 
@@ -1290,7 +1343,7 @@
         if add_row:
             for col in muts_info_cols:
                 cell_val = mut_info[col] if col in mut_info else None
-                if type(cell_val) == ListType:
+                if isinstance(cell_val, list):
                     cell_val = join_delim.join(cell_val)
                 row.append(cell_val)
             pt.add_row(row)
@@ -1313,7 +1366,7 @@
 
     # Prepare pretty table object to display test specification
     pt_cols = ["mcu"] + sorted(toolchains_info_cols)
-    pt = PrettyTable(pt_cols)
+    pt = PrettyTable(pt_cols, junction_char="|", hrules=HEADER)
     for col in pt_cols:
         pt.align[col] = "l"
 
@@ -1402,7 +1455,7 @@
                        'duration'] if cols is None else cols
 
     # All tests status table print
-    pt = PrettyTable(test_properties)
+    pt = PrettyTable(test_properties, junction_char="|", hrules=HEADER)
     for col in test_properties:
         pt.align[col] = "l"
     pt.align['duration'] = "r"
@@ -1423,7 +1476,7 @@
 
         for col in test_properties:
             col_value = test[col]
-            if type(test[col]) == ListType:
+            if isinstance(test[col], list):
                 col_value = join_delim.join(test[col])
             elif test[col] == None:
                 col_value = "-"
@@ -1442,7 +1495,7 @@
     if result_summary and not platform_filter:
         # Automation result summary
         test_id_cols = ['automated', 'all', 'percent [%]', 'progress']
-        pt = PrettyTable(test_id_cols)
+        pt = PrettyTable(test_id_cols, junction_char="|", hrules=HEADER)
         pt.align['automated'] = "r"
         pt.align['all'] = "r"
         pt.align['percent [%]'] = "r"
@@ -1456,7 +1509,7 @@
 
         # Test automation coverage table print
         test_id_cols = ['id', 'automated', 'all', 'percent [%]', 'progress']
-        pt = PrettyTable(test_id_cols)
+        pt = PrettyTable(test_id_cols, junction_char="|", hrules=HEADER)
         pt.align['id'] = "l"
         pt.align['automated'] = "r"
         pt.align['all'] = "r"
@@ -1502,13 +1555,14 @@
     # Human readable summary
     if not single_test.opts_suppress_summary:
         # prints well-formed summary with results (SQL table like)
-        print single_test.generate_test_summary(test_summary, shuffle_seed)
+        print(single_test.generate_test_summary(test_summary, shuffle_seed))
     if single_test.opts_test_x_toolchain_summary:
         # prints well-formed summary with results (SQL table like)
         # table shows text x toolchain test result matrix
-        print single_test.generate_test_summary_by_target(test_summary, shuffle_seed)
+        print(single_test.generate_test_summary_by_target(test_summary,
+                                                          shuffle_seed))
 
-    print "Completed in %.2f sec"% (elapsed_time)
+    print("Completed in %.2f sec" % elapsed_time)
     print
     # Write summary of the builds
 
@@ -1628,19 +1682,19 @@
         # Let's try to connect
         db_ = factory_db_logger(db_url)
         if db_ is not None:
-            print "Connecting to database '%s'..."% db_url,
+            print("Connecting to database '%s'..." % db_url)
             db_.connect(host, username, password, db_name)
             if db_.is_connected():
-                print "ok"
-                print "Detecting database..."
-                print db_.detect_database(verbose=True)
-                print "Disconnecting...",
+                print("ok")
+                print("Detecting database...")
+                print(db_.detect_database(verbose=True))
+                print("Disconnecting...")
                 db_.disconnect()
-                print "done"
+                print("done")
         else:
-            print "Database type '%s' unknown"% db_type
+            print("Database type '%s' unknown" % db_type)
     else:
-        print "Parse error: '%s' - DB Url error"% (db_url)
+        print("Parse error: '%s' - DB Url error" % db_url)
 
 
 def get_module_avail(module_name):
@@ -2003,7 +2057,7 @@
     """Finds the path to a test configuration file
     config_name: path to a custom configuration file OR mbed OS interface "ethernet, wifi_odin, etc"
     target_name: name of target to determing if mbed OS interface given is valid
-    returns path to config, boolean of whether it is a module or mbed OS interface
+    returns path to config, will return None if no valid config is found
     """
     # If they passed in a full path
     if exists(config_name):
@@ -2012,64 +2066,106 @@
     # Otherwise find the path to configuration file based on mbed OS interface
     return TestConfig.get_config_path(config_name, target_name)
 
-def find_tests(base_dir, target_name, toolchain_name, app_config=None):
+
+def find_tests(base_dir, target_name, toolchain_name, icetea, greentea, app_config=None):
     """ Finds all tests in a directory recursively
-    base_dir: path to the directory to scan for tests (ex. 'path/to/project')
-    target_name: name of the target to use for scanning (ex. 'K64F')
-    toolchain_name: name of the toolchain to use for scanning (ex. 'GCC_ARM')
-    options: Compile options to pass to the toolchain (ex. ['debug-info'])
-    app_config - location of a chosen mbed_app.json file
+    :param base_dir: path to the directory to scan for tests (ex. 'path/to/project')
+    :param target_name: name of the target to use for scanning (ex. 'K64F')
+    :param toolchain_name: name of the toolchain to use for scanning (ex. 'GCC_ARM')
+    :param icetea: icetea enabled
+    :param greentea: greentea enabled
+    :param app_config - location of a chosen mbed_app.json file
+
+    returns a dictionary where keys are the test name, and the values are
+    lists of paths needed to biuld the test.
     """
 
+    # Temporary structure: tests referenced by (name, base, group, case) tuple
     tests = {}
+    # List of common folders: (predicate function, path) tuple
+    commons = []
 
-    # Prepare the toolchain
-    toolchain = prepare_toolchain([base_dir], None, target_name, toolchain_name,
-                                  silent=True, app_config=app_config)
+    config = Config(target_name, base_dir, app_config)
 
     # Scan the directory for paths to probe for 'TESTS' folders
-    base_resources = scan_resources([base_dir], toolchain)
+    base_resources = Resources(MockNotifier(), collect_ignores=True)
+    base_resources.scan_with_config(base_dir, config)
 
-    dirs = base_resources.inc_dirs
-    for directory in dirs:
-        subdirs = os.listdir(directory)
+    if greentea:
+        dirs = [d for d in base_resources.ignored_dirs if basename(d) == 'TESTS']
+        ignoreset = MbedIgnoreSet()
 
-        # If the directory contains a subdirectory called 'TESTS', scan it for test cases
-        if 'TESTS' in subdirs:
-            walk_base_dir = join(directory, 'TESTS')
-            test_resources = toolchain.scan_resources(walk_base_dir, base_path=base_dir)
-
-            # Loop through all subdirectories
-            for d in test_resources.inc_dirs:
+        for directory in dirs:
+            ignorefile = join(directory, IGNORE_FILENAME)
+            if isfile(ignorefile):
+                ignoreset.add_mbedignore(directory, ignorefile)
+            for test_group_directory in os.listdir(directory):
+                grp_dir = join(directory, test_group_directory)
+                if not isdir(grp_dir) or ignoreset.is_ignored(grp_dir):
+                    continue
+                grpignorefile = join(grp_dir, IGNORE_FILENAME)
+                if isfile(grpignorefile):
+                    ignoreset.add_mbedignore(grp_dir, grpignorefile)
+                for test_case_directory in os.listdir(grp_dir):
+                    d = join(directory, test_group_directory, test_case_directory)
+                    if not isdir(d) or ignoreset.is_ignored(d):
+                        continue
+                    special_dirs = ['host_tests', 'COMMON']
+                    if test_group_directory not in special_dirs and test_case_directory not in special_dirs:
+                        test_name = test_path_to_name(d, base_dir)
+                        tests[(test_name, directory, test_group_directory, test_case_directory)] = [d]
+                    if test_case_directory == 'COMMON':
+                        def predicate(base_pred, group_pred, name_base_group_case):
+                            (name, base, group, case) = name_base_group_case
+                            return base == base_pred and group == group_pred
 
-                # If the test case folder is not called 'host_tests' and it is
-                # located two folders down from the main 'TESTS' folder (ex. TESTS/testgroup/testcase)
-                # then add it to the tests
-                path_depth = get_path_depth(relpath(d, walk_base_dir))
-                if path_depth == 2:
-                    test_group_directory_path, test_case_directory = os.path.split(d)
-                    test_group_directory = os.path.basename(test_group_directory_path)
+                        commons.append((functools.partial(predicate, directory, test_group_directory), d))
+                if test_group_directory == 'COMMON':
+                    def predicate(base_pred, name_base_group_case):
+                        (name, base, group, case) = name_base_group_case
+                        return base == base_pred
+
+                    commons.append((functools.partial(predicate, directory), grp_dir))
 
-                    # Check to make sure discoverd folder is not in a host test directory
-                    if test_case_directory != 'host_tests' and test_group_directory != 'host_tests':
-                        test_name = test_path_to_name(d, base_dir)
-                        tests[test_name] = d
+    if icetea:
+        dirs = [d for d in base_resources.ignored_dirs if basename(d) == 'TEST_APPS']
+        for directory in dirs:
+            if not isdir(directory):
+                continue
+            for subdir in os.listdir(directory):
+                d = join(directory, subdir)
+                if not isdir(d):
+                    continue
+                if 'device' == subdir:
+                    for test_dir in os.listdir(d):
+                        test_dir_path = join(d, test_dir)
+                        test_name = test_path_to_name(test_dir_path, base_dir)
+                        tests[(test_name, directory, subdir, test_dir)] = [test_dir_path]
 
-    return tests
+    # Apply common directories
+    for pred, path in commons:
+        for test_identity, test_paths in six.iteritems(tests):
+            if pred(test_identity):
+                test_paths.append(path)
+
+    # Drop identity besides name
+    return {name: paths for (name, _, _, _), paths in six.iteritems(tests)}
+
 
 def print_tests(tests, format="list", sort=True):
     """Given a dictionary of tests (as returned from "find_tests"), print them
     in the specified format"""
     if format == "list":
         for test_name in sorted(tests.keys()):
-            test_path = tests[test_name]
-            print "Test Case:"
-            print "    Name: %s" % test_name
-            print "    Path: %s" % test_path
+            test_path = tests[test_name][0]
+            print("Test Case:")
+            print("    Name: %s" % test_name)
+            print("    Path: %s" % test_path)
     elif format == "json":
-        print json.dumps(tests, indent=2)
+        print(json.dumps({test_name: test_path[0] for test_name, test_paths
+                          in tests}, indent=2))
     else:
-        print "Unknown format '%s'" % format
+        print("Unknown format '%s'" % format)
         sys.exit(1)
 
 def norm_relative_path(path, start):
@@ -2104,22 +2200,22 @@
     }
 
     # Use parent TOOLCHAIN_PATHS variable
-    for key, value in kwargs['toolchain_paths'].iteritems():
+    for key, value in kwargs['toolchain_paths'].items():
         TOOLCHAIN_PATHS[key] = value
 
     del kwargs['toolchain_paths']
 
     try:
-        bin_file = build_project(*args, **kwargs)
+        bin_file, _ = build_project(*args, **kwargs)
         ret['result'] = True
         ret['bin_file'] = bin_file
         ret['kwargs'] = kwargs
 
-    except NotSupportedException, e:
+    except NotSupportedException as e:
         ret['reason'] = e
-    except ToolException, e:
+    except ToolException as e:
         ret['reason'] = e
-    except KeyboardInterrupt, e:
+    except KeyboardInterrupt as e:
         ret['reason'] = e
     except:
         # Print unhandled exceptions here
@@ -2130,10 +2226,10 @@
 
 
 def build_tests(tests, base_source_paths, build_path, target, toolchain_name,
-                clean=False, notify=None, verbose=False, jobs=1, macros=None,
+                clean=False, notify=None, jobs=1, macros=None,
                 silent=False, report=None, properties=None,
                 continue_on_build_fail=False, app_config=None,
-                build_profile=None, stats_depth=None):
+                build_profile=None, stats_depth=None, ignore=None):
     """Given the data structure from 'find_tests' and the typical build parameters,
     build all the tests
 
@@ -2143,8 +2239,12 @@
     execution_directory = "."
     base_path = norm_relative_path(build_path, execution_directory)
 
-    target_name = target if isinstance(target, str) else target.name
-    cfg, _, _ = get_config(base_source_paths, target_name, toolchain_name)
+    if isinstance(target, Target):
+        target_name = target.name
+    else:
+        target_name = target
+        target = TARGET_MAP[target_name]
+    cfg, _, _ = get_config(base_source_paths, target, app_config=app_config)
 
     baud_rate = 9600
     if 'platform.stdio-baud-rate' in cfg:
@@ -2156,7 +2256,8 @@
         "base_path": base_path,
         "baud_rate": baud_rate,
         "binary_type": "bootable",
-        "tests": {}
+        "tests": {},
+        "test_apps": {}
     }
 
     result = True
@@ -2164,13 +2265,16 @@
     jobs_count = int(jobs if jobs else cpu_count())
     p = Pool(processes=jobs_count)
     results = []
-    for test_name, test_path in tests.iteritems():
-        test_build_path = os.path.join(build_path, test_path)
-        src_path = base_source_paths + [test_path]
+    for test_name, test_paths in tests.items():
+        if not isinstance(test_paths, list):
+            test_paths = [test_paths]
+
+        test_build_path = os.path.join(build_path, test_paths[0])
+        src_paths = base_source_paths + test_paths
         bin_file = None
-        test_case_folder_name = os.path.basename(test_path)
+        test_case_folder_name = os.path.basename(test_paths[0])
 
-        args = (src_path, test_build_path, target, toolchain_name)
+        args = (src_paths, test_build_path, deepcopy(target), toolchain_name)
         kwargs = {
             'jobs': 1,
             'clean': clean,
@@ -2179,12 +2283,11 @@
             'project_id': test_name,
             'report': report,
             'properties': properties,
-            'verbose': verbose,
             'app_config': app_config,
             'build_profile': build_profile,
-            'silent': True,
             'toolchain_paths': TOOLCHAIN_PATHS,
-            'stats_depth': stats_depth
+            'stats_depth': stats_depth,
+            'notify': MockNotifier()
         }
 
         results.append(p.apply_async(build_test_worker, args, kwargs))
@@ -2207,9 +2310,15 @@
                         worker_result = r.get()
                         results.remove(r)
 
+                        # Push all deferred notifications out to the actual notifier
+                        new_notify = deepcopy(notify)
+                        for message in worker_result['kwargs']['notify'].messages:
+                            new_notify.notify(message)
+
                         # Take report from the kwargs and merge it into existing report
                         if report:
                             report_entry = worker_result['kwargs']['report'][target_name][toolchain_name]
+                            report_entry[worker_result['kwargs']['project_id'].upper()][0][0]['output'] = new_notify.get_output()
                             for test_key in report_entry.keys():
                                 report[target_name][toolchain_name][test_key] = report_entry[test_key]
 
@@ -2220,13 +2329,15 @@
                             result = False
                             break
 
+
                         # Adding binary path to test build result
                         if ('result' in worker_result and
                             worker_result['result'] and
                             'bin_file' in worker_result):
                             bin_file = norm_relative_path(worker_result['bin_file'], execution_directory)
 
-                            test_build['tests'][worker_result['kwargs']['project_id']] = {
+                            test_key = 'test_apps' if 'test_apps-' in worker_result['kwargs']['project_id'] else 'tests'
+                            test_build[test_key][worker_result['kwargs']['project_id']] = {
                                 "binaries": [
                                     {
                                         "path": bin_file
@@ -2235,9 +2346,7 @@
                             }
 
                             test_key = worker_result['kwargs']['project_id'].upper()
-                            if report:
-                                print report[target_name][toolchain_name][test_key][0][0]['output'].rstrip()
-                            print 'Image: %s\n' % bin_file
+                            print('Image: %s\n' % bin_file)
 
                     except:
                         if p._taskqueue.queue:
@@ -2271,4 +2380,4 @@
 def test_spec_from_test_builds(test_builds):
     return {
         "builds": test_builds
-    }
+    }
\ No newline at end of file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/6lowpanInterface_host.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "MESH",
+            "nsapi.default-stack": "NANOSTACK",
+            "nsapi.default-mesh-type": "LOWPAN",
+            "nanostack.configuration": "lowpan_host",
+            "mbed-mesh-api.heap-size": 14000,
+            "mbed-mesh-api.6lowpan-nd-device-type": "NET_6LOWPAN_HOST",
+            "mbed-mesh-api.6lowpan-nd-panid-filter": "0xffff",
+            "mbed-mesh-api.6lowpan-nd-channel-page": 0,
+            "mbed-mesh-api.6lowpan-nd-channel": 12,
+            "mbed-mesh-api.6lowpan-nd-channel-mask": "(1<<12)",
+            "mbed-trace.enable": false
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/6lowpanInterface_router.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "MESH",
+            "nsapi.default-stack": "NANOSTACK",
+            "nsapi.default-mesh-type": "LOWPAN",
+            "nanostack.configuration": "lowpan_router",
+            "mbed-mesh-api.heap-size": 14000,
+            "mbed-mesh-api.6lowpan-nd-device-type": "NET_6LOWPAN_ROUTER",
+            "mbed-mesh-api.6lowpan-nd-panid-filter": "0xffff",
+            "mbed-mesh-api.6lowpan-nd-channel-page": 0,
+            "mbed-mesh-api.6lowpan-nd-channel": 12,
+            "mbed-mesh-api.6lowpan-nd-channel-mask": "(1<<12)",
+            "mbed-trace.enable": false
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/ESP8266Interface.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,21 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "WIFI",
+            "nsapi.default-wifi-ssid": "\"WIFI_SSID\"",
+            "nsapi.default-wifi-password": "\"WIFI_PASSWORD\"",
+            "nsapi.default-wifi-security": "WIFI_SECURITY",
+            "esp8266.provide-default": true
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/EthernetInterface.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,17 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "ETHERNET"
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/HeapBlockDevice.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,9 @@
+{
+    "config": {
+        "sim-blockdevice": {
+            "help": "Simulated block device, requires sufficient heap",
+            "macro_name": "MBED_TEST_SIM_BLOCKDEVICE",
+            "value": "HeapBlockDevice"
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/HeapBlockDeviceAndEthernetInterface.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,22 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "sim-blockdevice": {
+            "help": "Simulated block device, requires sufficient heap",
+            "macro_name": "MBED_TEST_SIM_BLOCKDEVICE",
+            "value": "HeapBlockDevice"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "ETHERNET"
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/HeapBlockDeviceAndWifiInterface.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,25 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "sim-blockdevice": {
+            "help": "Simulated block device, requires sufficient heap",
+            "macro_name": "MBED_TEST_SIM_BLOCKDEVICE",
+            "value": "HeapBlockDevice"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "WIFI",
+            "nsapi.default-wifi-ssid": "\"WIFI_SSID\"",
+            "nsapi.default-wifi-password": "\"WIFI_PASSWORD\"",
+            "nsapi.default-wifi-security": "WIFI_SECURITY"
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/ISM43362Interface.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,58 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "wifi-secure-ssid": {
+            "help": "WiFi SSID for WPA2 secured network",
+            "value": "\"SSID-SECURE\""
+        },
+        "wifi-unsecure-ssid": {
+            "help": "WiFi SSID for unsecure network",
+            "value": "\"SSID-UNSECURE\""
+        },
+        "wifi-password": {
+            "help": "WiFi Password",
+            "value": "\"PASSWORD\""
+        },
+        "wifi-secure-protocol": {
+            "help": "WiFi security protocol, valid values are WEP, WPA, WPA2, WPA/WPA2",
+            "value": "\"WPA2\""
+        },
+        "wifi-ch-secure": {
+            "help": "Channel number of secure SSID",
+            "value": 1
+        },
+        "wifi-ch-unsecure": {
+            "help": "Channel number of unsecure SSID",
+            "value": 2
+        },
+        "ap-mac-secure": {
+            "help": "BSSID of secure AP in form of AA:BB:CC:DD:EE:FF",
+            "value": "\"AA:AA:AA:AA:AA:AA\""
+        },
+        "ap-mac-unsecure": {
+            "help": "BSSID of unsecure AP in form of \"AA:BB:CC:DD:EE:FF\"",
+            "value": "\"BB:BB:BB:BB:BB:BB\""
+        },
+        "max-scan-size": {
+            "help": "How many networks may appear in Wifi scan result",
+            "value": 10
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "platform.stdio-convert-newlines": true,
+            "target.network-default-interface-type": "WIFI",
+            "nsapi.default-wifi-ssid": "\"WIFI_SSID\"",
+            "nsapi.default-wifi-password": "\"WIFI_PASSWORD\"",
+            "nsapi.default-wifi-security": "WIFI_SECURITY",
+            "ism43362.provide-default": true
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/SpwfSAInterface.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,29 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "WIFI-TX" : {
+            "help" : "Wifi TX pin",
+            "value" : "D8"
+        },
+        "WIFI-RX" : {
+            "help" : "Wifi RX pin",
+            "value" : "D2"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "WIFI",
+            "nsapi.default-wifi-ssid": "\"WIFI_SSID\"",
+            "nsapi.default-wifi-password": "\"WIFI_PASSWORD\"",
+            "nsapi.default-wifi-security": "WIFI_SECURITY",
+            "idw0xx1.provide-default": true
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/ThreadInterface_end_device.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,25 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "MESH",
+            "nsapi.default-stack": "NANOSTACK",
+            "nsapi.default-mesh-type": "THREAD",
+            "nanostack.configuration": "thread_end_device",
+            "mbed-mesh-api.thread-device-type": "MESH_DEVICE_TYPE_THREAD_MINIMAL_END_DEVICE",
+            "mbed-mesh-api.thread-config-panid": "0x0700",
+            "mbed-mesh-api.thread-master-key": "{0x10, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}",
+            "mbed-mesh-api.thread-config-channel": 22,
+            "mbed-trace.enable": false
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/ThreadInterface_router.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,25 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"echo.mbedcloudtesting.com\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": "MESH",
+            "nsapi.default-stack": "NANOSTACK",
+            "nsapi.default-mesh-type": "THREAD",
+            "nanostack.configuration": "thread_router",
+            "mbed-mesh-api.thread-device-type": "MESH_DEVICE_TYPE_THREAD_ROUTER",
+            "mbed-mesh-api.thread-config-panid": "0x0700",
+            "mbed-mesh-api.thread-master-key": "{0x10, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}",
+            "mbed-mesh-api.thread-config-channel": 22,
+            "mbed-trace.enable": false
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,43 @@
+from os.path import dirname, abspath, join, exists
+
+from tools.utils import json_file_to_dict
+from tools.targets import TARGET_MAP
+from tools.config import Config
+
+CONFIG_DIR = dirname(abspath(__file__))
+CONFIG_MAP = json_file_to_dict(join(CONFIG_DIR, "config_paths.json"))
+TARGET_CONFIGS = json_file_to_dict(join(CONFIG_DIR, "target_configs.json"))
+
+def get_valid_configs(target_name):
+    if target_name in TARGET_CONFIGS:
+        target_config = TARGET_CONFIGS[target_name]
+    elif (target_name in TARGET_MAP and 'EMAC' in TARGET_MAP[target_name].device_has):
+        target_config = { "default_test_configuration": "ETHERNET", "test_configurations": ["ETHERNET"] }
+    else:
+        return {}
+
+    config_dict = {}
+    for attr in CONFIG_MAP:
+        if attr in target_config['test_configurations']:
+            config_dict[attr] = CONFIG_MAP[attr]
+    return config_dict
+
+def get_config_path(conf_name, target_name):
+    configs = get_valid_configs(target_name)
+    if configs and conf_name.upper() in configs:
+        return join(CONFIG_DIR, configs[conf_name.upper()])
+    else:
+        return None
+
+def get_default_config(source_dir, target_name):
+    if target_name in TARGET_CONFIGS:
+        config_name = TARGET_CONFIGS[target_name]['default_test_configuration']
+        if config_name == "NONE":
+            return None
+        return join(CONFIG_DIR, CONFIG_MAP[config_name])
+    elif Config.find_app_config(source_dir):
+        return None
+    elif (target_name in TARGET_MAP and 'EMAC' in TARGET_MAP[target_name].device_has):
+        return join(CONFIG_DIR, CONFIG_MAP["ETHERNET"])
+    else:
+        return None
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/config_paths.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,17 @@
+{
+    "ETHERNET" : "EthernetInterface.json",
+    "HEAPBLOCKDEVICE": "HeapBlockDevice.json",
+    "HEAPBLOCKDEVICE_AND_ETHERNET": "HeapBlockDeviceAndEthernetInterface.json",
+    "HEAPBLOCKDEVICE_AND_WIFI": "HeapBlockDeviceAndWifiInterface.json",
+    "ODIN_WIFI" : "OdinInterface.json",
+    "ODIN_ETHERNET" : "Odin_EthernetInterface.json",
+    "REALTEK_WIFI" : "RealtekInterface.json",
+    "ESP8266_WIFI" : "ESP8266Interface.json",
+    "ISM43362_WIFI" : "ISM43362Interface.json",
+    "IDW0XX1_WIFI" : "SpwfSAInterface.json",
+    "6LOWPAN_HOST" : "6lowpanInterface_host.json",
+    "6LOWPAN_ROUTER" : "6lowpanInterface_router.json",
+    "THREAD_END_DEVICE" : "ThreadInterface_end_device.json",
+    "THREAD_ROUTER" : "ThreadInterface_router.json",
+    "NO_NETWORK": "no_network.json"
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/no_network.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,17 @@
+{
+    "config": {
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : null
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : null
+        }
+    },
+    "target_overrides": {
+        "*": {
+            "target.network-default-interface-type": null
+        }
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test_configs/target_configs.json	Tue Sep 25 13:43:09 2018 -0500
@@ -0,0 +1,50 @@
+{
+    "UBLOX_EVK_ODIN_W2": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI", "HEAPBLOCKDEVICE_AND_ETHERNET"]
+    },
+    "REALTEK_RTL8195AM": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"]
+    },
+    "K64F": {
+        "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_ETHERNET", "MAC_TESTER", "ESP8266_WIFI", "ETHERNET"]
+    },
+    "NUCLEO_F429ZI": {
+        "default_test_configuration": "HEAPBLOCKDEVICE_AND_ETHERNET",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_ETHERNET", "MAC_TESTER"]
+    },
+    "DISCO_L475VG_IOT01A": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["ISM43362_WIFI"]
+    },
+    "DISCO_F413ZH": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["ISM43362_WIFI"]
+    },
+    "MTB_UBLOX_ODIN_W2": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"]
+    },
+    "MTB_ADV_WISE_1530": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"]
+    },
+    "MTB_USI_WM_BN_BM_22": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"]
+    },
+    "MTB_MXCHIP_EMW3166": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["HEAPBLOCKDEVICE_AND_WIFI"]
+    },
+    "NUCLEO_F401RE": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["IDW0XX1_WIFI"]
+    },
+    "KW24D": {
+        "default_test_configuration": "NO_NETWORK",
+        "test_configurations": ["6LOWPAN_HOST", "6LOWPAN_ROUTER", "THREAD_END_DEVICE", "THREAD_ROUTER"]
+    }
+}
--- a/test_exporters.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/test_exporters.py	Tue Sep 25 13:43:09 2018 -0500
@@ -304,11 +304,13 @@
 
     def exporter_print_helper(self, array, print_log=False):
         for item in array:
-            print "  * %s::%s::%s" % (item["target_name"], item["toolchain_name"], item["id"])
+            print("  * %s::%s::%s" % (item["target_name"],
+                                      item["toolchain_name"],
+                                      item["id"]))
             if print_log:
                 log_lines = item["output"].split("\n")
                 for log_line in log_lines:
-                    print "        %s" % log_line
+                    print("        %s" % log_line)
 
     def exporter_print(self, test_result_ext, print_log_for_failures=False):
         """ Export test results in print format.
@@ -343,15 +345,15 @@
                             raise Exception("'test_run' did not have a 'result' value")
 
         if successes:
-            print "\n\nBuild successes:"
+            print("\n\nBuild successes:")
             self.exporter_print_helper(successes)
 
         if skips:
-            print "\n\nBuild skips:"
+            print("\n\nBuild skips:")
             self.exporter_print_helper(skips)
 
         if failures:
-            print "\n\nBuild failures:"
+            print("\n\nBuild failures:")
             self.exporter_print_helper(failures, print_log=print_log_for_failures)
             return False
         else:
@@ -410,5 +412,5 @@
         result += "\n"
 
         # Print result count
-        result += "Result: " + ' / '.join(['%s %s' % (value, key) for (key, value) in {k: v for k, v in result_dict.items() if v != 0}.iteritems()])
+        result += "Result: " + ' / '.join(['%s %s' % (value, key) for (key, value) in {k: v for k, v in result_dict.items() if v != 0}.items()])
         return result
--- a/tests.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/tests.py	Tue Sep 25 13:43:09 2018 -0500
@@ -15,14 +15,9 @@
 limitations under the License.
 """
 from tools.paths import *
-from tools.data.support import *
+from tools.data.support import DEFAULT_SUPPORT, CORTEX_ARM_SUPPORT
 from argparse import ArgumentTypeError
-from utils import columnate
-
-try:
-    import tools.private_settings as ps
-except:
-    ps = object()
+from tools.utils import columnate
 
 TEST_CMSIS_LIB = join(TEST_DIR, "cmsis", "lib")
 TEST_MBED_LIB = join(TEST_DIR, "mbed", "env")
@@ -320,7 +315,7 @@
         "DISCO_F469NI", "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG",
         "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC",
         "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG",
-        "DISCO_F413ZH"]
+        "DISCO_F413ZH", "NUCLEO_F413ZH"]
     },
     {
         "id": "MBED_A28", "description": "CAN loopback test",
@@ -334,7 +329,7 @@
 
         "DISCO_F746NG", "DISCO_L476VG", "NUCLEO_L476RG", "NUCLEO_L432KC",
         "DISCO_F769NI", "NUCLEO_F767ZI", "DISCO_F303VC", "NUCLEO_F412ZG",
-        "DISCO_F413ZH"]
+        "DISCO_F413ZH", "NUCLEO_F413ZH"]
     },
     {
         "id": "MBED_A29", "description": "i2c_master_slave_asynch",
@@ -584,23 +579,23 @@
         "id": "MBED_29", "description": "CAN network test",
         "source_dir": join(TEST_DIR, "mbed", "can"),
         "dependencies": [MBED_LIBRARIES],
-        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "B96B_F446VE", "NUCLEO_F091RC",
+        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "GR_LYCHEE", "B96B_F446VE", "NUCLEO_F091RC",
                 "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F303RE",
                 "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE","NUCLEO_F446ZE", "DISCO_F469NI", "NUCLEO_F207ZG",
                 "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG",
                 "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG",
-                "DISCO_F413ZH"]
+                "DISCO_F413ZH", "NUCLEO_F413ZH"]
     },
     {
         "id": "MBED_30", "description": "CAN network test using interrupts",
         "source_dir": join(TEST_DIR, "mbed", "can_interrupt"),
         "dependencies": [MBED_LIBRARIES],
-        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "B96B_F446VE", "NUCLEO_F091RC", "NUCLEO_F207ZG",
+        "mcu": ["LPC1768", "LPC4088", "LPC1549", "RZ_A1H", "GR_LYCHEE", "B96B_F446VE", "NUCLEO_F091RC", "NUCLEO_F207ZG",
                 "NUCLEO_F072RB", "NUCLEO_F042K6", "NUCLEO_F334R8", "NUCLEO_F303RE",
                 "NUCLEO_F303K8", "NUCLEO_F302R8", "NUCLEO_F446RE", "NUCLEO_F446ZE", "DISCO_F469NI",
                 "DISCO_F429ZI", "NUCLEO_F103RB", "NUCLEO_F746ZG", "DISCO_F746NG",
                 "NUCLEO_L476RG", "NUCLEO_L432KC", "DISCO_F303VC", "NUCLEO_F412ZG",
-                "DISCO_F413ZH"]
+                "DISCO_F413ZH", "NUCLEO_F413ZH"]
     },
     {
         "id": "MBED_31", "description": "PWM LED test",
@@ -916,9 +911,7 @@
         raise ArgumentTypeError("{0} does not index a test. The accepted range is 0 to {1}\nThe test mapping is:\n{2}".format(i, len(TEST_MAP) - 1, columnate([str(i) + ":" + t['id'] for i,t in zip(range(len(TESTS)), TESTS)])))
 
 def test_name_known(string):
-    if string not in TEST_MAP.keys() and \
-       (getattr(ps, "test_alias", None) is None or \
-        ps.test_alias.get(string, "") not in TEST_MAP.keys()):
+    if string not in TEST_MAP.keys():
         raise ArgumentTypeError("Program with name '{0}' not found. Supported tests are: \n{1}".format(string, columnate([t['id'] for t in TESTS])))
 
     return TEST_MAP[string].n
--- a/toolchains/__init__.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/toolchains/__init__.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,303 +14,39 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, division, absolute_import
 
 import re
 import sys
+import json
 from os import stat, walk, getcwd, sep, remove
 from copy import copy
 from time import time, sleep
-from types import ListType
 from shutil import copyfile
-from os.path import join, splitext, exists, relpath, dirname, basename, split, abspath, isfile, isdir, normcase
-from itertools import chain
+from os.path import (join, splitext, exists, relpath, dirname, basename, split,
+                     abspath, isfile, isdir, normcase)
 from inspect import getmro
 from copy import deepcopy
+from collections import namedtuple
 from abc import ABCMeta, abstractmethod
 from distutils.spawn import find_executable
+from multiprocessing import Pool, cpu_count
+from hashlib import md5
 
-from multiprocessing import Pool, cpu_count
-from tools.utils import run_cmd, mkdir, rel_path, ToolException, NotSupportedException, split_path, compile_worker
-from tools.settings import MBED_ORG_USER
-import tools.hooks as hooks
-from tools.memap import MemapParser
-from hashlib import md5
-import fnmatch
+from ..utils import (run_cmd, mkdir, rel_path, ToolException,
+                    NotSupportedException, split_path, compile_worker)
+from ..settings import MBED_ORG_USER, PRINT_COMPILER_OUTPUT_AS_LINK
+from .. import hooks
+from ..notifier.term import TerminalNotifier
+from ..resources import FileType
+from ..memap import MemapParser
+from ..config import ConfigException
 
 
 #Disables multiprocessing if set to higher number than the host machine CPUs
 CPU_COUNT_MIN = 1
 CPU_COEF = 1
 
-class LazyDict(dict):
-    def __init__(self):
-        self.eager = {}
-        self.lazy = {}
-
-    def add_lazy(self, key, thunk):
-        if key in self.eager:
-            del self.eager[key]
-        self.lazy[key] = thunk
-
-    def __getitem__(self, key):
-        if  (key not in self.eager
-             and key in self.lazy):
-            self.eager[key] = self.lazy[key]()
-            del self.lazy[key]
-        return self.eager[key]
-
-    def __setitem__(self, key, value):
-        self.eager[key] = value
-
-    def __delitem__(self, key):
-        if key in self.eager:
-            del self.eager[key]
-        else:
-            del self.lazy[key]
-
-    def __contains__(self, key):
-        return key in self.eager or key in self.lazy
-
-    def __iter__(self):
-        return chain(iter(self.eager), iter(self.lazy))
-
-    def __len__(self):
-        return len(self.eager) + len(self.lazy)
-
-    def __str__(self):
-        return "Lazy{%s}" % (
-            ", ".join("%r: %r" % (k, v) for k, v in
-                      chain(self.eager.iteritems(), ((k, "not evaluated")
-                                                     for k in self.lazy))))
-
-    def update(self, other):
-        if isinstance(other, LazyDict):
-            self.eager.update(other.eager)
-            self.lazy.update(other.lazy)
-        else:
-            self.eager.update(other)
-
-    def iteritems(self):
-        """Warning: This forces the evaluation all of the items in this LazyDict
-        that are iterated over."""
-        for k, v in self.eager.iteritems():
-            yield k, v
-        for k in self.lazy.keys():
-            yield k, self[k]
-
-    def apply(self, fn):
-        """Delay the application of a computation to all items of the lazy dict.
-        Does no computation now. Instead the comuptation is performed when a
-        consumer attempts to access a value in this LazyDict"""
-        new_lazy = {}
-        for k, f in self.lazy.iteritems():
-            def closure(f=f):
-                return fn(f())
-            new_lazy[k] = closure
-        for k, v in self.eager.iteritems():
-            def closure(v=v):
-                return fn(v)
-            new_lazy[k] = closure
-        self.lazy = new_lazy
-        self.eager = {}
-
-class Resources:
-    def __init__(self, base_path=None, collect_ignores=False):
-        self.base_path = base_path
-        self.collect_ignores = collect_ignores
-
-        self.file_basepath = {}
-
-        self.inc_dirs = []
-        self.headers = []
-
-        self.s_sources = []
-        self.c_sources = []
-        self.cpp_sources = []
-
-        self.lib_dirs = set([])
-        self.objects = []
-        self.libraries = []
-
-        # mbed special files
-        self.lib_builds = []
-        self.lib_refs = []
-
-        self.repo_dirs = []
-        self.repo_files = []
-
-        self.linker_script = None
-
-        # Other files
-        self.hex_files = []
-        self.bin_files = []
-        self.json_files = []
-
-        # Features
-        self.features = LazyDict()
-        self.ignored_dirs = []
-
-    def __add__(self, resources):
-        if resources is None:
-            return self
-        else:
-            return self.add(resources)
-
-    def __radd__(self, resources):
-        if resources is None:
-            return self
-        else:
-            return self.add(resources)
-
-    def ignore_dir(self, directory):
-        if self.collect_ignores:
-            self.ignored_dirs.append(directory)
-
-    def add(self, resources):
-        for f,p in resources.file_basepath.items():
-            self.file_basepath[f] = p
-
-        self.inc_dirs += resources.inc_dirs
-        self.headers += resources.headers
-
-        self.s_sources += resources.s_sources
-        self.c_sources += resources.c_sources
-        self.cpp_sources += resources.cpp_sources
-
-        self.lib_dirs |= resources.lib_dirs
-        self.objects += resources.objects
-        self.libraries += resources.libraries
-
-        self.lib_builds += resources.lib_builds
-        self.lib_refs += resources.lib_refs
-
-        self.repo_dirs += resources.repo_dirs
-        self.repo_files += resources.repo_files
-
-        if resources.linker_script is not None:
-            self.linker_script = resources.linker_script
-
-        self.hex_files += resources.hex_files
-        self.bin_files += resources.bin_files
-        self.json_files += resources.json_files
-
-        self.features.update(resources.features)
-        self.ignored_dirs += resources.ignored_dirs
-
-        return self
-
-    def _collect_duplicates(self, dupe_dict, dupe_headers):
-        for filename in self.s_sources + self.c_sources + self.cpp_sources:
-            objname, _ = splitext(basename(filename))
-            dupe_dict.setdefault(objname, set())
-            dupe_dict[objname] |= set([filename])
-        for filename in self.headers:
-            headername = basename(filename)
-            dupe_headers.setdefault(headername, set())
-            dupe_headers[headername] |= set([headername])
-        for res in self.features.values():
-            res._collect_duplicates(dupe_dict, dupe_headers)
-        return dupe_dict, dupe_headers
-
-    def detect_duplicates(self, toolchain):
-        """Detect all potential ambiguities in filenames and report them with
-        a toolchain notification
-
-        Positional Arguments:
-        toolchain - used for notifications
-        """
-        count = 0
-        dupe_dict, dupe_headers = self._collect_duplicates(dict(), dict())
-        for objname, filenames in dupe_dict.iteritems():
-            if len(filenames) > 1:
-                count+=1
-                toolchain.tool_error(
-                    "Object file %s.o is not unique! It could be made from: %s"\
-                    % (objname, " ".join(filenames)))
-        for headername, locations in dupe_headers.iteritems():
-            if len(locations) > 1:
-                count+=1
-                toolchain.tool_error(
-                    "Header file %s is not unique! It could be: %s" %\
-                    (headername, " ".join(locations)))
-        return count
-
-
-    def relative_to(self, base, dot=False):
-        for field in ['inc_dirs', 'headers', 's_sources', 'c_sources',
-                      'cpp_sources', 'lib_dirs', 'objects', 'libraries',
-                      'lib_builds', 'lib_refs', 'repo_dirs', 'repo_files',
-                      'hex_files', 'bin_files', 'json_files']:
-            v = [rel_path(f, base, dot) for f in getattr(self, field)]
-            setattr(self, field, v)
-
-        def to_apply(feature, base=base, dot=dot):
-            feature.relative_to(base, dot)
-        self.features.apply(to_apply)
-
-        if self.linker_script is not None:
-            self.linker_script = rel_path(self.linker_script, base, dot)
-
-    def win_to_unix(self):
-        for field in ['inc_dirs', 'headers', 's_sources', 'c_sources',
-                      'cpp_sources', 'lib_dirs', 'objects', 'libraries',
-                      'lib_builds', 'lib_refs', 'repo_dirs', 'repo_files',
-                      'hex_files', 'bin_files', 'json_files']:
-            v = [f.replace('\\', '/') for f in getattr(self, field)]
-            setattr(self, field, v)
-
-        def to_apply(feature):
-            feature.win_to_unix()
-        self.features.apply(to_apply)
-
-        if self.linker_script is not None:
-            self.linker_script = self.linker_script.replace('\\', '/')
-
-    def __str__(self):
-        s = []
-
-        for (label, resources) in (
-                ('Include Directories', self.inc_dirs),
-                ('Headers', self.headers),
-
-                ('Assembly sources', self.s_sources),
-                ('C sources', self.c_sources),
-                ('C++ sources', self.cpp_sources),
-
-                ('Library directories', self.lib_dirs),
-                ('Objects', self.objects),
-                ('Libraries', self.libraries),
-
-                ('Hex files', self.hex_files),
-                ('Bin files', self.bin_files),
-
-                ('Features', self.features),
-            ):
-            if resources:
-                s.append('%s:\n  ' % label + '\n  '.join(resources))
-
-        if self.linker_script:
-            s.append('Linker Script: ' + self.linker_script)
-
-        return '\n'.join(s)
-
-# Support legacy build conventions: the original mbed build system did not have
-# standard labels for the "TARGET_" and "TOOLCHAIN_" specific directories, but
-# had the knowledge of a list of these directories to be ignored.
-LEGACY_IGNORE_DIRS = set([
-    'LPC11U24', 'LPC1768', 'LPC2368', 'LPC4088', 'LPC812', 'KL25Z',
-    'ARM', 'uARM', 'IAR',
-    'GCC_ARM', 'GCC_CS', 'GCC_CR', 'GCC_CW', 'GCC_CW_EWL', 'GCC_CW_NEWLIB',
-    'ARMC6'
-])
-LEGACY_TOOLCHAIN_NAMES = {
-    'ARM_STD':'ARM', 'ARM_MICRO': 'uARM',
-    'GCC_ARM': 'GCC_ARM', 'GCC_CR': 'GCC_CR',
-    'IAR': 'IAR',
-    'ARMC6': 'ARMC6',
-}
-
-
 class mbedToolchain:
     # Verbose logging
     VERBOSE = True
@@ -333,10 +69,12 @@
         "Cortex-M7F" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
         "Cortex-M7FD" : ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
         "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"],
-        "Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
         "Cortex-M23": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
-        "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
-        "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M33F-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
+        "Cortex-M33F": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
     }
 
     MBED_CONFIG_FILE_NAME="mbed_config.h"
@@ -347,8 +85,8 @@
 
     profile_template = {'common':[], 'c':[], 'cxx':[], 'asm':[], 'ld':[]}
 
-    def __init__(self, target, notify=None, macros=None, silent=False,
-                 extra_verbose=False, build_profile=None, build_dir=None):
+    def __init__(self, target, notify=None, macros=None, build_profile=None,
+                 build_dir=None):
         self.target = target
         self.name = self.__class__.__name__
 
@@ -387,18 +125,12 @@
         self.build_all = False
 
         # Build output dir
-        self.build_dir = build_dir
+        self.build_dir = abspath(build_dir) if PRINT_COMPILER_OUTPUT_AS_LINK else build_dir
         self.timestamp = time()
 
         # Number of concurrent build jobs. 0 means auto (based on host system cores)
         self.jobs = 0
 
-        # Ignore patterns from .mbedignore files
-        self.ignore_patterns = []
-        self._ignore_regex = re.compile("$^")
-
-        # Pre-mbed 2.0 ignore dirs
-        self.legacy_ignore_dirs = (LEGACY_IGNORE_DIRS | TOOLCHAINS) - set([target.name, LEGACY_TOOLCHAIN_NAMES[self.name]])
 
         # Output notify function
         # This function is passed all events, and expected to handle notification of the
@@ -410,21 +142,10 @@
         #                  or an application was linked
         #       *Silent* is a boolean
         if notify:
-            self.notify_fun = notify
-        elif extra_verbose:
-            self.notify_fun = self.print_notify_verbose
+            self.notify = notify
         else:
-            self.notify_fun = self.print_notify
+            self.notify = TerminalNotifier()
 
-        # Silent builds (no output)
-        self.silent = silent
-
-        # Print output buffer
-        self.output = str()
-
-        # uVisor spepcific rules
-        if 'UVISOR' in self.target.features and 'UVISOR_SUPPORTED' in self.target.extra_labels:
-            self.target.core = re.sub(r"F$", '', self.target.core)
 
         # Stats cache is used to reduce the amount of IO requests to stat
         # header files during dependency change. See need_update()
@@ -443,65 +164,7 @@
         return True
 
     def get_output(self):
-        return self.output
-
-    def print_notify(self, event, silent=False):
-        """ Default command line notification
-        """
-        msg = None
-
-        if not self.VERBOSE and event['type'] == 'tool_error':
-            msg = event['message']
-
-        elif event['type'] in ['info', 'debug']:
-            msg = event['message']
-
-        elif event['type'] == 'cc':
-            event['severity'] = event['severity'].title()
-            event['file'] = basename(event['file'])
-            msg = '[%(severity)s] %(file)s@%(line)s,%(col)s: %(message)s' % event
-
-        elif event['type'] == 'progress':
-            if 'percent' in event:
-                msg = '{} [{:>5.1f}%]: {}'.format(event['action'].title(),
-                                                  event['percent'],
-                                                  basename(event['file']))
-            else:
-                msg = '{}: {}'.format(event['action'].title(),
-                                      basename(event['file']))
-
-        if msg:
-            if not silent:
-                print msg
-            self.output += msg + "\n"
-
-    def print_notify_verbose(self, event, silent=False):
-        """ Default command line notification with more verbose mode
-        """
-        if event['type'] in ['info', 'debug']:
-            self.print_notify(event, silent=silent) # standard handle
-
-        elif event['type'] == 'cc':
-            event['severity'] = event['severity'].title()
-            event['file'] = basename(event['file'])
-            event['mcu_name'] = "None"
-            event['target_name'] = event['target_name'].upper() if event['target_name'] else "Unknown"
-            event['toolchain_name'] = event['toolchain_name'].upper() if event['toolchain_name'] else "Unknown"
-            msg = '[%(severity)s] %(target_name)s::%(toolchain_name)s::%(file)s@%(line)s: %(message)s' % event
-            if not silent:
-                print msg
-            self.output += msg + "\n"
-
-        elif event['type'] == 'progress':
-            self.print_notify(event) # standard handle
-
-    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
-    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
-    def notify(self, event):
-        """ Little closure for notify functions
-        """
-        event['toolchain'] = self
-        return self.notify_fun(event, self.silent)
+        return self.notifier.get_output()
 
     def get_symbols(self, for_asm=False):
         if for_asm:
@@ -539,6 +202,8 @@
                 self.cxx_symbols += ["DEVICE_" + data + "=1" for data in self.target.device_has]
                 # Add target's features
                 self.cxx_symbols += ["FEATURE_" + data + "=1" for data in self.target.features]
+                # Add target's components
+                self.cxx_symbols += ["COMPONENT_" + data + "=1" for data in self.target.components]
                 # Add extra symbols passed via 'macros' parameter
                 self.cxx_symbols += self.macros
 
@@ -554,11 +219,11 @@
 
     def get_labels(self):
         if self.labels is None:
-            toolchain_labels = [c.__name__ for c in getmro(self.__class__)]
-            toolchain_labels.remove('mbedToolchain')
+            toolchain_labels = self._get_toolchain_labels()
             self.labels = {
                 'TARGET': self.target.labels,
                 'FEATURE': self.target.features,
+                'COMPONENT': self.target.components,
                 'TOOLCHAIN': toolchain_labels
             }
 
@@ -573,6 +238,12 @@
                 self.labels['TARGET'].append("RELEASE")
         return self.labels
 
+    def _get_toolchain_labels(self):
+        toolchain_labels = [c.__name__ for c in getmro(self.__class__)]
+        toolchain_labels.remove('mbedToolchain')
+        toolchain_labels.remove('object')
+        return toolchain_labels
+
 
     # Determine whether a source file needs updating/compiling
     def need_update(self, target, dependencies):
@@ -590,7 +261,7 @@
             if not d or not exists(d):
                 return True
 
-            if not self.stat_cache.has_key(d):
+            if d not in self.stat_cache:
                 self.stat_cache[d] = stat(d).st_mtime
 
             if self.stat_cache[d] >= target_mod_time:
@@ -598,183 +269,6 @@
 
         return False
 
-    def is_ignored(self, file_path):
-        """Check if file path is ignored by any .mbedignore thus far"""
-        return self._ignore_regex.match(normcase(file_path))
-
-    def add_ignore_patterns(self, root, base_path, patterns):
-        """Add a series of patterns to the ignored paths
-
-        Positional arguments:
-        root - the directory containing the ignore file
-        base_path - the location that the scan started from
-        patterns - the list of patterns we will ignore in the future
-        """
-        real_base = relpath(root, base_path)
-        if real_base == ".":
-            self.ignore_patterns.extend(normcase(p) for p in patterns)
-        else:
-            self.ignore_patterns.extend(normcase(join(real_base, pat)) for pat in patterns)
-        if self.ignore_patterns:
-            self._ignore_regex = re.compile("|".join(fnmatch.translate(p) for p in self.ignore_patterns))
-
-    # Create a Resources object from the path pointed to by *path* by either traversing a
-    # a directory structure, when *path* is a directory, or adding *path* to the resources,
-    # when *path* is a file.
-    # The parameter *base_path* is used to set the base_path attribute of the Resources
-    # object and the parameter *exclude_paths* is used by the directory traversal to
-    # exclude certain paths from the traversal.
-    def scan_resources(self, path, exclude_paths=None, base_path=None,
-                       collect_ignores=False):
-        self.progress("scan", path)
-
-        resources = Resources(path, collect_ignores=collect_ignores)
-        if not base_path:
-            if isfile(path):
-                base_path = dirname(path)
-            else:
-                base_path = path
-        resources.base_path = base_path
-
-        if isfile(path):
-            self._add_file(path, resources, base_path, exclude_paths=exclude_paths)
-        else:
-            self._add_dir(path, resources, base_path, exclude_paths=exclude_paths)
-        return resources
-
-    # A helper function for scan_resources. _add_dir traverses *path* (assumed to be a
-    # directory) and heeds the ".mbedignore" files along the way. _add_dir calls _add_file
-    # on every file it considers adding to the resources object.
-    def _add_dir(self, path, resources, base_path, exclude_paths=None):
-        """ os.walk(top[, topdown=True[, onerror=None[, followlinks=False]]])
-        When topdown is True, the caller can modify the dirnames list in-place
-        (perhaps using del or slice assignment), and walk() will only recurse into
-        the subdirectories whose names remain in dirnames; this can be used to prune
-        the search, impose a specific order of visiting, or even to inform walk()
-        about directories the caller creates or renames before it resumes walk()
-        again. Modifying dirnames when topdown is False is ineffective, because in
-        bottom-up mode the directories in dirnames are generated before dirpath
-        itself is generated.
-        """
-        labels = self.get_labels()
-        for root, dirs, files in walk(path, followlinks=True):
-            # Check if folder contains .mbedignore
-            if ".mbedignore" in files:
-                with open (join(root,".mbedignore"), "r") as f:
-                    lines=f.readlines()
-                    lines = [l.strip() for l in lines] # Strip whitespaces
-                    lines = [l for l in lines if l != ""] # Strip empty lines
-                    lines = [l for l in lines if not re.match("^#",l)] # Strip comment lines
-                    # Append root path to glob patterns and append patterns to ignore_patterns
-                    self.add_ignore_patterns(root, base_path, lines)
-
-            # Skip the whole folder if ignored, e.g. .mbedignore containing '*'
-            root_path =join(relpath(root, base_path))
-            if  (self.is_ignored(join(root_path,"")) or
-                 self.build_dir == root_path):
-                resources.ignore_dir(root_path)
-                dirs[:] = []
-                continue
-
-            for d in copy(dirs):
-                dir_path = join(root, d)
-                # Add internal repo folders/files. This is needed for exporters
-                if d == '.hg' or d == '.git':
-                    resources.repo_dirs.append(dir_path)
-
-                if ((d.startswith('.') or d in self.legacy_ignore_dirs) or
-                    # Ignore targets that do not match the TARGET in extra_labels list
-                    (d.startswith('TARGET_') and d[7:] not in labels['TARGET']) or
-                    # Ignore toolchain that do not match the current TOOLCHAIN
-                    (d.startswith('TOOLCHAIN_') and d[10:] not in labels['TOOLCHAIN']) or
-                    # Ignore .mbedignore files
-                    self.is_ignored(join(relpath(root, base_path), d,"")) or
-                    # Ignore TESTS dir
-                    (d == 'TESTS')):
-                        resources.ignore_dir(dir_path)
-                        dirs.remove(d)
-                elif d.startswith('FEATURE_'):
-                    # Recursively scan features but ignore them in the current scan.
-                    # These are dynamically added by the config system if the conditions are matched
-                    def closure (dir_path=dir_path, base_path=base_path):
-                        return self.scan_resources(dir_path, base_path=base_path,
-                                                   collect_ignores=resources.collect_ignores)
-                    resources.features.add_lazy(d[8:], closure)
-                    resources.ignore_dir(dir_path)
-                    dirs.remove(d)
-                elif exclude_paths:
-                    for exclude_path in exclude_paths:
-                        rel_path = relpath(dir_path, exclude_path)
-                        if not (rel_path.startswith('..')):
-                            resources.ignore_dir(dir_path)
-                            dirs.remove(d)
-                            break
-
-            # Add root to include paths
-            root = root.rstrip("/")
-            resources.inc_dirs.append(root)
-            resources.file_basepath[root] = base_path
-
-            for file in files:
-                file_path = join(root, file)
-                self._add_file(file_path, resources, base_path)
-
-    # A helper function for both scan_resources and _add_dir. _add_file adds one file
-    # (*file_path*) to the resources object based on the file type.
-    def _add_file(self, file_path, resources, base_path, exclude_paths=None):
-        resources.file_basepath[file_path] = base_path
-
-        if self.is_ignored(relpath(file_path, base_path)):
-            return
-
-        _, ext = splitext(file_path)
-        ext = ext.lower()
-
-        if   ext == '.s':
-            resources.s_sources.append(file_path)
-
-        elif ext == '.c':
-            resources.c_sources.append(file_path)
-
-        elif ext == '.cpp':
-            resources.cpp_sources.append(file_path)
-
-        elif ext == '.h' or ext == '.hpp':
-            resources.headers.append(file_path)
-
-        elif ext == '.o':
-            resources.objects.append(file_path)
-
-        elif ext == self.LIBRARY_EXT:
-            resources.libraries.append(file_path)
-            resources.lib_dirs.add(dirname(file_path))
-
-        elif ext == self.LINKER_EXT:
-            if resources.linker_script is not None:
-                self.info("Warning: Multiple linker scripts detected: %s -> %s" % (resources.linker_script, file_path))
-            resources.linker_script = file_path
-
-        elif ext == '.lib':
-            resources.lib_refs.append(file_path)
-
-        elif ext == '.bld':
-            resources.lib_builds.append(file_path)
-
-        elif basename(file_path) == '.hgignore':
-            resources.repo_files.append(file_path)
-
-        elif basename(file_path) == '.gitignore':
-            resources.repo_files.append(file_path)
-
-        elif ext == '.hex':
-            resources.hex_files.append(file_path)
-
-        elif ext == '.bin':
-            resources.bin_files.append(file_path)
-
-        elif ext == '.json':
-            resources.json_files.append(file_path)
-
 
     def scan_repository(self, path):
         resources = []
@@ -791,96 +285,86 @@
 
         return resources
 
-    def copy_files(self, files_paths, trg_path, resources=None, rel_path=None):
+    def copy_files(self, files_paths, trg_path, resources=None):
         # Handle a single file
-        if type(files_paths) != ListType: files_paths = [files_paths]
-
-        for source in files_paths:
-            if source is None:
-                files_paths.remove(source)
+        if not isinstance(files_paths, list):
+            files_paths = [files_paths]
 
-        for source in files_paths:
-            if resources is not None and resources.file_basepath.has_key(source):
-                relative_path = relpath(source, resources.file_basepath[source])
-            elif rel_path is not None:
-                relative_path = relpath(source, rel_path)
-            else:
-                _, relative_path = split(source)
-
-            target = join(trg_path, relative_path)
-
+        for dest, source in files_paths:
+            target = join(trg_path, dest)
             if (target != source) and (self.need_update(target, [source])):
-                self.progress("copy", relative_path)
+                self.progress("copy", dest)
                 mkdir(dirname(target))
                 copyfile(source, target)
 
     # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
     # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
-    def relative_object_path(self, build_path, base_dir, source):
-        source_dir, name, _ = split_path(source)
+    def relative_object_path(self, build_path, file_ref):
+        source_dir, name, _ = split_path(file_ref.name)
 
-        obj_dir = join(build_path, relpath(source_dir, base_dir))
+        obj_dir = relpath(join(build_path, source_dir))
         if obj_dir is not self.prev_dir:
             self.prev_dir = obj_dir
             mkdir(obj_dir)
         return join(obj_dir, name + '.o')
 
-    # Generate response file for all includes.
-    # ARM, GCC, IAR cross compatible
+    def make_option_file(self, options, naming=".options_{}.txt"):
+        """ Generate a via file for a pile of defines
+        ARM, GCC, IAR cross compatible
+        """
+        to_write = " ".join(options).encode('utf-8')
+        new_md5 = md5(to_write).hexdigest()
+        via_file = join(self.build_dir, naming.format(new_md5))
+        try:
+            with open(via_file, "r") as fd:
+                old_md5 = md5(fd.read().encode('utf-8')).hexdigest()
+        except IOError:
+            old_md5 = None
+        if old_md5 != new_md5:
+            with open(via_file, "wb") as fd:
+                fd.write(to_write)
+        return via_file
+
     def get_inc_file(self, includes):
-        include_file = join(self.build_dir, ".includes_%s.txt" % self.inc_md5)
-        if not exists(include_file):
-            with open(include_file, "wb") as f:
-                cmd_list = []
-                for c in includes:
-                    if c:
-                        c = c.replace("\\", "/")
-                        if self.CHROOT:
-                            c = c.replace(self.CHROOT, '')
-                        cmd_list.append('"-I%s"' % c)
-                string = " ".join(cmd_list)
-                f.write(string)
-        return include_file
+        """Generate a via file for all includes.
+        ARM, GCC, IAR cross compatible
+        """
+        cmd_list = ("-I{}".format(c.replace("\\", "/")) for c in includes if c)
+        if self.CHROOT:
+            cmd_list = (c.replace(self.CHROOT, '') for c in cmd_list)
+        return self.make_option_file(list(cmd_list), naming=".includes_{}.txt")
 
-    # Generate response file for all objects when linking.
-    # ARM, GCC, IAR cross compatible
     def get_link_file(self, cmd):
-        link_file = join(self.build_dir, ".link_files.txt")
-        with open(link_file, "wb") as f:
-            cmd_list = []
-            for c in cmd:
-                if c:
-                    c = c.replace("\\", "/")
-                    if self.CHROOT:
-                        c = c.replace(self.CHROOT, '')
-                    cmd_list.append(('"%s"' % c) if not c.startswith('-') else c)
-            string = " ".join(cmd_list)
-            f.write(string)
-        return link_file
+        """Generate a via file for all objects when linking.
+        ARM, GCC, IAR cross compatible
+        """
+        cmd_list = (c.replace("\\", "/") for c in cmd if c)
+        if self.CHROOT:
+            cmd_list = (c.replace(self.CHROOT, '') for c in cmd_list)
+        return self.make_option_file(list(cmd_list), naming=".link_options.txt")
 
-    # Generate response file for all objects when archiving.
-    # ARM, GCC, IAR cross compatible
     def get_arch_file(self, objects):
-        archive_file = join(self.build_dir, ".archive_files.txt")
-        with open(archive_file, "wb") as f:
-            o_list = []
-            for o in objects:
-                o_list.append('"%s"' % o)
-            string = " ".join(o_list).replace("\\", "/")
-            f.write(string)
-        return archive_file
+        """ Generate a via file for all objects when archiving.
+        ARM, GCC, IAR cross compatible
+        """
+        cmd_list = (c.replace("\\", "/") for c in objects if c)
+        return self.make_option_file(list(cmd_list), ".archive_files.txt")
 
     # THIS METHOD IS BEING CALLED BY THE MBED ONLINE BUILD SYSTEM
     # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
     def compile_sources(self, resources, inc_dirs=None):
         # Web IDE progress bar for project build
-        files_to_compile = resources.s_sources + resources.c_sources + resources.cpp_sources
+        files_to_compile = (
+            resources.get_file_refs(FileType.ASM_SRC) +
+            resources.get_file_refs(FileType.C_SRC) +
+            resources.get_file_refs(FileType.CPP_SRC)
+        )
         self.to_be_compiled = len(files_to_compile)
         self.compiled = 0
 
-        self.cc_verbose("Macros: "+' '.join(['-D%s' % s for s in self.get_symbols()]))
+        self.notify.cc_verbose("Macros: "+' '.join(['-D%s' % s for s in self.get_symbols()]))
 
-        inc_paths = resources.inc_dirs
+        inc_paths = resources.get_file_paths(FileType.INC_DIR)
         if inc_dirs is not None:
             if isinstance(inc_dirs, list):
                 inc_paths.extend(inc_dirs)
@@ -891,7 +375,7 @@
         # Sort include paths for consistency
         inc_paths = sorted(set(inc_paths))
         # Unique id of all include paths
-        self.inc_md5 = md5(' '.join(inc_paths)).hexdigest()
+        self.inc_md5 = md5(' '.join(inc_paths).encode('utf-8')).hexdigest()
 
         objects = []
         queue = []
@@ -905,11 +389,10 @@
         # Sort compile queue for consistency
         files_to_compile.sort()
         for source in files_to_compile:
-            object = self.relative_object_path(
-                self.build_dir, resources.file_basepath[source], source)
+            object = self.relative_object_path(self.build_dir, source)
 
             # Queue mode (multiprocessing)
-            commands = self.compile_command(source, object, inc_paths)
+            commands = self.compile_command(source.path, object, inc_paths)
             if commands is not None:
                 queue.append({
                     'source': source,
@@ -935,9 +418,9 @@
             result = compile_worker(item)
 
             self.compiled += 1
-            self.progress("compile", item['source'], build_update=True)
+            self.progress("compile", item['source'].name, build_update=True)
             for res in result['results']:
-                self.cc_verbose("Compile: %s" % ' '.join(res['command']), result['source'])
+                self.notify.cc_verbose("Compile: %s" % ' '.join(res['command']), result['source'])
                 self.compile_output([
                     res['code'],
                     res['output'],
@@ -967,22 +450,22 @@
             sleep(0.01)
             pending = 0
             for r in results:
-                if r._ready is True:
+                if r.ready():
                     try:
                         result = r.get()
                         results.remove(r)
 
                         self.compiled += 1
-                        self.progress("compile", result['source'], build_update=True)
+                        self.progress("compile", result['source'].name, build_update=True)
                         for res in result['results']:
-                            self.cc_verbose("Compile: %s" % ' '.join(res['command']), result['source'])
+                            self.notify.cc_verbose("Compile: %s" % ' '.join(res['command']), result['source'])
                             self.compile_output([
                                 res['code'],
                                 res['output'],
                                 res['command']
                             ])
                         objects.append(result['object'])
-                    except ToolException, err:
+                    except ToolException as err:
                         if p._taskqueue.queue:
                             p._taskqueue.queue.clear()
                             sleep(0.5)
@@ -1005,22 +488,24 @@
         _, ext = splitext(source)
         ext = ext.lower()
 
-        if ext == '.c' or  ext == '.cpp':
+        source = abspath(source) if PRINT_COMPILER_OUTPUT_AS_LINK else source
+
+        if ext == '.c' or  ext == '.cpp' or ext == '.cc':
             base, _ = splitext(object)
             dep_path = base + '.d'
             try:
                 deps = self.parse_dependencies(dep_path) if (exists(dep_path)) else []
-            except IOError, IndexError:
+            except (IOError, IndexError):
                 deps = []
             config_file = ([self.config.app_config_location]
                            if self.config.app_config_location else [])
             deps.extend(config_file)
-            if ext == '.cpp' or self.COMPILE_C_AS_CPP:
+            if ext != '.c' or self.COMPILE_C_AS_CPP:
                 deps.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-cxx"))
             else:
                 deps.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-c"))
             if len(deps) == 0 or self.need_update(object, deps):
-                if ext == '.cpp' or self.COMPILE_C_AS_CPP:
+                if ext != '.c' or self.COMPILE_C_AS_CPP:
                     return self.compile_cpp(source, object, includes)
                 else:
                     return self.compile_c(source, object, includes)
@@ -1054,7 +539,7 @@
             buff[0] = re.sub('^(.*?)\: ', '', buff[0])
             for line in buff:
                 filename = line.replace('\\\n', '').strip()
-                if file:
+                if filename:
                     filename = filename.replace('\\ ', '\a')
                     dependencies.extend(((self.CHROOT if self.CHROOT else '') +
                                          f.replace('\a', ' '))
@@ -1086,9 +571,9 @@
 
         # Parse output for Warnings and Errors
         self.parse_output(_stderr)
-        self.debug("Return: %s"% _rc)
+        self.notify.debug("Return: %s"% _rc)
         for error_line in _stderr.splitlines():
-            self.debug("Output: %s"% error_line)
+            self.notify.debug("Output: %s"% error_line)
 
         # Check return code
         if _rc != 0:
@@ -1102,7 +587,7 @@
         lib = self.STD_LIB_NAME % name
         fout = join(dir, lib)
         if self.need_update(fout, objects):
-            self.info("Library: %s" % lib)
+            self.notify.info("Library: %s" % lib)
             self.archive(objects, fout)
             needed_update = True
 
@@ -1115,7 +600,7 @@
             ext = self.target.OUTPUT_EXT
 
         if hasattr(self.target, 'OUTPUT_NAMING'):
-            self.var("binary_naming", self.target.OUTPUT_NAMING)
+            self.notify.var("binary_naming", self.target.OUTPUT_NAMING)
             if self.target.OUTPUT_NAMING == "8.3":
                 name = name[0:8]
                 ext = ext[0:3]
@@ -1126,19 +611,26 @@
         mkdir(new_path)
 
         filename = name+'.'+ext
+        # Absolute path of the final linked file
+        full_path = join(tmp_path, filename)
         elf = join(tmp_path, name + '.elf')
-        bin = None if ext is 'elf' else join(tmp_path, filename)
+        bin = None if ext == 'elf' else full_path
         map = join(tmp_path, name + '.map')
 
-        r.objects = sorted(set(r.objects))
+        objects = sorted(set(r.get_file_paths(FileType.OBJECT)))
         config_file = ([self.config.app_config_location]
                        if self.config.app_config_location else [])
-        dependencies = r.objects + r.libraries + [r.linker_script] + config_file
+        linker_script = [path for _, path in r.get_file_refs(FileType.LD_SCRIPT)
+                         if path.endswith(self.LINKER_EXT)][-1]
+        lib_dirs = r.get_file_paths(FileType.LIB_DIR)
+        libraries = [l for l in r.get_file_paths(FileType.LIB)
+                     if l.endswith(self.LIBRARY_EXT)]
+        dependencies = objects + libraries + [linker_script] + config_file
         dependencies.append(join(self.build_dir, self.PROFILE_FILE_NAME + "-ld"))
         if self.need_update(elf, dependencies):
             needed_update = True
             self.progress("link", name)
-            self.link(elf, r.objects, r.libraries, r.lib_dirs, r.linker_script)
+            self.link(elf, objects, libraries, lib_dirs, linker_script)
 
         if bin and self.need_update(bin, [elf]):
             needed_update = True
@@ -1148,63 +640,33 @@
         # Initialize memap and process map file. This doesn't generate output.
         self.mem_stats(map)
 
-        self.var("compile_succeded", True)
-        self.var("binary", filename)
+        self.notify.var("compile_succeded", True)
+        self.notify.var("binary", filename)
 
-        return bin, needed_update
+        return full_path, needed_update
 
     # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
     # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
     def default_cmd(self, command):
         _stdout, _stderr, _rc = run_cmd(command, work_dir=getcwd(), chroot=self.CHROOT)
-        self.debug("Return: %s"% _rc)
+        self.notify.debug("Return: %s"% _rc)
 
         for output_line in _stdout.splitlines():
-            self.debug("Output: %s"% output_line)
+            self.notify.debug("Output: %s"% output_line)
         for error_line in _stderr.splitlines():
-            self.debug("Errors: %s"% error_line)
+            self.notify.debug("Errors: %s"% error_line)
 
         if _rc != 0:
             for line in _stderr.splitlines():
-                self.tool_error(line)
+                self.notify.tool_error(line)
             raise ToolException(_stderr)
 
-    ### NOTIFICATIONS ###
-    def info(self, message):
-        self.notify({'type': 'info', 'message': message})
-
-    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
-    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
-    def debug(self, message):
-        if self.VERBOSE:
-            if type(message) is ListType:
-                message = ' '.join(message)
-            message = "[DEBUG] " + message
-            self.notify({'type': 'debug', 'message': message})
-
-    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
-    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
-    def cc_info(self, info=None):
-        if info is not None:
-            info['type'] = 'cc'
-            self.notify(info)
-
-    # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
-    # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
-    def cc_verbose(self, message, file=""):
-        self.debug(message)
-
     def progress(self, action, file, build_update=False):
-        msg = {'type': 'progress', 'action': action, 'file': file}
         if build_update:
-            msg['percent'] = 100. * float(self.compiled) / float(self.to_be_compiled)
-        self.notify(msg)
-
-    def tool_error(self, message):
-        self.notify({'type': 'tool_error', 'message': message})
-
-    def var(self, key, value):
-        self.notify({'type': 'var', 'key': key, 'val': value})
+            percent = 100. * float(self.compiled) / float(self.to_be_compiled)
+        else:
+            percent = None
+        self.notify.progress(action, file, percent)
 
     # THIS METHOD IS BEING OVERRIDDEN BY THE MBED ONLINE BUILD SYSTEM
     # ANY CHANGE OF PARAMETERS OR RETURN VALUES WILL BREAK COMPATIBILITY
@@ -1220,7 +682,7 @@
 
         # Parse and decode a map file
         if memap.parse(abspath(map), toolchain) is False:
-            self.info("Unknown toolchain for memory statistics %s" % toolchain)
+            self.notify.info("Unknown toolchain for memory statistics %s" % toolchain)
             return None
 
         # Store the memap instance for later use
@@ -1231,9 +693,66 @@
 
         return None
 
+    def _add_defines_from_region(self, region, suffixes=['_ADDR', '_SIZE']):
+        for define in [(region.name.upper() + suffixes[0], region.start),
+                       (region.name.upper() + suffixes[1], region.size)]:
+            define_string = "-D%s=0x%x" %  define
+            self.cc.append(define_string)
+            self.cppc.append(define_string)
+            self.flags["common"].append(define_string)
+
+    def _add_all_regions(self, region_list, active_region_name):
+        for region in region_list:
+            self._add_defines_from_region(region)
+            if region.active:
+                for define in [
+                        ("%s_START" % active_region_name, "0x%x" % region.start),
+                        ("%s_SIZE" % active_region_name, "0x%x" % region.size)
+                ]:
+                    define_string = self.make_ld_define(*define)
+                    self.ld.append(define_string)
+                    self.flags["ld"].append(define_string)
+            self.notify.info("  Region %s: size 0x%x, offset 0x%x"
+                             % (region.name, region.size, region.start))
+
+    def add_regions(self):
+        """Add regions to the build profile, if there are any.
+        """
+        if self.config.has_regions:
+            regions = list(self.config.regions)
+            self.notify.info("Using ROM region%s %s in this build." % (
+                "s" if len(regions) > 1 else "",
+                ", ".join(r.name for r in regions)
+            ))
+            self._add_all_regions(regions, "MBED_APP")
+        if self.config.has_ram_regions:
+            regions = list(self.config.ram_regions)
+            self.notify.info("Using RAM region%s %s in this build." % (
+                "s" if len(regions) > 1 else "",
+                ", ".join(r.name for r in regions)
+            ))
+            self._add_all_regions(regions, "MBED_RAM")
+        try:
+            rom_start, rom_size = self.config.rom
+            Region = namedtuple("Region", "name start size")
+            self._add_defines_from_region(
+                Region("MBED_ROM", rom_start, rom_size),
+                suffixes=["_START", "_SIZE"]
+            )
+        except ConfigException:
+            pass
+
     # Set the configuration data
     def set_config_data(self, config_data):
         self.config_data = config_data
+        # new configuration data can change labels, so clear the cache
+        self.labels = None
+        # pass info about softdevice presence to linker (see NRF52)
+        if "SOFTDEVICE_PRESENT" in config_data[1]:
+            define_string = self.make_ld_define("SOFTDEVICE_PRESENT", config_data[1]["SOFTDEVICE_PRESENT"].macro_value)
+            self.ld.append(define_string)
+            self.flags["ld"].append(define_string)
+        self.add_regions()
 
     # Creates the configuration header if needed:
     # - if there is no configuration data, "mbed_config.h" is not create (or deleted if it exists).
@@ -1252,7 +771,7 @@
         self.config_file = join(self.build_dir, self.MBED_CONFIG_FILE_NAME)
         # If the file exists, read its current content in prev_data
         if exists(self.config_file):
-            with open(self.config_file, "rt") as f:
+            with open(self.config_file, "r") as f:
                 prev_data = f.read()
         else:
             prev_data = None
@@ -1266,12 +785,12 @@
                 self.config_file = None # this means "config file not present"
                 changed = True
             elif crt_data != prev_data: # different content of config file
-                with open(self.config_file, "wt") as f:
+                with open(self.config_file, "w") as f:
                     f.write(crt_data)
                 changed = True
         else: # a previous mbed_config.h does not exist
             if crt_data is not None: # there's configuration data available
-                with open(self.config_file, "wt") as f:
+                with open(self.config_file, "w") as f:
                     f.write(crt_data)
                 changed = True
             else:
@@ -1287,16 +806,22 @@
         """Dump the current build profile and macros into the `.profile` file
         in the build directory"""
         for key in ["cxx", "c", "asm", "ld"]:
-            to_dump = (str(self.flags[key]) + str(sorted(self.macros)))
+            to_dump = {
+                "flags": sorted(self.flags[key]),
+                "macros": sorted(self.macros),
+                "symbols": sorted(self.get_symbols(for_asm=(key == "asm"))),
+            }
             if key in ["cxx", "c"]:
-                to_dump += str(self.flags['common'])
+                to_dump["symbols"].remove('MBED_BUILD_TIMESTAMP=%s' % self.timestamp)
+                to_dump["flags"].extend(sorted(self.flags['common']))
             where = join(self.build_dir, self.PROFILE_FILE_NAME + "-" + key)
-            self._overwrite_when_not_equal(where, to_dump)
+            self._overwrite_when_not_equal(where, json.dumps(
+                to_dump, sort_keys=True, indent=4))
 
     @staticmethod
     def _overwrite_when_not_equal(filename, content):
         if not exists(filename) or content != open(filename).read():
-            with open(filename, "wb") as out:
+            with open(filename, "w") as out:
                 out.write(content)
 
     @staticmethod
@@ -1555,6 +1080,13 @@
     def get_config_macros(self):
         return self.config.config_to_macros(self.config_data) if self.config_data else []
 
+    @abstractmethod
+    def version_check(self):
+        """Check the version of a compiler being used and raise a
+        NotSupportedException when it's incorrect.
+        """
+        raise NotImplemented
+
     @property
     def report(self):
         to_ret = {}
@@ -1583,11 +1115,11 @@
 from tools.toolchains.iar import IAR
 
 TOOLCHAIN_CLASSES = {
-    'ARM': ARM_STD,
-    'uARM': ARM_MICRO,
-    'ARMC6': ARMC6,
-    'GCC_ARM': GCC_ARM,
-    'IAR': IAR
+    u'ARM': ARM_STD,
+    u'uARM': ARM_MICRO,
+    u'ARMC6': ARMC6,
+    u'GCC_ARM': GCC_ARM,
+    u'IAR': IAR
 }
 
 TOOLCHAINS = set(TOOLCHAIN_CLASSES.keys())
--- a/toolchains/arm.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/toolchains/arm.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,15 +14,21 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, absolute_import
+from builtins import str
+
 import re
 from copy import copy
-from os.path import join, dirname, splitext, basename, exists
-from os import makedirs, write
+from os.path import join, dirname, splitext, basename, exists, relpath, isfile
+from os import makedirs, write, curdir, remove
 from tempfile import mkstemp
+from shutil import rmtree
+from distutils.version import LooseVersion
 
+from tools.targets import CORE_ARCH
 from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS
 from tools.hooks import hook_tool
-from tools.utils import mkdir, NotSupportedException
+from tools.utils import mkdir, NotSupportedException, run_cmd
 
 class ARM(mbedToolchain):
     LINKER_EXT = '.sct'
@@ -34,7 +40,9 @@
     DEP_PATTERN = re.compile('\S+:\s(?P<file>.+)\n')
     SHEBANG = "#! armcc -E"
     SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
-                       "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"]
+                       "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD", "Cortex-A9"]
+    ARMCC_RANGE = (LooseVersion("5.06"), LooseVersion("5.07"))
+    ARMCC_VERSION_RE = re.compile(b"Component: ARM Compiler (\d+\.\d+)")
 
     @staticmethod
     def check_executable():
@@ -44,16 +52,24 @@
         return mbedToolchain.generic_check_executable("ARM", 'armcc', 2, 'bin')
 
     def __init__(self, target, notify=None, macros=None,
-                 silent=False, extra_verbose=False, build_profile=None,
-                 build_dir=None):
-        mbedToolchain.__init__(self, target, notify, macros, silent,
-                               build_dir=build_dir,
-                               extra_verbose=extra_verbose,
-                               build_profile=build_profile)
+                 build_profile=None, build_dir=None):
+        mbedToolchain.__init__(
+            self, target, notify, macros, build_dir=build_dir,
+            build_profile=build_profile)
         if target.core not in self.SUPPORTED_CORES:
             raise NotSupportedException(
                 "this compiler does not support the core %s" % target.core)
 
+        if getattr(target, "default_lib", "std") == "small":
+            if "-DMBED_RTOS_SINGLE_THREAD" not in self.flags['common']:
+                self.flags['common'].append("-DMBED_RTOS_SINGLE_THREAD")
+            if "-D__MICROLIB" not in self.flags['common']:
+                self.flags['common'].append("-D__MICROLIB")
+            if "--library_type=microlib" not in self.flags['ld']:
+                self.flags['ld'].append("--library_type=microlib")
+            if "--library_type=microlib" not in self.flags['common']:
+                self.flags['common'].append("--library_type=microlib")
+
         if target.core == "Cortex-M0+":
             cpu = "Cortex-M0"
         elif target.core == "Cortex-M4F":
@@ -67,7 +83,7 @@
 
         ARM_BIN = join(TOOLCHAIN_PATHS['ARM'], "bin")
         ARM_INC = join(TOOLCHAIN_PATHS['ARM'], "include")
-        
+
         main_cc = join(ARM_BIN, "armcc")
 
         self.flags['common'] += ["--cpu=%s" % cpu]
@@ -81,6 +97,39 @@
         self.ar = join(ARM_BIN, "armar")
         self.elf2bin = join(ARM_BIN, "fromelf")
 
+        self.SHEBANG += " --cpu=%s" % cpu
+
+    def version_check(self):
+        stdout, _, retcode = run_cmd([self.cc[0], "--vsn"], redirect=True)
+        msg = None
+        min_ver, max_ver = self.ARMCC_RANGE
+        match = self.ARMCC_VERSION_RE.search(stdout)
+        found_version = LooseVersion(match.group(1).decode("utf-8")) if match else None
+        min_ver, max_ver = self.ARMCC_RANGE
+        if found_version and (found_version < min_ver or found_version >= max_ver):
+            msg = ("Compiler version mismatch: Have {}; "
+                   "expected version >= {} and < {}"
+                   .format(found_version, min_ver, max_ver))
+        elif not match or len(match.groups()) != 1:
+            msg = ("Compiler version mismatch: Could not detect version; "
+                   "expected version >= {} and < {}"
+                   .format(min_ver, max_ver))
+
+        if msg:
+            self.notify.cc_info({
+                "message": msg,
+                "file": "",
+                "line": "",
+                "col": "",
+                "severity": "ERROR",
+            })
+
+    def _get_toolchain_labels(self):
+        if getattr(self.target, "default_lib", "std") == "small":
+            return ["ARM", "ARM_MICRO"]
+        else:
+            return ["ARM", "ARM_STD"]
+
     def parse_dependencies(self, dep_path):
         dependencies = []
         for line in open(dep_path).readlines():
@@ -96,7 +145,7 @@
             match = ARM.DIAGNOSTIC_PATTERN.match(line)
             if match is not None:
                 if msg is not None:
-                    self.cc_info(msg)
+                    self.notify.cc_info(msg)
                     msg = None
                 msg = {
                     'severity': match.group('severity').lower(),
@@ -113,13 +162,13 @@
                 match = ARM.INDEX_PATTERN.match(line)
                 if match is not None:
                     msg['col'] = len(match.group('col'))
-                    self.cc_info(msg)
+                    self.notify.cc_info(msg)
                     msg = None
                 else:
                     msg['text'] += line+"\n"
         
         if msg is not None:
-            self.cc_info(msg)
+            self.notify.cc_info(msg)
 
     def get_dep_option(self, object):
         base, _ = splitext(object)
@@ -129,17 +178,18 @@
     def get_config_option(self, config_header):
         return ['--preinclude=' + config_header]
 
-    def get_compile_options(self, defines, includes, for_asm=False):        
+    def get_compile_options(self, defines, includes, for_asm=False):
         opts = ['-D%s' % d for d in defines]
+        config_header = self.get_config_header()
+        if config_header is not None:
+            opts = opts + self.get_config_option(config_header)
+        if for_asm:
+            return opts
         if self.RESPONSE_FILES:
             opts += ['--via', self.get_inc_file(includes)]
         else:
             opts += ["-I%s" % i for i in includes]
 
-        if not for_asm:
-            config_header = self.get_config_header()
-            if config_header is not None:
-                opts = opts + self.get_config_option(config_header)
         return opts
 
     @hook_tool
@@ -148,9 +198,12 @@
         dir = join(dirname(object), '.temp')
         mkdir(dir)
         tempfile = join(dir, basename(object) + '.E.s')
-        
+
         # Build preprocess assemble command
-        cmd_pre = self.asm + self.get_compile_options(self.get_symbols(True), includes) + ["-E", "-o", tempfile, source]
+        cmd_pre = copy(self.asm)
+        cmd_pre.extend(self.get_compile_options(
+            self.get_symbols(True), includes, True))
+        cmd_pre.extend(["-E", "-o", tempfile, source])
 
         # Build main assemble command
         cmd = self.asm + ["-o", object, tempfile]
@@ -158,7 +211,7 @@
         # Call cmdline hook
         cmd_pre = self.hook.get_cmdline_assembler(cmd_pre)
         cmd = self.hook.get_cmdline_assembler(cmd)
-       
+
         # Return command array, don't execute
         return [cmd_pre, cmd]
 
@@ -166,9 +219,9 @@
     def compile(self, cc, source, object, includes):
         # Build compile command
         cmd = cc + self.get_compile_options(self.get_symbols(), includes)
-        
+
         cmd.extend(self.get_dep_option(object))
-            
+
         cmd.extend(["-o", object, source])
 
         # Call cmdline hook
@@ -182,30 +235,38 @@
     def compile_cpp(self, source, object, includes):
         return self.compile(self.cppc, source, object, includes)
 
-    def correct_scatter_shebang(self, scatter_file):
+    def correct_scatter_shebang(self, scatter_file, cur_dir_name=None):
         """Correct the shebang at the top of a scatter file.
 
         Positional arguments:
         scatter_file -- the scatter file to correct
 
+        Keyword arguments:
+        cur_dir_name -- the name (not path) of the directory containing the
+                        scatter file
+
         Return:
         The location of the correct scatter file
 
         Side Effects:
         This method MAY write a new scatter file to disk
         """
-        with open(scatter_file, "rb") as input:
+        with open(scatter_file, "r") as input:
             lines = input.readlines()
-            if  (lines[0].startswith(self.SHEBANG) or
-                 not lines[0].startswith("#!")):
+            if (lines[0].startswith(self.SHEBANG) or
+                not lines[0].startswith("#!")):
                 return scatter_file
             else:
                 new_scatter = join(self.build_dir, ".link_script.sct")
+                if cur_dir_name is None:
+                    cur_dir_name = dirname(scatter_file)
+                self.SHEBANG += " -I %s" % cur_dir_name
                 if self.need_update(new_scatter, [scatter_file]):
-                    with open(new_scatter, "wb") as out:
+                    with open(new_scatter, "w") as out:
                         out.write(self.SHEBANG)
                         out.write("\n")
                         out.write("".join(lines[1:]))
+
                 return new_scatter
 
     @hook_tool
@@ -229,7 +290,7 @@
             link_files = self.get_link_file(cmd[1:])
             cmd = [cmd_linker, '--via', link_files]
 
-        self.cc_verbose("Link: %s" % ' '.join(cmd))
+        self.notify.cc_verbose("Link: %s" % ' '.join(cmd))
         self.default_cmd(cmd)
 
     @hook_tool
@@ -243,10 +304,19 @@
     @hook_tool
     def binary(self, resources, elf, bin):
         _, fmt = splitext(bin)
-        bin_arg = {".bin": "--bin", ".hex": "--i32"}[fmt]
+        # On .hex format, combine multiple .hex files (for multiple load regions) into one 
+        bin_arg = {".bin": "--bin", ".hex": "--i32combined"}[fmt]
         cmd = [self.elf2bin, bin_arg, '-o', bin, elf]
         cmd = self.hook.get_cmdline_binary(cmd)
-        self.cc_verbose("FromELF: %s" % ' '.join(cmd))
+
+        # remove target binary file/path
+        if exists(bin):
+            if isfile(bin):
+                remove(bin)
+            else:
+                rmtree(bin)
+
+        self.notify.cc_verbose("FromELF: %s" % ' '.join(cmd))
         self.default_cmd(cmd)
 
     @staticmethod
@@ -255,7 +325,7 @@
 
     @staticmethod
     def make_ld_define(name, value):
-        return "--predefine=\"-D%s=0x%x\"" % (name, value)
+        return "--predefine=\"-D%s=%s\"" % (name, value)
 
     @staticmethod
     def redirect_symbol(source, sync, build_dir):
@@ -268,13 +338,11 @@
 
 class ARM_STD(ARM):
     def __init__(self, target, notify=None, macros=None,
-                 silent=False, extra_verbose=False, build_profile=None,
-                 build_dir=None):
-        ARM.__init__(self, target, notify, macros, silent,
-                     build_dir=build_dir, extra_verbose=extra_verbose,
+                 build_profile=None, build_dir=None):
+        ARM.__init__(self, target, notify, macros, build_dir=build_dir,
                      build_profile=build_profile)
-        if "ARM" not in target.supported_toolchains:
-            raise NotSupportedException("ARM compiler support is required for ARM build")
+        if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)):
+            raise NotSupportedException("ARM/uARM compiler support is required for ARM build")
 
 
 class ARM_MICRO(ARM):
@@ -282,8 +350,8 @@
     def __init__(self, target, notify=None, macros=None,
                  silent=False, extra_verbose=False, build_profile=None,
                  build_dir=None):
-        ARM.__init__(self, target, notify, macros, silent,
-                     build_dir=build_dir, extra_verbose=extra_verbose,
+        target.default_lib = "small"
+        ARM.__init__(self, target, notify, macros, build_dir=build_dir,
                      build_profile=build_profile)
         if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)):
             raise NotSupportedException("ARM/uARM compiler support is required for ARM build")
@@ -293,7 +361,9 @@
     SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
                        "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD",
                        "Cortex-M23", "Cortex-M23-NS", "Cortex-M33",
-                       "CortexM33-NS"]
+                       "Cortex-M33-NS", "Cortex-A9"]
+    ARMCC_RANGE = (LooseVersion("6.10"), LooseVersion("7.0"))
+
     @staticmethod
     def check_executable():
         return mbedToolchain.generic_check_executable("ARMC6", "armclang", 1)
@@ -303,6 +373,14 @@
         if target.core not in self.SUPPORTED_CORES:
             raise NotSupportedException(
                 "this compiler does not support the core %s" % target.core)
+        if CORE_ARCH[target.core] < 8:
+            self.notify.cc_info({
+                'severity': "Error", 'file': "", 'line': "", 'col': "",
+                'message': "ARMC6 does not support ARM architecture v{}"
+                " targets".format(CORE_ARCH[target.core]),
+                'text': '', 'target_name': self.target.name,
+                'toolchain_name': self.name
+            })
 
         if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)):
             raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build")
@@ -310,15 +388,19 @@
         if target.core.lower().endswith("fd"):
             self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-2])
             self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-2])
+            self.SHEBANG += " -mcpu=%s" % target.core.lower()[:-2]
         elif target.core.lower().endswith("f"):
             self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-1])
             self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-1])
-        elif target.core.lower().endswith("ns"):
-            self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-3])
-            self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-3])
-        else:
+            self.SHEBANG += " -mcpu=%s" % target.core.lower()[:-1]
+        elif target.core.startswith("Cortex-M33"):
+            self.flags['common'].append("-mcpu=cortex-m33+nodsp")
+            self.flags['common'].append("-mfpu=none")
+            self.flags['ld'].append("--cpu=Cortex-M33.no_dsp.no_fp")
+        elif not target.core.startswith("Cortex-M23"):
             self.flags['common'].append("-mcpu=%s" % target.core.lower())
             self.flags['ld'].append("--cpu=%s" % target.core.lower())
+            self.SHEBANG += " -mcpu=%s" % target.core.lower()
 
         if target.core == "Cortex-M4F":
             self.flags['common'].append("-mfpu=fpv4-sp-d16")
@@ -331,11 +413,21 @@
             self.flags['common'].append("-mfloat-abi=softfp")
         elif target.core.startswith("Cortex-M23"):
             self.flags['common'].append("-march=armv8-m.base")
-        elif target.core.startswith("Cortex-M33"):
-            self.flags['common'].append("-march=armv8-m.main")
 
         if target.core == "Cortex-M23" or target.core == "Cortex-M33":
-            self.flags['common'].append("-mcmse")
+            self.flags['cxx'].append("-mcmse")
+            self.flags['c'].append("-mcmse")
+
+        # Create Secure library
+        if ((target.core == "Cortex-M23" or self.target.core == "Cortex-M33") and
+            kwargs.get('build_dir', False)):
+            build_dir = kwargs['build_dir']
+            secure_file = join(build_dir, "cmse_lib.o")
+            self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file]
+        # Add linking time preprocessor macro __DOMAIN_NS
+        if target.core == "Cortex-M23-NS" or self.target.core == "Cortex-M33-NS":
+            define_string = self.make_ld_define("__DOMAIN_NS", "0x1")
+            self.flags["ld"].append(define_string)
 
         asm_cpu = {
             "Cortex-M0+": "Cortex-M0",
@@ -345,7 +437,10 @@
             "Cortex-M23-NS": "Cortex-M23",
             "Cortex-M33-NS": "Cortex-M33" }.get(target.core, target.core)
 
-        self.flags['asm'].append("--cpu=%s" % asm_cpu)
+        if target.core.startswith("Cortex-M33"):
+            self.flags['asm'].append("--cpu=Cortex-M33.no_dsp.no_fp")
+        else :
+            self.flags['asm'].append("--cpu=%s" % asm_cpu)
 
         self.cc = ([join(TOOLCHAIN_PATHS["ARMC6"], "armclang")] +
                    self.flags['common'] + self.flags['c'])
@@ -356,6 +451,8 @@
         self.ar = [join(TOOLCHAIN_PATHS["ARMC6"], "armar")]
         self.elf2bin = join(TOOLCHAIN_PATHS["ARMC6"], "fromelf")
 
+    def _get_toolchain_labels(self):
+        return ["ARM", "ARM_STD", "ARMC6"]
 
     def parse_dependencies(self, dep_path):
         return mbedToolchain.parse_dependencies(self, dep_path)
--- a/toolchains/gcc.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/toolchains/gcc.py	Tue Sep 25 13:43:09 2018 -0500
@@ -16,24 +16,27 @@
 """
 import re
 from os.path import join, basename, splitext, dirname, exists
+from os import getenv
 from distutils.spawn import find_executable
+from distutils.version import LooseVersion
 
 from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS
 from tools.hooks import hook_tool
+from tools.utils import run_cmd, NotSupportedException
 
 class GCC(mbedToolchain):
     LINKER_EXT = '.ld'
     LIBRARY_EXT = '.a'
 
     STD_LIB_NAME = "lib%s.a"
-    DIAGNOSTIC_PATTERN = re.compile('((?P<file>[^:]+):(?P<line>\d+):)(\d+:)? (?P<severity>warning|[eE]rror|fatal error): (?P<message>.+)')
-    INDEX_PATTERN  = re.compile('(?P<col>\s*)\^')
+    DIAGNOSTIC_PATTERN = re.compile('((?P<file>[^:]+):(?P<line>\d+):)(?P<col>\d+):? (?P<severity>warning|[eE]rror|fatal error): (?P<message>.+)')
 
-    def __init__(self, target,  notify=None, macros=None,
-                 silent=False, extra_verbose=False, build_profile=None,
+    GCC_RANGE = (LooseVersion("6.0.0"), LooseVersion("7.0.0"))
+    GCC_VERSION_RE = re.compile(b"\d+\.\d+\.\d+")
+
+    def __init__(self, target,  notify=None, macros=None, build_profile=None,
                  build_dir=None):
-        mbedToolchain.__init__(self, target, notify, macros, silent,
-                               extra_verbose=extra_verbose,
+        mbedToolchain.__init__(self, target, notify, macros,
                                build_profile=build_profile, build_dir=build_dir)
 
         tool_path=TOOLCHAIN_PATHS['GCC_ARM']
@@ -49,21 +52,20 @@
             self.flags["ld"].append("--specs=nano.specs")
 
         if target.core == "Cortex-M0+":
-            cpu = "cortex-m0plus"
-        elif target.core == "Cortex-M4F":
-            cpu = "cortex-m4"
-        elif target.core == "Cortex-M7F":
-            cpu = "cortex-m7"
-        elif target.core == "Cortex-M7FD":
-            cpu = "cortex-m7"
-        elif target.core == "Cortex-M23-NS":
-            cpu = "cortex-m23"
-        elif target.core == "Cortex-M33-NS":
-            cpu = "cortex-m33"
+            self.cpu = ["-mcpu=cortex-m0plus"]
+        elif target.core.startswith("Cortex-M4"):
+            self.cpu = ["-mcpu=cortex-m4"]
+        elif target.core.startswith("Cortex-M7"):
+            self.cpu = ["-mcpu=cortex-m7"]
+        elif target.core.startswith("Cortex-M23"):
+            self.cpu = ["-mcpu=cortex-m23"]
+        elif target.core.startswith("Cortex-M33F"):
+            self.cpu = ["-mcpu=cortex-m33"]
+        elif target.core.startswith("Cortex-M33"):
+            self.cpu = ["-march=armv8-m.main"]
         else:
-            cpu = target.core.lower()
+            self.cpu = ["-mcpu={}".format(target.core.lower())]
 
-        self.cpu = ["-mcpu=%s" % cpu]
         if target.core.startswith("Cortex-M"):
             self.cpu.append("-mthumb")
 
@@ -86,13 +88,16 @@
             self.cpu.append("-mfloat-abi=hard")
             self.cpu.append("-mno-unaligned-access")
 
-        if target.core.startswith("Cortex-M23"):
-            self.cpu.append("-march=armv8-m.base")
-        elif target.core.startswith("Cortex-M33"):
-            self.cpu.append("-march=armv8-m.main")
-
-        if target.core == "Cortex-M23" or target.core == "Cortex-M33":
+        if ((target.core.startswith("Cortex-M23") or
+             target.core.startswith("Cortex-M33")) and
+            not target.core.endswith("-NS")):
             self.cpu.append("-mcmse")
+            self.flags["ld"].extend([
+                "-Wl,--cmse-implib",
+                "-Wl,--out-implib=%s" % join(build_dir, "cmse_lib.o")
+            ])
+        elif target.core == "Cortex-M23-NS" or target.core == "Cortex-M33-NS":
+             self.flags["ld"].append("-D__DOMAIN_NS=1")
 
         self.flags["common"] += self.cpu
 
@@ -112,6 +117,32 @@
         self.ar = join(tool_path, "arm-none-eabi-ar")
         self.elf2bin = join(tool_path, "arm-none-eabi-objcopy")
 
+        self.use_distcc = (bool(getenv("DISTCC_POTENTIAL_HOSTS", False))
+                           and not getenv("MBED_DISABLE_DISTCC", False))
+
+    def version_check(self):
+        stdout, _, retcode = run_cmd([self.cc[0], "--version"], redirect=True)
+        msg = None
+        match = self.GCC_VERSION_RE.search(stdout)
+        found_version = LooseVersion(match.group(0).decode('utf-8')) if match else None
+        min_ver, max_ver = self.GCC_RANGE
+        if found_version and (found_version < min_ver or found_version >= max_ver):
+            msg = ("Compiler version mismatch: Have {}; "
+                   "expected version >= {} and < {}"
+                   .format(found_version, min_ver, max_ver))
+        elif not match:
+            msg = ("Compiler version mismatch: Could not detect version; "
+                   "expected version >= {} and < {}"
+                   .format(min_ver, max_ver))
+        if msg:
+            self.notify.cc_info({
+                "message": msg,
+                "file": "",
+                "line": "",
+                "col": "",
+                "severity": "ERROR",
+            })
+
     def is_not_supported_error(self, output):
         return "error: #error [NOT_SUPPORTED]" in output
 
@@ -122,30 +153,21 @@
             match = self.DIAGNOSTIC_PATTERN.search(line)
             if match is not None:
                 if msg is not None:
-                    self.cc_info(msg)
+                    self.notify.cc_info(msg)
                     msg = None
                 msg = {
                     'severity': match.group('severity').lower(),
                     'file': match.group('file'),
                     'line': match.group('line'),
-                    'col': 0,
+                    'col': match.group('col'),
                     'message': match.group('message'),
                     'text': '',
                     'target_name': self.target.name,
                     'toolchain_name': self.name
                 }
-            elif msg is not None:
-                # Determine the warning/error column by calculating the ^ position
-                match = self.INDEX_PATTERN.match(line)
-                if match is not None:
-                    msg['col'] = len(match.group('col'))
-                    self.cc_info(msg)
-                    msg = None
-                else:
-                    msg['text'] += line+"\n"
 
         if msg is not None:
-            self.cc_info(msg)
+            self.notify.cc_info(msg)
 
     def get_dep_option(self, object):
         base, _ = splitext(object)
@@ -162,10 +184,9 @@
         else:
             opts += ["-I%s" % i for i in includes]
 
-        if not for_asm:
-            config_header = self.get_config_header()
-            if config_header is not None:
-                opts = opts + self.get_config_option(config_header)
+        config_header = self.get_config_header()
+        if config_header is not None:
+            opts = opts + self.get_config_option(config_header)
         return opts
 
     @hook_tool
@@ -190,6 +211,8 @@
 
         # Call cmdline hook
         cmd = self.hook.get_cmdline_compiler(cmd)
+        if self.use_distcc:
+            cmd = ["distcc"] + cmd
 
         return [cmd]
 
@@ -212,13 +235,14 @@
             preproc_output = join(dirname(output), ".link_script.ld")
             cmd = (self.preproc + [mem_map] + self.ld[1:] +
                    [ "-o", preproc_output])
-            self.cc_verbose("Preproc: %s" % ' '.join(cmd))
+            self.notify.cc_verbose("Preproc: %s" % ' '.join(cmd))
             self.default_cmd(cmd)
             mem_map = preproc_output
 
         # Build linker command
         map_file = splitext(output)[0] + ".map"
         cmd = self.ld + ["-o", output, "-Wl,-Map=%s" % map_file] + objects + ["-Wl,--start-group"] + libs + ["-Wl,--end-group"]
+
         if mem_map:
             cmd.extend(['-T', mem_map])
 
@@ -236,7 +260,7 @@
             cmd = [cmd_linker, "@%s" % link_files]
 
         # Exec command
-        self.cc_verbose("Link: %s" % ' '.join(cmd))
+        self.notify.cc_verbose("Link: %s" % ' '.join(cmd))
         self.default_cmd(cmd)
 
     @hook_tool
@@ -260,7 +284,7 @@
         cmd = self.hook.get_cmdline_binary(cmd)
 
         # Exec command
-        self.cc_verbose("FromELF: %s" % ' '.join(cmd))
+        self.notify.cc_verbose("FromELF: %s" % ' '.join(cmd))
         self.default_cmd(cmd)
 
     @staticmethod
@@ -269,7 +293,7 @@
 
     @staticmethod
     def make_ld_define(name, value):
-        return "-D%s=0x%x" % (name, value)
+        return "-D%s=%s" % (name, value)
 
     @staticmethod
     def redirect_symbol(source, sync, build_dir):
--- a/toolchains/iar.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/toolchains/iar.py	Tue Sep 25 13:43:09 2018 -0500
@@ -17,9 +17,11 @@
 import re
 from os import remove
 from os.path import join, splitext, exists
+from distutils.version import LooseVersion
 
 from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS
 from tools.hooks import hook_tool
+from tools.utils import run_cmd, NotSupportedException
 
 class IAR(mbedToolchain):
     LIBRARY_EXT = '.a'
@@ -28,6 +30,8 @@
 
     DIAGNOSTIC_PATTERN = re.compile('"(?P<file>[^"]+)",(?P<line>[\d]+)\s+(?P<severity>Warning|Error|Fatal error)(?P<message>.+)')
     INDEX_PATTERN  = re.compile('(?P<col>\s*)\^')
+    IAR_VERSION_RE = re.compile(b"IAR ANSI C/C\+\+ Compiler V(\d+\.\d+)")
+    IAR_VERSION = LooseVersion("7.80")
 
     @staticmethod
     def check_executable():
@@ -36,12 +40,9 @@
         Returns False otherwise."""
         return mbedToolchain.generic_check_executable("IAR", 'iccarm', 2, "bin")
 
-    def __init__(self, target, notify=None, macros=None,
-                 silent=False, extra_verbose=False, build_profile=None,
+    def __init__(self, target, notify=None, macros=None, build_profile=None,
                  build_dir=None):
-        mbedToolchain.__init__(self, target, notify, macros, silent,
-                               build_dir=build_dir,
-                               extra_verbose=extra_verbose,
+        mbedToolchain.__init__(self, target, notify, macros, build_dir=build_dir,
                                build_profile=build_profile)
         if target.core == "Cortex-M7F" or target.core == "Cortex-M7FD":
             cpuchoice = "Cortex-M7"
@@ -74,6 +75,12 @@
             c_flags_cmd.append("--fpu=VFPv5_sp")
         elif target.core == "Cortex-M23" or target.core == "Cortex-M33":
             self.flags["asm"] += ["--cmse"]
+            self.flags["common"] += ["--cmse"]
+
+        # Create Secure library
+        if target.core == "Cortex-M23" or self.target.core == "Cortex-M33":
+            secure_file = join(build_dir, "cmse_lib.o")
+            self.flags["ld"] += ["--import_cmse_lib_out=%s" % secure_file]
 
         IAR_BIN = join(TOOLCHAIN_PATHS['IAR'], "bin")
         main_cc = join(IAR_BIN, "iccarm")
@@ -88,6 +95,27 @@
         self.ar = join(IAR_BIN, "iarchive")
         self.elf2bin = join(IAR_BIN, "ielftool")
 
+    def version_check(self):
+        stdout, _, retcode = run_cmd([self.cc[0], "--version"], redirect=True)
+        msg = None
+        match = self.IAR_VERSION_RE.search(stdout)
+        found_version = match.group(1).decode("utf-8") if match else None
+        if found_version and LooseVersion(found_version) != self.IAR_VERSION:
+            msg = "Compiler version mismatch: Have {}; expected {}".format(
+                found_version, self.IAR_VERSION)
+        elif not match or len(match.groups()) != 1:
+            msg = ("Compiler version mismatch: Could Not detect compiler "
+                   "version; expected {}".format(self.IAR_VERSION))
+        if msg:
+            self.notify.cc_info({
+                "message": msg,
+                "file": "",
+                "line": "",
+                "col": "",
+                "severity": "ERROR",
+            })
+
+
     def parse_dependencies(self, dep_path):
         return [(self.CHROOT if self.CHROOT else '')+path.strip() for path in open(dep_path).readlines()
                 if (path and not path.isspace())]
@@ -98,7 +126,7 @@
             match = IAR.DIAGNOSTIC_PATTERN.match(line)
             if match is not None:
                 if msg is not None:
-                    self.cc_info(msg)
+                    self.notify.cc_info(msg)
                     msg = None
                 msg = {
                     'severity': match.group('severity').lower(),
@@ -115,13 +143,13 @@
                 match = IAR.INDEX_PATTERN.match(line)
                 if match is not None:
                     msg['col'] = len(match.group('col'))
-                    self.cc_info(msg)
+                    self.notify.cc_info(msg)
                     msg = None
                 else:
                     msg['text'] += line+"\n"
 
         if msg is not None:
-            self.cc_info(msg)
+            self.notify.cc_info(msg)
 
     def get_dep_option(self, object):
         base, _ = splitext(object)
@@ -137,17 +165,26 @@
 
     def get_compile_options(self, defines, includes, for_asm=False):
         opts = ['-D%s' % d for d in defines]
-        if for_asm :
+        if for_asm:
+            config_macros = self.config.get_config_data_macros()
+            macros_cmd = ['"-D%s"' % d.replace('"', '').replace('//','/\/') for d in config_macros]
+            if self.RESPONSE_FILES:
+                via_file = self.make_option_file(
+                    macros_cmd, "asm_macros_{}.xcl")
+                opts += ['-f', via_file]
+            else:
+                opts += macros_cmd
             return opts
-        if self.RESPONSE_FILES:
-            opts += ['-f', self.get_inc_file(includes)]
         else:
-            opts += ["-I%s" % i for i in includes]
+            if self.RESPONSE_FILES:
+                opts += ['-f', self.get_inc_file(includes)]
+            else:
+                opts += ["-I%s" % i for i in includes]
+            config_header = self.get_config_header()
+            if config_header is not None:
+                opts = opts + self.get_config_option(config_header)
 
-        config_header = self.get_config_header()
-        if config_header is not None:
-            opts = opts + self.get_config_option(config_header)
-        return opts
+            return opts
 
     @hook_tool
     def assemble(self, source, object, includes):
@@ -201,7 +238,7 @@
             cmd = [cmd_linker, '-f', link_files]
 
         # Exec command
-        self.cc_verbose("Link: %s" % ' '.join(cmd))
+        self.notify.cc_verbose("Link: %s" % ' '.join(cmd))
         self.default_cmd(cmd)
 
     @hook_tool
@@ -227,7 +264,7 @@
         cmd = self.hook.get_cmdline_binary(cmd)
 
         # Exec command
-        self.cc_verbose("FromELF: %s" % ' '.join(cmd))
+        self.notify.cc_verbose("FromELF: %s" % ' '.join(cmd))
         self.default_cmd(cmd)
 
     @staticmethod
@@ -236,7 +273,7 @@
 
     @staticmethod
     def make_ld_define(name, value):
-        return "--config_def %s=0x%x" % (name, value)
+        return "--config_def %s=%s" % (name, value)
 
     @staticmethod
     def redirect_symbol(source, sync, build_dir):
--- a/upload_results.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/upload_results.py	Tue Sep 25 13:43:09 2018 -0500
@@ -181,10 +181,10 @@
     ts_data = prep_ts_data()
     ts_data['projectRuns'] = []
 
-    for hostOs_name, hostOs in project_run_data['projectRuns'].iteritems():
-        for platform_name, platform in hostOs.iteritems():
-            for toolchain_name, toolchain in platform.iteritems():
-                for project_name, project in toolchain.iteritems():
+    for hostOs_name, hostOs in project_run_data['projectRuns'].items():
+        for platform_name, platform in hostOs.items():
+            for toolchain_name, toolchain in platform.items():
+                for project_name, project in toolchain.items():
                     if current_limit_count >= limit:
                         finish_ts_data(ts_data, project_run_data)
                         all_ts_data.append(ts_data)
--- a/utils.py	Mon Nov 06 13:17:14 2017 -0600
+++ b/utils.py	Tue Sep 25 13:43:09 2018 -0500
@@ -14,6 +14,7 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+from __future__ import print_function, division, absolute_import
 import sys
 import inspect
 import os
@@ -30,6 +31,11 @@
 import logging
 from intelhex import IntelHex
 
+try:
+    unicode
+except NameError:
+    unicode = str
+
 def remove_if_in(lst, thing):
     if thing in lst:
         lst.remove(thing)
@@ -66,14 +72,14 @@
     """A wrapper to run a command as a blocking job"""
     text = command if shell else ' '.join(command)
     if verbose:
-        print text
+        print(text)
     return_code = call(command, shell=shell, cwd=cwd)
     if check and return_code != 0:
         raise Exception('ERROR %d: "%s"' % (return_code, text))
 
 
 def run_cmd(command, work_dir=None, chroot=None, redirect=False):
-    """Run a command in the forground
+    """Run a command in the foreground
 
     Positional arguments:
     command - the command to run
@@ -100,7 +106,7 @@
                         stderr=STDOUT if redirect else PIPE, cwd=work_dir)
         _stdout, _stderr = process.communicate()
     except OSError:
-        print "[OS ERROR] Command: "+(' '.join(command))
+        print("[OS ERROR] Command: "+(' '.join(command)))
         raise
 
     return _stdout, _stderr, process.returncode
@@ -173,6 +179,27 @@
         makedirs(path)
 
 
+def write_json_to_file(json_data, file_name):
+    """
+    Write json content in file
+    :param json_data:
+    :param file_name:
+    :return:
+    """
+    # Create the target dir for file if necessary
+    test_spec_dir = os.path.dirname(file_name)
+
+    if test_spec_dir:
+        mkdir(test_spec_dir)
+
+    try:
+        with open(file_name, 'w') as f:
+            f.write(json.dumps(json_data, indent=2))
+    except IOError as e:
+        print("[ERROR] Error writing test spec to file")
+        print(e)
+
+
 def copy_file(src, dst):
     """ Implement the behaviour of "shutil.copy(src, dst)" without copying the
     permissions (this was causing errors with directories mounted with samba)
@@ -199,7 +226,7 @@
     for element in listdir(directory):
         to_remove = join(directory, element)
         if not isdir(to_remove):
-            remove(file)
+            remove(to_remove)
 
 
 def get_caller_name(steps=2):
@@ -318,38 +345,19 @@
             except ImportError as exc:
                 not_installed_modules.append(module_name)
                 if verbose:
-                    print "Error: %s" % exc
+                    print("Error: %s" % exc)
 
     if verbose:
         if not_installed_modules:
-            print ("Warning: Module(s) %s not installed. Please install " + \
-                   "required module(s) before using this script.")\
-                % (', '.join(not_installed_modules))
+            print("Warning: Module(s) %s not installed. Please install "
+                  "required module(s) before using this script."
+                  % (', '.join(not_installed_modules)))
 
     if not_installed_modules:
         return False
     else:
         return True
 
-def dict_to_ascii(dictionary):
-    """ Utility function: traverse a dictionary and change all the strings in
-    the dictionary to ASCII from Unicode. Useful when reading ASCII JSON data,
-    because the JSON decoder always returns Unicode string. Based on
-    http://stackoverflow.com/a/13105359
-
-    Positional arguments:
-    dictionary - The dict that contains some Unicode that should be ASCII
-    """
-    if isinstance(dictionary, dict):
-        return OrderedDict([(dict_to_ascii(key), dict_to_ascii(value))
-                            for key, value in dictionary.iteritems()])
-    elif isinstance(dictionary, list):
-        return [dict_to_ascii(element) for element in dictionary]
-    elif isinstance(dictionary, unicode):
-        return dictionary.encode('ascii')
-    else:
-        return dictionary
-
 def json_file_to_dict(fname):
     """ Read a JSON file and return its Python representation, transforming all
     the strings from Unicode to ASCII. The order of keys in the JSON file is
@@ -360,8 +368,8 @@
     """
     try:
         with open(fname, "r") as file_obj:
-            return dict_to_ascii(json.load(file_obj,
-                                           object_pairs_hook=OrderedDict))
+            return json.loads(file_obj.read().encode('ascii', 'ignore'),
+                              object_pairs_hook=OrderedDict)
     except (ValueError, IOError):
         sys.stderr.write("Error parsing '%s':\n" % fname)
         raise
@@ -375,6 +383,8 @@
             the string, or the hyphens/underscores do not match the expected
             style of the argument.
             """
+            if not isinstance(string, unicode):
+                string = string.decode()
             if prefer_hyphen:
                 newstring = casedness(string).replace("_", "-")
             else:
@@ -393,10 +403,10 @@
     return middle
 
 # short cuts for the argparse_type versions
-argparse_uppercase_type = argparse_type(str.upper, False)
-argparse_lowercase_type = argparse_type(str.lower, False)
-argparse_uppercase_hyphen_type = argparse_type(str.upper, True)
-argparse_lowercase_hyphen_type = argparse_type(str.lower, True)
+argparse_uppercase_type = argparse_type(unicode.upper, False)
+argparse_lowercase_type = argparse_type(unicode.lower, False)
+argparse_uppercase_hyphen_type = argparse_type(unicode.upper, True)
+argparse_lowercase_hyphen_type = argparse_type(unicode.lower, True)
 
 def argparse_force_type(case):
     """ validate that an argument passed in (as string) is a member of the list
@@ -404,8 +414,12 @@
     """
     def middle(lst, type_name):
         """ The parser type generator"""
+        if not isinstance(lst[0], unicode):
+            lst = [o.decode() for o in lst]
         def parse_type(string):
             """ The parser type"""
+            if not isinstance(string, unicode):
+                string = string.decode()
             for option in lst:
                 if case(string) == case(option):
                     return option
@@ -416,8 +430,8 @@
     return middle
 
 # these two types convert the case of their arguments _before_ validation
-argparse_force_uppercase_type = argparse_force_type(str.upper)
-argparse_force_lowercase_type = argparse_force_type(str.lower)
+argparse_force_uppercase_type = argparse_force_type(unicode.upper)
+argparse_force_lowercase_type = argparse_force_type(unicode.lower)
 
 def argparse_many(func):
     """ An argument parser combinator that takes in an argument parser and
@@ -529,3 +543,11 @@
         raise ToolException("File %s does not have a known binary file type"
                             % filename)
     return ih
+
+
+def integer(maybe_string, base):
+    """Make an integer of a number or a string"""
+    if isinstance(maybe_string, int):
+        return maybe_string
+    else:
+        return int(maybe_string, base)