Diff: export/iar/iar_definitions.json

Revision:

35:da9c89f8be7d

Parent:

31:8ea194f6145b

Child:

36:96847d42f010

diff -r 42f20e28adf5 -r da9c89f8be7d export/iar/iar_definitions.json
--- a/export/iar/iar_definitions.json	Mon Feb 13 09:29:13 2017 -0600
+++ b/export/iar/iar_definitions.json	Wed Feb 15 13:53:18 2017 -0600
@@ -5,6 +5,9 @@
     "LPC11U24FBD48/401": {
         "OGChipSelectEditMenu": "LPC11U24FBD64_401\tNXP LPC11U24FBD64_401"
     },
+    "STM32F207ZG": {
+         "OGChipSelectEditMenu": "STM32F207ZG\tST STM32F207ZG"
+    },
     "STM32F334R8": {
         "OGChipSelectEditMenu": "STM32F334x8\tST STM32F334x8"
     },
@@ -133,20 +136,27 @@
     "STM32F091RC": {
         "OGChipSelectEditMenu": "STM32F091RC\tST STM32F091RC"
     },
-    "r7s721001": {
+    "RZ_A1H": {
         "OGChipSelectEditMenu": "R7S721001\tRenesas R7S721001",
         "CoreVariant": 37,
         "GFPUCoreSlave": 37,
         "GBECoreSlave": 37,
         "NEON":1
     },
+    "VK_RZ_A1H": {
+        "OGChipSelectEditMenu": "R7S721000\tRenesas R7S721000",
+        "CoreVariant": 37,
+        "GFPUCoreSlave": 37,
+        "GBECoreSlave": 37,
+        "NEON":1
+    },
     "MKL05Z32xxx4": {
         "OGChipSelectEditMenu": "MKL05Z32xxx4\tFreescale MKL05Z32xxx4"
     },
     "STM32F031K6": {
         "OGChipSelectEditMenu": "STM32F031x6\tST STM32F031x6"
     },
-    "max326000x85": {
+    "MAX32600MBED": {
         "OGChipSelectEditMenu": "MAX32600x85\tMaxim MAX32600x85"
     },
     "STM32F407VG": {