Anasse Abdoul / Mbed 2 deprecated Test_MPU6050

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Dependencies:   mbed

mbed-rtos/rtx/TARGET_ARM7/HAL_CM.c@0:a59a3d743804, 2022-03-31 (annotated)

Committer:
anasse
Date:
Thu Mar 31 07:43:50 2022 +0000
Revision:
0:a59a3d743804
vers0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
anasse 0:a59a3d743804 1 /*----------------------------------------------------------------------------
anasse 0:a59a3d743804 2 * RL-ARM - RTX
anasse 0:a59a3d743804 3 *----------------------------------------------------------------------------
anasse 0:a59a3d743804 4 * Name: HAL_CM.C
anasse 0:a59a3d743804 5 * Purpose: Hardware Abstraction Layer for ARM7TDMI
anasse 0:a59a3d743804 6 * Rev.: V1.0
anasse 0:a59a3d743804 7 *----------------------------------------------------------------------------
anasse 0:a59a3d743804 8 *
anasse 0:a59a3d743804 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
anasse 0:a59a3d743804 10 * All rights reserved.
anasse 0:a59a3d743804 11 * Redistribution and use in source and binary forms, with or without
anasse 0:a59a3d743804 12 * modification, are permitted provided that the following conditions are met:
anasse 0:a59a3d743804 13 * - Redistributions of source code must retain the above copyright
anasse 0:a59a3d743804 14 * notice, this list of conditions and the following disclaimer.
anasse 0:a59a3d743804 15 * - Redistributions in binary form must reproduce the above copyright
anasse 0:a59a3d743804 16 * notice, this list of conditions and the following disclaimer in the
anasse 0:a59a3d743804 17 * documentation and/or other materials provided with the distribution.
anasse 0:a59a3d743804 18 * - Neither the name of ARM nor the names of its contributors may be used
anasse 0:a59a3d743804 19 * to endorse or promote products derived from this software without
anasse 0:a59a3d743804 20 * specific prior written permission.
anasse 0:a59a3d743804 21 *
anasse 0:a59a3d743804 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
anasse 0:a59a3d743804 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
anasse 0:a59a3d743804 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
anasse 0:a59a3d743804 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
anasse 0:a59a3d743804 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
anasse 0:a59a3d743804 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
anasse 0:a59a3d743804 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
anasse 0:a59a3d743804 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
anasse 0:a59a3d743804 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
anasse 0:a59a3d743804 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
anasse 0:a59a3d743804 32 * POSSIBILITY OF SUCH DAMAGE.
anasse 0:a59a3d743804 33 *---------------------------------------------------------------------------*/
anasse 0:a59a3d743804 34
anasse 0:a59a3d743804 35 #include "rt_TypeDef.h"
anasse 0:a59a3d743804 36 #include "RTX_Conf.h"
anasse 0:a59a3d743804 37 #include "rt_HAL_CM.h"
anasse 0:a59a3d743804 38
anasse 0:a59a3d743804 39
anasse 0:a59a3d743804 40 /*----------------------------------------------------------------------------
anasse 0:a59a3d743804 41 * Global Variables
anasse 0:a59a3d743804 42 *---------------------------------------------------------------------------*/
anasse 0:a59a3d743804 43
anasse 0:a59a3d743804 44 #ifdef DBG_MSG
anasse 0:a59a3d743804 45 BIT dbg_msg;
anasse 0:a59a3d743804 46 #endif
anasse 0:a59a3d743804 47
anasse 0:a59a3d743804 48 /*----------------------------------------------------------------------------
anasse 0:a59a3d743804 49 * Functions
anasse 0:a59a3d743804 50 *---------------------------------------------------------------------------*/
anasse 0:a59a3d743804 51
anasse 0:a59a3d743804 52
anasse 0:a59a3d743804 53 /*--------------------------- rt_init_stack ---------------------------------*/
anasse 0:a59a3d743804 54
anasse 0:a59a3d743804 55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
anasse 0:a59a3d743804 56 /* Prepare TCB and saved context for a first time start of a task. */
anasse 0:a59a3d743804 57 U32 *stk,i,size;
anasse 0:a59a3d743804 58
anasse 0:a59a3d743804 59 /* Prepare a complete interrupt frame for first task start */
anasse 0:a59a3d743804 60 size = p_TCB->priv_stack >> 2;
anasse 0:a59a3d743804 61
anasse 0:a59a3d743804 62 /* Write to the top of stack. */
anasse 0:a59a3d743804 63 stk = &p_TCB->stack[size];
anasse 0:a59a3d743804 64
anasse 0:a59a3d743804 65 /* Auto correct to 8-byte ARM stack alignment. */
anasse 0:a59a3d743804 66 if ((U32)stk & 0x04) {
anasse 0:a59a3d743804 67 stk--;
anasse 0:a59a3d743804 68 }
anasse 0:a59a3d743804 69
anasse 0:a59a3d743804 70 stk -= 16;
anasse 0:a59a3d743804 71
anasse 0:a59a3d743804 72 /* Default xPSR and initial PC */
anasse 0:a59a3d743804 73 stk[15] = (U32)task_body + 4; /* add 4 byte offset because SUB PC, LR - 4 */
anasse 0:a59a3d743804 74 stk[0] = INITIAL_xPSR;
anasse 0:a59a3d743804 75
anasse 0:a59a3d743804 76 /* Clear R0-R13/LR registers. */
anasse 0:a59a3d743804 77 for (i = 1; i < 14; i++) {
anasse 0:a59a3d743804 78 stk[i] = 0;
anasse 0:a59a3d743804 79 }
anasse 0:a59a3d743804 80
anasse 0:a59a3d743804 81 /* Assign a void pointer to R0. */
anasse 0:a59a3d743804 82 stk[TCB_STACK_R0_OFFSET_DWORDS] = (U32)p_TCB->msg;
anasse 0:a59a3d743804 83
anasse 0:a59a3d743804 84 /* Initial Task stack pointer. */
anasse 0:a59a3d743804 85 p_TCB->tsk_stack = (U32)stk;
anasse 0:a59a3d743804 86
anasse 0:a59a3d743804 87 /* Task entry point. */
anasse 0:a59a3d743804 88 p_TCB->ptask = task_body;
anasse 0:a59a3d743804 89
anasse 0:a59a3d743804 90 /* Set a magic word for checking of stack overflow.
anasse 0:a59a3d743804 91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
anasse 0:a59a3d743804 92 heap, therefore the last word of the stack is a moving target.
anasse 0:a59a3d743804 93 We want to do stack/heap collision detection instead.
anasse 0:a59a3d743804 94 */
anasse 0:a59a3d743804 95 if (p_TCB->task_id != 0x01)
anasse 0:a59a3d743804 96 p_TCB->stack[0] = MAGIC_WORD;
anasse 0:a59a3d743804 97 }
anasse 0:a59a3d743804 98
anasse 0:a59a3d743804 99
anasse 0:a59a3d743804 100 /*--------------------------- rt_ret_val ----------------------------------*/
anasse 0:a59a3d743804 101
anasse 0:a59a3d743804 102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
anasse 0:a59a3d743804 103 /* Get pointer to task return value registers (R0..R3) in Stack */
anasse 0:a59a3d743804 104
anasse 0:a59a3d743804 105 /* Stack Frame: CPSR,R0-R13,PC */
anasse 0:a59a3d743804 106 return (U32 *)(p_TCB->tsk_stack + TCB_STACK_R0_OFFSET_BYTES);
anasse 0:a59a3d743804 107 }
anasse 0:a59a3d743804 108
anasse 0:a59a3d743804 109 void rt_ret_val (P_TCB p_TCB, U32 v0) {
anasse 0:a59a3d743804 110 U32 *ret;
anasse 0:a59a3d743804 111
anasse 0:a59a3d743804 112 ret = rt_ret_regs(p_TCB);
anasse 0:a59a3d743804 113 ret[0] = v0;
anasse 0:a59a3d743804 114 }
anasse 0:a59a3d743804 115
anasse 0:a59a3d743804 116 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
anasse 0:a59a3d743804 117 U32 *ret;
anasse 0:a59a3d743804 118
anasse 0:a59a3d743804 119 ret = rt_ret_regs(p_TCB);
anasse 0:a59a3d743804 120 ret[0] = v0;
anasse 0:a59a3d743804 121 ret[1] = v1;
anasse 0:a59a3d743804 122 }
anasse 0:a59a3d743804 123
anasse 0:a59a3d743804 124
anasse 0:a59a3d743804 125 /*--------------------------- dbg_init --------------------------------------*/
anasse 0:a59a3d743804 126
anasse 0:a59a3d743804 127 #ifdef DBG_MSG
anasse 0:a59a3d743804 128 void dbg_init (void) {
anasse 0:a59a3d743804 129 if ((DEMCR & DEMCR_TRCENA) &&
anasse 0:a59a3d743804 130 (ITM_CONTROL & ITM_ITMENA) &&
anasse 0:a59a3d743804 131 (ITM_ENABLE & (1UL << 31))) {
anasse 0:a59a3d743804 132 dbg_msg = __TRUE;
anasse 0:a59a3d743804 133 }
anasse 0:a59a3d743804 134 }
anasse 0:a59a3d743804 135 #endif
anasse 0:a59a3d743804 136
anasse 0:a59a3d743804 137 /*--------------------------- dbg_task_notify -------------------------------*/
anasse 0:a59a3d743804 138
anasse 0:a59a3d743804 139 #ifdef DBG_MSG
anasse 0:a59a3d743804 140 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
anasse 0:a59a3d743804 141 while (ITM_PORT31_U32 == 0);
anasse 0:a59a3d743804 142 ITM_PORT31_U32 = (U32)p_tcb->ptask;
anasse 0:a59a3d743804 143 while (ITM_PORT31_U32 == 0);
anasse 0:a59a3d743804 144 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
anasse 0:a59a3d743804 145 }
anasse 0:a59a3d743804 146 #endif
anasse 0:a59a3d743804 147
anasse 0:a59a3d743804 148 /*--------------------------- dbg_task_switch -------------------------------*/
anasse 0:a59a3d743804 149
anasse 0:a59a3d743804 150 #ifdef DBG_MSG
anasse 0:a59a3d743804 151 void dbg_task_switch (U32 task_id) {
anasse 0:a59a3d743804 152 while (ITM_PORT31_U32 == 0);
anasse 0:a59a3d743804 153 ITM_PORT31_U8 = task_id;
anasse 0:a59a3d743804 154 }
anasse 0:a59a3d743804 155 #endif
anasse 0:a59a3d743804 156
anasse 0:a59a3d743804 157
anasse 0:a59a3d743804 158 /*----------------------------------------------------------------------------
anasse 0:a59a3d743804 159 * end of file
anasse 0:a59a3d743804 160 *---------------------------------------------------------------------------*/
anasse 0:a59a3d743804 161