Arunkumar Mourougappane / UniGraphic

UniGraphics Library Fork to support mbed os 6.3 Release for ILI9341

Dependents:   TFT_ILI9341_UniGraphic TFT_ILI9341_os6

Protocols/PAR8.cpp@1:6f267dbbafec, 2020-10-08 (annotated)

Committer:
amouroug
Date:
Thu Oct 08 17:58:07 2020 -0500
Revision:
1:6f267dbbafec
Parent:
0:bb2bda4f5846 
Updated for ThisThread::sleep_for() pnemonics, cleaned up API Libs.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
amouroug 0:bb2bda4f5846 1 /* mbed UniGraphic library - PAR8 protocol class
amouroug 0:bb2bda4f5846 2 * Copyright (c) 2015 Giuliano Dianda
amouroug 0:bb2bda4f5846 3 * Released under the MIT License: http://mbed.org/license/mit
amouroug 0:bb2bda4f5846 4 *
amouroug 0:bb2bda4f5846 5 * Derived work of:
amouroug 0:bb2bda4f5846 6 *
amouroug 0:bb2bda4f5846 7 * mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller
amouroug 0:bb2bda4f5846 8 * Copyright (c) 2013 Peter Drescher - DC2PD
amouroug 0:bb2bda4f5846 9 *
amouroug 0:bb2bda4f5846 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
amouroug 0:bb2bda4f5846 11 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
amouroug 0:bb2bda4f5846 12 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
amouroug 0:bb2bda4f5846 13 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
amouroug 0:bb2bda4f5846 14 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
amouroug 0:bb2bda4f5846 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
amouroug 0:bb2bda4f5846 16 * THE SOFTWARE.
amouroug 0:bb2bda4f5846 17 */
amouroug 0:bb2bda4f5846 18 #include "platform.h"
amouroug 0:bb2bda4f5846 19 #if DEVICE_PORTINOUT
amouroug 0:bb2bda4f5846 20
amouroug 0:bb2bda4f5846 21 #include "PAR8.h"
amouroug 0:bb2bda4f5846 22
amouroug 0:bb2bda4f5846 23 PAR8::PAR8(PortName port, PinName CS, PinName reset, PinName DC, PinName WR, PinName RD)
amouroug 0:bb2bda4f5846 24 : _port(port,0xFF), _CS(CS), _reset(reset), _DC(DC), _WR(WR), _RD(RD)
amouroug 0:bb2bda4f5846 25 {
amouroug 0:bb2bda4f5846 26 _reset = 1;
amouroug 0:bb2bda4f5846 27 _DC=1;
amouroug 0:bb2bda4f5846 28 _WR=1;
amouroug 0:bb2bda4f5846 29 _RD=1;
amouroug 0:bb2bda4f5846 30 _CS=1;
amouroug 0:bb2bda4f5846 31 _port.mode(PullNone);
amouroug 0:bb2bda4f5846 32 _port.output(); // will re-enable our GPIO port
amouroug 0:bb2bda4f5846 33 hw_reset();
amouroug 0:bb2bda4f5846 34 }
amouroug 0:bb2bda4f5846 35
amouroug 0:bb2bda4f5846 36 void PAR8::wr_cmd8(unsigned char cmd)
amouroug 0:bb2bda4f5846 37 {
amouroug 0:bb2bda4f5846 38 _DC = 0; // 0=cmd
amouroug 0:bb2bda4f5846 39 _port.write(cmd); // write 8bit
amouroug 0:bb2bda4f5846 40 _WR=0;
amouroug 0:bb2bda4f5846 41 _WR=1;
amouroug 0:bb2bda4f5846 42 _DC = 1; // 1=data next
amouroug 0:bb2bda4f5846 43 }
amouroug 0:bb2bda4f5846 44 void PAR8::wr_data8(unsigned char data)
amouroug 0:bb2bda4f5846 45 {
amouroug 0:bb2bda4f5846 46 _port.write(data); // write 8bit
amouroug 0:bb2bda4f5846 47 _WR=0;
amouroug 0:bb2bda4f5846 48 _WR=1;
amouroug 0:bb2bda4f5846 49 }
amouroug 0:bb2bda4f5846 50 void PAR8::wr_cmd16(unsigned short cmd)
amouroug 0:bb2bda4f5846 51 {
amouroug 0:bb2bda4f5846 52 _DC = 0; // 0=cmd
amouroug 0:bb2bda4f5846 53 _port.write(cmd>>8); // write 8bit
amouroug 0:bb2bda4f5846 54 _WR=0;
amouroug 0:bb2bda4f5846 55 _WR=1;
amouroug 0:bb2bda4f5846 56 _port.write(cmd&0xFF); // write 8bit
amouroug 0:bb2bda4f5846 57 _WR=0;
amouroug 0:bb2bda4f5846 58 _WR=1;
amouroug 0:bb2bda4f5846 59 _DC = 1; // 1=data next
amouroug 0:bb2bda4f5846 60 }
amouroug 0:bb2bda4f5846 61 void PAR8::wr_data16(unsigned short data)
amouroug 0:bb2bda4f5846 62 {
amouroug 0:bb2bda4f5846 63 _port.write(data>>8); // write 8bit
amouroug 0:bb2bda4f5846 64 _WR=0;
amouroug 0:bb2bda4f5846 65 _WR=1;
amouroug 0:bb2bda4f5846 66 _port.write(data&0xFF); // write 8bit
amouroug 0:bb2bda4f5846 67 _WR=0;
amouroug 0:bb2bda4f5846 68 _WR=1;
amouroug 0:bb2bda4f5846 69 }
amouroug 0:bb2bda4f5846 70 void PAR8::wr_gram(unsigned short data)
amouroug 0:bb2bda4f5846 71 {
amouroug 0:bb2bda4f5846 72 _port.write(data>>8); // write 8bit
amouroug 0:bb2bda4f5846 73 _WR=0;
amouroug 0:bb2bda4f5846 74 _WR=1;
amouroug 0:bb2bda4f5846 75 _port.write(data&0xFF); // write 8bit
amouroug 0:bb2bda4f5846 76 _WR=0;
amouroug 0:bb2bda4f5846 77 _WR=1;
amouroug 0:bb2bda4f5846 78 }
amouroug 0:bb2bda4f5846 79 void PAR8::wr_gram(unsigned short data, unsigned int count)
amouroug 0:bb2bda4f5846 80 {
amouroug 0:bb2bda4f5846 81 if((data>>8)==(data&0xFF))
amouroug 0:bb2bda4f5846 82 {
amouroug 0:bb2bda4f5846 83 count<<=1;
amouroug 0:bb2bda4f5846 84 // _port.write(data); // write 8bit
amouroug 0:bb2bda4f5846 85 while(count)
amouroug 0:bb2bda4f5846 86 {
amouroug 0:bb2bda4f5846 87 _port.write(data); // rewrite even if same data, otherwise too much fast
amouroug 0:bb2bda4f5846 88 _WR=0;
amouroug 0:bb2bda4f5846 89 _WR=1;
amouroug 0:bb2bda4f5846 90 count--;
amouroug 0:bb2bda4f5846 91 }
amouroug 0:bb2bda4f5846 92 }
amouroug 0:bb2bda4f5846 93 else
amouroug 0:bb2bda4f5846 94 {
amouroug 0:bb2bda4f5846 95 while(count)
amouroug 0:bb2bda4f5846 96 {
amouroug 0:bb2bda4f5846 97 _port.write(data>>8); // write 8bit
amouroug 0:bb2bda4f5846 98 _WR=0;
amouroug 0:bb2bda4f5846 99 _WR=1;
amouroug 0:bb2bda4f5846 100 _port.write(data&0xFF); // write 8bit
amouroug 0:bb2bda4f5846 101 _WR=0;
amouroug 0:bb2bda4f5846 102 _WR=1;
amouroug 0:bb2bda4f5846 103 count--;
amouroug 0:bb2bda4f5846 104 }
amouroug 0:bb2bda4f5846 105 }
amouroug 0:bb2bda4f5846 106 }
amouroug 0:bb2bda4f5846 107 void PAR8::wr_grambuf(unsigned short* data, unsigned int lenght)
amouroug 0:bb2bda4f5846 108 {
amouroug 0:bb2bda4f5846 109 while(lenght)
amouroug 0:bb2bda4f5846 110 {
amouroug 0:bb2bda4f5846 111 _port.write((*data)>>8); // write 8bit
amouroug 0:bb2bda4f5846 112 _WR=0;
amouroug 0:bb2bda4f5846 113 _WR=1;
amouroug 0:bb2bda4f5846 114 _port.write((*data)&0xFF); // write 8bit
amouroug 0:bb2bda4f5846 115 _WR=0;
amouroug 0:bb2bda4f5846 116 _WR=1;
amouroug 0:bb2bda4f5846 117 data++;
amouroug 0:bb2bda4f5846 118 lenght--;
amouroug 0:bb2bda4f5846 119 }
amouroug 0:bb2bda4f5846 120 }
amouroug 0:bb2bda4f5846 121 unsigned short PAR8::rd_gram(bool convert)
amouroug 0:bb2bda4f5846 122 {
amouroug 0:bb2bda4f5846 123 unsigned int r=0;
amouroug 0:bb2bda4f5846 124 _port.input();
amouroug 0:bb2bda4f5846 125
amouroug 0:bb2bda4f5846 126 _RD = 0;
amouroug 0:bb2bda4f5846 127 _RD = 0; // add wait
amouroug 0:bb2bda4f5846 128 _port.read(); //dummy read
amouroug 0:bb2bda4f5846 129 _RD = 1;
amouroug 0:bb2bda4f5846 130
amouroug 0:bb2bda4f5846 131 _RD = 0;
amouroug 0:bb2bda4f5846 132 _RD = 0; // add wait
amouroug 0:bb2bda4f5846 133 r |= _port.read();
amouroug 0:bb2bda4f5846 134 _RD = 1;
amouroug 0:bb2bda4f5846 135 r <<= 8;
amouroug 0:bb2bda4f5846 136
amouroug 0:bb2bda4f5846 137 _RD = 0;
amouroug 0:bb2bda4f5846 138 _RD = 0; // add wait
amouroug 0:bb2bda4f5846 139 r |= _port.read();
amouroug 0:bb2bda4f5846 140 _RD = 1;
amouroug 0:bb2bda4f5846 141 if(convert)
amouroug 0:bb2bda4f5846 142 {
amouroug 0:bb2bda4f5846 143 r <<= 8;
amouroug 0:bb2bda4f5846 144 _RD = 0;
amouroug 0:bb2bda4f5846 145 // _RD = 0; // add wait
amouroug 0:bb2bda4f5846 146 r |= _port.read();
amouroug 0:bb2bda4f5846 147 _RD = 1;
amouroug 0:bb2bda4f5846 148 // gram is 18bit/pixel, if you set 16bit/pixel (cmd 3A), during writing the 16bits are expanded to 18bit
amouroug 0:bb2bda4f5846 149 // during reading, you read the raw 18bit gram
amouroug 0:bb2bda4f5846 150 r = RGB24to16((r&0xFF0000)>>16, (r&0xFF00)>>8, r&0xFF);// 18bit pixel padded to 24bits, rrrrrr00_gggggg00_bbbbbb00, converted to 16bit
amouroug 0:bb2bda4f5846 151 }
amouroug 0:bb2bda4f5846 152 _port.output();
amouroug 0:bb2bda4f5846 153 return (unsigned short)r;
amouroug 0:bb2bda4f5846 154 }
amouroug 0:bb2bda4f5846 155 unsigned int PAR8::rd_reg_data32(unsigned char reg)
amouroug 0:bb2bda4f5846 156 {
amouroug 0:bb2bda4f5846 157 wr_cmd8(reg);
amouroug 0:bb2bda4f5846 158 unsigned int r=0;
amouroug 0:bb2bda4f5846 159 _port.input();
amouroug 0:bb2bda4f5846 160
amouroug 0:bb2bda4f5846 161 _RD = 0;
amouroug 0:bb2bda4f5846 162 _port.read(); //dummy read
amouroug 0:bb2bda4f5846 163 _RD = 1;
amouroug 0:bb2bda4f5846 164
amouroug 0:bb2bda4f5846 165 _RD = 0;
amouroug 0:bb2bda4f5846 166 // _RD = 0; // add wait
amouroug 0:bb2bda4f5846 167 r |= (_port.read()&0xFF);
amouroug 0:bb2bda4f5846 168 r <<= 8;
amouroug 0:bb2bda4f5846 169 _RD = 1;
amouroug 0:bb2bda4f5846 170
amouroug 0:bb2bda4f5846 171 _RD = 0;
amouroug 0:bb2bda4f5846 172 // _RD = 0; // add wait
amouroug 0:bb2bda4f5846 173 r |= (_port.read()&0xFF);
amouroug 0:bb2bda4f5846 174 r <<= 8;
amouroug 0:bb2bda4f5846 175 _RD = 1;
amouroug 0:bb2bda4f5846 176
amouroug 0:bb2bda4f5846 177 _RD = 0;
amouroug 0:bb2bda4f5846 178 // _RD = 0; // add wait
amouroug 0:bb2bda4f5846 179 r |= (_port.read()&0xFF);
amouroug 0:bb2bda4f5846 180 r <<= 8;
amouroug 0:bb2bda4f5846 181 _RD = 1;
amouroug 0:bb2bda4f5846 182
amouroug 0:bb2bda4f5846 183 _RD = 0;
amouroug 0:bb2bda4f5846 184 // _RD = 0; // add wait
amouroug 0:bb2bda4f5846 185 r |= (_port.read()&0xFF);
amouroug 0:bb2bda4f5846 186 _RD = 1;
amouroug 0:bb2bda4f5846 187
amouroug 0:bb2bda4f5846 188 _CS = 1; // force CS HIG to interupt the cmd in case was not supported
amouroug 0:bb2bda4f5846 189 _CS = 0;
amouroug 0:bb2bda4f5846 190 _port.output();
amouroug 0:bb2bda4f5846 191 return r;
amouroug 0:bb2bda4f5846 192 }
amouroug 0:bb2bda4f5846 193 // in Par mode EXTC regs (0xB0-0xFF) can be directly read
amouroug 0:bb2bda4f5846 194 unsigned int PAR8::rd_extcreg_data32(unsigned char reg, unsigned char SPIreadenablecmd)
amouroug 0:bb2bda4f5846 195 {
amouroug 0:bb2bda4f5846 196 return rd_reg_data32(reg);
amouroug 0:bb2bda4f5846 197 }
amouroug 0:bb2bda4f5846 198 // ILI932x specific
amouroug 0:bb2bda4f5846 199 void PAR8::dummyread()
amouroug 0:bb2bda4f5846 200 {
amouroug 0:bb2bda4f5846 201 _port.input();
amouroug 0:bb2bda4f5846 202 _RD=0;
amouroug 0:bb2bda4f5846 203 _RD=0; // add wait
amouroug 0:bb2bda4f5846 204 _port.read(); // dummy read
amouroug 0:bb2bda4f5846 205 _RD=1;
amouroug 0:bb2bda4f5846 206 // _port.output();
amouroug 0:bb2bda4f5846 207 }
amouroug 0:bb2bda4f5846 208 // ILI932x specific
amouroug 0:bb2bda4f5846 209 void PAR8::reg_select(unsigned char reg, bool forread)
amouroug 0:bb2bda4f5846 210 {
amouroug 0:bb2bda4f5846 211 _DC = 0;
amouroug 0:bb2bda4f5846 212 _port.write(0); // write MSB
amouroug 0:bb2bda4f5846 213 _WR=0;
amouroug 0:bb2bda4f5846 214 _WR=1;
amouroug 0:bb2bda4f5846 215 _port.write(reg); // write LSB
amouroug 0:bb2bda4f5846 216 _WR=0;
amouroug 0:bb2bda4f5846 217 _WR=1;
amouroug 0:bb2bda4f5846 218 _DC = 1; // 1=data next
amouroug 0:bb2bda4f5846 219 }
amouroug 0:bb2bda4f5846 220 // ILI932x specific
amouroug 0:bb2bda4f5846 221 void PAR8::reg_write(unsigned char reg, unsigned short data)
amouroug 0:bb2bda4f5846 222 {
amouroug 0:bb2bda4f5846 223 _DC = 0;
amouroug 0:bb2bda4f5846 224 _port.write(0); // write MSB
amouroug 0:bb2bda4f5846 225 _WR=0;
amouroug 0:bb2bda4f5846 226 _WR=1;
amouroug 0:bb2bda4f5846 227 _port.write(reg); // write MSB
amouroug 0:bb2bda4f5846 228 _WR=0;
amouroug 0:bb2bda4f5846 229 _WR=1;
amouroug 0:bb2bda4f5846 230 _DC = 1;
amouroug 0:bb2bda4f5846 231 _port.write(data>>8);
amouroug 0:bb2bda4f5846 232 _WR=0;
amouroug 0:bb2bda4f5846 233 _WR=1;
amouroug 0:bb2bda4f5846 234 _port.write(data&0xFF);
amouroug 0:bb2bda4f5846 235 _WR=0;
amouroug 0:bb2bda4f5846 236 _WR=1;
amouroug 0:bb2bda4f5846 237 }
amouroug 0:bb2bda4f5846 238 // ILI932x specific
amouroug 0:bb2bda4f5846 239 unsigned short PAR8::reg_read(unsigned char reg)
amouroug 0:bb2bda4f5846 240 {
amouroug 0:bb2bda4f5846 241 unsigned short r=0;
amouroug 0:bb2bda4f5846 242 _DC = 0;
amouroug 0:bb2bda4f5846 243 _port.write(0);
amouroug 0:bb2bda4f5846 244 _WR=0;
amouroug 0:bb2bda4f5846 245 _WR=1;
amouroug 0:bb2bda4f5846 246 _port.write(reg);
amouroug 0:bb2bda4f5846 247 _WR=0;
amouroug 0:bb2bda4f5846 248 _WR=1;
amouroug 0:bb2bda4f5846 249 _DC = 1;
amouroug 0:bb2bda4f5846 250 _port.input();
amouroug 0:bb2bda4f5846 251 _RD=0;
amouroug 0:bb2bda4f5846 252 r |= _port.read(); // read 8bit
amouroug 0:bb2bda4f5846 253 _RD=1;
amouroug 0:bb2bda4f5846 254 r <<= 8;
amouroug 0:bb2bda4f5846 255 _RD=0;
amouroug 0:bb2bda4f5846 256 r |= _port.read(); // read 8bit
amouroug 0:bb2bda4f5846 257 _RD=1;
amouroug 0:bb2bda4f5846 258 _port.output();
amouroug 0:bb2bda4f5846 259
amouroug 0:bb2bda4f5846 260 return r;
amouroug 0:bb2bda4f5846 261 }
amouroug 0:bb2bda4f5846 262 void PAR8::hw_reset()
amouroug 0:bb2bda4f5846 263 {
amouroug 1:6f267dbbafec 264 ThisThread::sleep_for(15ms);
amouroug 0:bb2bda4f5846 265 _DC = 1;
amouroug 0:bb2bda4f5846 266 _CS = 1;
amouroug 0:bb2bda4f5846 267 _WR = 1;
amouroug 0:bb2bda4f5846 268 _RD = 1;
amouroug 0:bb2bda4f5846 269 _reset = 0; // display reset
amouroug 1:6f267dbbafec 270 ThisThread::sleep_for(2ms);
amouroug 0:bb2bda4f5846 271 _reset = 1; // end reset
amouroug 1:6f267dbbafec 272 ThisThread::sleep_for(100ms);
amouroug 0:bb2bda4f5846 273 }
amouroug 0:bb2bda4f5846 274 void PAR8::BusEnable(bool enable)
amouroug 0:bb2bda4f5846 275 {
amouroug 0:bb2bda4f5846 276 _CS = enable ? 0:1;
amouroug 0:bb2bda4f5846 277 }
amouroug 0:bb2bda4f5846 278
amouroug 0:bb2bda4f5846 279 #endif