Arunkumar Mourougappane / UniGraphic

UniGraphics Library Fork to support mbed os 6.3 Release for ILI9341

Dependents:   TFT_ILI9341_UniGraphic TFT_ILI9341_os6

Protocols/SPI16.cpp@2:59188908eb60, 2020-10-08 (annotated)

Committer:
amouroug
Date:
Thu Oct 08 18:11:03 2020 -0500
Revision:
2:59188908eb60
Parent:
1:6f267dbbafec 
Added GraphicsDisplay GFX API to draw triangle.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
amouroug 0:bb2bda4f5846 1 /* mbed UniGraphic library - SPI16 protocol class
amouroug 0:bb2bda4f5846 2 * Copyright (c) 2015 Giuliano Dianda
amouroug 0:bb2bda4f5846 3 * Released under the MIT License: http://mbed.org/license/mit
amouroug 0:bb2bda4f5846 4 *
amouroug 0:bb2bda4f5846 5 * Derived work of:
amouroug 0:bb2bda4f5846 6 *
amouroug 0:bb2bda4f5846 7 * mbed library for 240*320 pixel display TFT based on ILI9341 LCD Controller
amouroug 0:bb2bda4f5846 8 * Copyright (c) 2013 Peter Drescher - DC2PD
amouroug 0:bb2bda4f5846 9 *
amouroug 0:bb2bda4f5846 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
amouroug 0:bb2bda4f5846 11 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
amouroug 0:bb2bda4f5846 12 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
amouroug 0:bb2bda4f5846 13 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
amouroug 0:bb2bda4f5846 14 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
amouroug 0:bb2bda4f5846 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
amouroug 0:bb2bda4f5846 16 * THE SOFTWARE.
amouroug 0:bb2bda4f5846 17 */
amouroug 0:bb2bda4f5846 18
amouroug 0:bb2bda4f5846 19 #include "SPI16.h"
amouroug 0:bb2bda4f5846 20
amouroug 0:bb2bda4f5846 21 SPI16::SPI16(int Hz, PinName mosi, PinName miso, PinName sclk, PinName CS, PinName reset, PinName DC)
amouroug 0:bb2bda4f5846 22 : _CS(CS), _spi(mosi, miso, sclk), _reset(reset), _DC(DC)
amouroug 0:bb2bda4f5846 23 {
amouroug 0:bb2bda4f5846 24 _reset = 1;
amouroug 0:bb2bda4f5846 25 _DC=1;
amouroug 0:bb2bda4f5846 26 _CS=1;
amouroug 0:bb2bda4f5846 27 _spi.format(16,0); // 8 bit spi mode 0
amouroug 0:bb2bda4f5846 28 // _spi.frequency(12000000); // 10 Mhz SPI clock, 12mhz for F411
amouroug 0:bb2bda4f5846 29 _spi.frequency(Hz);
amouroug 0:bb2bda4f5846 30 hw_reset();
amouroug 0:bb2bda4f5846 31 }
amouroug 0:bb2bda4f5846 32
amouroug 0:bb2bda4f5846 33 void SPI16::wr_cmd8(unsigned char cmd)
amouroug 0:bb2bda4f5846 34 {
amouroug 0:bb2bda4f5846 35 _spi.format(8,0); // it takes time, better use wr_cmd16 with NOP cmd
amouroug 0:bb2bda4f5846 36 _DC.write(0); // 0=cmd
amouroug 0:bb2bda4f5846 37 _spi.write(cmd); // write 8bit
amouroug 0:bb2bda4f5846 38 _spi.format(16,0);
amouroug 0:bb2bda4f5846 39 _DC.write(1); // 1=data next
amouroug 0:bb2bda4f5846 40 }
amouroug 0:bb2bda4f5846 41 void SPI16::wr_data8(unsigned char data)
amouroug 0:bb2bda4f5846 42 {
amouroug 0:bb2bda4f5846 43 _spi.format(8,0); // it takes time, check prev cmd parameter, in case use wr_data16 with repeated byte
amouroug 0:bb2bda4f5846 44 _spi.write(data); // write 8bit
amouroug 0:bb2bda4f5846 45 _spi.format(16,0);
amouroug 0:bb2bda4f5846 46 }
amouroug 0:bb2bda4f5846 47 void SPI16::wr_cmd16(unsigned short cmd)
amouroug 0:bb2bda4f5846 48 {
amouroug 0:bb2bda4f5846 49 _DC.write(0); // 0=cmd
amouroug 0:bb2bda4f5846 50 _spi.write(cmd); // write 16bit
amouroug 0:bb2bda4f5846 51 _DC.write(1); // 1=data next
amouroug 0:bb2bda4f5846 52 }
amouroug 0:bb2bda4f5846 53 void SPI16::wr_data16(unsigned short data)
amouroug 0:bb2bda4f5846 54 {
amouroug 0:bb2bda4f5846 55 _spi.write(data); // write 16bit
amouroug 0:bb2bda4f5846 56 }
amouroug 0:bb2bda4f5846 57 void SPI16::wr_gram(unsigned short data)
amouroug 0:bb2bda4f5846 58 {
amouroug 0:bb2bda4f5846 59 _spi.write(data); // write 16bit
amouroug 0:bb2bda4f5846 60 }
amouroug 0:bb2bda4f5846 61 void SPI16::wr_gram(unsigned short data, unsigned int count)
amouroug 0:bb2bda4f5846 62 {
amouroug 0:bb2bda4f5846 63 while(count)
amouroug 0:bb2bda4f5846 64 {
amouroug 0:bb2bda4f5846 65 _spi.write(data);
amouroug 0:bb2bda4f5846 66 count--;
amouroug 0:bb2bda4f5846 67 }
amouroug 0:bb2bda4f5846 68 }
amouroug 0:bb2bda4f5846 69 void SPI16::wr_grambuf(unsigned short* data, unsigned int lenght)
amouroug 0:bb2bda4f5846 70 {
amouroug 0:bb2bda4f5846 71 while(lenght)
amouroug 0:bb2bda4f5846 72 {
amouroug 0:bb2bda4f5846 73 _spi.write(*data);
amouroug 0:bb2bda4f5846 74 data++;
amouroug 0:bb2bda4f5846 75 lenght--;
amouroug 0:bb2bda4f5846 76 }
amouroug 0:bb2bda4f5846 77 }
amouroug 0:bb2bda4f5846 78 unsigned short SPI16::rd_gram(bool convert)
amouroug 0:bb2bda4f5846 79 {
amouroug 0:bb2bda4f5846 80 unsigned int r=0;
amouroug 0:bb2bda4f5846 81 r |= _spi.write(0); // 16bit, whole first byte is dummy, second is red
amouroug 0:bb2bda4f5846 82 r <<= 16;
amouroug 0:bb2bda4f5846 83 r |= _spi.write(0);
amouroug 0:bb2bda4f5846 84 if(convert)
amouroug 0:bb2bda4f5846 85 {
amouroug 0:bb2bda4f5846 86 // gram is 18bit/pixel, if you set 16bit/pixel (cmd 3A), during writing the 16bits are expanded to 18bit
amouroug 0:bb2bda4f5846 87 // during reading, you read the raw 18bit gram
amouroug 0:bb2bda4f5846 88 r = RGB24to16((r&0xFF0000)>>16, (r&0xFF00)>>8, r&0xFF);// 18bit pixel padded to 24bits, rrrrrr00_gggggg00_bbbbbb00, converted to 16bit
amouroug 0:bb2bda4f5846 89 }
amouroug 0:bb2bda4f5846 90 else r >>= 8;
amouroug 0:bb2bda4f5846 91 _CS = 1; // force CS HIG to interupt the "read state"
amouroug 0:bb2bda4f5846 92 _CS = 0;
amouroug 0:bb2bda4f5846 93
amouroug 0:bb2bda4f5846 94 return (unsigned short)r;
amouroug 0:bb2bda4f5846 95 }
amouroug 0:bb2bda4f5846 96 unsigned int SPI16::rd_reg_data32(unsigned char reg)
amouroug 0:bb2bda4f5846 97 {
amouroug 0:bb2bda4f5846 98 wr_cmd8(reg);
amouroug 0:bb2bda4f5846 99 unsigned int r=0;
amouroug 0:bb2bda4f5846 100
amouroug 0:bb2bda4f5846 101 r |= _spi.write(0); // we get only 15bit valid, first bit was the dummy cycle
amouroug 0:bb2bda4f5846 102 r <<= 16;
amouroug 0:bb2bda4f5846 103 r |= _spi.write(0);
amouroug 0:bb2bda4f5846 104 r <<= 1; // 32bits are aligned, now collecting bit_0
amouroug 0:bb2bda4f5846 105 r |= (_spi.write(0) >> 15);
amouroug 0:bb2bda4f5846 106 // we clocked 15 more bit so ILI waiting for 16th, we need to reset spi bus
amouroug 0:bb2bda4f5846 107 _CS = 1; // force CS HIG to interupt the cmd
amouroug 0:bb2bda4f5846 108 _CS = 0;
amouroug 0:bb2bda4f5846 109 return r;
amouroug 0:bb2bda4f5846 110 }
amouroug 0:bb2bda4f5846 111 unsigned int SPI16::rd_extcreg_data32(unsigned char reg, unsigned char SPIreadenablecmd)
amouroug 0:bb2bda4f5846 112 {
amouroug 0:bb2bda4f5846 113 unsigned int r=0;
amouroug 0:bb2bda4f5846 114 for(int regparam=1; regparam<4; regparam++) // when reading EXTC regs, first parameter is always dummy, so start with 1
amouroug 0:bb2bda4f5846 115 {
amouroug 0:bb2bda4f5846 116 wr_cmd8(SPIreadenablecmd); // spi-in enable cmd, 0xD9 (ili9341) or 0xFB (ili9488) or don't know
amouroug 0:bb2bda4f5846 117 wr_data8(0xF0|regparam); // in low nibble specify which reg parameter we want
amouroug 0:bb2bda4f5846 118 wr_cmd8(reg); // now send cmd (select register we want to read)
amouroug 0:bb2bda4f5846 119 r <<= 8;
amouroug 0:bb2bda4f5846 120 r |= (_spi.write(0) >> 8);
amouroug 0:bb2bda4f5846 121 }
amouroug 0:bb2bda4f5846 122 _CS = 1; // force CS HIG to interupt the cmd
amouroug 0:bb2bda4f5846 123 _CS = 0;
amouroug 0:bb2bda4f5846 124
amouroug 0:bb2bda4f5846 125 return r;
amouroug 0:bb2bda4f5846 126 }
amouroug 0:bb2bda4f5846 127 // ILI932x specific
amouroug 0:bb2bda4f5846 128 void SPI16::dummyread()
amouroug 0:bb2bda4f5846 129 {
amouroug 0:bb2bda4f5846 130 _spi.write(0); // dummy read
amouroug 0:bb2bda4f5846 131 }
amouroug 0:bb2bda4f5846 132 // ILI932x specific
amouroug 0:bb2bda4f5846 133 void SPI16::reg_select(unsigned char reg, bool forread)
amouroug 0:bb2bda4f5846 134 {
amouroug 0:bb2bda4f5846 135 _CS = 1; //fixme: really needed?
amouroug 0:bb2bda4f5846 136 _CS = 0; //fixme: really needed?
amouroug 0:bb2bda4f5846 137 _spi.write(0x70); // write 0070
amouroug 0:bb2bda4f5846 138 _spi.write(reg); // write 16bit
amouroug 0:bb2bda4f5846 139 _CS = 1; //fixme: really needed?
amouroug 0:bb2bda4f5846 140 _CS = 0; //fixme: really needed?
amouroug 0:bb2bda4f5846 141 if(forread) _spi.write(0x73);
amouroug 0:bb2bda4f5846 142 else _spi.write(0x72);
amouroug 0:bb2bda4f5846 143 }
amouroug 0:bb2bda4f5846 144 // ILI932x specific
amouroug 0:bb2bda4f5846 145 void SPI16::reg_write(unsigned char reg, unsigned short data)
amouroug 0:bb2bda4f5846 146 {
amouroug 0:bb2bda4f5846 147 _CS = 1; //fixme: really needed?
amouroug 0:bb2bda4f5846 148 _CS = 0; //fixme: really needed?
amouroug 0:bb2bda4f5846 149 _spi.write(0x70); // write 0070
amouroug 0:bb2bda4f5846 150 _spi.write(reg); // write 16bit
amouroug 0:bb2bda4f5846 151 _CS = 1; //fixme: really needed?
amouroug 0:bb2bda4f5846 152 _CS = 0; //fixme: really needed?
amouroug 0:bb2bda4f5846 153 _spi.write(0x72); // write 0072
amouroug 0:bb2bda4f5846 154 _spi.write(data); // write 16bit
amouroug 0:bb2bda4f5846 155 }
amouroug 0:bb2bda4f5846 156 // ILI932x specific
amouroug 0:bb2bda4f5846 157 unsigned short SPI16::reg_read(unsigned char reg)
amouroug 0:bb2bda4f5846 158 {
amouroug 0:bb2bda4f5846 159 unsigned int r=0;
amouroug 0:bb2bda4f5846 160 _CS = 1; //fixme: really needed?
amouroug 0:bb2bda4f5846 161 _CS = 0; //fixme: really needed?
amouroug 0:bb2bda4f5846 162 _spi.write(0x70); // write 0070
amouroug 0:bb2bda4f5846 163 _spi.write(reg); // write 16bit
amouroug 0:bb2bda4f5846 164 _CS = 1; //fixme: really needed?
amouroug 0:bb2bda4f5846 165 _CS = 0; //fixme: really needed?
amouroug 0:bb2bda4f5846 166 _spi.write(0x73); // write 0073
amouroug 0:bb2bda4f5846 167 r |= _spi.write(0); // read 16bit, 8bit dummy + 8bit valid
amouroug 0:bb2bda4f5846 168 r <<= 16;
amouroug 0:bb2bda4f5846 169 r |= _spi.write(0); // read 16bit
amouroug 0:bb2bda4f5846 170
amouroug 0:bb2bda4f5846 171 _CS = 1; //fixme: to resync, maybe really needed
amouroug 0:bb2bda4f5846 172 _CS = 0; //fixme: to resync, maybe really needed
amouroug 0:bb2bda4f5846 173 return (r>>8);
amouroug 0:bb2bda4f5846 174 }
amouroug 0:bb2bda4f5846 175 void SPI16::hw_reset()
amouroug 0:bb2bda4f5846 176 {
amouroug 1:6f267dbbafec 177 ThisThread::sleep_for(15ms);
amouroug 0:bb2bda4f5846 178 _DC = 1;
amouroug 0:bb2bda4f5846 179 _CS = 1;
amouroug 0:bb2bda4f5846 180 _reset = 0; // display reset
amouroug 1:6f267dbbafec 181 ThisThread::sleep_for(2ms);
amouroug 0:bb2bda4f5846 182 _reset = 1; // end reset
amouroug 1:6f267dbbafec 183 ThisThread::sleep_for(100ms);
amouroug 0:bb2bda4f5846 184 }
amouroug 0:bb2bda4f5846 185 void SPI16::BusEnable(bool enable)
amouroug 0:bb2bda4f5846 186 {
amouroug 0:bb2bda4f5846 187 _CS = enable ? 0:1;
amouroug 0:bb2bda4f5846 188 }