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Diff: targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h
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- 167:e84263d55307
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- 149:156823d33999
diff -r c97ed07ec1a8 -r e84263d55307 targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h Thu Jun 08 15:02:37 2017 +0100 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f411xe.h Wed Jun 21 17:46:44 2017 +0100 @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f411xe.h * @author MCD Application Team - * @version V2.5.0 - * @date 22-April-2016 - * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File. + * @version V2.6.1 + * @date 14-February-2017 + * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -41,7 +41,7 @@ ****************************************************************************** */ -/** @addtogroup CMSIS +/** @addtogroup CMSIS_Device * @{ */ @@ -55,7 +55,6 @@ #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ - /** @addtogroup Configuration_section_for_CMSIS * @{ @@ -75,7 +74,7 @@ /** * @} */ - + /** @addtogroup Peripheral_interrupt_number_definition * @{ */ @@ -126,14 +125,14 @@ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ @@ -152,7 +151,7 @@ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ } IRQn_Type; /** @@ -174,7 +173,7 @@ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ @@ -251,7 +250,6 @@ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; - /** * @brief External Interrupt/Event Controller */ @@ -301,13 +299,13 @@ /** * @brief System configuration controller */ - + typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; @@ -341,6 +339,7 @@ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; + /** * @brief Power Control */ @@ -388,7 +387,7 @@ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ } RCC_TypeDef; /** @@ -439,33 +438,32 @@ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; - /** * @brief SD host Interface */ typedef struct { - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ } SDIO_TypeDef; /** @@ -485,6 +483,7 @@ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; + /** * @brief TIM */ @@ -539,132 +538,121 @@ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; - - /** - * @brief __USB_OTG_Core_register + * @brief USB_OTG_Core_Registers */ typedef struct { - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ - uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ - __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ - uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ -} -USB_OTG_GlobalTypeDef; - - + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; /** - * @brief __device_Registers + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register */ typedef struct { - __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ - __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ - __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ - uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ - __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ - uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ - uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ - __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ - uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ - uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ -} -USB_OTG_DeviceTypeDef; - + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; /** - * @brief __IN_Endpoint-Specific_Register + * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ typedef struct { - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ -} -USB_OTG_INEndpointTypeDef; - + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; /** - * @brief __OUT_Endpoint-Specific_Registers + * @brief USB_OTG_Host_Mode_Register_Structures */ typedef struct { - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEndpointTypeDef; - + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; /** - * @brief __Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HostTypeDef; - - -/** - * @brief __Host_Channel_Specific_Registers + * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct { - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HostChannelTypeDef; - - -/** - * @brief Peripheral_memory_map + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ */ #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ #define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */ @@ -673,13 +661,14 @@ #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END 0x0807FFFFU /*!< FLASH end address */ +#define FLASH_END 0x0807FFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE - /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) @@ -709,7 +698,9 @@ #define USART1_BASE (APB2PERIPH_BASE + 0x1000U) #define USART6_BASE (APB2PERIPH_BASE + 0x1400U) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) +/* Legacy define */ +#define ADC_BASE ADC1_COMMON_BASE #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) @@ -749,9 +740,9 @@ #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) -/* Debug MCU registers base address */ + +/*!< Debug MCU registers base address */ #define DBGMCU_BASE 0xE0042000U - /*!< USB registers base address */ #define USB_OTG_FS_PERIPH_BASE 0x50000000U @@ -768,10 +759,13 @@ #define USB_OTG_FIFO_BASE 0x1000U #define USB_OTG_FIFO_SIZE 0x1000U +#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ */ @@ -794,11 +788,13 @@ #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +/* Legacy define */ +#define ADC ADC1_COMMON #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) @@ -832,9 +828,7 @@ #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) - #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) /** @@ -858,366 +852,557 @@ /* Analog to Digital Converter */ /* */ /******************************************************************************/ + /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */ -#define ADC_SR_EOC 0x00000002U /*!<End of conversion */ -#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */ -#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */ -#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */ -#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */ +#define ADC_SR_EOC_Pos (1U) +#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */ +#define ADC_SR_JEOC_Pos (2U) +#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */ +#define ADC_SR_OVR_Pos (5U) +#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ +#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */ /******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */ -#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */ -#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */ -#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */ -#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */ -#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */ -#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */ -#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */ -#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */ -#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */ -#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */ -#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */ -#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */ -#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */ -#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */ -#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */ -#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */ -#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_CR1_EOCIE_Pos (5U) +#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE_Pos (7U) +#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */ +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */ +#define ADC_CR1_RES_Pos (24U) +#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ +#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */ +#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ +#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ +#define ADC_CR1_OVRIE_Pos (26U) +#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ +#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */ /******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */ -#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */ -#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */ -#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */ -#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */ -#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */ -#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */ -#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */ -#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */ -#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ -#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */ -#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */ -#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */ -#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */ -#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */ -#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */ -#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */ -#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ -#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */ -#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */ -#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */ +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */ +#define ADC_CR2_DDS_Pos (9U) +#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ +#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS_Pos (10U) +#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ +#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */ +#define ADC_CR2_JEXTSEL_Pos (16U) +#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ +#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ +#define ADC_CR2_JEXTEN_Pos (20U) +#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ +#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ +#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ +#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART_Pos (22U) +#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */ +#define ADC_CR2_EXTSEL_Pos (24U) +#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ +#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ +#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ +#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ +#define ADC_CR2_EXTEN_Pos (28U) +#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ +#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ +#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ +#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ +#define ADC_CR2_SWSTART_Pos (30U) +#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */ /****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */ -#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */ -#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */ -#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */ -#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */ -#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */ -#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */ -#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */ -#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */ -#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */ -#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */ -#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */ -#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */ -#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */ -#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */ -#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */ -#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */ -#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */ -#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */ -#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */ -#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */ -#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */ -#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */ -#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */ -#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */ -#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */ -#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */ +#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP18_Pos (24U) +#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */ -#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */ -#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */ -#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */ -#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */ -#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */ -#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */ -#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */ -#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */ -#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */ -#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */ -#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */ -#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */ -#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */ -#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */ -#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */ -#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */ -#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */ -#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */ -#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */ -#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */ -#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */ -#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */ -#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */ -#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */ -#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */ -#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */ -#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */ -#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */ -#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */ +#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ +#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */ /******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */ -#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */ -#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */ -#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */ -#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */ -#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */ -#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */ -#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */ -#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */ -#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */ -#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */ -#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */ -#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */ -#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */ -#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */ -#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */ -#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */ -#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */ -#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */ -#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */ -#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */ -#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */ -#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */ -#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */ -#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */ -#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */ -#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */ -#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */ -#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */ -#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */ -#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */ -#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */ -#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */ -#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */ -#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */ -#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */ -#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */ -#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */ -#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */ -#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */ -#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */ -#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */ -#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */ -#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */ -#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */ -#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */ -#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */ -#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */ -#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */ -#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */ -#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */ -#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */ -#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */ -#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */ -#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */ -#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */ -#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */ -#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */ -#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */ -#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */ -#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */ -#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */ -#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */ -#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */ -#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */ -#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */ -#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */ -#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */ -#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */ -#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */ -#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */ -#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */ -#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */ -#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */ -#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */ -#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */ -#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */ -#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */ -#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */ -#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */ -#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */ -#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */ -#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */ -#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */ -#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */ -#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */ -#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */ -#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */ -#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */ -#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */ -#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */ -#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */ -#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */ -#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */ -#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */ -#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */ -#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */ -#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */ -#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */ -#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */ -#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */ -#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */ -#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */ /******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */ /******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */ /******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */ -#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */ +#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ +#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */ /******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */ -#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */ -#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */ -#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */ -#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */ -#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */ -#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */ -#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */ -#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */ -#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */ -#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */ -#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */ -#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */ -#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */ +#define ADC_CSR_AWD1_Pos (0U) +#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ +#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1_Pos (1U) +#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */ +#define ADC_CSR_JEOC1_Pos (2U) +#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */ +#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1_Pos (3U) +#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ +#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1_Pos (4U) +#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ +#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1_Pos (5U) +#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ +#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */ /* Legacy defines */ #define ADC_CSR_DOVR1 ADC_CSR_OVR1 -#define ADC_CSR_DOVR2 ADC_CSR_OVR2 -#define ADC_CSR_DOVR3 ADC_CSR_OVR3 /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ -#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */ -#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */ -#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */ -#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */ -#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */ -#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ -#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */ -#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */ -#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */ -#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */ -#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */ -#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ -#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */ -#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */ -#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */ -#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */ -#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */ -#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */ -#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */ +#define ADC_CCR_MULTI_Pos (0U) +#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */ +#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ +#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */ +#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */ +#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */ +#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */ +#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */ +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ +#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DDS_Pos (13U) +#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */ +#define ADC_CCR_DMA_Pos (14U) +#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ +#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */ +#define ADC_CCR_ADCPRE_Pos (16U) +#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */ +#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ +#define ADC_CCR_VBATE_Pos (22U) +#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */ +#define ADC_CCR_TSVREFE_Pos (23U) +#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */ /******************* Bit definition for ADC_CDR register ********************/ -#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */ -#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */ +#define ADC_CDR_DATA1_Pos (0U) +#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */ +#define ADC_CDR_DATA2_Pos (16U) +#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */ + +/* Legacy defines */ +#define ADC_CDR_RDATA_MST ADC_CDR_DATA1 +#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 /******************************************************************************/ /* */ @@ -1225,21 +1410,22 @@ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET 0x01U /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ + /******************************************************************************/ /* */ @@ -1247,161 +1433,386 @@ /* */ /******************************************************************************/ /******************** Bits definition for DMA_SxCR register *****************/ -#define DMA_SxCR_CHSEL 0x0E000000U -#define DMA_SxCR_CHSEL_0 0x02000000U -#define DMA_SxCR_CHSEL_1 0x04000000U -#define DMA_SxCR_CHSEL_2 0x08000000U -#define DMA_SxCR_MBURST 0x01800000U -#define DMA_SxCR_MBURST_0 0x00800000U -#define DMA_SxCR_MBURST_1 0x01000000U -#define DMA_SxCR_PBURST 0x00600000U -#define DMA_SxCR_PBURST_0 0x00200000U -#define DMA_SxCR_PBURST_1 0x00400000U -#define DMA_SxCR_CT 0x00080000U -#define DMA_SxCR_DBM 0x00040000U -#define DMA_SxCR_PL 0x00030000U -#define DMA_SxCR_PL_0 0x00010000U -#define DMA_SxCR_PL_1 0x00020000U -#define DMA_SxCR_PINCOS 0x00008000U -#define DMA_SxCR_MSIZE 0x00006000U -#define DMA_SxCR_MSIZE_0 0x00002000U -#define DMA_SxCR_MSIZE_1 0x00004000U -#define DMA_SxCR_PSIZE 0x00001800U -#define DMA_SxCR_PSIZE_0 0x00000800U -#define DMA_SxCR_PSIZE_1 0x00001000U -#define DMA_SxCR_MINC 0x00000400U -#define DMA_SxCR_PINC 0x00000200U -#define DMA_SxCR_CIRC 0x00000100U -#define DMA_SxCR_DIR 0x000000C0U -#define DMA_SxCR_DIR_0 0x00000040U -#define DMA_SxCR_DIR_1 0x00000080U -#define DMA_SxCR_PFCTRL 0x00000020U -#define DMA_SxCR_TCIE 0x00000010U -#define DMA_SxCR_HTIE 0x00000008U -#define DMA_SxCR_TEIE 0x00000004U -#define DMA_SxCR_DMEIE 0x00000002U -#define DMA_SxCR_EN 0x00000001U +#define DMA_SxCR_CHSEL_Pos (25U) +#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */ +#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk +#define DMA_SxCR_CHSEL_0 0x02000000U +#define DMA_SxCR_CHSEL_1 0x04000000U +#define DMA_SxCR_CHSEL_2 0x08000000U +#define DMA_SxCR_MBURST_Pos (23U) +#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */ +#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk +#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */ +#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */ +#define DMA_SxCR_PBURST_Pos (21U) +#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */ +#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk +#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ +#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ +#define DMA_SxCR_CT_Pos (19U) +#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ +#define DMA_SxCR_CT DMA_SxCR_CT_Msk +#define DMA_SxCR_DBM_Pos (18U) +#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */ +#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk +#define DMA_SxCR_PL_Pos (16U) +#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */ +#define DMA_SxCR_PL DMA_SxCR_PL_Msk +#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */ +#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */ +#define DMA_SxCR_PINCOS_Pos (15U) +#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */ +#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk +#define DMA_SxCR_MSIZE_Pos (13U) +#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */ +#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk +#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */ +#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */ +#define DMA_SxCR_PSIZE_Pos (11U) +#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */ +#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk +#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */ +#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */ +#define DMA_SxCR_MINC_Pos (10U) +#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */ +#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk +#define DMA_SxCR_PINC_Pos (9U) +#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */ +#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk +#define DMA_SxCR_CIRC_Pos (8U) +#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */ +#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk +#define DMA_SxCR_DIR_Pos (6U) +#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */ +#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk +#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */ +#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */ +#define DMA_SxCR_PFCTRL_Pos (5U) +#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */ +#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk +#define DMA_SxCR_TCIE_Pos (4U) +#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */ +#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk +#define DMA_SxCR_HTIE_Pos (3U) +#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */ +#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk +#define DMA_SxCR_TEIE_Pos (2U) +#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */ +#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk +#define DMA_SxCR_DMEIE_Pos (1U) +#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */ +#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk +#define DMA_SxCR_EN_Pos (0U) +#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_SxCR_EN DMA_SxCR_EN_Msk /* Legacy defines */ -#define DMA_SxCR_ACK 0x00100000U +#define DMA_SxCR_ACK_Pos (20U) +#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ +#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk /******************** Bits definition for DMA_SxCNDTR register **************/ -#define DMA_SxNDT 0x0000FFFFU -#define DMA_SxNDT_0 0x00000001U -#define DMA_SxNDT_1 0x00000002U -#define DMA_SxNDT_2 0x00000004U -#define DMA_SxNDT_3 0x00000008U -#define DMA_SxNDT_4 0x00000010U -#define DMA_SxNDT_5 0x00000020U -#define DMA_SxNDT_6 0x00000040U -#define DMA_SxNDT_7 0x00000080U -#define DMA_SxNDT_8 0x00000100U -#define DMA_SxNDT_9 0x00000200U -#define DMA_SxNDT_10 0x00000400U -#define DMA_SxNDT_11 0x00000800U -#define DMA_SxNDT_12 0x00001000U -#define DMA_SxNDT_13 0x00002000U -#define DMA_SxNDT_14 0x00004000U -#define DMA_SxNDT_15 0x00008000U +#define DMA_SxNDT_Pos (0U) +#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_SxNDT DMA_SxNDT_Msk +#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */ +#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */ +#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */ +#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */ +#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */ +#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */ +#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */ +#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */ +#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */ +#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */ +#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */ +#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */ +#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */ +#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */ +#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */ +#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */ /******************** Bits definition for DMA_SxFCR register ****************/ -#define DMA_SxFCR_FEIE 0x00000080U -#define DMA_SxFCR_FS 0x00000038U -#define DMA_SxFCR_FS_0 0x00000008U -#define DMA_SxFCR_FS_1 0x00000010U -#define DMA_SxFCR_FS_2 0x00000020U -#define DMA_SxFCR_DMDIS 0x00000004U -#define DMA_SxFCR_FTH 0x00000003U -#define DMA_SxFCR_FTH_0 0x00000001U -#define DMA_SxFCR_FTH_1 0x00000002U +#define DMA_SxFCR_FEIE_Pos (7U) +#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */ +#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk +#define DMA_SxFCR_FS_Pos (3U) +#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */ +#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk +#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */ +#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */ +#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */ +#define DMA_SxFCR_DMDIS_Pos (2U) +#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */ +#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk +#define DMA_SxFCR_FTH_Pos (0U) +#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */ +#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk +#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */ +#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */ /******************** Bits definition for DMA_LISR register *****************/ -#define DMA_LISR_TCIF3 0x08000000U -#define DMA_LISR_HTIF3 0x04000000U -#define DMA_LISR_TEIF3 0x02000000U -#define DMA_LISR_DMEIF3 0x01000000U -#define DMA_LISR_FEIF3 0x00400000U -#define DMA_LISR_TCIF2 0x00200000U -#define DMA_LISR_HTIF2 0x00100000U -#define DMA_LISR_TEIF2 0x00080000U -#define DMA_LISR_DMEIF2 0x00040000U -#define DMA_LISR_FEIF2 0x00010000U -#define DMA_LISR_TCIF1 0x00000800U -#define DMA_LISR_HTIF1 0x00000400U -#define DMA_LISR_TEIF1 0x00000200U -#define DMA_LISR_DMEIF1 0x00000100U -#define DMA_LISR_FEIF1 0x00000040U -#define DMA_LISR_TCIF0 0x00000020U -#define DMA_LISR_HTIF0 0x00000010U -#define DMA_LISR_TEIF0 0x00000008U -#define DMA_LISR_DMEIF0 0x00000004U -#define DMA_LISR_FEIF0 0x00000001U +#define DMA_LISR_TCIF3_Pos (27U) +#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */ +#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk +#define DMA_LISR_HTIF3_Pos (26U) +#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */ +#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk +#define DMA_LISR_TEIF3_Pos (25U) +#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */ +#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk +#define DMA_LISR_DMEIF3_Pos (24U) +#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */ +#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk +#define DMA_LISR_FEIF3_Pos (22U) +#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */ +#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk +#define DMA_LISR_TCIF2_Pos (21U) +#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */ +#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk +#define DMA_LISR_HTIF2_Pos (20U) +#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */ +#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk +#define DMA_LISR_TEIF2_Pos (19U) +#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */ +#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk +#define DMA_LISR_DMEIF2_Pos (18U) +#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */ +#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk +#define DMA_LISR_FEIF2_Pos (16U) +#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */ +#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk +#define DMA_LISR_TCIF1_Pos (11U) +#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */ +#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk +#define DMA_LISR_HTIF1_Pos (10U) +#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */ +#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk +#define DMA_LISR_TEIF1_Pos (9U) +#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */ +#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk +#define DMA_LISR_DMEIF1_Pos (8U) +#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */ +#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk +#define DMA_LISR_FEIF1_Pos (6U) +#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */ +#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk +#define DMA_LISR_TCIF0_Pos (5U) +#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */ +#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk +#define DMA_LISR_HTIF0_Pos (4U) +#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */ +#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk +#define DMA_LISR_TEIF0_Pos (3U) +#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */ +#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk +#define DMA_LISR_DMEIF0_Pos (2U) +#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */ +#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk +#define DMA_LISR_FEIF0_Pos (0U) +#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */ +#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /******************** Bits definition for DMA_HISR register *****************/ -#define DMA_HISR_TCIF7 0x08000000U -#define DMA_HISR_HTIF7 0x04000000U -#define DMA_HISR_TEIF7 0x02000000U -#define DMA_HISR_DMEIF7 0x01000000U -#define DMA_HISR_FEIF7 0x00400000U -#define DMA_HISR_TCIF6 0x00200000U -#define DMA_HISR_HTIF6 0x00100000U -#define DMA_HISR_TEIF6 0x00080000U -#define DMA_HISR_DMEIF6 0x00040000U -#define DMA_HISR_FEIF6 0x00010000U -#define DMA_HISR_TCIF5 0x00000800U -#define DMA_HISR_HTIF5 0x00000400U -#define DMA_HISR_TEIF5 0x00000200U -#define DMA_HISR_DMEIF5 0x00000100U -#define DMA_HISR_FEIF5 0x00000040U -#define DMA_HISR_TCIF4 0x00000020U -#define DMA_HISR_HTIF4 0x00000010U -#define DMA_HISR_TEIF4 0x00000008U -#define DMA_HISR_DMEIF4 0x00000004U -#define DMA_HISR_FEIF4 0x00000001U +#define DMA_HISR_TCIF7_Pos (27U) +#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */ +#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk +#define DMA_HISR_HTIF7_Pos (26U) +#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk +#define DMA_HISR_TEIF7_Pos (25U) +#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */ +#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk +#define DMA_HISR_DMEIF7_Pos (24U) +#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */ +#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk +#define DMA_HISR_FEIF7_Pos (22U) +#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */ +#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk +#define DMA_HISR_TCIF6_Pos (21U) +#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk +#define DMA_HISR_HTIF6_Pos (20U) +#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */ +#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk +#define DMA_HISR_TEIF6_Pos (19U) +#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */ +#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk +#define DMA_HISR_DMEIF6_Pos (18U) +#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */ +#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk +#define DMA_HISR_FEIF6_Pos (16U) +#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */ +#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk +#define DMA_HISR_TCIF5_Pos (11U) +#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ +#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk +#define DMA_HISR_HTIF5_Pos (10U) +#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */ +#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk +#define DMA_HISR_TEIF5_Pos (9U) +#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */ +#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk +#define DMA_HISR_DMEIF5_Pos (8U) +#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */ +#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk +#define DMA_HISR_FEIF5_Pos (6U) +#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */ +#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk +#define DMA_HISR_TCIF4_Pos (5U) +#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */ +#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk +#define DMA_HISR_HTIF4_Pos (4U) +#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */ +#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk +#define DMA_HISR_TEIF4_Pos (3U) +#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */ +#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk +#define DMA_HISR_DMEIF4_Pos (2U) +#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */ +#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk +#define DMA_HISR_FEIF4_Pos (0U) +#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */ +#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /******************** Bits definition for DMA_LIFCR register ****************/ -#define DMA_LIFCR_CTCIF3 0x08000000U -#define DMA_LIFCR_CHTIF3 0x04000000U -#define DMA_LIFCR_CTEIF3 0x02000000U -#define DMA_LIFCR_CDMEIF3 0x01000000U -#define DMA_LIFCR_CFEIF3 0x00400000U -#define DMA_LIFCR_CTCIF2 0x00200000U -#define DMA_LIFCR_CHTIF2 0x00100000U -#define DMA_LIFCR_CTEIF2 0x00080000U -#define DMA_LIFCR_CDMEIF2 0x00040000U -#define DMA_LIFCR_CFEIF2 0x00010000U -#define DMA_LIFCR_CTCIF1 0x00000800U -#define DMA_LIFCR_CHTIF1 0x00000400U -#define DMA_LIFCR_CTEIF1 0x00000200U -#define DMA_LIFCR_CDMEIF1 0x00000100U -#define DMA_LIFCR_CFEIF1 0x00000040U -#define DMA_LIFCR_CTCIF0 0x00000020U -#define DMA_LIFCR_CHTIF0 0x00000010U -#define DMA_LIFCR_CTEIF0 0x00000008U -#define DMA_LIFCR_CDMEIF0 0x00000004U -#define DMA_LIFCR_CFEIF0 0x00000001U +#define DMA_LIFCR_CTCIF3_Pos (27U) +#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */ +#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk +#define DMA_LIFCR_CHTIF3_Pos (26U) +#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */ +#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk +#define DMA_LIFCR_CTEIF3_Pos (25U) +#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */ +#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk +#define DMA_LIFCR_CDMEIF3_Pos (24U) +#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */ +#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk +#define DMA_LIFCR_CFEIF3_Pos (22U) +#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */ +#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk +#define DMA_LIFCR_CTCIF2_Pos (21U) +#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */ +#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk +#define DMA_LIFCR_CHTIF2_Pos (20U) +#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */ +#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk +#define DMA_LIFCR_CTEIF2_Pos (19U) +#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */ +#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk +#define DMA_LIFCR_CDMEIF2_Pos (18U) +#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */ +#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk +#define DMA_LIFCR_CFEIF2_Pos (16U) +#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */ +#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk +#define DMA_LIFCR_CTCIF1_Pos (11U) +#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */ +#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk +#define DMA_LIFCR_CHTIF1_Pos (10U) +#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */ +#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk +#define DMA_LIFCR_CTEIF1_Pos (9U) +#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */ +#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk +#define DMA_LIFCR_CDMEIF1_Pos (8U) +#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */ +#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk +#define DMA_LIFCR_CFEIF1_Pos (6U) +#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */ +#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk +#define DMA_LIFCR_CTCIF0_Pos (5U) +#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */ +#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk +#define DMA_LIFCR_CHTIF0_Pos (4U) +#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */ +#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk +#define DMA_LIFCR_CTEIF0_Pos (3U) +#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */ +#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk +#define DMA_LIFCR_CDMEIF0_Pos (2U) +#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */ +#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk +#define DMA_LIFCR_CFEIF0_Pos (0U) +#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */ +#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /******************** Bits definition for DMA_HIFCR register ****************/ -#define DMA_HIFCR_CTCIF7 0x08000000U -#define DMA_HIFCR_CHTIF7 0x04000000U -#define DMA_HIFCR_CTEIF7 0x02000000U -#define DMA_HIFCR_CDMEIF7 0x01000000U -#define DMA_HIFCR_CFEIF7 0x00400000U -#define DMA_HIFCR_CTCIF6 0x00200000U -#define DMA_HIFCR_CHTIF6 0x00100000U -#define DMA_HIFCR_CTEIF6 0x00080000U -#define DMA_HIFCR_CDMEIF6 0x00040000U -#define DMA_HIFCR_CFEIF6 0x00010000U -#define DMA_HIFCR_CTCIF5 0x00000800U -#define DMA_HIFCR_CHTIF5 0x00000400U -#define DMA_HIFCR_CTEIF5 0x00000200U -#define DMA_HIFCR_CDMEIF5 0x00000100U -#define DMA_HIFCR_CFEIF5 0x00000040U -#define DMA_HIFCR_CTCIF4 0x00000020U -#define DMA_HIFCR_CHTIF4 0x00000010U -#define DMA_HIFCR_CTEIF4 0x00000008U -#define DMA_HIFCR_CDMEIF4 0x00000004U -#define DMA_HIFCR_CFEIF4 0x00000001U +#define DMA_HIFCR_CTCIF7_Pos (27U) +#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */ +#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk +#define DMA_HIFCR_CHTIF7_Pos (26U) +#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk +#define DMA_HIFCR_CTEIF7_Pos (25U) +#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */ +#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk +#define DMA_HIFCR_CDMEIF7_Pos (24U) +#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */ +#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk +#define DMA_HIFCR_CFEIF7_Pos (22U) +#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */ +#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk +#define DMA_HIFCR_CTCIF6_Pos (21U) +#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk +#define DMA_HIFCR_CHTIF6_Pos (20U) +#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */ +#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk +#define DMA_HIFCR_CTEIF6_Pos (19U) +#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */ +#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk +#define DMA_HIFCR_CDMEIF6_Pos (18U) +#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */ +#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk +#define DMA_HIFCR_CFEIF6_Pos (16U) +#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */ +#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk +#define DMA_HIFCR_CTCIF5_Pos (11U) +#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */ +#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk +#define DMA_HIFCR_CHTIF5_Pos (10U) +#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */ +#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk +#define DMA_HIFCR_CTEIF5_Pos (9U) +#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */ +#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk +#define DMA_HIFCR_CDMEIF5_Pos (8U) +#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */ +#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk +#define DMA_HIFCR_CFEIF5_Pos (6U) +#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */ +#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk +#define DMA_HIFCR_CTCIF4_Pos (5U) +#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */ +#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk +#define DMA_HIFCR_CHTIF4_Pos (4U) +#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */ +#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk +#define DMA_HIFCR_CTEIF4_Pos (3U) +#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */ +#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk +#define DMA_HIFCR_CDMEIF4_Pos (2U) +#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */ +#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk +#define DMA_HIFCR_CFEIF4_Pos (0U) +#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */ +#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk + +/****************** Bit definition for DMA_SxPAR register ********************/ +#define DMA_SxPAR_PA_Pos (0U) +#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_SxM0AR register ********************/ +#define DMA_SxM0AR_M0A_Pos (0U) +#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */ +#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */ + +/****************** Bit definition for DMA_SxM1AR register ********************/ +#define DMA_SxM1AR_M1A_Pos (0U) +#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ +#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */ /******************************************************************************/ @@ -1410,154 +1821,483 @@ /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19_Pos (19U) +#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_MR20_Pos (20U) +#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR_MR21_Pos (21U) +#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR_MR22_Pos (22U) +#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ + +/* Reference Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM16 EXTI_IMR_MR16 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM19 EXTI_IMR_MR19 +#define EXTI_IMR_IM20 EXTI_IMR_MR20 +#define EXTI_IMR_IM21 EXTI_IMR_MR21 +#define EXTI_IMR_IM22 EXTI_IMR_MR22 +#define EXTI_IMR_IM_Pos (0U) +#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */ +#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */ -#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */ -#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */ -#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19_Pos (19U) +#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR_MR20_Pos (20U) +#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ +#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ +#define EXTI_EMR_MR21_Pos (21U) +#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR_MR22_Pos (22U) +#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ +#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ + +/* Reference Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM16 EXTI_EMR_MR16 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 +#define EXTI_EMR_EM19 EXTI_EMR_MR19 +#define EXTI_EMR_EM20 EXTI_EMR_MR20 +#define EXTI_EMR_EM21 EXTI_EMR_MR21 +#define EXTI_EMR_EM22 EXTI_EMR_MR22 /****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19_Pos (19U) +#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_TR20_Pos (20U) +#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ +#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ +#define EXTI_RTSR_TR21_Pos (21U) +#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ +#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ +#define EXTI_RTSR_TR22_Pos (22U) +#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ +#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ /****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19_Pos (19U) +#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ +#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_TR20_Pos (20U) +#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ +#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ +#define EXTI_FTSR_TR21_Pos (21U) +#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ +#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ +#define EXTI_FTSR_TR22_Pos (22U) +#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ +#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ /****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19_Pos (19U) +#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ +#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWIER20_Pos (20U) +#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ +#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ +#define EXTI_SWIER_SWIER21_Pos (21U) +#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ +#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ +#define EXTI_SWIER_SWIER22_Pos (22U) +#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ +#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ /******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */ -#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */ -#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */ -#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ +#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19_Pos (19U) +#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ +#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ +#define EXTI_PR_PR20_Pos (20U) +#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ +#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ +#define EXTI_PR_PR21_Pos (21U) +#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ +#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ +#define EXTI_PR_PR22_Pos (22U) +#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ +#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ /******************************************************************************/ /* */ @@ -1565,97 +2305,164 @@ /* */ /******************************************************************************/ /******************* Bits definition for FLASH_ACR register *****************/ -#define FLASH_ACR_LATENCY 0x0000000FU -#define FLASH_ACR_LATENCY_0WS 0x00000000U -#define FLASH_ACR_LATENCY_1WS 0x00000001U -#define FLASH_ACR_LATENCY_2WS 0x00000002U -#define FLASH_ACR_LATENCY_3WS 0x00000003U -#define FLASH_ACR_LATENCY_4WS 0x00000004U -#define FLASH_ACR_LATENCY_5WS 0x00000005U -#define FLASH_ACR_LATENCY_6WS 0x00000006U -#define FLASH_ACR_LATENCY_7WS 0x00000007U - -#define FLASH_ACR_PRFTEN 0x00000100U -#define FLASH_ACR_ICEN 0x00000200U -#define FLASH_ACR_DCEN 0x00000400U -#define FLASH_ACR_ICRST 0x00000800U -#define FLASH_ACR_DCRST 0x00001000U -#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U -#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0WS 0x00000000U +#define FLASH_ACR_LATENCY_1WS 0x00000001U +#define FLASH_ACR_LATENCY_2WS 0x00000002U +#define FLASH_ACR_LATENCY_3WS 0x00000003U +#define FLASH_ACR_LATENCY_4WS 0x00000004U +#define FLASH_ACR_LATENCY_5WS 0x00000005U +#define FLASH_ACR_LATENCY_6WS 0x00000006U +#define FLASH_ACR_LATENCY_7WS 0x00000007U + +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_DCEN_Pos (10U) +#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ +#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_DCRST_Pos (12U) +#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk +#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U) +#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */ +#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk +#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U) +#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */ +#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk /******************* Bits definition for FLASH_SR register ******************/ -#define FLASH_SR_EOP 0x00000001U -#define FLASH_SR_SOP 0x00000002U -#define FLASH_SR_WRPERR 0x00000010U -#define FLASH_SR_PGAERR 0x00000020U -#define FLASH_SR_PGPERR 0x00000040U -#define FLASH_SR_PGSERR 0x00000080U -#define FLASH_SR_BSY 0x00010000U +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_SOP_Pos (1U) +#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */ +#define FLASH_SR_SOP FLASH_SR_SOP_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_PGPERR_Pos (6U) +#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_RDERR_Pos (8U) +#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /******************* Bits definition for FLASH_CR register ******************/ -#define FLASH_CR_PG 0x00000001U -#define FLASH_CR_SER 0x00000002U -#define FLASH_CR_MER 0x00000004U -#define FLASH_CR_SNB 0x000000F8U -#define FLASH_CR_SNB_0 0x00000008U -#define FLASH_CR_SNB_1 0x00000010U -#define FLASH_CR_SNB_2 0x00000020U -#define FLASH_CR_SNB_3 0x00000040U -#define FLASH_CR_SNB_4 0x00000080U -#define FLASH_CR_PSIZE 0x00000300U -#define FLASH_CR_PSIZE_0 0x00000100U -#define FLASH_CR_PSIZE_1 0x00000200U -#define FLASH_CR_STRT 0x00010000U -#define FLASH_CR_EOPIE 0x01000000U -#define FLASH_CR_LOCK 0x80000000U +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_SER_Pos (1U) +#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk +#define FLASH_CR_SNB_Pos (3U) +#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk +#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */ +#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */ +#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */ +#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_PSIZE_Pos (8U) +#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */ +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk +#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */ +#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */ +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /******************* Bits definition for FLASH_OPTCR register ***************/ -#define FLASH_OPTCR_OPTLOCK 0x00000001U -#define FLASH_OPTCR_OPTSTRT 0x00000002U -#define FLASH_OPTCR_BOR_LEV_0 0x00000004U -#define FLASH_OPTCR_BOR_LEV_1 0x00000008U -#define FLASH_OPTCR_BOR_LEV 0x0000000CU - -#define FLASH_OPTCR_WDG_SW 0x00000020U -#define FLASH_OPTCR_nRST_STOP 0x00000040U -#define FLASH_OPTCR_nRST_STDBY 0x00000080U -#define FLASH_OPTCR_RDP 0x0000FF00U -#define FLASH_OPTCR_RDP_0 0x00000100U -#define FLASH_OPTCR_RDP_1 0x00000200U -#define FLASH_OPTCR_RDP_2 0x00000400U -#define FLASH_OPTCR_RDP_3 0x00000800U -#define FLASH_OPTCR_RDP_4 0x00001000U -#define FLASH_OPTCR_RDP_5 0x00002000U -#define FLASH_OPTCR_RDP_6 0x00004000U -#define FLASH_OPTCR_RDP_7 0x00008000U -#define FLASH_OPTCR_nWRP 0x0FFF0000U -#define FLASH_OPTCR_nWRP_0 0x00010000U -#define FLASH_OPTCR_nWRP_1 0x00020000U -#define FLASH_OPTCR_nWRP_2 0x00040000U -#define FLASH_OPTCR_nWRP_3 0x00080000U -#define FLASH_OPTCR_nWRP_4 0x00100000U -#define FLASH_OPTCR_nWRP_5 0x00200000U -#define FLASH_OPTCR_nWRP_6 0x00400000U -#define FLASH_OPTCR_nWRP_7 0x00800000U -#define FLASH_OPTCR_nWRP_8 0x01000000U -#define FLASH_OPTCR_nWRP_9 0x02000000U -#define FLASH_OPTCR_nWRP_10 0x04000000U -#define FLASH_OPTCR_nWRP_11 0x08000000U +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk +#define FLASH_OPTCR_OPTSTRT_Pos (1U) +#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk + +#define FLASH_OPTCR_BOR_LEV_0 0x00000004U +#define FLASH_OPTCR_BOR_LEV_1 0x00000008U +#define FLASH_OPTCR_BOR_LEV_Pos (2U) +#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */ +#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk +#define FLASH_OPTCR_WDG_SW_Pos (5U) +#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */ +#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk +#define FLASH_OPTCR_nRST_STOP_Pos (6U) +#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk +#define FLASH_OPTCR_nRST_STDBY_Pos (7U) +#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk +#define FLASH_OPTCR_RDP_Pos (8U) +#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk +#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */ +#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */ +#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */ +#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */ +#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */ +#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */ +#define FLASH_OPTCR_nWRP_Pos (16U) +#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */ +#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk +#define FLASH_OPTCR_nWRP_0 0x00010000U +#define FLASH_OPTCR_nWRP_1 0x00020000U +#define FLASH_OPTCR_nWRP_2 0x00040000U +#define FLASH_OPTCR_nWRP_3 0x00080000U +#define FLASH_OPTCR_nWRP_4 0x00100000U +#define FLASH_OPTCR_nWRP_5 0x00200000U +#define FLASH_OPTCR_nWRP_6 0x00400000U +#define FLASH_OPTCR_nWRP_7 0x00800000U +#define FLASH_OPTCR_nWRP_8 0x01000000U +#define FLASH_OPTCR_nWRP_9 0x02000000U +#define FLASH_OPTCR_nWRP_10 0x04000000U +#define FLASH_OPTCR_nWRP_11 0x08000000U /****************** Bits definition for FLASH_OPTCR1 register ***************/ -#define FLASH_OPTCR1_nWRP 0x0FFF0000U -#define FLASH_OPTCR1_nWRP_0 0x00010000U -#define FLASH_OPTCR1_nWRP_1 0x00020000U -#define FLASH_OPTCR1_nWRP_2 0x00040000U -#define FLASH_OPTCR1_nWRP_3 0x00080000U -#define FLASH_OPTCR1_nWRP_4 0x00100000U -#define FLASH_OPTCR1_nWRP_5 0x00200000U -#define FLASH_OPTCR1_nWRP_6 0x00400000U -#define FLASH_OPTCR1_nWRP_7 0x00800000U -#define FLASH_OPTCR1_nWRP_8 0x01000000U -#define FLASH_OPTCR1_nWRP_9 0x02000000U -#define FLASH_OPTCR1_nWRP_10 0x04000000U -#define FLASH_OPTCR1_nWRP_11 0x08000000U +#define FLASH_OPTCR1_nWRP_Pos (16U) +#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */ +#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk +#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */ +#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */ +#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */ +#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */ +#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */ +#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */ +#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */ +#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */ +#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */ +#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */ /******************************************************************************/ /* */ @@ -1663,340 +2470,1069 @@ /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODER0 0x00000003U -#define GPIO_MODER_MODER0_0 0x00000001U -#define GPIO_MODER_MODER0_1 0x00000002U - -#define GPIO_MODER_MODER1 0x0000000CU -#define GPIO_MODER_MODER1_0 0x00000004U -#define GPIO_MODER_MODER1_1 0x00000008U - -#define GPIO_MODER_MODER2 0x00000030U -#define GPIO_MODER_MODER2_0 0x00000010U -#define GPIO_MODER_MODER2_1 0x00000020U - -#define GPIO_MODER_MODER3 0x000000C0U -#define GPIO_MODER_MODER3_0 0x00000040U -#define GPIO_MODER_MODER3_1 0x00000080U - -#define GPIO_MODER_MODER4 0x00000300U -#define GPIO_MODER_MODER4_0 0x00000100U -#define GPIO_MODER_MODER4_1 0x00000200U - -#define GPIO_MODER_MODER5 0x00000C00U -#define GPIO_MODER_MODER5_0 0x00000400U -#define GPIO_MODER_MODER5_1 0x00000800U - -#define GPIO_MODER_MODER6 0x00003000U -#define GPIO_MODER_MODER6_0 0x00001000U -#define GPIO_MODER_MODER6_1 0x00002000U - -#define GPIO_MODER_MODER7 0x0000C000U -#define GPIO_MODER_MODER7_0 0x00004000U -#define GPIO_MODER_MODER7_1 0x00008000U - -#define GPIO_MODER_MODER8 0x00030000U -#define GPIO_MODER_MODER8_0 0x00010000U -#define GPIO_MODER_MODER8_1 0x00020000U - -#define GPIO_MODER_MODER9 0x000C0000U -#define GPIO_MODER_MODER9_0 0x00040000U -#define GPIO_MODER_MODER9_1 0x00080000U - -#define GPIO_MODER_MODER10 0x00300000U -#define GPIO_MODER_MODER10_0 0x00100000U -#define GPIO_MODER_MODER10_1 0x00200000U - -#define GPIO_MODER_MODER11 0x00C00000U -#define GPIO_MODER_MODER11_0 0x00400000U -#define GPIO_MODER_MODER11_1 0x00800000U - -#define GPIO_MODER_MODER12 0x03000000U -#define GPIO_MODER_MODER12_0 0x01000000U -#define GPIO_MODER_MODER12_1 0x02000000U - -#define GPIO_MODER_MODER13 0x0C000000U -#define GPIO_MODER_MODER13_0 0x04000000U -#define GPIO_MODER_MODER13_1 0x08000000U - -#define GPIO_MODER_MODER14 0x30000000U -#define GPIO_MODER_MODER14_0 0x10000000U -#define GPIO_MODER_MODER14_1 0x20000000U - -#define GPIO_MODER_MODER15 0xC0000000U -#define GPIO_MODER_MODER15_0 0x40000000U -#define GPIO_MODER_MODER15_1 0x80000000U +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_OTYPER register ****************/ -#define GPIO_OTYPER_OT_0 0x00000001U -#define GPIO_OTYPER_OT_1 0x00000002U -#define GPIO_OTYPER_OT_2 0x00000004U -#define GPIO_OTYPER_OT_3 0x00000008U -#define GPIO_OTYPER_OT_4 0x00000010U -#define GPIO_OTYPER_OT_5 0x00000020U -#define GPIO_OTYPER_OT_6 0x00000040U -#define GPIO_OTYPER_OT_7 0x00000080U -#define GPIO_OTYPER_OT_8 0x00000100U -#define GPIO_OTYPER_OT_9 0x00000200U -#define GPIO_OTYPER_OT_10 0x00000400U -#define GPIO_OTYPER_OT_11 0x00000800U -#define GPIO_OTYPER_OT_12 0x00001000U -#define GPIO_OTYPER_OT_13 0x00002000U -#define GPIO_OTYPER_OT_14 0x00004000U -#define GPIO_OTYPER_OT_15 0x00008000U +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/* Legacy defines */ +#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 +#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 +#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 +#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 +#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 +#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 +#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 +#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 +#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 +#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 +#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 +#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 +#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 +#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 +#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 +#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 /****************** Bits definition for GPIO_OSPEEDR register ***************/ -#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U -#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U -#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U - -#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU -#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U -#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U - -#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U -#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U -#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U - -#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U -#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U -#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U - -#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U -#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U -#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U - -#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U -#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U -#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U - -#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U -#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U -#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U - -#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U -#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U -#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U - -#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U -#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U -#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U - -#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U -#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U -#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U - -#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U -#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U -#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U - -#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U -#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U -#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U - -#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U -#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U -#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U - -#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U -#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U -#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U - -#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U -#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U -#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U - -#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U -#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U -#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 /****************** Bits definition for GPIO_PUPDR register *****************/ -#define GPIO_PUPDR_PUPDR0 0x00000003U -#define GPIO_PUPDR_PUPDR0_0 0x00000001U -#define GPIO_PUPDR_PUPDR0_1 0x00000002U - -#define GPIO_PUPDR_PUPDR1 0x0000000CU -#define GPIO_PUPDR_PUPDR1_0 0x00000004U -#define GPIO_PUPDR_PUPDR1_1 0x00000008U - -#define GPIO_PUPDR_PUPDR2 0x00000030U -#define GPIO_PUPDR_PUPDR2_0 0x00000010U -#define GPIO_PUPDR_PUPDR2_1 0x00000020U - -#define GPIO_PUPDR_PUPDR3 0x000000C0U -#define GPIO_PUPDR_PUPDR3_0 0x00000040U -#define GPIO_PUPDR_PUPDR3_1 0x00000080U - -#define GPIO_PUPDR_PUPDR4 0x00000300U -#define GPIO_PUPDR_PUPDR4_0 0x00000100U -#define GPIO_PUPDR_PUPDR4_1 0x00000200U - -#define GPIO_PUPDR_PUPDR5 0x00000C00U -#define GPIO_PUPDR_PUPDR5_0 0x00000400U -#define GPIO_PUPDR_PUPDR5_1 0x00000800U - -#define GPIO_PUPDR_PUPDR6 0x00003000U -#define GPIO_PUPDR_PUPDR6_0 0x00001000U -#define GPIO_PUPDR_PUPDR6_1 0x00002000U - -#define GPIO_PUPDR_PUPDR7 0x0000C000U -#define GPIO_PUPDR_PUPDR7_0 0x00004000U -#define GPIO_PUPDR_PUPDR7_1 0x00008000U - -#define GPIO_PUPDR_PUPDR8 0x00030000U -#define GPIO_PUPDR_PUPDR8_0 0x00010000U -#define GPIO_PUPDR_PUPDR8_1 0x00020000U - -#define GPIO_PUPDR_PUPDR9 0x000C0000U -#define GPIO_PUPDR_PUPDR9_0 0x00040000U -#define GPIO_PUPDR_PUPDR9_1 0x00080000U - -#define GPIO_PUPDR_PUPDR10 0x00300000U -#define GPIO_PUPDR_PUPDR10_0 0x00100000U -#define GPIO_PUPDR_PUPDR10_1 0x00200000U - -#define GPIO_PUPDR_PUPDR11 0x00C00000U -#define GPIO_PUPDR_PUPDR11_0 0x00400000U -#define GPIO_PUPDR_PUPDR11_1 0x00800000U - -#define GPIO_PUPDR_PUPDR12 0x03000000U -#define GPIO_PUPDR_PUPDR12_0 0x01000000U -#define GPIO_PUPDR_PUPDR12_1 0x02000000U - -#define GPIO_PUPDR_PUPDR13 0x0C000000U -#define GPIO_PUPDR_PUPDR13_0 0x04000000U -#define GPIO_PUPDR_PUPDR13_1 0x08000000U - -#define GPIO_PUPDR_PUPDR14 0x30000000U -#define GPIO_PUPDR_PUPDR14_0 0x10000000U -#define GPIO_PUPDR_PUPDR14_1 0x20000000U - -#define GPIO_PUPDR_PUPDR15 0xC0000000U -#define GPIO_PUPDR_PUPDR15_0 0x40000000U -#define GPIO_PUPDR_PUPDR15_1 0x80000000U +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 +#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 +#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 +#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 +#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 +#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 +#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 +#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 +#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 +#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 +#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 +#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 +#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 +#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 +#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 +#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 +#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 +#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 +#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 +#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 +#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 +#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 +#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 +#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 +#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 +#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 +#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 +#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 +#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 +#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 +#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 +#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 +#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 +#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 +#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 +#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 +#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 +#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 +#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 +#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 +#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 +#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 +#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 +#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 +#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 +#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 +#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 +#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR_0 0x00000001U -#define GPIO_IDR_IDR_1 0x00000002U -#define GPIO_IDR_IDR_2 0x00000004U -#define GPIO_IDR_IDR_3 0x00000008U -#define GPIO_IDR_IDR_4 0x00000010U -#define GPIO_IDR_IDR_5 0x00000020U -#define GPIO_IDR_IDR_6 0x00000040U -#define GPIO_IDR_IDR_7 0x00000080U -#define GPIO_IDR_IDR_8 0x00000100U -#define GPIO_IDR_IDR_9 0x00000200U -#define GPIO_IDR_IDR_10 0x00000400U -#define GPIO_IDR_IDR_11 0x00000800U -#define GPIO_IDR_IDR_12 0x00001000U -#define GPIO_IDR_IDR_13 0x00002000U -#define GPIO_IDR_IDR_14 0x00004000U -#define GPIO_IDR_IDR_15 0x00008000U -/* Old GPIO_IDR register bits definition, maintained for legacy purpose */ -#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 -#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 -#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 -#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 -#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 -#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 -#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 -#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 -#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 -#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 -#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 -#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 -#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 -#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 -#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 -#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/* Legacy defines */ +#define GPIO_IDR_IDR_0 GPIO_IDR_ID0 +#define GPIO_IDR_IDR_1 GPIO_IDR_ID1 +#define GPIO_IDR_IDR_2 GPIO_IDR_ID2 +#define GPIO_IDR_IDR_3 GPIO_IDR_ID3 +#define GPIO_IDR_IDR_4 GPIO_IDR_ID4 +#define GPIO_IDR_IDR_5 GPIO_IDR_ID5 +#define GPIO_IDR_IDR_6 GPIO_IDR_ID6 +#define GPIO_IDR_IDR_7 GPIO_IDR_ID7 +#define GPIO_IDR_IDR_8 GPIO_IDR_ID8 +#define GPIO_IDR_IDR_9 GPIO_IDR_ID9 +#define GPIO_IDR_IDR_10 GPIO_IDR_ID10 +#define GPIO_IDR_IDR_11 GPIO_IDR_ID11 +#define GPIO_IDR_IDR_12 GPIO_IDR_ID12 +#define GPIO_IDR_IDR_13 GPIO_IDR_ID13 +#define GPIO_IDR_IDR_14 GPIO_IDR_ID14 +#define GPIO_IDR_IDR_15 GPIO_IDR_ID15 /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR_0 0x00000001U -#define GPIO_ODR_ODR_1 0x00000002U -#define GPIO_ODR_ODR_2 0x00000004U -#define GPIO_ODR_ODR_3 0x00000008U -#define GPIO_ODR_ODR_4 0x00000010U -#define GPIO_ODR_ODR_5 0x00000020U -#define GPIO_ODR_ODR_6 0x00000040U -#define GPIO_ODR_ODR_7 0x00000080U -#define GPIO_ODR_ODR_8 0x00000100U -#define GPIO_ODR_ODR_9 0x00000200U -#define GPIO_ODR_ODR_10 0x00000400U -#define GPIO_ODR_ODR_11 0x00000800U -#define GPIO_ODR_ODR_12 0x00001000U -#define GPIO_ODR_ODR_13 0x00002000U -#define GPIO_ODR_ODR_14 0x00004000U -#define GPIO_ODR_ODR_15 0x00008000U -/* Old GPIO_ODR register bits definition, maintained for legacy purpose */ -#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 -#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 -#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 -#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 -#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 -#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 -#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 -#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 -#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 -#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 -#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 -#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 -#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 -#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 -#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 -#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk +/* Legacy defines */ +#define GPIO_ODR_ODR_0 GPIO_ODR_OD0 +#define GPIO_ODR_ODR_1 GPIO_ODR_OD1 +#define GPIO_ODR_ODR_2 GPIO_ODR_OD2 +#define GPIO_ODR_ODR_3 GPIO_ODR_OD3 +#define GPIO_ODR_ODR_4 GPIO_ODR_OD4 +#define GPIO_ODR_ODR_5 GPIO_ODR_OD5 +#define GPIO_ODR_ODR_6 GPIO_ODR_OD6 +#define GPIO_ODR_ODR_7 GPIO_ODR_OD7 +#define GPIO_ODR_ODR_8 GPIO_ODR_OD8 +#define GPIO_ODR_ODR_9 GPIO_ODR_OD9 +#define GPIO_ODR_ODR_10 GPIO_ODR_OD10 +#define GPIO_ODR_ODR_11 GPIO_ODR_OD11 +#define GPIO_ODR_ODR_12 GPIO_ODR_OD12 +#define GPIO_ODR_ODR_13 GPIO_ODR_OD13 +#define GPIO_ODR_ODR_14 GPIO_ODR_OD14 +#define GPIO_ODR_ODR_15 GPIO_ODR_OD15 /****************** Bits definition for GPIO_BSRR register ******************/ -#define GPIO_BSRR_BS_0 0x00000001U -#define GPIO_BSRR_BS_1 0x00000002U -#define GPIO_BSRR_BS_2 0x00000004U -#define GPIO_BSRR_BS_3 0x00000008U -#define GPIO_BSRR_BS_4 0x00000010U -#define GPIO_BSRR_BS_5 0x00000020U -#define GPIO_BSRR_BS_6 0x00000040U -#define GPIO_BSRR_BS_7 0x00000080U -#define GPIO_BSRR_BS_8 0x00000100U -#define GPIO_BSRR_BS_9 0x00000200U -#define GPIO_BSRR_BS_10 0x00000400U -#define GPIO_BSRR_BS_11 0x00000800U -#define GPIO_BSRR_BS_12 0x00001000U -#define GPIO_BSRR_BS_13 0x00002000U -#define GPIO_BSRR_BS_14 0x00004000U -#define GPIO_BSRR_BS_15 0x00008000U -#define GPIO_BSRR_BR_0 0x00010000U -#define GPIO_BSRR_BR_1 0x00020000U -#define GPIO_BSRR_BR_2 0x00040000U -#define GPIO_BSRR_BR_3 0x00080000U -#define GPIO_BSRR_BR_4 0x00100000U -#define GPIO_BSRR_BR_5 0x00200000U -#define GPIO_BSRR_BR_6 0x00400000U -#define GPIO_BSRR_BR_7 0x00800000U -#define GPIO_BSRR_BR_8 0x01000000U -#define GPIO_BSRR_BR_9 0x02000000U -#define GPIO_BSRR_BR_10 0x04000000U -#define GPIO_BSRR_BR_11 0x08000000U -#define GPIO_BSRR_BR_12 0x10000000U -#define GPIO_BSRR_BR_13 0x20000000U -#define GPIO_BSRR_BR_14 0x40000000U -#define GPIO_BSRR_BR_15 0x80000000U - +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/* Legacy defines */ +#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 +#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 +#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 +#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 +#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 +#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 +#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 +#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 +#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 +#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 +#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 +#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 +#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 +#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 +#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 +#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 +#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 +#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 +#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 +#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 +#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 +#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 +#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 +#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 +#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 +#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 +#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 +#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 +#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 +#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 +#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 +#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 /****************** Bit definition for GPIO_LCKR register *********************/ -#define GPIO_LCKR_LCK0 0x00000001U -#define GPIO_LCKR_LCK1 0x00000002U -#define GPIO_LCKR_LCK2 0x00000004U -#define GPIO_LCKR_LCK3 0x00000008U -#define GPIO_LCKR_LCK4 0x00000010U -#define GPIO_LCKR_LCK5 0x00000020U -#define GPIO_LCKR_LCK6 0x00000040U -#define GPIO_LCKR_LCK7 0x00000080U -#define GPIO_LCKR_LCK8 0x00000100U -#define GPIO_LCKR_LCK9 0x00000200U -#define GPIO_LCKR_LCK10 0x00000400U -#define GPIO_LCKR_LCK11 0x00000800U -#define GPIO_LCKR_LCK12 0x00001000U -#define GPIO_LCKR_LCK13 0x00002000U -#define GPIO_LCKR_LCK14 0x00004000U -#define GPIO_LCKR_LCK15 0x00008000U -#define GPIO_LCKR_LCKK 0x00010000U +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 +#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0 +#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1 +#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2 +#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3 +#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 +#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0 +#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1 +#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2 +#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3 +#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 +#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0 +#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1 +#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2 +#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3 +#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 +#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0 +#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1 +#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2 +#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3 +#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 +#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0 +#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1 +#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2 +#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3 +#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 +#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0 +#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1 +#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2 +#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3 +#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 +#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0 +#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1 +#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2 +#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3 +#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 +#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0 +#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1 +#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2 +#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3 + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 +#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0 +#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1 +#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2 +#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3 +#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 +#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0 +#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1 +#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2 +#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3 +#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 +#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0 +#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1 +#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2 +#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3 +#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 +#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0 +#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1 +#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2 +#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3 +#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 +#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0 +#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1 +#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2 +#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3 +#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 +#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0 +#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1 +#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2 +#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3 +#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 +#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0 +#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1 +#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2 +#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3 +#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 +#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0 +#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1 +#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2 +#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3 + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + /******************************************************************************/ /* */ @@ -2004,97 +3540,221 @@ /* */ /******************************************************************************/ /******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */ -#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */ -#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */ -#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */ -#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */ -#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */ -#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START 0x00000100U /*!<Start Generation */ -#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */ -#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */ -#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */ -#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */ -#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */ +#define I2C_CR1_SMBUS_Pos (1U) +#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ +#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */ +#define I2C_CR1_SMBTYPE_Pos (3U) +#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */ +#define I2C_CR1_ENARP_Pos (4U) +#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ +#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */ +#define I2C_CR1_ENPEC_Pos (5U) +#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ +#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */ +#define I2C_CR1_ENGC_Pos (6U) +#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ +#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */ +#define I2C_CR1_NOSTRETCH_Pos (7U) +#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START_Pos (8U) +#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ +#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */ +#define I2C_CR1_STOP_Pos (9U) +#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ +#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */ +#define I2C_CR1_ACK_Pos (10U) +#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ +#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */ +#define I2C_CR1_POS_Pos (11U) +#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ +#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC_Pos (12U) +#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ +#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */ +#define I2C_CR1_ALERT_Pos (13U) +#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */ +#define I2C_CR1_SWRST_Pos (15U) +#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */ /******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */ -#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */ -#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */ -#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */ -#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */ -#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */ - -#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */ -#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */ +#define I2C_CR2_FREQ_Pos (0U) +#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ +#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ +#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ +#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ +#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ +#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ +#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ + +#define I2C_CR2_ITERREN_Pos (8U) +#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ +#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN_Pos (9U) +#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ +#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN_Pos (10U) +#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN_Pos (11U) +#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ +#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */ +#define I2C_CR2_LAST_Pos (12U) +#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ +#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */ /******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */ -#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */ - -#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */ -#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */ -#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */ -#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */ -#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */ -#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */ -#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */ -#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */ -#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */ -#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */ - -#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */ +#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */ +#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */ + +#define I2C_OAR1_ADD0_Pos (0U) +#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ +#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */ +#define I2C_OAR1_ADD1_Pos (1U) +#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ +#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */ +#define I2C_OAR1_ADD2_Pos (2U) +#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ +#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */ +#define I2C_OAR1_ADD3_Pos (3U) +#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ +#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */ +#define I2C_OAR1_ADD4_Pos (4U) +#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ +#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */ +#define I2C_OAR1_ADD5_Pos (5U) +#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ +#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */ +#define I2C_OAR1_ADD6_Pos (6U) +#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ +#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */ +#define I2C_OAR1_ADD7_Pos (7U) +#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ +#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */ +#define I2C_OAR1_ADD8_Pos (8U) +#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ +#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */ +#define I2C_OAR1_ADD9_Pos (9U) +#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ +#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */ + +#define I2C_OAR1_ADDMODE_Pos (15U) +#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */ /******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */ -#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */ +#define I2C_OAR2_ENDUAL_Pos (0U) +#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ +#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */ +#define I2C_OAR2_ADD2_Pos (1U) +#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */ /******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */ +#define I2C_DR_DR_Pos (0U) +#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ +#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */ /******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */ -#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */ -#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */ -#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */ -#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */ -#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */ -#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */ -#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */ -#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */ -#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */ -#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */ +#define I2C_SR1_SB_Pos (0U) +#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ +#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */ +#define I2C_SR1_ADDR_Pos (1U) +#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ +#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF_Pos (2U) +#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ +#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */ +#define I2C_SR1_ADD10_Pos (3U) +#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ +#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF_Pos (4U) +#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ +#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */ +#define I2C_SR1_RXNE_Pos (6U) +#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ +#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */ +#define I2C_SR1_TXE_Pos (7U) +#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ +#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */ +#define I2C_SR1_BERR_Pos (8U) +#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ +#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */ +#define I2C_SR1_ARLO_Pos (9U) +#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */ +#define I2C_SR1_AF_Pos (10U) +#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ +#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */ +#define I2C_SR1_OVR_Pos (11U) +#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ +#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */ +#define I2C_SR1_PECERR_Pos (12U) +#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ +#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */ +#define I2C_SR1_TIMEOUT_Pos (14U) +#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ +#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT_Pos (15U) +#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ +#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */ /******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */ -#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */ -#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */ -#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */ -#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */ +#define I2C_SR2_MSL_Pos (0U) +#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ +#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */ +#define I2C_SR2_BUSY_Pos (1U) +#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ +#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */ +#define I2C_SR2_TRA_Pos (2U) +#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ +#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */ +#define I2C_SR2_GENCALL_Pos (4U) +#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ +#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT_Pos (5U) +#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ +#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST_Pos (6U) +#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ +#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF_Pos (7U) +#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ +#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */ +#define I2C_SR2_PEC_Pos (8U) +#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ +#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */ /******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */ -#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */ +#define I2C_CCR_CCR_Pos (0U) +#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ +#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY_Pos (14U) +#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ +#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */ +#define I2C_CCR_FS_Pos (15U) +#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ +#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */ /****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ +#define I2C_TRISE_TRISE_Pos (0U) +#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ +#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ /****************** Bit definition for I2C_FLTR register *******************/ -#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */ -#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */ +#define I2C_FLTR_DNF_Pos (0U) +#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */ +#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */ +#define I2C_FLTR_ANOFF_Pos (4U) +#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */ +#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */ /******************************************************************************/ /* */ @@ -2102,20 +3762,31 @@ /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */ -#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */ -#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */ +#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */ +#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */ /******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */ -#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */ + /******************************************************************************/ @@ -2124,50 +3795,90 @@ /* */ /******************************************************************************/ /******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */ -#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */ -#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */ -#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */ -#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */ -#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */ -#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */ -#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */ -#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */ -#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */ -#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */ - -#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */ -#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */ -#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */ -#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */ -#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */ - -#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ -#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */ -#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */ - -#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */ -#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */ +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR_FPDS_Pos (9U) +#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */ +#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */ +#define PWR_CR_LPLVDS_Pos (10U) +#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */ +#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low Power Regulator Low Voltage in Deep Sleep mode */ +#define PWR_CR_MRLVDS_Pos (11U) +#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */ +#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main Regulator Low Voltage in Deep Sleep mode */ +#define PWR_CR_ADCDC1_Pos (13U) +#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */ +#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */ +#define PWR_CR_VOS_Pos (14U) +#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */ +#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ +#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */ +#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */ +#define PWR_CR_FMSSR_Pos (20U) +#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */ +#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */ +#define PWR_CR_FISSR_Pos (21U) +#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */ +#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */ + /* Legacy define */ #define PWR_CR_PMODE PWR_CR_VOS /******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */ -#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */ -#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */ -#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */ -#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */ -#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */ -#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_BRR_Pos (3U) +#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ +#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ +#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ +#define PWR_CSR_BRE_Pos (9U) +#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ +#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ +#define PWR_CSR_VOSRDY_Pos (14U) +#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */ +#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */ /* Legacy define */ #define PWR_CSR_REGRDY PWR_CSR_VOSRDY @@ -2178,382 +3889,748 @@ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION 0x00000001U -#define RCC_CR_HSIRDY 0x00000002U - -#define RCC_CR_HSITRIM 0x000000F8U -#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */ -#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */ -#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */ -#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */ -#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */ - -#define RCC_CR_HSICAL 0x0000FF00U -#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */ -#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */ -#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */ -#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */ -#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */ -#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */ -#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */ -#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */ - -#define RCC_CR_HSEON 0x00010000U -#define RCC_CR_HSERDY 0x00020000U -#define RCC_CR_HSEBYP 0x00040000U -#define RCC_CR_CSSON 0x00080000U -#define RCC_CR_PLLON 0x01000000U -#define RCC_CR_PLLRDY 0x02000000U -#define RCC_CR_PLLI2SON 0x04000000U -#define RCC_CR_PLLI2SRDY 0x08000000U +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk + +#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk +#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ +#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ +#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ + +#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk +#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ +#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ + +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + */ +#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ + +#define RCC_CR_PLLI2SON_Pos (26U) +#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk +#define RCC_CR_PLLI2SRDY_Pos (27U) +#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk /******************** Bit definition for RCC_PLLCFGR register ***************/ -#define RCC_PLLCFGR_PLLM 0x0000003FU -#define RCC_PLLCFGR_PLLM_0 0x00000001U -#define RCC_PLLCFGR_PLLM_1 0x00000002U -#define RCC_PLLCFGR_PLLM_2 0x00000004U -#define RCC_PLLCFGR_PLLM_3 0x00000008U -#define RCC_PLLCFGR_PLLM_4 0x00000010U -#define RCC_PLLCFGR_PLLM_5 0x00000020U - -#define RCC_PLLCFGR_PLLN 0x00007FC0U -#define RCC_PLLCFGR_PLLN_0 0x00000040U -#define RCC_PLLCFGR_PLLN_1 0x00000080U -#define RCC_PLLCFGR_PLLN_2 0x00000100U -#define RCC_PLLCFGR_PLLN_3 0x00000200U -#define RCC_PLLCFGR_PLLN_4 0x00000400U -#define RCC_PLLCFGR_PLLN_5 0x00000800U -#define RCC_PLLCFGR_PLLN_6 0x00001000U -#define RCC_PLLCFGR_PLLN_7 0x00002000U -#define RCC_PLLCFGR_PLLN_8 0x00004000U - -#define RCC_PLLCFGR_PLLP 0x00030000U -#define RCC_PLLCFGR_PLLP_0 0x00010000U -#define RCC_PLLCFGR_PLLP_1 0x00020000U - -#define RCC_PLLCFGR_PLLSRC 0x00400000U -#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U -#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U - -#define RCC_PLLCFGR_PLLQ 0x0F000000U -#define RCC_PLLCFGR_PLLQ_0 0x01000000U -#define RCC_PLLCFGR_PLLQ_1 0x02000000U -#define RCC_PLLCFGR_PLLQ_2 0x04000000U -#define RCC_PLLCFGR_PLLQ_3 0x08000000U +#define RCC_PLLCFGR_PLLM_Pos (0U) +#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */ +#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk +#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ +#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCFGR_PLLN_Pos (6U) +#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */ +#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk +#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ +#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ +#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ + +#define RCC_PLLCFGR_PLLP_Pos (16U) +#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */ +#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk +#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCFGR_PLLSRC_Pos (22U) +#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk +#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) +#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk +#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U + +#define RCC_PLLCFGR_PLLQ_Pos (24U) +#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */ +#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk +#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */ +#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */ + /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ -#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */ -#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ -#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ -#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_Pos (10U) +#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */ + +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_Pos (13U) +#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ +#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */ +#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */ /*!< RTCPRE configuration */ -#define RCC_CFGR_RTCPRE 0x001F0000U -#define RCC_CFGR_RTCPRE_0 0x00010000U -#define RCC_CFGR_RTCPRE_1 0x00020000U -#define RCC_CFGR_RTCPRE_2 0x00040000U -#define RCC_CFGR_RTCPRE_3 0x00080000U -#define RCC_CFGR_RTCPRE_4 0x00100000U +#define RCC_CFGR_RTCPRE_Pos (16U) +#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk +#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */ /*!< MCO1 configuration */ -#define RCC_CFGR_MCO1 0x00600000U -#define RCC_CFGR_MCO1_0 0x00200000U -#define RCC_CFGR_MCO1_1 0x00400000U - -#define RCC_CFGR_I2SSRC 0x00800000U - -#define RCC_CFGR_MCO1PRE 0x07000000U -#define RCC_CFGR_MCO1PRE_0 0x01000000U -#define RCC_CFGR_MCO1PRE_1 0x02000000U -#define RCC_CFGR_MCO1PRE_2 0x04000000U - -#define RCC_CFGR_MCO2PRE 0x38000000U -#define RCC_CFGR_MCO2PRE_0 0x08000000U -#define RCC_CFGR_MCO2PRE_1 0x10000000U -#define RCC_CFGR_MCO2PRE_2 0x20000000U - -#define RCC_CFGR_MCO2 0xC0000000U -#define RCC_CFGR_MCO2_0 0x40000000U -#define RCC_CFGR_MCO2_1 0x80000000U +#define RCC_CFGR_MCO1_Pos (21U) +#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */ +#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk +#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */ +#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */ + +#define RCC_CFGR_I2SSRC_Pos (23U) +#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk + +#define RCC_CFGR_MCO1PRE_Pos (24U) +#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk +#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (27U) +#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk +#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */ + +#define RCC_CFGR_MCO2_Pos (30U) +#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */ +#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk +#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */ /******************** Bit definition for RCC_CIR register *******************/ -#define RCC_CIR_LSIRDYF 0x00000001U -#define RCC_CIR_LSERDYF 0x00000002U -#define RCC_CIR_HSIRDYF 0x00000004U -#define RCC_CIR_HSERDYF 0x00000008U -#define RCC_CIR_PLLRDYF 0x00000010U -#define RCC_CIR_PLLI2SRDYF 0x00000020U - -#define RCC_CIR_CSSF 0x00000080U -#define RCC_CIR_LSIRDYIE 0x00000100U -#define RCC_CIR_LSERDYIE 0x00000200U -#define RCC_CIR_HSIRDYIE 0x00000400U -#define RCC_CIR_HSERDYIE 0x00000800U -#define RCC_CIR_PLLRDYIE 0x00001000U -#define RCC_CIR_PLLI2SRDYIE 0x00002000U - -#define RCC_CIR_LSIRDYC 0x00010000U -#define RCC_CIR_LSERDYC 0x00020000U -#define RCC_CIR_HSIRDYC 0x00040000U -#define RCC_CIR_HSERDYC 0x00080000U -#define RCC_CIR_PLLRDYC 0x00100000U -#define RCC_CIR_PLLI2SRDYC 0x00200000U - -#define RCC_CIR_CSSC 0x00800000U +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk +#define RCC_CIR_PLLI2SRDYF_Pos (5U) +#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk + +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ +#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ +#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk +#define RCC_CIR_PLLI2SRDYIE_Pos (13U) +#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */ +#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk + +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ +#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ +#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ +#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ +#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ +#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk +#define RCC_CIR_PLLI2SRDYC_Pos (21U) +#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */ +#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk + +#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ +#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /******************** Bit definition for RCC_AHB1RSTR register **************/ -#define RCC_AHB1RSTR_GPIOARST 0x00000001U -#define RCC_AHB1RSTR_GPIOBRST 0x00000002U -#define RCC_AHB1RSTR_GPIOCRST 0x00000004U -#define RCC_AHB1RSTR_GPIODRST 0x00000008U -#define RCC_AHB1RSTR_GPIOERST 0x00000010U -#define RCC_AHB1RSTR_GPIOHRST 0x00000080U -#define RCC_AHB1RSTR_CRCRST 0x00001000U -#define RCC_AHB1RSTR_DMA1RST 0x00200000U -#define RCC_AHB1RSTR_DMA2RST 0x00400000U +#define RCC_AHB1RSTR_GPIOARST_Pos (0U) +#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk +#define RCC_AHB1RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk +#define RCC_AHB1RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk +#define RCC_AHB1RSTR_GPIODRST_Pos (3U) +#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk +#define RCC_AHB1RSTR_GPIOERST_Pos (4U) +#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk +#define RCC_AHB1RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_DMA1RST_Pos (21U) +#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */ +#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk +#define RCC_AHB1RSTR_DMA2RST_Pos (22U) +#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */ +#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk /******************** Bit definition for RCC_AHB2RSTR register **************/ -#define RCC_AHB2RSTR_OTGFSRST 0x00000080U - +#define RCC_AHB2RSTR_OTGFSRST_Pos (7U) +#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk /******************** Bit definition for RCC_AHB3RSTR register **************/ + /******************** Bit definition for RCC_APB1RSTR register **************/ -#define RCC_APB1RSTR_TIM2RST 0x00000001U -#define RCC_APB1RSTR_TIM3RST 0x00000002U -#define RCC_APB1RSTR_TIM4RST 0x00000004U -#define RCC_APB1RSTR_TIM5RST 0x00000008U -#define RCC_APB1RSTR_WWDGRST 0x00000800U -#define RCC_APB1RSTR_SPI2RST 0x00004000U -#define RCC_APB1RSTR_SPI3RST 0x00008000U -#define RCC_APB1RSTR_USART2RST 0x00020000U -#define RCC_APB1RSTR_I2C1RST 0x00200000U -#define RCC_APB1RSTR_I2C2RST 0x00400000U -#define RCC_APB1RSTR_I2C3RST 0x00800000U -#define RCC_APB1RSTR_PWRRST 0x10000000U +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk +#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk +#define RCC_APB1RSTR_TIM5RST_Pos (3U) +#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk +#define RCC_APB1RSTR_SPI3RST_Pos (15U) +#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk +#define RCC_APB1RSTR_I2C3RST_Pos (23U) +#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /******************** Bit definition for RCC_APB2RSTR register **************/ -#define RCC_APB2RSTR_TIM1RST 0x00000001U -#define RCC_APB2RSTR_USART1RST 0x00000010U -#define RCC_APB2RSTR_USART6RST 0x00000020U -#define RCC_APB2RSTR_ADCRST 0x00000100U -#define RCC_APB2RSTR_SDIORST 0x00000800U -#define RCC_APB2RSTR_SPI1RST 0x00001000U -#define RCC_APB2RSTR_SPI4RST 0x00002000U -#define RCC_APB2RSTR_SYSCFGRST 0x00004000U -#define RCC_APB2RSTR_TIM9RST 0x00010000U -#define RCC_APB2RSTR_TIM10RST 0x00020000U -#define RCC_APB2RSTR_TIM11RST 0x00040000U -#define RCC_APB2RSTR_SPI5RST 0x00100000U +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_USART6RST_Pos (5U) +#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk +#define RCC_APB2RSTR_ADCRST_Pos (8U) +#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk +#define RCC_APB2RSTR_SDIORST_Pos (11U) +#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_SYSCFGRST_Pos (14U) +#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (16U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_TIM10RST_Pos (17U) +#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk +#define RCC_APB2RSTR_TIM11RST_Pos (18U) +#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /* Old SPI1RST bit definition, maintained for legacy purpose */ #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST /******************** Bit definition for RCC_AHB1ENR register ***************/ -#define RCC_AHB1ENR_GPIOAEN 0x00000001U -#define RCC_AHB1ENR_GPIOBEN 0x00000002U -#define RCC_AHB1ENR_GPIOCEN 0x00000004U -#define RCC_AHB1ENR_GPIODEN 0x00000008U -#define RCC_AHB1ENR_GPIOEEN 0x00000010U -#define RCC_AHB1ENR_GPIOHEN 0x00000080U -#define RCC_AHB1ENR_CRCEN 0x00001000U -#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U -#define RCC_AHB1ENR_DMA1EN 0x00200000U -#define RCC_AHB1ENR_DMA2EN 0x00400000U - +#define RCC_AHB1ENR_GPIOAEN_Pos (0U) +#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk +#define RCC_AHB1ENR_GPIOBEN_Pos (1U) +#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk +#define RCC_AHB1ENR_GPIOCEN_Pos (2U) +#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk +#define RCC_AHB1ENR_GPIODEN_Pos (3U) +#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk +#define RCC_AHB1ENR_GPIOEEN_Pos (4U) +#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk +#define RCC_AHB1ENR_GPIOHEN_Pos (7U) +#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_DMA1EN_Pos (21U) +#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk +#define RCC_AHB1ENR_DMA2EN_Pos (22U) +#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */ +#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ -#define RCC_AHB2ENR_OTGFSEN 0x00000080U - -/******************** Bit definition for RCC_AHB3ENR register ***************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) + */ +#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ + +#define RCC_AHB2ENR_OTGFSEN_Pos (7U) +#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk /******************** Bit definition for RCC_APB1ENR register ***************/ -#define RCC_APB1ENR_TIM2EN 0x00000001U -#define RCC_APB1ENR_TIM3EN 0x00000002U -#define RCC_APB1ENR_TIM4EN 0x00000004U -#define RCC_APB1ENR_TIM5EN 0x00000008U -#define RCC_APB1ENR_WWDGEN 0x00000800U -#define RCC_APB1ENR_SPI2EN 0x00004000U -#define RCC_APB1ENR_SPI3EN 0x00008000U -#define RCC_APB1ENR_USART2EN 0x00020000U -#define RCC_APB1ENR_I2C1EN 0x00200000U -#define RCC_APB1ENR_I2C2EN 0x00400000U -#define RCC_APB1ENR_I2C3EN 0x00800000U -#define RCC_APB1ENR_PWREN 0x10000000U +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk +#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk +#define RCC_APB1ENR_TIM5EN_Pos (3U) +#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk +#define RCC_APB1ENR_SPI3EN_Pos (15U) +#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk +#define RCC_APB1ENR_I2C3EN_Pos (23U) +#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /******************** Bit definition for RCC_APB2ENR register ***************/ -#define RCC_APB2ENR_TIM1EN 0x00000001U -#define RCC_APB2ENR_USART1EN 0x00000010U -#define RCC_APB2ENR_USART6EN 0x00000020U -#define RCC_APB2ENR_ADC1EN 0x00000100U -#define RCC_APB2ENR_SDIOEN 0x00000800U -#define RCC_APB2ENR_SPI1EN 0x00001000U -#define RCC_APB2ENR_SPI4EN 0x00002000U -#define RCC_APB2ENR_SYSCFGEN 0x00004000U -#define RCC_APB2ENR_TIM9EN 0x00010000U -#define RCC_APB2ENR_TIM10EN 0x00020000U -#define RCC_APB2ENR_TIM11EN 0x00040000U -#define RCC_APB2ENR_SPI5EN 0x00100000U +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_USART6EN_Pos (5U) +#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk +#define RCC_APB2ENR_ADC1EN_Pos (8U) +#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */ +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk +#define RCC_APB2ENR_SDIOEN_Pos (11U) +#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_SYSCFGEN_Pos (14U) +#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (16U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_TIM10EN_Pos (17U) +#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk +#define RCC_APB2ENR_TIM11EN_Pos (18U) +#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /******************** Bit definition for RCC_AHB1LPENR register *************/ -#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U -#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U -#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U -#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U -#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U -#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U -#define RCC_AHB1LPENR_CRCLPEN 0x00001000U -#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U -#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U -#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U -#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U -#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U -#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U +#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk +#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk +#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk +#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk +#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk +#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk +#define RCC_AHB1LPENR_CRCLPEN_Pos (12U) +#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk +#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) +#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk +#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) +#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk +#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) +#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk +#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) +#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk + /******************** Bit definition for RCC_AHB2LPENR register *************/ -#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U +#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) +#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk /******************** Bit definition for RCC_AHB3LPENR register *************/ /******************** Bit definition for RCC_APB1LPENR register *************/ -#define RCC_APB1LPENR_TIM2LPEN 0x00000001U -#define RCC_APB1LPENR_TIM3LPEN 0x00000002U -#define RCC_APB1LPENR_TIM4LPEN 0x00000004U -#define RCC_APB1LPENR_TIM5LPEN 0x00000008U -#define RCC_APB1LPENR_WWDGLPEN 0x00000800U -#define RCC_APB1LPENR_SPI2LPEN 0x00004000U -#define RCC_APB1LPENR_SPI3LPEN 0x00008000U -#define RCC_APB1LPENR_USART2LPEN 0x00020000U -#define RCC_APB1LPENR_I2C1LPEN 0x00200000U -#define RCC_APB1LPENR_I2C2LPEN 0x00400000U -#define RCC_APB1LPENR_I2C3LPEN 0x00800000U -#define RCC_APB1LPENR_PWRLPEN 0x10000000U -#define RCC_APB1LPENR_DACLPEN 0x20000000U +#define RCC_APB1LPENR_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk +#define RCC_APB1LPENR_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk +#define RCC_APB1LPENR_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk +#define RCC_APB1LPENR_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk +#define RCC_APB1LPENR_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk +#define RCC_APB1LPENR_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk +#define RCC_APB1LPENR_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk +#define RCC_APB1LPENR_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk +#define RCC_APB1LPENR_I2C1LPEN_Pos (21U) +#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk +#define RCC_APB1LPENR_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk +#define RCC_APB1LPENR_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk +#define RCC_APB1LPENR_PWRLPEN_Pos (28U) +#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ +#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /******************** Bit definition for RCC_APB2LPENR register *************/ -#define RCC_APB2LPENR_TIM1LPEN 0x00000001U -#define RCC_APB2LPENR_USART1LPEN 0x00000010U -#define RCC_APB2LPENR_USART6LPEN 0x00000020U -#define RCC_APB2LPENR_ADC1LPEN 0x00000100U -#define RCC_APB2LPENR_SDIOLPEN 0x00000800U -#define RCC_APB2LPENR_SPI1LPEN 0x00001000U -#define RCC_APB2LPENR_SPI4LPEN 0x00002000U -#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U -#define RCC_APB2LPENR_TIM9LPEN 0x00010000U -#define RCC_APB2LPENR_TIM10LPEN 0x00020000U -#define RCC_APB2LPENR_TIM11LPEN 0x00040000U -#define RCC_APB2LPENR_SPI5LPEN 0x00100000U +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_USART6LPEN_Pos (5U) +#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk +#define RCC_APB2LPENR_ADC1LPEN_Pos (8U) +#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk +#define RCC_APB2LPENR_SDIOLPEN_Pos (11U) +#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) +#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_TIM10LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk +#define RCC_APB2LPENR_TIM11LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /******************** Bit definition for RCC_BDCR register ******************/ -#define RCC_BDCR_LSEON 0x00000001U -#define RCC_BDCR_LSERDY 0x00000002U -#define RCC_BDCR_LSEBYP 0x00000004U -#define RCC_BDCR_LSEMOD 0x00000008U - -#define RCC_BDCR_RTCSEL 0x00000300U -#define RCC_BDCR_RTCSEL_0 0x00000100U -#define RCC_BDCR_RTCSEL_1 0x00000200U - -#define RCC_BDCR_RTCEN 0x00008000U -#define RCC_BDCR_BDRST 0x00010000U +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEMOD_Pos (3U) +#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /******************** Bit definition for RCC_CSR register *******************/ -#define RCC_CSR_LSION 0x00000001U -#define RCC_CSR_LSIRDY 0x00000002U -#define RCC_CSR_RMVF 0x01000000U -#define RCC_CSR_BORRSTF 0x02000000U -#define RCC_CSR_PADRSTF 0x04000000U -#define RCC_CSR_PORRSTF 0x08000000U -#define RCC_CSR_SFTRSTF 0x10000000U -#define RCC_CSR_WDGRSTF 0x20000000U -#define RCC_CSR_WWDGRSTF 0x40000000U -#define RCC_CSR_LPWRRSTF 0x80000000U +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_BORRSTF_Pos (25U) +#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk +/* Legacy defines */ +#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF +#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF /******************** Bit definition for RCC_SSCGR register *****************/ -#define RCC_SSCGR_MODPER 0x00001FFFU -#define RCC_SSCGR_INCSTEP 0x0FFFE000U -#define RCC_SSCGR_SPREADSEL 0x40000000U -#define RCC_SSCGR_SSCGEN 0x80000000U +#define RCC_SSCGR_MODPER_Pos (0U) +#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk +#define RCC_SSCGR_INCSTEP_Pos (13U) +#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */ +#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk +#define RCC_SSCGR_SPREADSEL_Pos (30U) +#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */ +#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk +#define RCC_SSCGR_SSCGEN_Pos (31U) +#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */ +#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk /******************** Bit definition for RCC_PLLI2SCFGR register ************/ -#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU -#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U -#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U -#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U -#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U -#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U -#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U - -#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U -#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U -#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U -#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U -#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U -#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U -#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U -#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U -#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U -#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U - -#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U -#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U -#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U -#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U +#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U) +#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */ +#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk +#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */ +#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */ +#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */ +#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */ +#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */ +#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */ + +#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) +#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */ +#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk +#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */ +#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */ +#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */ +#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */ +#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */ +#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */ +#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */ +#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */ +#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */ + +#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) +#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */ +#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk +#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */ +#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */ +#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_DCKCFGR register ***************/ -#define RCC_DCKCFGR_TIMPRE 0x01000000U + +#define RCC_DCKCFGR_TIMPRE_Pos (24U) +#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */ +#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk + /******************************************************************************/ /* */ @@ -2561,380 +4638,672 @@ /* */ /******************************************************************************/ /******************** Bits definition for RTC_TR register *******************/ -#define RTC_TR_PM 0x00400000U -#define RTC_TR_HT 0x00300000U -#define RTC_TR_HT_0 0x00100000U -#define RTC_TR_HT_1 0x00200000U -#define RTC_TR_HU 0x000F0000U -#define RTC_TR_HU_0 0x00010000U -#define RTC_TR_HU_1 0x00020000U -#define RTC_TR_HU_2 0x00040000U -#define RTC_TR_HU_3 0x00080000U -#define RTC_TR_MNT 0x00007000U -#define RTC_TR_MNT_0 0x00001000U -#define RTC_TR_MNT_1 0x00002000U -#define RTC_TR_MNT_2 0x00004000U -#define RTC_TR_MNU 0x00000F00U -#define RTC_TR_MNU_0 0x00000100U -#define RTC_TR_MNU_1 0x00000200U -#define RTC_TR_MNU_2 0x00000400U -#define RTC_TR_MNU_3 0x00000800U -#define RTC_TR_ST 0x00000070U -#define RTC_TR_ST_0 0x00000010U -#define RTC_TR_ST_1 0x00000020U -#define RTC_TR_ST_2 0x00000040U -#define RTC_TR_SU 0x0000000FU -#define RTC_TR_SU_0 0x00000001U -#define RTC_TR_SU_1 0x00000002U -#define RTC_TR_SU_2 0x00000004U -#define RTC_TR_SU_3 0x00000008U +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ -#define RTC_DR_YT 0x00F00000U -#define RTC_DR_YT_0 0x00100000U -#define RTC_DR_YT_1 0x00200000U -#define RTC_DR_YT_2 0x00400000U -#define RTC_DR_YT_3 0x00800000U -#define RTC_DR_YU 0x000F0000U -#define RTC_DR_YU_0 0x00010000U -#define RTC_DR_YU_1 0x00020000U -#define RTC_DR_YU_2 0x00040000U -#define RTC_DR_YU_3 0x00080000U -#define RTC_DR_WDU 0x0000E000U -#define RTC_DR_WDU_0 0x00002000U -#define RTC_DR_WDU_1 0x00004000U -#define RTC_DR_WDU_2 0x00008000U -#define RTC_DR_MT 0x00001000U -#define RTC_DR_MU 0x00000F00U -#define RTC_DR_MU_0 0x00000100U -#define RTC_DR_MU_1 0x00000200U -#define RTC_DR_MU_2 0x00000400U -#define RTC_DR_MU_3 0x00000800U -#define RTC_DR_DT 0x00000030U -#define RTC_DR_DT_0 0x00000010U -#define RTC_DR_DT_1 0x00000020U -#define RTC_DR_DU 0x0000000FU -#define RTC_DR_DU_0 0x00000001U -#define RTC_DR_DU_1 0x00000002U -#define RTC_DR_DU_2 0x00000004U -#define RTC_DR_DU_3 0x00000008U +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ -#define RTC_CR_COE 0x00800000U -#define RTC_CR_OSEL 0x00600000U -#define RTC_CR_OSEL_0 0x00200000U -#define RTC_CR_OSEL_1 0x00400000U -#define RTC_CR_POL 0x00100000U -#define RTC_CR_COSEL 0x00080000U -#define RTC_CR_BCK 0x00040000U -#define RTC_CR_SUB1H 0x00020000U -#define RTC_CR_ADD1H 0x00010000U -#define RTC_CR_TSIE 0x00008000U -#define RTC_CR_WUTIE 0x00004000U -#define RTC_CR_ALRBIE 0x00002000U -#define RTC_CR_ALRAIE 0x00001000U -#define RTC_CR_TSE 0x00000800U -#define RTC_CR_WUTE 0x00000400U -#define RTC_CR_ALRBE 0x00000200U -#define RTC_CR_ALRAE 0x00000100U -#define RTC_CR_DCE 0x00000080U -#define RTC_CR_FMT 0x00000040U -#define RTC_CR_BYPSHAD 0x00000020U -#define RTC_CR_REFCKON 0x00000010U -#define RTC_CR_TSEDGE 0x00000008U -#define RTC_CR_WUCKSEL 0x00000007U -#define RTC_CR_WUCKSEL_0 0x00000001U -#define RTC_CR_WUCKSEL_1 0x00000002U -#define RTC_CR_WUCKSEL_2 0x00000004U +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_DCE_Pos (7U) +#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */ +#define RTC_CR_DCE RTC_CR_DCE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/* Legacy defines */ +#define RTC_CR_BCK RTC_CR_BKP /******************** Bits definition for RTC_ISR register ******************/ -#define RTC_ISR_RECALPF 0x00010000U -#define RTC_ISR_TAMP1F 0x00002000U -#define RTC_ISR_TAMP2F 0x00004000U -#define RTC_ISR_TSOVF 0x00001000U -#define RTC_ISR_TSF 0x00000800U -#define RTC_ISR_WUTF 0x00000400U -#define RTC_ISR_ALRBF 0x00000200U -#define RTC_ISR_ALRAF 0x00000100U -#define RTC_ISR_INIT 0x00000080U -#define RTC_ISR_INITF 0x00000040U -#define RTC_ISR_RSF 0x00000020U -#define RTC_ISR_INITS 0x00000010U -#define RTC_ISR_SHPF 0x00000008U -#define RTC_ISR_WUTWF 0x00000004U -#define RTC_ISR_ALRBWF 0x00000002U -#define RTC_ISR_ALRAWF 0x00000001U +#define RTC_ISR_RECALPF_Pos (16U) +#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk +#define RTC_ISR_TAMP1F_Pos (13U) +#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ +#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk +#define RTC_ISR_TAMP2F_Pos (14U) +#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ +#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk +#define RTC_ISR_TSOVF_Pos (12U) +#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ +#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk +#define RTC_ISR_TSF_Pos (11U) +#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ +#define RTC_ISR_TSF RTC_ISR_TSF_Msk +#define RTC_ISR_WUTF_Pos (10U) +#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ +#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk +#define RTC_ISR_ALRBF_Pos (9U) +#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ +#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk +#define RTC_ISR_ALRAF_Pos (8U) +#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ +#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk +#define RTC_ISR_INIT_Pos (7U) +#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ISR_INIT RTC_ISR_INIT_Msk +#define RTC_ISR_INITF_Pos (6U) +#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ISR_INITF RTC_ISR_INITF_Msk +#define RTC_ISR_RSF_Pos (5U) +#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ISR_RSF RTC_ISR_RSF_Msk +#define RTC_ISR_INITS_Pos (4U) +#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ISR_INITS RTC_ISR_INITS_Msk +#define RTC_ISR_SHPF_Pos (3U) +#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk +#define RTC_ISR_WUTWF_Pos (2U) +#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk +#define RTC_ISR_ALRBWF_Pos (1U) +#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk +#define RTC_ISR_ALRAWF_Pos (0U) +#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ -#define RTC_PRER_PREDIV_A 0x007F0000U -#define RTC_PRER_PREDIV_S 0x00007FFFU +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /******************** Bits definition for RTC_WUTR register *****************/ -#define RTC_WUTR_WUT 0x0000FFFFU +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_CALIBR register ***************/ -#define RTC_CALIBR_DCS 0x00000080U -#define RTC_CALIBR_DC 0x0000001FU +#define RTC_CALIBR_DCS_Pos (7U) +#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ +#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk +#define RTC_CALIBR_DC_Pos (0U) +#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ +#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_MSK4 0x80000000U -#define RTC_ALRMAR_WDSEL 0x40000000U -#define RTC_ALRMAR_DT 0x30000000U -#define RTC_ALRMAR_DT_0 0x10000000U -#define RTC_ALRMAR_DT_1 0x20000000U -#define RTC_ALRMAR_DU 0x0F000000U -#define RTC_ALRMAR_DU_0 0x01000000U -#define RTC_ALRMAR_DU_1 0x02000000U -#define RTC_ALRMAR_DU_2 0x04000000U -#define RTC_ALRMAR_DU_3 0x08000000U -#define RTC_ALRMAR_MSK3 0x00800000U -#define RTC_ALRMAR_PM 0x00400000U -#define RTC_ALRMAR_HT 0x00300000U -#define RTC_ALRMAR_HT_0 0x00100000U -#define RTC_ALRMAR_HT_1 0x00200000U -#define RTC_ALRMAR_HU 0x000F0000U -#define RTC_ALRMAR_HU_0 0x00010000U -#define RTC_ALRMAR_HU_1 0x00020000U -#define RTC_ALRMAR_HU_2 0x00040000U -#define RTC_ALRMAR_HU_3 0x00080000U -#define RTC_ALRMAR_MSK2 0x00008000U -#define RTC_ALRMAR_MNT 0x00007000U -#define RTC_ALRMAR_MNT_0 0x00001000U -#define RTC_ALRMAR_MNT_1 0x00002000U -#define RTC_ALRMAR_MNT_2 0x00004000U -#define RTC_ALRMAR_MNU 0x00000F00U -#define RTC_ALRMAR_MNU_0 0x00000100U -#define RTC_ALRMAR_MNU_1 0x00000200U -#define RTC_ALRMAR_MNU_2 0x00000400U -#define RTC_ALRMAR_MNU_3 0x00000800U -#define RTC_ALRMAR_MSK1 0x00000080U -#define RTC_ALRMAR_ST 0x00000070U -#define RTC_ALRMAR_ST_0 0x00000010U -#define RTC_ALRMAR_ST_1 0x00000020U -#define RTC_ALRMAR_ST_2 0x00000040U -#define RTC_ALRMAR_SU 0x0000000FU -#define RTC_ALRMAR_SU_0 0x00000001U -#define RTC_ALRMAR_SU_1 0x00000002U -#define RTC_ALRMAR_SU_2 0x00000004U -#define RTC_ALRMAR_SU_3 0x00000008U +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_MSK4 0x80000000U -#define RTC_ALRMBR_WDSEL 0x40000000U -#define RTC_ALRMBR_DT 0x30000000U -#define RTC_ALRMBR_DT_0 0x10000000U -#define RTC_ALRMBR_DT_1 0x20000000U -#define RTC_ALRMBR_DU 0x0F000000U -#define RTC_ALRMBR_DU_0 0x01000000U -#define RTC_ALRMBR_DU_1 0x02000000U -#define RTC_ALRMBR_DU_2 0x04000000U -#define RTC_ALRMBR_DU_3 0x08000000U -#define RTC_ALRMBR_MSK3 0x00800000U -#define RTC_ALRMBR_PM 0x00400000U -#define RTC_ALRMBR_HT 0x00300000U -#define RTC_ALRMBR_HT_0 0x00100000U -#define RTC_ALRMBR_HT_1 0x00200000U -#define RTC_ALRMBR_HU 0x000F0000U -#define RTC_ALRMBR_HU_0 0x00010000U -#define RTC_ALRMBR_HU_1 0x00020000U -#define RTC_ALRMBR_HU_2 0x00040000U -#define RTC_ALRMBR_HU_3 0x00080000U -#define RTC_ALRMBR_MSK2 0x00008000U -#define RTC_ALRMBR_MNT 0x00007000U -#define RTC_ALRMBR_MNT_0 0x00001000U -#define RTC_ALRMBR_MNT_1 0x00002000U -#define RTC_ALRMBR_MNT_2 0x00004000U -#define RTC_ALRMBR_MNU 0x00000F00U -#define RTC_ALRMBR_MNU_0 0x00000100U -#define RTC_ALRMBR_MNU_1 0x00000200U -#define RTC_ALRMBR_MNU_2 0x00000400U -#define RTC_ALRMBR_MNU_3 0x00000800U -#define RTC_ALRMBR_MSK1 0x00000080U -#define RTC_ALRMBR_ST 0x00000070U -#define RTC_ALRMBR_ST_0 0x00000010U -#define RTC_ALRMBR_ST_1 0x00000020U -#define RTC_ALRMBR_ST_2 0x00000040U -#define RTC_ALRMBR_SU 0x0000000FU -#define RTC_ALRMBR_SU_0 0x00000001U -#define RTC_ALRMBR_SU_1 0x00000002U -#define RTC_ALRMBR_SU_2 0x00000004U -#define RTC_ALRMBR_SU_3 0x00000008U +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ -#define RTC_WPR_KEY 0x000000FFU +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk /******************** Bits definition for RTC_SSR register ******************/ -#define RTC_SSR_SS 0x0000FFFFU +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk /******************** Bits definition for RTC_SHIFTR register ***************/ -#define RTC_SHIFTR_SUBFS 0x00007FFFU -#define RTC_SHIFTR_ADD1S 0x80000000U +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /******************** Bits definition for RTC_TSTR register *****************/ -#define RTC_TSTR_PM 0x00400000U -#define RTC_TSTR_HT 0x00300000U -#define RTC_TSTR_HT_0 0x00100000U -#define RTC_TSTR_HT_1 0x00200000U -#define RTC_TSTR_HU 0x000F0000U -#define RTC_TSTR_HU_0 0x00010000U -#define RTC_TSTR_HU_1 0x00020000U -#define RTC_TSTR_HU_2 0x00040000U -#define RTC_TSTR_HU_3 0x00080000U -#define RTC_TSTR_MNT 0x00007000U -#define RTC_TSTR_MNT_0 0x00001000U -#define RTC_TSTR_MNT_1 0x00002000U -#define RTC_TSTR_MNT_2 0x00004000U -#define RTC_TSTR_MNU 0x00000F00U -#define RTC_TSTR_MNU_0 0x00000100U -#define RTC_TSTR_MNU_1 0x00000200U -#define RTC_TSTR_MNU_2 0x00000400U -#define RTC_TSTR_MNU_3 0x00000800U -#define RTC_TSTR_ST 0x00000070U -#define RTC_TSTR_ST_0 0x00000010U -#define RTC_TSTR_ST_1 0x00000020U -#define RTC_TSTR_ST_2 0x00000040U -#define RTC_TSTR_SU 0x0000000FU -#define RTC_TSTR_SU_0 0x00000001U -#define RTC_TSTR_SU_1 0x00000002U -#define RTC_TSTR_SU_2 0x00000004U -#define RTC_TSTR_SU_3 0x00000008U +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ -#define RTC_TSDR_WDU 0x0000E000U -#define RTC_TSDR_WDU_0 0x00002000U -#define RTC_TSDR_WDU_1 0x00004000U -#define RTC_TSDR_WDU_2 0x00008000U -#define RTC_TSDR_MT 0x00001000U -#define RTC_TSDR_MU 0x00000F00U -#define RTC_TSDR_MU_0 0x00000100U -#define RTC_TSDR_MU_1 0x00000200U -#define RTC_TSDR_MU_2 0x00000400U -#define RTC_TSDR_MU_3 0x00000800U -#define RTC_TSDR_DT 0x00000030U -#define RTC_TSDR_DT_0 0x00000010U -#define RTC_TSDR_DT_1 0x00000020U -#define RTC_TSDR_DU 0x0000000FU -#define RTC_TSDR_DU_0 0x00000001U -#define RTC_TSDR_DU_1 0x00000002U -#define RTC_TSDR_DU_2 0x00000004U -#define RTC_TSDR_DU_3 0x00000008U +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk +#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ -#define RTC_TSSSR_SS 0x0000FFFFU +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CAL register *****************/ -#define RTC_CALR_CALP 0x00008000U -#define RTC_CALR_CALW8 0x00004000U -#define RTC_CALR_CALW16 0x00002000U -#define RTC_CALR_CALM 0x000001FFU -#define RTC_CALR_CALM_0 0x00000001U -#define RTC_CALR_CALM_1 0x00000002U -#define RTC_CALR_CALM_2 0x00000004U -#define RTC_CALR_CALM_3 0x00000008U -#define RTC_CALR_CALM_4 0x00000010U -#define RTC_CALR_CALM_5 0x00000020U -#define RTC_CALR_CALM_6 0x00000040U -#define RTC_CALR_CALM_7 0x00000080U -#define RTC_CALR_CALM_8 0x00000100U +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /******************** Bits definition for RTC_TAFCR register ****************/ -#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U -#define RTC_TAFCR_TSINSEL 0x00020000U -#define RTC_TAFCR_TAMPINSEL 0x00010000U -#define RTC_TAFCR_TAMPPUDIS 0x00008000U -#define RTC_TAFCR_TAMPPRCH 0x00006000U -#define RTC_TAFCR_TAMPPRCH_0 0x00002000U -#define RTC_TAFCR_TAMPPRCH_1 0x00004000U -#define RTC_TAFCR_TAMPFLT 0x00001800U -#define RTC_TAFCR_TAMPFLT_0 0x00000800U -#define RTC_TAFCR_TAMPFLT_1 0x00001000U -#define RTC_TAFCR_TAMPFREQ 0x00000700U -#define RTC_TAFCR_TAMPFREQ_0 0x00000100U -#define RTC_TAFCR_TAMPFREQ_1 0x00000200U -#define RTC_TAFCR_TAMPFREQ_2 0x00000400U -#define RTC_TAFCR_TAMPTS 0x00000080U -#define RTC_TAFCR_TAMP2TRG 0x00000010U -#define RTC_TAFCR_TAMP2E 0x00000008U -#define RTC_TAFCR_TAMPIE 0x00000004U -#define RTC_TAFCR_TAMP1TRG 0x00000002U -#define RTC_TAFCR_TAMP1E 0x00000001U +#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) +#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk +#define RTC_TAFCR_TSINSEL_Pos (17U) +#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */ +#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk +#define RTC_TAFCR_TAMP1INSEL_Pos (16U) +#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */ +#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP2TRG_Pos (4U) +#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ +#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk +#define RTC_TAFCR_TAMP2E_Pos (3U) +#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ +#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Legacy defines */ +#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_MASKSS 0x0F000000U -#define RTC_ALRMASSR_MASKSS_0 0x01000000U -#define RTC_ALRMASSR_MASKSS_1 0x02000000U -#define RTC_ALRMASSR_MASKSS_2 0x04000000U -#define RTC_ALRMASSR_MASKSS_3 0x08000000U -#define RTC_ALRMASSR_SS 0x00007FFFU +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_MASKSS 0x0F000000U -#define RTC_ALRMBSSR_MASKSS_0 0x01000000U -#define RTC_ALRMBSSR_MASKSS_1 0x02000000U -#define RTC_ALRMBSSR_MASKSS_2 0x04000000U -#define RTC_ALRMBSSR_MASKSS_3 0x08000000U -#define RTC_ALRMBSSR_SS 0x00007FFFU +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_BKP0R register ****************/ -#define RTC_BKP0R 0xFFFFFFFFU +#define RTC_BKP0R_Pos (0U) +#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP0R RTC_BKP0R_Msk /******************** Bits definition for RTC_BKP1R register ****************/ -#define RTC_BKP1R 0xFFFFFFFFU +#define RTC_BKP1R_Pos (0U) +#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP1R RTC_BKP1R_Msk /******************** Bits definition for RTC_BKP2R register ****************/ -#define RTC_BKP2R 0xFFFFFFFFU +#define RTC_BKP2R_Pos (0U) +#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP2R RTC_BKP2R_Msk /******************** Bits definition for RTC_BKP3R register ****************/ -#define RTC_BKP3R 0xFFFFFFFFU +#define RTC_BKP3R_Pos (0U) +#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP3R RTC_BKP3R_Msk /******************** Bits definition for RTC_BKP4R register ****************/ -#define RTC_BKP4R 0xFFFFFFFFU +#define RTC_BKP4R_Pos (0U) +#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP4R RTC_BKP4R_Msk /******************** Bits definition for RTC_BKP5R register ****************/ -#define RTC_BKP5R 0xFFFFFFFFU +#define RTC_BKP5R_Pos (0U) +#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP5R RTC_BKP5R_Msk /******************** Bits definition for RTC_BKP6R register ****************/ -#define RTC_BKP6R 0xFFFFFFFFU +#define RTC_BKP6R_Pos (0U) +#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP6R RTC_BKP6R_Msk /******************** Bits definition for RTC_BKP7R register ****************/ -#define RTC_BKP7R 0xFFFFFFFFU +#define RTC_BKP7R_Pos (0U) +#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP7R RTC_BKP7R_Msk /******************** Bits definition for RTC_BKP8R register ****************/ -#define RTC_BKP8R 0xFFFFFFFFU +#define RTC_BKP8R_Pos (0U) +#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP8R RTC_BKP8R_Msk /******************** Bits definition for RTC_BKP9R register ****************/ -#define RTC_BKP9R 0xFFFFFFFFU +#define RTC_BKP9R_Pos (0U) +#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP9R RTC_BKP9R_Msk /******************** Bits definition for RTC_BKP10R register ***************/ -#define RTC_BKP10R 0xFFFFFFFFU +#define RTC_BKP10R_Pos (0U) +#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP10R RTC_BKP10R_Msk /******************** Bits definition for RTC_BKP11R register ***************/ -#define RTC_BKP11R 0xFFFFFFFFU +#define RTC_BKP11R_Pos (0U) +#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP11R RTC_BKP11R_Msk /******************** Bits definition for RTC_BKP12R register ***************/ -#define RTC_BKP12R 0xFFFFFFFFU +#define RTC_BKP12R_Pos (0U) +#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP12R RTC_BKP12R_Msk /******************** Bits definition for RTC_BKP13R register ***************/ -#define RTC_BKP13R 0xFFFFFFFFU +#define RTC_BKP13R_Pos (0U) +#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP13R RTC_BKP13R_Msk /******************** Bits definition for RTC_BKP14R register ***************/ -#define RTC_BKP14R 0xFFFFFFFFU +#define RTC_BKP14R_Pos (0U) +#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP14R RTC_BKP14R_Msk /******************** Bits definition for RTC_BKP15R register ***************/ -#define RTC_BKP15R 0xFFFFFFFFU +#define RTC_BKP15R_Pos (0U) +#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP15R RTC_BKP15R_Msk /******************** Bits definition for RTC_BKP16R register ***************/ -#define RTC_BKP16R 0xFFFFFFFFU +#define RTC_BKP16R_Pos (0U) +#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP16R RTC_BKP16R_Msk /******************** Bits definition for RTC_BKP17R register ***************/ -#define RTC_BKP17R 0xFFFFFFFFU +#define RTC_BKP17R_Pos (0U) +#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP17R RTC_BKP17R_Msk /******************** Bits definition for RTC_BKP18R register ***************/ -#define RTC_BKP18R 0xFFFFFFFFU +#define RTC_BKP18R_Pos (0U) +#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP18R RTC_BKP18R_Msk /******************** Bits definition for RTC_BKP19R register ***************/ -#define RTC_BKP19R 0xFFFFFFFFU - +#define RTC_BKP19R_Pos (0U) +#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define RTC_BKP19R RTC_BKP19R_Msk + +/******************** Number of backup registers ******************************/ +#define RTC_BKP_NUMBER 0x000000014U /******************************************************************************/ @@ -2943,442 +5312,771 @@ /* */ /******************************************************************************/ /****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */ +#define SDIO_POWER_PWRCTRL_Pos (0U) +#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ +#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ +#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ /****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */ -#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */ -#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */ +#define SDIO_CLKCR_CLKDIV_Pos (0U) +#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ +#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */ +#define SDIO_CLKCR_CLKEN_Pos (8U) +#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ +#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */ +#define SDIO_CLKCR_PWRSAV_Pos (9U) +#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ +#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS_Pos (10U) +#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ +#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS_Pos (11U) +#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ +#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ +#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ + +#define SDIO_CLKCR_NEGEDGE_Pos (13U) +#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ +#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN_Pos (14U) +#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ +#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */ /******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */ +#define SDIO_ARG_CMDARG_Pos (0U) +#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */ /******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */ - -#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */ -#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */ - -#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */ -#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */ +#define SDIO_CMD_CMDINDEX_Pos (0U) +#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ +#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */ + +#define SDIO_CMD_WAITRESP_Pos (6U) +#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ +#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ +#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ + +#define SDIO_CMD_WAITINT_Pos (8U) +#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ +#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND_Pos (9U) +#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ +#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN_Pos (10U) +#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ +#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND_Pos (11U) +#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ +#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL_Pos (12U) +#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ +#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */ +#define SDIO_CMD_NIEN_Pos (13U) +#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ +#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD_Pos (14U) +#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ +#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */ /***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */ +#define SDIO_RESPCMD_RESPCMD_Pos (0U) +#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ +#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */ /****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */ +#define SDIO_RESP0_CARDSTATUS0_Pos (0U) +#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */ +#define SDIO_RESP1_CARDSTATUS1_Pos (0U) +#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */ +#define SDIO_RESP2_CARDSTATUS2_Pos (0U) +#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */ +#define SDIO_RESP3_CARDSTATUS3_Pos (0U) +#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */ +#define SDIO_RESP4_CARDSTATUS4_Pos (0U) +#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */ /****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */ +#define SDIO_DTIMER_DATATIME_Pos (0U) +#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */ /****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */ +#define SDIO_DLEN_DATALENGTH_Pos (0U) +#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */ /****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */ - -#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */ -#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */ -#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */ -#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */ +#define SDIO_DCTRL_DTEN_Pos (0U) +#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ +#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR_Pos (1U) +#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ +#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE_Pos (2U) +#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ +#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN_Pos (3U) +#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ +#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) +#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ +#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ + +#define SDIO_DCTRL_RWSTART_Pos (8U) +#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ +#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */ +#define SDIO_DCTRL_RWSTOP_Pos (9U) +#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ +#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */ +#define SDIO_DCTRL_RWMOD_Pos (10U) +#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ +#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */ +#define SDIO_DCTRL_SDIOEN_Pos (11U) +#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ +#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */ /****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */ +#define SDIO_DCOUNT_DATACOUNT_Pos (0U) +#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ +#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */ /****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */ -#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */ -#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */ -#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */ -#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */ -#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */ -#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */ -#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */ -#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */ -#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */ -#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */ -#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */ -#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */ +#define SDIO_STA_CCRCFAIL_Pos (0U) +#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ +#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL_Pos (1U) +#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ +#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT_Pos (2U) +#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ +#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */ +#define SDIO_STA_DTIMEOUT_Pos (3U) +#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ +#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */ +#define SDIO_STA_TXUNDERR_Pos (4U) +#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ +#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR_Pos (5U) +#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ +#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */ +#define SDIO_STA_CMDREND_Pos (6U) +#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ +#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT_Pos (7U) +#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ +#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */ +#define SDIO_STA_DATAEND_Pos (8U) +#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ +#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR_Pos (9U) +#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ +#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND_Pos (10U) +#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ +#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT_Pos (11U) +#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ +#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */ +#define SDIO_STA_TXACT_Pos (12U) +#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ +#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */ +#define SDIO_STA_RXACT_Pos (13U) +#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ +#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */ +#define SDIO_STA_TXFIFOHE_Pos (14U) +#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ +#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF_Pos (15U) +#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ +#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF_Pos (16U) +#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ +#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */ +#define SDIO_STA_RXFIFOF_Pos (17U) +#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ +#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */ +#define SDIO_STA_TXFIFOE_Pos (18U) +#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ +#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE_Pos (19U) +#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ +#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */ +#define SDIO_STA_TXDAVL_Pos (20U) +#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ +#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL_Pos (21U) +#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ +#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */ +#define SDIO_STA_SDIOIT_Pos (22U) +#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ +#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */ +#define SDIO_STA_CEATAEND_Pos (23U) +#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ +#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */ /******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */ +#define SDIO_ICR_CCRCFAILC_Pos (0U) +#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ +#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC_Pos (1U) +#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ +#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC_Pos (2U) +#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ +#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC_Pos (3U) +#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ +#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC_Pos (4U) +#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ +#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC_Pos (5U) +#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ +#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC_Pos (6U) +#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ +#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC_Pos (7U) +#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ +#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC_Pos (8U) +#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ +#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC_Pos (9U) +#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ +#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC_Pos (10U) +#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ +#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC_Pos (22U) +#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ +#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC_Pos (23U) +#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ +#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */ /****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */ +#define SDIO_MASK_CCRCFAILIE_Pos (0U) +#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ +#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE_Pos (1U) +#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ +#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE_Pos (2U) +#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ +#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE_Pos (3U) +#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ +#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE_Pos (4U) +#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ +#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE_Pos (5U) +#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ +#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE_Pos (6U) +#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ +#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE_Pos (7U) +#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ +#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE_Pos (8U) +#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ +#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE_Pos (9U) +#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ +#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE_Pos (10U) +#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ +#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE_Pos (11U) +#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ +#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE_Pos (12U) +#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ +#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE_Pos (13U) +#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ +#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE_Pos (14U) +#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ +#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE_Pos (15U) +#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ +#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE_Pos (16U) +#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ +#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE_Pos (17U) +#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ +#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE_Pos (18U) +#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ +#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE_Pos (19U) +#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ +#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE_Pos (20U) +#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ +#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE_Pos (21U) +#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ +#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE_Pos (22U) +#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ +#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE_Pos (23U) +#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ +#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */ /***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */ +#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) +#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ +#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */ /****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */ +#define SDIO_FIFO_FIFODATA_Pos (0U) +#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ +#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */ /******************************************************************************/ /* */ /* Serial Peripheral Interface */ /* */ /******************************************************************************/ +#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */ + /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */ -#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */ -#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */ - -#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */ -#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */ -#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */ - -#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */ -#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */ -#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */ -#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */ -#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */ -#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */ -#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */ -#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ + +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ + +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */ -#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */ -#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */ -#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */ -#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */ -#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */ -#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */ -#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */ -#define SPI_SR_MODF 0x00000020U /*!<Mode fault */ -#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */ -#define SPI_SR_BSY 0x00000080U /*!<Busy flag */ -#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ /******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */ - -#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */ - -#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */ -#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */ +#define SPI_I2SCFGR_CHLEN_Pos (0U) +#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN_Pos (1U) +#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCFGR_CKPOL_Pos (3U) +#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD_Pos (4U) +#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ +#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ +#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCFGR_PCMSYNC_Pos (7U) +#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ +#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG_Pos (8U) +#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ +#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ +#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCFGR_I2SE_Pos (10U) +#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ +#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ +#define SPI_I2SCFGR_I2SMOD_Pos (11U) +#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ +#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ /****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */ -#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */ +#define SPI_I2SPR_I2SDIV_Pos (0U) +#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ +#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ +#define SPI_I2SPR_ODD_Pos (8U) +#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE_Pos (9U) +#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ /******************************************************************************/ /* */ /* SYSCFG */ /* */ /******************************************************************************/ -/****************** Bit definition for SYSCFG_MEMRMP register ***************/ -#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */ -#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U -#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U -#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U - +/****************** Bit definition for SYSCFG_MEMRMP register ***************/ +#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) +#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ +#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ +#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ /****************** Bit definition for SYSCFG_PMC register ******************/ -#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */ +#define SYSCFG_PMC_ADC1DC2_Pos (16U) +#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */ +#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */ /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ -#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */ -/** +#define SYSCFG_EXTICR1_EXTI0_Pos (0U) +#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1_Pos (4U) +#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2_Pos (8U) +#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3_Pos (12U) +#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ +/** * @brief EXTI0 configuration - */ -#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */ - -/** + */ +#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */ + +/** * @brief EXTI1 configuration - */ -#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */ - -/** + */ +#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */ + +/** * @brief EXTI2 configuration - */ -#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */ - -/** + */ +#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */ + +/** * @brief EXTI3 configuration - */ -#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */ + */ +#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ -#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */ -/** +#define SYSCFG_EXTICR2_EXTI4_Pos (0U) +#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5_Pos (4U) +#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6_Pos (8U) +#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7_Pos (12U) +#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ + +/** * @brief EXTI4 configuration - */ -#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */ - -/** + */ +#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */ + +/** * @brief EXTI5 configuration - */ -#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */ - -/** + */ +#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */ + +/** * @brief EXTI6 configuration - */ -#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */ - -/** + */ +#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */ + +/** * @brief EXTI7 configuration - */ -#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */ - + */ +#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ -#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */ - -/** +#define SYSCFG_EXTICR3_EXTI8_Pos (0U) +#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9_Pos (4U) +#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10_Pos (8U) +#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11_Pos (12U) +#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ + +/** * @brief EXTI8 configuration - */ -#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */ - -/** + */ +#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */ + +/** * @brief EXTI9 configuration - */ -#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */ - -/** + */ +#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */ + +/** * @brief EXTI10 configuration - */ -#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */ - -/** + */ +#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */ + +/** * @brief EXTI11 configuration - */ -#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */ + */ +#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ -#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */ -/** +#define SYSCFG_EXTICR4_EXTI12_Pos (0U) +#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13_Pos (4U) +#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14_Pos (8U) +#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15_Pos (12U) +#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ + +/** * @brief EXTI12 configuration - */ -#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */ - -/** + */ +#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */ + +/** * @brief EXTI13 configuration - */ -#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */ - -/** + */ +#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */ + +/** * @brief EXTI14 configuration - */ -#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */ - -/** + */ +#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */ + +/** * @brief EXTI15 configuration - */ -#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */ - -/****************** Bit definition for SYSCFG_CMPCR register ****************/ -#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */ -#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */ + */ +#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */ + +/****************** Bit definition for SYSCFG_CMPCR register ****************/ +#define SYSCFG_CMPCR_CMP_PD_Pos (0U) +#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */ +#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */ +#define SYSCFG_CMPCR_READY_Pos (8U) +#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ +#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ /******************************************************************************/ /* */ @@ -3386,298 +6084,556 @@ /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN 0x0001U /*!<Counter enable */ -#define TIM_CR1_UDIS 0x0002U /*!<Update disable */ -#define TIM_CR1_URS 0x0004U /*!<Update request source */ -#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */ -#define TIM_CR1_DIR 0x0010U /*!<Direction */ - -#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */ -#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */ - -#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */ - -#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */ -#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ +#define TIM_CR1_UDIS_Pos (1U) +#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ +#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ +#define TIM_CR1_URS_Pos (2U) +#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ +#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ +#define TIM_CR1_OPM_Pos (3U) +#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ +#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ +#define TIM_CR1_DIR_Pos (4U) +#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ +#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ + +#define TIM_CR1_CMS_Pos (5U) +#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ +#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */ +#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */ + +#define TIM_CR1_ARPE_Pos (7U) +#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ +#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ + +#define TIM_CR1_CKD_Pos (8U) +#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ +#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */ +#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */ /******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */ -#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */ -#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */ - -#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */ -#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */ +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ +#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ +#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ +#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS_Pos (4U) +#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ +#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */ +#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */ +#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */ + +#define TIM_CR2_TI1S_Pos (7U) +#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ +#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ +#define TIM_CR2_OIS1_Pos (8U) +#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ +#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N_Pos (9U) +#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ +#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2_Pos (10U) +#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ +#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N_Pos (11U) +#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ +#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3_Pos (12U) +#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ +#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N_Pos (13U) +#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ +#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4_Pos (14U) +#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ +#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ /******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */ -#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */ -#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */ - -#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */ -#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */ -#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */ - -#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */ - -#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */ -#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */ -#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */ -#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */ - -#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */ -#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */ - -#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */ -#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */ +#define TIM_SMCR_SMS_Pos (0U) +#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ +#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */ +#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */ +#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */ + +#define TIM_SMCR_TS_Pos (4U) +#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ +#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */ +#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */ +#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */ + +#define TIM_SMCR_MSM_Pos (7U) +#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ +#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ + +#define TIM_SMCR_ETF_Pos (8U) +#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ +#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */ +#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */ +#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */ +#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */ + +#define TIM_SMCR_ETPS_Pos (12U) +#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ +#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */ +#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */ + +#define TIM_SMCR_ECE_Pos (14U) +#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ +#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ +#define TIM_SMCR_ETP_Pos (15U) +#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ +#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ /******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */ -#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */ -#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */ -#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */ -#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */ -#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */ -#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */ +#define TIM_DIER_UIE_Pos (0U) +#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ +#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ +#define TIM_DIER_CC1IE_Pos (1U) +#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ +#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE_Pos (2U) +#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ +#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE_Pos (3U) +#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ +#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE_Pos (4U) +#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ +#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE_Pos (5U) +#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ +#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ +#define TIM_DIER_TIE_Pos (6U) +#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ +#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ +#define TIM_DIER_BIE_Pos (7U) +#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ +#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ +#define TIM_DIER_UDE_Pos (8U) +#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ +#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ +#define TIM_DIER_CC1DE_Pos (9U) +#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ +#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE_Pos (10U) +#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ +#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE_Pos (11U) +#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ +#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE_Pos (12U) +#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ +#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE_Pos (13U) +#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ +#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ +#define TIM_DIER_TDE_Pos (14U) +#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ +#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ /******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */ -#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */ -#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */ -#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */ -#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */ +#define TIM_SR_UIF_Pos (0U) +#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ +#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ +#define TIM_SR_CC1IF_Pos (1U) +#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ +#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF_Pos (2U) +#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ +#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF_Pos (3U) +#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ +#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF_Pos (4U) +#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ +#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF_Pos (5U) +#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ +#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ +#define TIM_SR_TIF_Pos (6U) +#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ +#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ +#define TIM_SR_BIF_Pos (7U) +#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ +#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ +#define TIM_SR_CC1OF_Pos (9U) +#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ +#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF_Pos (10U) +#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ +#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF_Pos (11U) +#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ +#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF_Pos (12U) +#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ +#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ /******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG 0x01U /*!<Update Generation */ -#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */ -#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */ -#define TIM_EGR_TG 0x40U /*!<Trigger Generation */ -#define TIM_EGR_BG 0x80U /*!<Break Generation */ +#define TIM_EGR_UG_Pos (0U) +#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ +#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ +#define TIM_EGR_CC1G_Pos (1U) +#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ +#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G_Pos (2U) +#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ +#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G_Pos (3U) +#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ +#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G_Pos (4U) +#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ +#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ +#define TIM_EGR_COMG_Pos (5U) +#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ +#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ +#define TIM_EGR_TG_Pos (6U) +#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ +#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ +#define TIM_EGR_BG_Pos (7U) +#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ +#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ /****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */ -#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */ - -#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */ -#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */ -#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */ - -#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */ -#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */ - -#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */ -#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */ -#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */ - -#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */ +#define TIM_CCMR1_CC1S_Pos (0U) +#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ +#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */ +#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */ + +#define TIM_CCMR1_OC1FE_Pos (2U) +#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE_Pos (3U) +#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M_Pos (4U) +#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ +#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */ +#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */ +#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */ + +#define TIM_CCMR1_OC1CE_Pos (7U) +#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S_Pos (8U) +#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ +#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */ +#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */ + +#define TIM_CCMR1_OC2FE_Pos (10U) +#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE_Pos (11U) +#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M_Pos (12U) +#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ +#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */ +#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */ +#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */ + +#define TIM_CCMR1_OC2CE_Pos (15U) +#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ /*----------------------------------------------------------------------------*/ -#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */ - -#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */ -#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */ -#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */ -#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */ - -#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */ - -#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */ -#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */ -#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */ -#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */ +#define TIM_CCMR1_IC1PSC_Pos (2U) +#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ +#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */ +#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */ + +#define TIM_CCMR1_IC1F_Pos (4U) +#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ +#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */ +#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */ +#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */ +#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */ + +#define TIM_CCMR1_IC2PSC_Pos (10U) +#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ +#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */ +#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */ + +#define TIM_CCMR1_IC2F_Pos (12U) +#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ +#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */ +#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */ +#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */ +#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */ /****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */ -#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */ - -#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */ -#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */ -#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */ - -#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */ -#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */ - -#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */ -#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */ -#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */ - -#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */ +#define TIM_CCMR2_CC3S_Pos (0U) +#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ +#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */ +#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */ + +#define TIM_CCMR2_OC3FE_Pos (2U) +#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE_Pos (3U) +#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M_Pos (4U) +#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ +#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */ +#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */ +#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */ + +#define TIM_CCMR2_OC3CE_Pos (7U) +#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S_Pos (8U) +#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ +#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */ +#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */ + +#define TIM_CCMR2_OC4FE_Pos (10U) +#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE_Pos (11U) +#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M_Pos (12U) +#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ +#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */ +#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */ +#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */ + +#define TIM_CCMR2_OC4CE_Pos (15U) +#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ /*----------------------------------------------------------------------------*/ -#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */ - -#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */ -#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */ -#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */ -#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */ - -#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */ - -#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */ -#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */ -#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */ -#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */ +#define TIM_CCMR2_IC3PSC_Pos (2U) +#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ +#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */ +#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */ + +#define TIM_CCMR2_IC3F_Pos (4U) +#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ +#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */ +#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */ +#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */ +#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */ + +#define TIM_CCMR2_IC4PSC_Pos (10U) +#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ +#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */ +#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */ + +#define TIM_CCMR2_IC4F_Pos (12U) +#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ +#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */ +#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */ +#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */ +#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */ /******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */ -#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */ +#define TIM_CCER_CC1E_Pos (0U) +#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ +#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P_Pos (1U) +#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ +#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE_Pos (2U) +#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ +#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP_Pos (3U) +#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ +#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E_Pos (4U) +#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ +#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P_Pos (5U) +#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ +#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE_Pos (6U) +#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ +#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP_Pos (7U) +#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ +#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E_Pos (8U) +#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ +#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P_Pos (9U) +#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ +#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE_Pos (10U) +#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ +#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP_Pos (11U) +#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ +#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E_Pos (12U) +#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ +#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P_Pos (13U) +#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ +#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP_Pos (15U) +#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ +#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ /******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */ +#define TIM_CNT_CNT_Pos (0U) +#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ /******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */ +#define TIM_PSC_PSC_Pos (0U) +#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ +#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ /******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */ +#define TIM_ARR_ARR_Pos (0U) +#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ +#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ /******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */ +#define TIM_RCR_REP_Pos (0U) +#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ +#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ /******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */ +#define TIM_CCR1_CCR1_Pos (0U) +#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ /******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */ +#define TIM_CCR2_CCR2_Pos (0U) +#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ /******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */ +#define TIM_CCR3_CCR3_Pos (0U) +#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ /******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */ +#define TIM_CCR4_CCR4_Pos (0U) +#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ /******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */ -#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */ -#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */ -#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */ -#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */ -#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */ -#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */ -#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */ - -#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */ -#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */ - -#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */ -#define TIM_BDTR_BKE 0x1000U /*!<Break enable */ -#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */ -#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */ -#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */ +#define TIM_BDTR_DTG_Pos (0U) +#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ +#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */ +#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */ +#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */ +#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */ +#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */ +#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */ +#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */ +#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */ + +#define TIM_BDTR_LOCK_Pos (8U) +#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ +#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */ +#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */ + +#define TIM_BDTR_OSSI_Pos (10U) +#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ +#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR_Pos (11U) +#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ +#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ +#define TIM_BDTR_BKE_Pos (12U) +#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ +#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ +#define TIM_BDTR_BKP_Pos (13U) +#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ +#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ +#define TIM_BDTR_AOE_Pos (14U) +#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ +#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ +#define TIM_BDTR_MOE_Pos (15U) +#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ +#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ /******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */ -#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */ -#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */ -#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */ -#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */ - -#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */ -#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */ -#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */ -#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */ -#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */ +#define TIM_DCR_DBA_Pos (0U) +#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ +#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */ +#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */ +#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */ +#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */ +#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */ + +#define TIM_DCR_DBL_Pos (8U) +#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ +#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */ +#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */ +#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */ +#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */ +#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */ /******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */ +#define TIM_DMAR_DMAB_Pos (0U) +#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ +#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ /******************* Bit definition for TIM_OR register *********************/ -#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ -#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */ -#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */ -#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ -#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */ -#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */ +#define TIM_OR_TI1_RMP_Pos (0U) +#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */ +#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */ +#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */ +#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */ + +#define TIM_OR_TI4_RMP_Pos (6U) +#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */ +#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ +#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */ +#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */ +#define TIM_OR_ITR1_RMP_Pos (10U) +#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */ +#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ +#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */ +#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */ /******************************************************************************/ @@ -3686,82 +6642,184 @@ /* */ /******************************************************************************/ /******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE 0x0001U /*!<Parity Error */ -#define USART_SR_FE 0x0002U /*!<Framing Error */ -#define USART_SR_NE 0x0004U /*!<Noise Error Flag */ -#define USART_SR_ORE 0x0008U /*!<OverRun Error */ -#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */ -#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */ -#define USART_SR_TC 0x0040U /*!<Transmission Complete */ -#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */ -#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */ -#define USART_SR_CTS 0x0200U /*!<CTS Flag */ +#define USART_SR_PE_Pos (0U) +#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ +#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */ +#define USART_SR_FE_Pos (1U) +#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ +#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */ +#define USART_SR_NE_Pos (2U) +#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ +#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */ +#define USART_SR_ORE_Pos (3U) +#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ +#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */ +#define USART_SR_IDLE_Pos (4U) +#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ +#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */ +#define USART_SR_RXNE_Pos (5U) +#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ +#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */ +#define USART_SR_TC_Pos (6U) +#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ +#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */ +#define USART_SR_TXE_Pos (7U) +#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ +#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */ +#define USART_SR_LBD_Pos (8U) +#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ +#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */ +#define USART_SR_CTS_Pos (9U) +#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ +#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */ /******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR 0x01FFU /*!<Data value */ +#define USART_DR_DR_Pos (0U) +#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ +#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */ /****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */ +#define USART_BRR_DIV_Fraction_Pos (0U) +#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ +#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa_Pos (4U) +#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ +#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */ /****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK 0x0001U /*!<Send Break */ -#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */ -#define USART_CR1_RE 0x0004U /*!<Receiver Enable */ -#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */ -#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */ -#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */ -#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */ -#define USART_CR1_PS 0x0200U /*!<Parity Selection */ -#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */ -#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */ -#define USART_CR1_M 0x1000U /*!<Word length */ -#define USART_CR1_UE 0x2000U /*!<USART Enable */ -#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */ +#define USART_CR1_SBK_Pos (0U) +#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ +#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */ +#define USART_CR1_RWU_Pos (1U) +#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ +#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */ +#define USART_CR1_RE_Pos (2U) +#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ +#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */ +#define USART_CR1_TE_Pos (3U) +#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ +#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */ +#define USART_CR1_IDLEIE_Pos (4U) +#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ +#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE_Pos (5U) +#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ +#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */ +#define USART_CR1_TCIE_Pos (6U) +#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE_Pos (7U) +#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_PEIE_Pos (8U) +#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ +#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_PS_Pos (9U) +#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ +#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */ +#define USART_CR1_PCE_Pos (10U) +#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ +#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */ +#define USART_CR1_WAKE_Pos (11U) +#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ +#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */ +#define USART_CR1_M_Pos (12U) +#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ +#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */ +#define USART_CR1_UE_Pos (13U) +#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ +#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */ +#define USART_CR1_OVER8_Pos (15U) +#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ +#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */ /****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */ -#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */ -#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */ -#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */ -#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */ -#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */ - -#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */ -#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */ - -#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */ +#define USART_CR2_ADD_Pos (0U) +#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ +#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */ +#define USART_CR2_LBDL_Pos (5U) +#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ +#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */ +#define USART_CR2_LBDIE_Pos (6U) +#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ +#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL_Pos (8U) +#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ +#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */ +#define USART_CR2_CPHA_Pos (9U) +#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ +#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */ +#define USART_CR2_CPOL_Pos (10U) +#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ +#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */ +#define USART_CR2_CLKEN_Pos (11U) +#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */ + +#define USART_CR2_STOP_Pos (12U) +#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ +#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */ +#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */ + +#define USART_CR2_LINEN_Pos (14U) +#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */ /****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */ -#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */ -#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */ -#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */ -#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */ -#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */ -#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */ -#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */ -#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */ -#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */ -#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */ -#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */ +#define USART_CR3_EIE_Pos (0U) +#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ +#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */ +#define USART_CR3_IREN_Pos (1U) +#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ +#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */ +#define USART_CR3_IRLP_Pos (2U) +#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ +#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */ +#define USART_CR3_HDSEL_Pos (3U) +#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ +#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */ +#define USART_CR3_NACK_Pos (4U) +#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ +#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */ +#define USART_CR3_SCEN_Pos (5U) +#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ +#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */ +#define USART_CR3_DMAR_Pos (6U) +#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ +#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */ +#define USART_CR3_DMAT_Pos (7U) +#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ +#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */ +#define USART_CR3_RTSE_Pos (8U) +#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ +#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */ +#define USART_CR3_CTSE_Pos (9U) +#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ +#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */ +#define USART_CR3_CTSIE_Pos (10U) +#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ +#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */ +#define USART_CR3_ONEBIT_Pos (11U) +#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ +#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */ /****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */ -#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */ -#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */ -#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */ -#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */ -#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */ -#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */ -#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */ - -#define USART_GTPR_GT 0xFF00U /*!<Guard time value */ +#define USART_GTPR_PSC_Pos (0U) +#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ +#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */ +#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */ +#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */ +#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */ +#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */ +#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */ +#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */ +#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */ + +#define USART_GTPR_GT_Pos (8U) +#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ +#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */ /******************************************************************************/ /* */ @@ -3769,14 +6827,16 @@ /* */ /******************************************************************************/ /******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T_0 0x01U /*!<Bit 0 */ -#define WWDG_CR_T_1 0x02U /*!<Bit 1 */ -#define WWDG_CR_T_2 0x04U /*!<Bit 2 */ -#define WWDG_CR_T_3 0x08U /*!<Bit 3 */ -#define WWDG_CR_T_4 0x10U /*!<Bit 4 */ -#define WWDG_CR_T_5 0x20U /*!<Bit 5 */ -#define WWDG_CR_T_6 0x40U /*!<Bit 6 */ +#define WWDG_CR_T_Pos (0U) +#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ +#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */ +#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */ +#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */ +#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */ +#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */ +#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */ +#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */ /* Legacy defines */ #define WWDG_CR_T0 WWDG_CR_T_0 #define WWDG_CR_T1 WWDG_CR_T_1 @@ -3786,17 +6846,21 @@ #define WWDG_CR_T5 WWDG_CR_T_5 #define WWDG_CR_T6 WWDG_CR_T_6 -#define WWDG_CR_WDGA 0x80U /*!<Activation bit */ +#define WWDG_CR_WDGA_Pos (7U) +#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ +#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ /******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */ -#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */ -#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */ -#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */ -#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */ -#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */ -#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */ +#define WWDG_CFR_W_Pos (0U) +#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ +#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */ +#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */ +#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */ +#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */ +#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */ +#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */ +#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */ /* Legacy defines */ #define WWDG_CFR_W0 WWDG_CFR_W_0 #define WWDG_CFR_W1 WWDG_CFR_W_1 @@ -3806,17 +6870,23 @@ #define WWDG_CFR_W5 WWDG_CFR_W_5 #define WWDG_CFR_W6 WWDG_CFR_W_6 -#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */ -#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */ +#define WWDG_CFR_WDGTB_Pos (7U) +#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ +#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */ +#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */ /* Legacy defines */ #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 -#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */ +#define WWDG_CFR_EWI_Pos (9U) +#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ +#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ /******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */ +#define WWDG_SR_EWIF_Pos (0U) +#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ +#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ /******************************************************************************/ @@ -3825,701 +6895,1386 @@ /* */ /******************************************************************************/ /******************** Bit definition for DBGMCU_IDCODE register *************/ -#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU -#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /******************** Bit definition for DBGMCU_CR register *****************/ -#define DBGMCU_CR_DBG_SLEEP 0x00000001U -#define DBGMCU_CR_DBG_STOP 0x00000002U -#define DBGMCU_CR_DBG_STANDBY 0x00000004U -#define DBGMCU_CR_TRACE_IOEN 0x00000020U - -#define DBGMCU_CR_TRACE_MODE 0x000000C0U -#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk +#define DBGMCU_CR_TRACE_IOEN_Pos (5U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk + +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk +#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ /******************** Bit definition for DBGMCU_APB1_FZ register ************/ -#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U -#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U -#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U -#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U -#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U -#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U -#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U -#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U -#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U -#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U -#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U -#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U -#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U -#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U -#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U -#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U -#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) +#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ +#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) +#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ +#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk +#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) +#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk +#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) +#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */ +#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk /* Old IWDGSTOP bit definition, maintained for legacy purpose */ #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /******************** Bit definition for DBGMCU_APB2_FZ register ************/ -#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U -#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U -#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U -#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U -#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) +#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk +#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) +#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk +#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) +#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /******************************************************************************/ /* */ -/* USB_OTG */ +/* USB_OTG */ /* */ /******************************************************************************/ -/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/ -#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */ -#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */ -#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */ -#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */ -#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */ -#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */ -#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */ -#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */ -#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */ +/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ -#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */ -#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */ - -/******************** Bit definition forUSB_OTG_DCFG register ********************/ - -#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */ -#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */ - -#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */ -#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */ -#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */ -#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */ -#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */ -#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */ -#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */ -#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */ - -#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */ -#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */ -#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */ - -#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */ -#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */ -#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */ - -/******************** Bit definition forUSB_OTG_PCGCR register ********************/ -#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */ -#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */ -#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */ - -/******************** Bit definition forUSB_OTG_GOTGINT register ********************/ -#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */ -#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */ -#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */ -#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */ -#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */ -#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */ - -/******************** Bit definition forUSB_OTG_DCTL register ********************/ -#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */ -#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */ -#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */ -#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */ - -#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */ -#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */ -#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */ -#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */ -#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */ -#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */ -#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */ -#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */ -#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */ - -/******************** Bit definition forUSB_OTG_HFIR register ********************/ -#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */ - -/******************** Bit definition forUSB_OTG_HFNUM register ********************/ -#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */ -#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */ - -/******************** Bit definition forUSB_OTG_DSTS register ********************/ -#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */ - -#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */ -#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */ -#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */ -#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */ -#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */ - -/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */ - -#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */ -#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */ -#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */ -#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */ -#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */ -#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */ -#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */ -#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */ - -/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/ - -#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */ -#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */ -#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */ -#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */ - -#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */ -#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */ -#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */ -#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */ -#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */ -#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */ -#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */ -#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */ -#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */ -#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */ -#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */ -#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */ -#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */ -#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */ -#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */ -#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */ - -/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ -#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */ -#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */ -#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */ -#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */ - -#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */ -#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */ -#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */ -#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */ -#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */ -#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */ -#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */ -#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */ - -/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/ -#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */ -#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */ - -/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/ -#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */ - -#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */ -#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */ -#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */ -#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */ -#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */ -#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */ -#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */ -#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */ - -#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */ -#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */ -#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */ -#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */ -#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */ -#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */ -#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */ -#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */ -#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */ - -/******************** Bit definition forUSB_OTG_HAINT register ********************/ -#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */ - -/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/ -#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */ -#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */ -#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */ -#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */ - -/******************** Bit definition forUSB_OTG_GINTSTS register ********************/ -#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */ -#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */ -#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */ -#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */ -#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */ -#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */ -#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */ -#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */ -#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */ -#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */ -#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */ -#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */ -#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */ -#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */ -#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */ -#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */ -#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */ -#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */ -#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */ -#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */ -#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */ -#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */ -#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */ - -/******************** Bit definition forUSB_OTG_GINTMSK register ********************/ -#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */ -#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */ -#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */ -#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */ -#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */ -#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */ -#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */ -#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */ -#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */ -#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */ -#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */ -#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */ -#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */ -#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */ -#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */ -#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */ -#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */ -#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */ -#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */ -#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */ -#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */ -#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */ -#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */ - -/******************** Bit definition forUSB_OTG_DAINT register ********************/ -#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */ -#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */ - -/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/ -#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */ +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ + + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */ - -/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/ -#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */ -#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for OTG register ********************/ -#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */ -#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */ -#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */ -#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */ - -#define USB_OTG_DPID 0x00018000U /*!< Data PID */ -#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */ -#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */ - -#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */ -#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */ -#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */ -#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */ -#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */ - -#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */ -#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */ - -#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */ -#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */ -#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */ -#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */ -#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /******************** Bit definition for OTG register ********************/ -#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */ -#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */ -#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */ -#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */ - -#define USB_OTG_DPID 0x00018000U /*!< Data PID */ -#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */ -#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */ - -#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */ -#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */ -#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */ -#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */ -#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */ - -#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */ -#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */ - -#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */ -#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */ -#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */ -#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */ -#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */ - -/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/ -#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */ - -/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/ -#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ -#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */ -#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */ -#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */ -#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ -#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */ - -/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/ -#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */ - -#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */ - -#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */ - -/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/ -#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */ -#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */ - -#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */ -#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */ -#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */ - -#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */ -#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */ -#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */ - -/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */ - -/******************** Bit definition forUSB_OTG_DEACHINT register ********************/ -#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */ -#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */ - -/******************** Bit definition forUSB_OTG_GCCFG register ********************/ -#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */ -#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */ -#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */ -#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_I2CPADEN_Pos (17U) +#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ +#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U) +#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/ /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ -#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */ -#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */ - -/******************** Bit definition forUSB_OTG_CID register ********************/ -#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */ - -/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/ -#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */ -#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */ - -/******************** Bit definition forUSB_OTG_HPRT register ********************/ -#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */ -#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */ -#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */ -#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */ -#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */ -#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */ -#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */ -#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */ -#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */ - -#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */ -#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */ -#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */ -#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */ - -#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */ -#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */ -#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */ -#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */ -#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */ - -#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */ -#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */ -#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */ - -/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/ -#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */ -#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */ - -/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/ -#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */ - -/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/ -#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ -#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */ -#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */ -#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */ - -#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */ -#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */ -#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */ -#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */ - -#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */ -#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */ -#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */ -#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */ -#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */ -#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */ -#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */ -#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */ -#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */ - -/******************** Bit definition forUSB_OTG_HCCHAR register ********************/ -#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */ - -#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */ -#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */ -#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */ -#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */ -#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */ -#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */ -#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */ - -#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */ -#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */ -#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */ - -#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */ -#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */ - -#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */ -#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */ -#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */ -#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */ -#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */ -#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */ -#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */ -#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */ -#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */ -#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */ -#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */ - -/******************** Bit definition forUSB_OTG_HCSPLT register ********************/ - -#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */ -#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */ -#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */ -#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */ -#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */ -#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */ -#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */ -#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */ - -#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */ -#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */ -#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */ -#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */ -#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */ -#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */ -#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */ -#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */ - -#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */ -#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */ -#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */ -#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */ -#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */ - -/******************** Bit definition forUSB_OTG_HCINT register ********************/ -#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */ -#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */ -#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */ -#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */ -#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */ -#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */ -#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */ -#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */ -#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */ -#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */ -#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */ - -/******************** Bit definition forUSB_OTG_DIEPINT register ********************/ -#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */ -#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */ -#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */ -#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */ -#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */ -#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */ -#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */ -#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */ -#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */ -#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */ -#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ -#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */ -#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */ -#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */ -#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */ -#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */ -#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */ -#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */ -#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */ -#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */ -#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ -#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */ -#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */ -/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/ -#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */ -#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */ -#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */ -#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */ -#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */ - -/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/ -#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */ - -/******************** Bit definition forUSB_OTG_HCDMA register ********************/ -#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */ - -/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/ -#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */ - -/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/ -#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */ -#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */ - -/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/ - -#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */ -#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */ -#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */ -#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */ -#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */ -#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */ -#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */ -#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */ -#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */ -#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */ -#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */ -#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */ - -/******************** Bit definition forUSB_OTG_DOEPINT register ********************/ -#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */ -#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */ -#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */ -#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */ -#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */ -#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */ - -/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/ - -#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */ -#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */ - -#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */ +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ +#define USB_OTG_DOEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DOEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DOEPCTL_SNPM_Pos (20U) +#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ +#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ +#define USB_OTG_DOEPCTL_STALL_Pos (21U) +#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ +#define USB_OTG_DOEPCTL_CNAK_Pos (26U) +#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DOEPCTL_SNAK_Pos (27U) +#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DOEPCTL_EPENA_Pos (31U) +#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_DOEPINT register ********************/ +#define USB_OTG_DOEPINT_XFRC_Pos (0U) +#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DOEPINT_EPDISD_Pos (1U) +#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_STUP_Pos (3U) +#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ +#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) +#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_NYET_Pos (14U) +#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ + +/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ + +#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ + +#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) +#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */ -#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */ +#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) +#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ +#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) +#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ +#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ /** * @} @@ -4532,13 +8287,15 @@ /** @addtogroup Exported_macros * @{ */ - + /******************************* ADC Instances ********************************/ #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) - + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) /******************************* CRC Instances ********************************/ #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + /******************************** DMA Instances *******************************/ #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ ((INSTANCE) == DMA1_Stream1) || \ @@ -4570,37 +8327,36 @@ ((INSTANCE) == I2C2) || \ ((INSTANCE) == I2C3)) +/******************************* SMBUS Instances ******************************/ +#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE + /******************************** I2S Instances *******************************/ + #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2) || \ - ((INSTANCE) == SPI3) || \ - ((INSTANCE) == SPI4) || \ - ((INSTANCE) == SPI5)) + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3) || \ + ((INSTANCE) == SPI4) || \ + ((INSTANCE) == SPI5)) /*************************** I2S Extended Instances ***************************/ -#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \ - ((INSTANCE) == SPI3) || \ - ((INSTANCE) == I2S2ext) || \ - ((INSTANCE) == I2S3ext)) +#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \ + ((INSTANCE) == I2S3ext)) +/* Legacy Defines */ +#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE /****************************** RTC Instances *********************************/ #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + /******************************** SPI Instances *******************************/ + #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI4) || \ ((INSTANCE) == SPI5)) -/*************************** SPI Extended Instances ***************************/ -#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \ - ((INSTANCE) == SPI2) || \ - ((INSTANCE) == SPI3) || \ - ((INSTANCE) == SPI4) || \ - ((INSTANCE) == SPI5) || \ - ((INSTANCE) == I2S2ext) || \ - ((INSTANCE) == I2S3ext)) + /****************** TIM Instances : All supported instances *******************/ #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ @@ -4687,8 +8443,7 @@ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM9)) + ((INSTANCE) == TIM5)) /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ @@ -4763,22 +8518,89 @@ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3)))) +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5)) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM10) || \ + ((INSTANCE) == TIM11)) + +/****************** TIM Instances : supporting commutation event generation ***/ + +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM9)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM9)) +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5)) +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) + /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART6)) -/******************** UART Instances : Asynchronous mode **********************/ -#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ - ((INSTANCE) == USART2) || \ - ((INSTANCE) == USART6)) +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART6)) + +/* Legacy defines */ +#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE /****************** UART Instances : Hardware Flow control ********************/ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART6)) - -/********************* UART Instances : Smard card mode ***********************/ +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE + +/********************* UART Instances : Smart card mode ***********************/ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART6)) @@ -4794,24 +8616,53 @@ /*********************** HCD Instances ****************************************/ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS)) +/****************************** SDIO Instances ********************************/ +#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) + /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) /****************************** WWDG Instances ********************************/ #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) -/****************************** SDIO Instances ********************************/ -#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) - /****************************** USB Exported Constants ************************/ #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */ #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */ #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */ +/* + * @brief Specific devices reset values definitions + */ +#define RCC_PLLCFGR_RST_VALUE 0x24003010U +#define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U + +#define RCC_MAX_FREQUENCY 100000000U /*!< Max frequency of family in Hz*/ +#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define RCC_MAX_FREQUENCY_SCALE2 84000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define RCC_MAX_FREQUENCY_SCALE3 64000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ +#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */ +#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */ +#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */ +#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */ + +#define RCC_PLLN_MIN_VALUE 50U +#define RCC_PLLN_MAX_VALUE 432U + +#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define FLASH_SCALE1_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ + +#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define FLASH_SCALE2_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ + +#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +#define FLASH_SCALE3_LATENCY2_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ + + /** * @} - */ + */ /** * @}