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Diff: targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx.h
- Revision:
- 151:5eaa88a5bcc7
- Parent:
- 149:156823d33999
diff -r 02e0a0aed4ec -r 5eaa88a5bcc7 targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx.h --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx.h Tue Nov 08 17:45:16 2016 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/stm32l0xx.h Thu Nov 24 17:03:03 2016 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx.h * @author MCD Application Team - * @version V1.4.0 - * @date 01-October-2015 + * @version V1.7.0 + * @date 31-May-2016 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L0xx devices. @@ -12,8 +12,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * @@ -89,7 +89,7 @@ /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */ /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ -#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ + #define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ /* #define STM32L061xx */ /*!< */ /* #define STM32L062xx */ /*!< STM32L062K8 */ /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ @@ -114,16 +114,16 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.2.0RC1 + * @brief CMSIS Device version number V1.7.0 */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ - |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ - |(__CMSIS_DEVICE_HAL_VERSION_RC)) +#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L0xx_CMSIS_VERSION_RC)) /** * @} @@ -216,8 +216,6 @@ #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - /** * @} */