Amit Gandhi / sensen_copy_2

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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff
Child:
148:21d94c44109e
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f4xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.5.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f4xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 24 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
<> 144:ef7eb2e8f9f7 26 * | (external 8 MHz clock) | (internal 16 MHz)
<> 144:ef7eb2e8f9f7 27 * | 2- PLL_HSE_XTAL |
<> 144:ef7eb2e8f9f7 28 * | (external 8 MHz xtal) |
<> 144:ef7eb2e8f9f7 29 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 * SYSCLK(MHz) | 100 | 100
<> 144:ef7eb2e8f9f7 31 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * AHBCLK (MHz) | 100 | 100
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * APB1CLK (MHz) | 50 | 50
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * APB2CLK (MHz) | 100 | 100
<> 144:ef7eb2e8f9f7 37 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * USB capable (48 MHz precise clock) | NO | NO
<> 144:ef7eb2e8f9f7 39 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 * @attention
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 44 *
<> 144:ef7eb2e8f9f7 45 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 46 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 47 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 48 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 50 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 51 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 53 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 54 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 66 *
<> 144:ef7eb2e8f9f7 67 ******************************************************************************
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** @addtogroup stm32f4xx_system
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @addtogroup STM32F4xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #include "stm32f4xx.h"
<> 144:ef7eb2e8f9f7 84 #include "hal_tick.h"
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 88 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 92 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /**
<> 144:ef7eb2e8f9f7 95 * @}
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @}
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup STM32F4xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
<> 144:ef7eb2e8f9f7 112 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 113 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 114 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 115 /* #define DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 116 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
<> 144:ef7eb2e8f9f7 117 STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 120 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 121 /* #define DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 122 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
<> 144:ef7eb2e8f9f7 123 STM32F479xx */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 126 Internal SRAM. */
<> 144:ef7eb2e8f9f7 127 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 128 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 129 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 130 /******************************************************************************/
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @}
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /** @addtogroup STM32F4xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 141 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
<> 144:ef7eb2e8f9f7 142 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @addtogroup STM32F4xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 152 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 153 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 154 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 155 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 156 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 157 variable is updated automatically.
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 uint32_t SystemCoreClock = 16000000;
<> 144:ef7eb2e8f9f7 160 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /**
<> 144:ef7eb2e8f9f7 163 * @}
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 171 static void SystemInit_ExtMemCtl(void);
<> 144:ef7eb2e8f9f7 172 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 175 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** @addtogroup STM32F4xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @brief Setup the microcontroller system
<> 144:ef7eb2e8f9f7 190 * Initialize the FPU setting, vector table location and External memory
<> 144:ef7eb2e8f9f7 191 * configuration.
<> 144:ef7eb2e8f9f7 192 * @param None
<> 144:ef7eb2e8f9f7 193 * @retval None
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 void SystemInit(void)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 /* FPU settings ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 198 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 199 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
<> 144:ef7eb2e8f9f7 200 #endif
<> 144:ef7eb2e8f9f7 201 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 202 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 203 RCC->CR |= (uint32_t)0x00000001;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 206 RCC->CFGR = 0x00000000;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 209 RCC->CR &= (uint32_t)0xFEF6FFFF;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 212 RCC->PLLCFGR = 0x24003010;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 215 RCC->CR &= (uint32_t)0xFFFBFFFF;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 218 RCC->CIR = 0x00000000;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 221 SystemInit_ExtMemCtl();
<> 144:ef7eb2e8f9f7 222 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Configure the Vector Table location add offset address ------------------*/
<> 144:ef7eb2e8f9f7 225 #ifdef VECT_TAB_SRAM
<> 144:ef7eb2e8f9f7 226 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
<> 144:ef7eb2e8f9f7 227 #else
<> 144:ef7eb2e8f9f7 228 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
<> 144:ef7eb2e8f9f7 229 #endif
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Configure the Cube driver */
<> 144:ef7eb2e8f9f7 232 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
<> 144:ef7eb2e8f9f7 233 HAL_Init();
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Configure the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 236 AHB/APBx prescalers and Flash settings */
<> 144:ef7eb2e8f9f7 237 SetSysClock();
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Reset the timer to avoid issues after the RAM initialization */
<> 144:ef7eb2e8f9f7 240 TIM_MST_RESET_ON;
<> 144:ef7eb2e8f9f7 241 TIM_MST_RESET_OFF;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 246 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 247 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 248 * other parameters.
<> 144:ef7eb2e8f9f7 249 *
<> 144:ef7eb2e8f9f7 250 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 251 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 252 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 253 *
<> 144:ef7eb2e8f9f7 254 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 255 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 256 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 259 *
<> 144:ef7eb2e8f9f7 260 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 261 *
<> 144:ef7eb2e8f9f7 262 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 263 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 264 *
<> 144:ef7eb2e8f9f7 265 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 266 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 267 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 268 *
<> 144:ef7eb2e8f9f7 269 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
<> 144:ef7eb2e8f9f7 270 * depends on the application requirements), user has to ensure that HSE_VALUE
<> 144:ef7eb2e8f9f7 271 * is same as the real frequency of the crystal used. Otherwise, this function
<> 144:ef7eb2e8f9f7 272 * may have wrong result.
<> 144:ef7eb2e8f9f7 273 *
<> 144:ef7eb2e8f9f7 274 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 275 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 276 *
<> 144:ef7eb2e8f9f7 277 * @param None
<> 144:ef7eb2e8f9f7 278 * @retval None
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 285 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 switch (tmp)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 case 0x00: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 290 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 291 break;
<> 144:ef7eb2e8f9f7 292 case 0x04: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 293 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 294 break;
<> 144:ef7eb2e8f9f7 295 case 0x08: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
<> 144:ef7eb2e8f9f7 298 SYSCLK = PLL_VCO / PLL_P
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
<> 144:ef7eb2e8f9f7 301 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 if (pllsource != 0)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 306 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308 else
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 311 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
<> 144:ef7eb2e8f9f7 315 SystemCoreClock = pllvco/pllp;
<> 144:ef7eb2e8f9f7 316 break;
<> 144:ef7eb2e8f9f7 317 default:
<> 144:ef7eb2e8f9f7 318 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 319 break;
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 /* Compute HCLK frequency --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 322 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 323 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 324 /* HCLK frequency */
<> 144:ef7eb2e8f9f7 325 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 329 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
<> 144:ef7eb2e8f9f7 330 defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 333 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 334 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 335 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 336 * @param None
<> 144:ef7eb2e8f9f7 337 * @retval None
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 344 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
<> 144:ef7eb2e8f9f7 347 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 350 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 353 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 354 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 355 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 356 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 357 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 358 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 359 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 360 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 361 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 362 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 365 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 366 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 367 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 368 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 369 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 370 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 371 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 372 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 373 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 374 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 377 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 378 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 379 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 380 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 381 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 382 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 383 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 384 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 385 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 386 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 389 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 390 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 391 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 392 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 393 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 394 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 395 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 396 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 397 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 398 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 401 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 402 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 403 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 404 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 405 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 406 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 407 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 408 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 409 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 410 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 413 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 414 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 415 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 416 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 417 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 418 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 419 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 420 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 421 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 422 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 425 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 426 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 427 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 428 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 431 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 434 /* Clock enable command */
<> 144:ef7eb2e8f9f7 435 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 436 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 437 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Delay */
<> 144:ef7eb2e8f9f7 443 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* PALL command */
<> 144:ef7eb2e8f9f7 446 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 447 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 448 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 454 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 455 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 456 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* MRD register program */
<> 144:ef7eb2e8f9f7 462 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 463 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 464 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Set refresh count */
<> 144:ef7eb2e8f9f7 470 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 471 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Disable write protection */
<> 144:ef7eb2e8f9f7 474 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 475 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 478 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 479 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 480 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 481 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 482 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 483 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 484 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 485 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 486 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 487 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 488 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 (void)(tmp);
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 493 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 496 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 497 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 498 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 499 * @param None
<> 144:ef7eb2e8f9f7 500 * @retval None
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 505 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 506 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 507 #if defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 508 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 509 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 512 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
<> 144:ef7eb2e8f9f7 513 clock */
<> 144:ef7eb2e8f9f7 514 RCC->AHB1ENR |= 0x0000007D;
<> 144:ef7eb2e8f9f7 515 #else
<> 144:ef7eb2e8f9f7 516 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
<> 144:ef7eb2e8f9f7 517 clock */
<> 144:ef7eb2e8f9f7 518 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 519 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 520 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 521 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 524 /* Connect PAx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 525 GPIOA->AFR[0] |= 0xC0000000;
<> 144:ef7eb2e8f9f7 526 GPIOA->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 527 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 528 GPIOA->MODER |= 0x00008000;
<> 144:ef7eb2e8f9f7 529 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 530 GPIOA->OSPEEDR |= 0x00008000;
<> 144:ef7eb2e8f9f7 531 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 532 GPIOA->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 533 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 534 GPIOA->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Connect PCx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 537 GPIOC->AFR[0] |= 0x00CC0000;
<> 144:ef7eb2e8f9f7 538 GPIOC->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 539 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 540 GPIOC->MODER |= 0x00000A00;
<> 144:ef7eb2e8f9f7 541 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 542 GPIOC->OSPEEDR |= 0x00000A00;
<> 144:ef7eb2e8f9f7 543 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 544 GPIOC->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 545 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 546 GPIOC->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 547 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 550 GPIOD->AFR[0] = 0x000000CC;
<> 144:ef7eb2e8f9f7 551 GPIOD->AFR[1] = 0xCC000CCC;
<> 144:ef7eb2e8f9f7 552 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 553 GPIOD->MODER = 0xA02A000A;
<> 144:ef7eb2e8f9f7 554 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 555 GPIOD->OSPEEDR = 0xA02A000A;
<> 144:ef7eb2e8f9f7 556 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 557 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 558 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 559 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 562 GPIOE->AFR[0] = 0xC00000CC;
<> 144:ef7eb2e8f9f7 563 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 564 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 565 GPIOE->MODER = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 566 /* Configure PEx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 567 GPIOE->OSPEEDR = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 568 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 569 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 570 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 571 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 574 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 575 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 576 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 577 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 578 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 579 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 580 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 581 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 582 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 583 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 586 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 587 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 588 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 589 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 590 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 591 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 592 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 593 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 594 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 595 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 598 || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 599 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 600 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 601 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 602 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 603 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 604 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 605 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 606 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 607 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 608 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 609 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 612 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 613 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 614 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 615 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 616 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 617 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 618 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 619 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 620 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 621 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 622 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 625 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 626 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 627 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 628 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Configure and enable SDRAM bank1 */
<> 144:ef7eb2e8f9f7 631 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 632 FMC_Bank5_6->SDCR[0] = 0x00001954;
<> 144:ef7eb2e8f9f7 633 #else
<> 144:ef7eb2e8f9f7 634 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 635 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 636 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 639 /* Clock enable command */
<> 144:ef7eb2e8f9f7 640 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 641 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 642 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Delay */
<> 144:ef7eb2e8f9f7 648 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* PALL command */
<> 144:ef7eb2e8f9f7 651 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 652 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 653 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 659 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 660 FMC_Bank5_6->SDCMR = 0x000000F3;
<> 144:ef7eb2e8f9f7 661 #else
<> 144:ef7eb2e8f9f7 662 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 663 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 664 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 665 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* MRD register program */
<> 144:ef7eb2e8f9f7 671 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 672 FMC_Bank5_6->SDCMR = 0x00044014;
<> 144:ef7eb2e8f9f7 673 #else
<> 144:ef7eb2e8f9f7 674 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 675 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 676 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 677 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Set refresh count */
<> 144:ef7eb2e8f9f7 683 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 684 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 685 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
<> 144:ef7eb2e8f9f7 686 #else
<> 144:ef7eb2e8f9f7 687 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 688 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Disable write protection */
<> 144:ef7eb2e8f9f7 691 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 692 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 693 #endif /* DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 694 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 697 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 698 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #if defined(DATA_IN_ExtSRAM)
<> 144:ef7eb2e8f9f7 701 /*-- GPIOs Configuration -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 702 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
<> 144:ef7eb2e8f9f7 703 RCC->AHB1ENR |= 0x00000078;
<> 144:ef7eb2e8f9f7 704 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 705 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 708 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 709 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 710 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 711 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 712 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 713 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 714 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 715 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 716 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 717 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 720 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 721 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 722 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 723 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 724 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 725 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 726 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 727 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 728 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 729 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 732 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 733 GPIOF->AFR[1] = 0xCCCC0000;
<> 144:ef7eb2e8f9f7 734 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 735 GPIOF->MODER = 0xAA000AAA;
<> 144:ef7eb2e8f9f7 736 /* Configure PFx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 737 GPIOF->OSPEEDR = 0xFF000FFF;
<> 144:ef7eb2e8f9f7 738 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 739 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 740 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 741 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 744 GPIOG->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 745 GPIOG->AFR[1] = 0x000000C0;
<> 144:ef7eb2e8f9f7 746 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 747 GPIOG->MODER = 0x00085AAA;
<> 144:ef7eb2e8f9f7 748 /* Configure PGx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 749 GPIOG->OSPEEDR = 0x000CAFFF;
<> 144:ef7eb2e8f9f7 750 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 751 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 752 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 753 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /*-- FMC/FSMC Configuration --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 756 /* Enable the FMC/FSMC interface clock */
<> 144:ef7eb2e8f9f7 757 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 760 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 761 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 762 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 763 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 764 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 765 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 766 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 767 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 768 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 769 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 770 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 771 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 772 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 773 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 774 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 775 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 776 || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 777 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 778 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
<> 144:ef7eb2e8f9f7 779 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 780 FSMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 781 FSMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 782 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 783 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 #endif /* DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 786 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
<> 144:ef7eb2e8f9f7 787 STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 788 (void)(tmp);
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /**
<> 144:ef7eb2e8f9f7 793 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 794 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 795 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 796 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 797 * @param None
<> 144:ef7eb2e8f9f7 798 * @retval None
<> 144:ef7eb2e8f9f7 799 */
<> 144:ef7eb2e8f9f7 800 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 803 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 804 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 805 #endif
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 808 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 809 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 810 #endif
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 /* 3- If fail start with HSI clock */
<> 144:ef7eb2e8f9f7 813 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 while(1)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Output clock on MCO2 pin(PC9) for debugging purpose */
<> 144:ef7eb2e8f9f7 824 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 828 /******************************************************************************/
<> 144:ef7eb2e8f9f7 829 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 830 /******************************************************************************/
<> 144:ef7eb2e8f9f7 831 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 834 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* The voltage scaling allows optimizing the power consumption when the device is
<> 144:ef7eb2e8f9f7 837 clocked below the maximum system frequency, to update the voltage scaling value
<> 144:ef7eb2e8f9f7 838 regarding system frequency refer to product datasheet. */
<> 144:ef7eb2e8f9f7 839 __PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 840 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Enable HSE oscillator and activate PLL with HSE as source */
<> 144:ef7eb2e8f9f7 843 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 844 if (bypass == 0)
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 else
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 853 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 854 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
<> 144:ef7eb2e8f9f7 855 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
<> 144:ef7eb2e8f9f7 856 //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
<> 144:ef7eb2e8f9f7 857 //RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
<> 144:ef7eb2e8f9f7 858 #define VCO_IN_FREQ 2000000
<> 144:ef7eb2e8f9f7 859 RCC_OscInitStruct.PLL.PLLM = (HSE_VALUE / VCO_IN_FREQ); // VCO input clock = 2 MHz = (24 MHz / 12)
<> 144:ef7eb2e8f9f7 860 RCC_OscInitStruct.PLL.PLLN = (400000000 / VCO_IN_FREQ); // VCO output clock = 400 MHz = (2 MHz * 200)
<> 144:ef7eb2e8f9f7 861 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
<> 144:ef7eb2e8f9f7 862 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
<> 144:ef7eb2e8f9f7 863 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 return 0; // FAIL
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 869 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 870 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
<> 144:ef7eb2e8f9f7 871 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
<> 144:ef7eb2e8f9f7 872 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
<> 144:ef7eb2e8f9f7 873 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
<> 144:ef7eb2e8f9f7 874 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 return 0; // FAIL
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 //if (bypass == 0)
<> 144:ef7eb2e8f9f7 882 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
<> 144:ef7eb2e8f9f7 883 //else
<> 144:ef7eb2e8f9f7 884 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 return 1; // OK
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888 #endif
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /******************************************************************************/
<> 144:ef7eb2e8f9f7 891 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 892 /******************************************************************************/
<> 144:ef7eb2e8f9f7 893 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 896 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* The voltage scaling allows optimizing the power consumption when the device is
<> 144:ef7eb2e8f9f7 899 clocked below the maximum system frequency, to update the voltage scaling value
<> 144:ef7eb2e8f9f7 900 regarding system frequency refer to product datasheet. */
<> 144:ef7eb2e8f9f7 901 __PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 902 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Enable HSI oscillator and activate PLL with HSI as source */
<> 144:ef7eb2e8f9f7 905 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 906 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 907 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 908 RCC_OscInitStruct.HSICalibrationValue = 16;
<> 144:ef7eb2e8f9f7 909 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 910 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
<> 144:ef7eb2e8f9f7 911 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
<> 144:ef7eb2e8f9f7 912 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
<> 144:ef7eb2e8f9f7 913 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
<> 144:ef7eb2e8f9f7 914 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
<> 144:ef7eb2e8f9f7 915 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
<> 144:ef7eb2e8f9f7 916 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
<> 144:ef7eb2e8f9f7 917 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 return 0; // FAIL
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
<> 144:ef7eb2e8f9f7 923 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 924 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
<> 144:ef7eb2e8f9f7 925 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
<> 144:ef7eb2e8f9f7 926 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
<> 144:ef7eb2e8f9f7 927 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
<> 144:ef7eb2e8f9f7 928 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 return 0; // FAIL
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /* Output clock on MCO1 pin(PA8) for debugging purpose */
<> 144:ef7eb2e8f9f7 934 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 return 1; // OK
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @}
<> 144:ef7eb2e8f9f7 941 */
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /**
<> 144:ef7eb2e8f9f7 944 * @}
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @}
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/