Amit Gandhi / sensen_copy_2

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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f411xe.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.5.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file contains:
<> 144:ef7eb2e8f9f7 10 * - Data structures and the address mapping for all peripherals
<> 144:ef7eb2e8f9f7 11 * - peripherals registers declarations and bits definition
<> 144:ef7eb2e8f9f7 12 * - Macros to access peripheral's registers hardware
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 ******************************************************************************
<> 144:ef7eb2e8f9f7 15 * @attention
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 20 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 25 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 27 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 28 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 ******************************************************************************
<> 144:ef7eb2e8f9f7 42 */
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup stm32f411xe
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #ifndef __STM32F411xE_H
<> 144:ef7eb2e8f9f7 53 #define __STM32F411xE_H
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 56 extern "C" {
<> 144:ef7eb2e8f9f7 57 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /** @addtogroup Configuration_section_for_CMSIS
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
<> 144:ef7eb2e8f9f7 68 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
<> 144:ef7eb2e8f9f7 69 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 70 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 71 #ifndef __FPU_PRESENT
<> 144:ef7eb2e8f9f7 72 #define __FPU_PRESENT 1U /*!< FPU present */
<> 144:ef7eb2e8f9f7 73 #endif /* __FPU_PRESENT */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /**
<> 144:ef7eb2e8f9f7 76 * @}
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @addtogroup Peripheral_interrupt_number_definition
<> 144:ef7eb2e8f9f7 80 * @{
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
<> 144:ef7eb2e8f9f7 85 * in @ref Library_configuration_section
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 typedef enum
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
<> 144:ef7eb2e8f9f7 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 92 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 94 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 96 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 97 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 98 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 144:ef7eb2e8f9f7 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 144:ef7eb2e8f9f7 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 144:ef7eb2e8f9f7 101 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 144:ef7eb2e8f9f7 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 144:ef7eb2e8f9f7 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 144:ef7eb2e8f9f7 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 144:ef7eb2e8f9f7 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 144:ef7eb2e8f9f7 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 144:ef7eb2e8f9f7 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 144:ef7eb2e8f9f7 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 144:ef7eb2e8f9f7 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 144:ef7eb2e8f9f7 110 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 111 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 112 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 113 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 114 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 115 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 144:ef7eb2e8f9f7 116 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 144:ef7eb2e8f9f7 117 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 144:ef7eb2e8f9f7 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 144:ef7eb2e8f9f7 119 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 144:ef7eb2e8f9f7 120 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 144:ef7eb2e8f9f7 121 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 144:ef7eb2e8f9f7 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 144:ef7eb2e8f9f7 124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 144:ef7eb2e8f9f7 125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 144:ef7eb2e8f9f7 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 144:ef7eb2e8f9f7 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 144:ef7eb2e8f9f7 128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 144:ef7eb2e8f9f7 129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 144:ef7eb2e8f9f7 130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 144:ef7eb2e8f9f7 131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 144:ef7eb2e8f9f7 132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 144:ef7eb2e8f9f7 133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 144:ef7eb2e8f9f7 134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 144:ef7eb2e8f9f7 135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
<> 144:ef7eb2e8f9f7 136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 144:ef7eb2e8f9f7 137 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 144:ef7eb2e8f9f7 138 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
<> 144:ef7eb2e8f9f7 139 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 144:ef7eb2e8f9f7 140 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 144:ef7eb2e8f9f7 141 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 142 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 143 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 144 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 145 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 144:ef7eb2e8f9f7 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 144:ef7eb2e8f9f7 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 144:ef7eb2e8f9f7 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 144:ef7eb2e8f9f7 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 144:ef7eb2e8f9f7 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 144:ef7eb2e8f9f7 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 144:ef7eb2e8f9f7 153 FPU_IRQn = 81, /*!< FPU global interrupt */
<> 144:ef7eb2e8f9f7 154 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
<> 144:ef7eb2e8f9f7 155 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
<> 144:ef7eb2e8f9f7 156 } IRQn_Type;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 144:ef7eb2e8f9f7 163 #include "system_stm32f4xx.h"
<> 144:ef7eb2e8f9f7 164 #include <stdint.h>
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @addtogroup Peripheral_registers_structures
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @brief Analog to Digital Converter
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 typedef struct
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 177 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 178 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 179 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 180 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 181 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 182 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 183 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 184 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 185 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 186 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 187 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 188 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 189 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 190 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 144:ef7eb2e8f9f7 191 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 192 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 193 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 194 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 195 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 196 } ADC_TypeDef;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 typedef struct
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 144:ef7eb2e8f9f7 201 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 144:ef7eb2e8f9f7 202 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 144:ef7eb2e8f9f7 203 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 144:ef7eb2e8f9f7 204 } ADC_Common_TypeDef;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief CRC calculation unit
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 typedef struct
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 213 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 214 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 144:ef7eb2e8f9f7 215 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 144:ef7eb2e8f9f7 216 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 217 } CRC_TypeDef;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @brief Debug MCU
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 typedef struct
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 228 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 229 }DBGMCU_TypeDef;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief DMA Controller
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 typedef struct
<> 144:ef7eb2e8f9f7 237 {
<> 144:ef7eb2e8f9f7 238 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 144:ef7eb2e8f9f7 239 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 144:ef7eb2e8f9f7 240 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 144:ef7eb2e8f9f7 241 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 144:ef7eb2e8f9f7 242 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 144:ef7eb2e8f9f7 244 } DMA_Stream_TypeDef;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 typedef struct
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 249 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 250 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 251 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 252 } DMA_TypeDef;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief External Interrupt/Event Controller
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 typedef struct
<> 144:ef7eb2e8f9f7 260 {
<> 144:ef7eb2e8f9f7 261 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 262 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 263 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 264 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 265 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 266 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 267 } EXTI_TypeDef;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief FLASH Registers
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 typedef struct
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 276 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 277 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 278 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 279 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 280 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 282 } FLASH_TypeDef;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @brief General Purpose I/O
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 typedef struct
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 291 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 292 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 293 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 294 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 295 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 296 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 297 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 298 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 144:ef7eb2e8f9f7 299 } GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @brief System configuration controller
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 typedef struct
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 308 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 309 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 144:ef7eb2e8f9f7 310 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
<> 144:ef7eb2e8f9f7 311 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 312 } SYSCFG_TypeDef;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Inter-integrated Circuit Interface
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 typedef struct
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 321 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 322 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 324 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 325 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 326 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 327 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 328 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 329 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 330 } I2C_TypeDef;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @brief Independent WATCHDOG
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 typedef struct
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 340 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 341 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 342 } IWDG_TypeDef;
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Power Control
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 typedef struct
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 352 } PWR_TypeDef;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @brief Reset and Clock Control
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 typedef struct
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 364 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 365 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 366 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 367 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 144:ef7eb2e8f9f7 368 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 369 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 370 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 144:ef7eb2e8f9f7 371 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 372 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 373 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 374 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 144:ef7eb2e8f9f7 375 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 376 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 377 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 144:ef7eb2e8f9f7 378 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 379 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 381 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 144:ef7eb2e8f9f7 382 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 383 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 384 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 144:ef7eb2e8f9f7 385 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 386 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 387 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 389 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 390 uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
<> 144:ef7eb2e8f9f7 391 __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 392 } RCC_TypeDef;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /**
<> 144:ef7eb2e8f9f7 395 * @brief Real-Time Clock
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 typedef struct
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 401 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 402 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 403 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 404 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 405 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 406 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 407 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 408 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 409 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 410 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 411 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 412 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 414 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 415 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 416 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 417 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 418 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 419 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 144:ef7eb2e8f9f7 420 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 421 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 422 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 423 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 144:ef7eb2e8f9f7 424 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 425 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 426 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 144:ef7eb2e8f9f7 427 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 144:ef7eb2e8f9f7 428 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 429 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 430 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 144:ef7eb2e8f9f7 431 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 144:ef7eb2e8f9f7 432 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 433 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 434 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 435 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 436 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 437 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 438 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 144:ef7eb2e8f9f7 439 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 144:ef7eb2e8f9f7 440 } RTC_TypeDef;
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @brief SD host Interface
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 typedef struct
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 450 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 451 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 452 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 453 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 454 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 455 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 456 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 457 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 458 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 460 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 461 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 462 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 464 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 465 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
<> 144:ef7eb2e8f9f7 466 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 467 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
<> 144:ef7eb2e8f9f7 468 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 469 } SDIO_TypeDef;
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @brief Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 typedef struct
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 478 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 479 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 480 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 481 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 482 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 483 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 484 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 485 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 486 } SPI_TypeDef;
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief TIM
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 typedef struct
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 495 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 496 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 497 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 498 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 499 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 500 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 501 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 502 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 503 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 504 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 510 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 512 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 513 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 514 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 515 } TIM_TypeDef;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 typedef struct
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 524 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 525 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 526 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 527 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 528 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 529 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 530 } USART_TypeDef;
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /**
<> 144:ef7eb2e8f9f7 533 * @brief Window WATCHDOG
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 typedef struct
<> 144:ef7eb2e8f9f7 537 {
<> 144:ef7eb2e8f9f7 538 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 539 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 540 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 541 } WWDG_TypeDef;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief __USB_OTG_Core_register
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 typedef struct
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
<> 144:ef7eb2e8f9f7 550 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
<> 144:ef7eb2e8f9f7 551 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
<> 144:ef7eb2e8f9f7 552 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
<> 144:ef7eb2e8f9f7 553 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
<> 144:ef7eb2e8f9f7 554 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
<> 144:ef7eb2e8f9f7 555 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
<> 144:ef7eb2e8f9f7 556 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
<> 144:ef7eb2e8f9f7 557 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
<> 144:ef7eb2e8f9f7 558 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
<> 144:ef7eb2e8f9f7 559 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
<> 144:ef7eb2e8f9f7 560 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
<> 144:ef7eb2e8f9f7 561 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
<> 144:ef7eb2e8f9f7 562 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
<> 144:ef7eb2e8f9f7 563 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
<> 144:ef7eb2e8f9f7 564 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
<> 144:ef7eb2e8f9f7 565 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
<> 144:ef7eb2e8f9f7 566 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 USB_OTG_GlobalTypeDef;
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /**
<> 144:ef7eb2e8f9f7 573 * @brief __device_Registers
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575 typedef struct
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
<> 144:ef7eb2e8f9f7 578 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
<> 144:ef7eb2e8f9f7 579 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
<> 144:ef7eb2e8f9f7 580 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
<> 144:ef7eb2e8f9f7 581 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
<> 144:ef7eb2e8f9f7 582 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
<> 144:ef7eb2e8f9f7 583 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
<> 144:ef7eb2e8f9f7 584 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
<> 144:ef7eb2e8f9f7 585 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
<> 144:ef7eb2e8f9f7 586 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
<> 144:ef7eb2e8f9f7 587 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
<> 144:ef7eb2e8f9f7 588 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
<> 144:ef7eb2e8f9f7 589 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
<> 144:ef7eb2e8f9f7 590 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
<> 144:ef7eb2e8f9f7 591 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
<> 144:ef7eb2e8f9f7 592 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
<> 144:ef7eb2e8f9f7 593 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
<> 144:ef7eb2e8f9f7 594 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
<> 144:ef7eb2e8f9f7 595 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
<> 144:ef7eb2e8f9f7 596 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 USB_OTG_DeviceTypeDef;
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief __IN_Endpoint-Specific_Register
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604 typedef struct
<> 144:ef7eb2e8f9f7 605 {
<> 144:ef7eb2e8f9f7 606 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
<> 144:ef7eb2e8f9f7 607 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
<> 144:ef7eb2e8f9f7 608 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
<> 144:ef7eb2e8f9f7 609 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
<> 144:ef7eb2e8f9f7 610 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
<> 144:ef7eb2e8f9f7 611 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
<> 144:ef7eb2e8f9f7 612 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
<> 144:ef7eb2e8f9f7 613 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615 USB_OTG_INEndpointTypeDef;
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief __OUT_Endpoint-Specific_Registers
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621 typedef struct
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
<> 144:ef7eb2e8f9f7 624 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
<> 144:ef7eb2e8f9f7 625 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
<> 144:ef7eb2e8f9f7 626 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
<> 144:ef7eb2e8f9f7 627 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
<> 144:ef7eb2e8f9f7 628 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
<> 144:ef7eb2e8f9f7 629 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631 USB_OTG_OUTEndpointTypeDef;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /**
<> 144:ef7eb2e8f9f7 635 * @brief __Host_Mode_Register_Structures
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 typedef struct
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
<> 144:ef7eb2e8f9f7 640 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
<> 144:ef7eb2e8f9f7 641 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
<> 144:ef7eb2e8f9f7 642 uint32_t Reserved40C; /* Reserved 40Ch*/
<> 144:ef7eb2e8f9f7 643 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
<> 144:ef7eb2e8f9f7 644 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
<> 144:ef7eb2e8f9f7 645 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 USB_OTG_HostTypeDef;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @brief __Host_Channel_Specific_Registers
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653 typedef struct
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 __IO uint32_t HCCHAR;
<> 144:ef7eb2e8f9f7 656 __IO uint32_t HCSPLT;
<> 144:ef7eb2e8f9f7 657 __IO uint32_t HCINT;
<> 144:ef7eb2e8f9f7 658 __IO uint32_t HCINTMSK;
<> 144:ef7eb2e8f9f7 659 __IO uint32_t HCTSIZ;
<> 144:ef7eb2e8f9f7 660 __IO uint32_t HCDMA;
<> 144:ef7eb2e8f9f7 661 uint32_t Reserved[2];
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 USB_OTG_HostChannelTypeDef;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief Peripheral_memory_map
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
<> 144:ef7eb2e8f9f7 670 #define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 671 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
<> 144:ef7eb2e8f9f7 672 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 673 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
<> 144:ef7eb2e8f9f7 674 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
<> 144:ef7eb2e8f9f7 675 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
<> 144:ef7eb2e8f9f7 676 #define FLASH_END 0x0807FFFFU /*!< FLASH end address */
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Legacy defines */
<> 144:ef7eb2e8f9f7 679 #define SRAM_BASE SRAM1_BASE
<> 144:ef7eb2e8f9f7 680 #define SRAM_BB_BASE SRAM1_BB_BASE
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /*!< Peripheral memory map */
<> 144:ef7eb2e8f9f7 684 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 685 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 686 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 144:ef7eb2e8f9f7 687 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 690 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 691 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 692 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 693 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 694 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 695 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 696 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 697 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 698 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 699 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 700 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 701 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 702 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 703 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 704 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 705 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 708 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 709 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 710 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 711 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 712 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 144:ef7eb2e8f9f7 713 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 714 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 715 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 716 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 717 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 718 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 719 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 720 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 721 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /*!< AHB1 peripherals */
<> 144:ef7eb2e8f9f7 724 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 725 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 726 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 727 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 728 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 729 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 730 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 731 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 732 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 733 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 734 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 735 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 736 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 737 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 738 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 739 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 740 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 741 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 742 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 743 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 744 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 745 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 746 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 747 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 748 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 749 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 750 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Debug MCU registers base address */
<> 144:ef7eb2e8f9f7 753 #define DBGMCU_BASE 0xE0042000U
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /*!< USB registers base address */
<> 144:ef7eb2e8f9f7 756 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 #define USB_OTG_GLOBAL_BASE 0x000U
<> 144:ef7eb2e8f9f7 759 #define USB_OTG_DEVICE_BASE 0x800U
<> 144:ef7eb2e8f9f7 760 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 144:ef7eb2e8f9f7 761 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 144:ef7eb2e8f9f7 762 #define USB_OTG_EP_REG_SIZE 0x20U
<> 144:ef7eb2e8f9f7 763 #define USB_OTG_HOST_BASE 0x400U
<> 144:ef7eb2e8f9f7 764 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 144:ef7eb2e8f9f7 765 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 144:ef7eb2e8f9f7 766 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 144:ef7eb2e8f9f7 767 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 144:ef7eb2e8f9f7 768 #define USB_OTG_FIFO_BASE 0x1000U
<> 144:ef7eb2e8f9f7 769 #define USB_OTG_FIFO_SIZE 0x1000U
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @}
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /** @addtogroup Peripheral_declaration
<> 144:ef7eb2e8f9f7 776 * @{
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 144:ef7eb2e8f9f7 779 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 144:ef7eb2e8f9f7 780 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 144:ef7eb2e8f9f7 781 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 144:ef7eb2e8f9f7 782 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 144:ef7eb2e8f9f7 783 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 144:ef7eb2e8f9f7 784 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 144:ef7eb2e8f9f7 785 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
<> 144:ef7eb2e8f9f7 786 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 144:ef7eb2e8f9f7 787 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 144:ef7eb2e8f9f7 788 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
<> 144:ef7eb2e8f9f7 789 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 144:ef7eb2e8f9f7 790 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 791 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 144:ef7eb2e8f9f7 792 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 144:ef7eb2e8f9f7 793 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 144:ef7eb2e8f9f7 794 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 144:ef7eb2e8f9f7 795 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 144:ef7eb2e8f9f7 796 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 144:ef7eb2e8f9f7 797 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
<> 144:ef7eb2e8f9f7 798 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 144:ef7eb2e8f9f7 799 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
<> 144:ef7eb2e8f9f7 800 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 144:ef7eb2e8f9f7 801 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 144:ef7eb2e8f9f7 802 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 144:ef7eb2e8f9f7 803 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 144:ef7eb2e8f9f7 804 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 144:ef7eb2e8f9f7 805 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 144:ef7eb2e8f9f7 806 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 144:ef7eb2e8f9f7 807 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
<> 144:ef7eb2e8f9f7 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 144:ef7eb2e8f9f7 814 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 144:ef7eb2e8f9f7 815 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 144:ef7eb2e8f9f7 816 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 144:ef7eb2e8f9f7 817 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 144:ef7eb2e8f9f7 818 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 144:ef7eb2e8f9f7 819 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 144:ef7eb2e8f9f7 820 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 144:ef7eb2e8f9f7 821 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 144:ef7eb2e8f9f7 822 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 144:ef7eb2e8f9f7 823 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 144:ef7eb2e8f9f7 824 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 144:ef7eb2e8f9f7 825 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 144:ef7eb2e8f9f7 826 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 144:ef7eb2e8f9f7 827 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 144:ef7eb2e8f9f7 828 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 144:ef7eb2e8f9f7 829 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 144:ef7eb2e8f9f7 830 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 144:ef7eb2e8f9f7 831 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 144:ef7eb2e8f9f7 832 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 144:ef7eb2e8f9f7 833 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 144:ef7eb2e8f9f7 834 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /**
<> 144:ef7eb2e8f9f7 841 * @}
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /** @addtogroup Exported_constants
<> 144:ef7eb2e8f9f7 845 * @{
<> 144:ef7eb2e8f9f7 846 */
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 144:ef7eb2e8f9f7 849 * @{
<> 144:ef7eb2e8f9f7 850 */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /******************************************************************************/
<> 144:ef7eb2e8f9f7 853 /* Peripheral Registers_Bits_Definition */
<> 144:ef7eb2e8f9f7 854 /******************************************************************************/
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /******************************************************************************/
<> 144:ef7eb2e8f9f7 857 /* */
<> 144:ef7eb2e8f9f7 858 /* Analog to Digital Converter */
<> 144:ef7eb2e8f9f7 859 /* */
<> 144:ef7eb2e8f9f7 860 /******************************************************************************/
<> 144:ef7eb2e8f9f7 861 /******************** Bit definition for ADC_SR register ********************/
<> 144:ef7eb2e8f9f7 862 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
<> 144:ef7eb2e8f9f7 863 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
<> 144:ef7eb2e8f9f7 864 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 865 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
<> 144:ef7eb2e8f9f7 866 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
<> 144:ef7eb2e8f9f7 867 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /******************* Bit definition for ADC_CR1 register ********************/
<> 144:ef7eb2e8f9f7 870 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 144:ef7eb2e8f9f7 871 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 872 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 873 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 874 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 875 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 876 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
<> 144:ef7eb2e8f9f7 877 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
<> 144:ef7eb2e8f9f7 878 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
<> 144:ef7eb2e8f9f7 879 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
<> 144:ef7eb2e8f9f7 880 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
<> 144:ef7eb2e8f9f7 881 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
<> 144:ef7eb2e8f9f7 882 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
<> 144:ef7eb2e8f9f7 883 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
<> 144:ef7eb2e8f9f7 884 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 144:ef7eb2e8f9f7 885 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 886 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 887 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 888 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
<> 144:ef7eb2e8f9f7 889 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
<> 144:ef7eb2e8f9f7 890 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
<> 144:ef7eb2e8f9f7 891 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 892 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 893 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /******************* Bit definition for ADC_CR2 register ********************/
<> 144:ef7eb2e8f9f7 896 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
<> 144:ef7eb2e8f9f7 897 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
<> 144:ef7eb2e8f9f7 898 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
<> 144:ef7eb2e8f9f7 899 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
<> 144:ef7eb2e8f9f7 900 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
<> 144:ef7eb2e8f9f7 901 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
<> 144:ef7eb2e8f9f7 902 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 144:ef7eb2e8f9f7 903 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 904 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 905 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 906 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 907 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 144:ef7eb2e8f9f7 908 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 909 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 910 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
<> 144:ef7eb2e8f9f7 911 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 144:ef7eb2e8f9f7 912 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 913 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 914 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 915 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 916 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 144:ef7eb2e8f9f7 917 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 918 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 919 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 144:ef7eb2e8f9f7 922 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 144:ef7eb2e8f9f7 923 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 924 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 925 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 926 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 144:ef7eb2e8f9f7 927 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 928 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 929 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 930 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 144:ef7eb2e8f9f7 931 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 932 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 933 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 934 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 144:ef7eb2e8f9f7 935 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 936 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 937 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 938 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 144:ef7eb2e8f9f7 939 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 940 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 941 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 942 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 144:ef7eb2e8f9f7 943 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 944 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 945 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 946 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 144:ef7eb2e8f9f7 947 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 948 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 949 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 950 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 144:ef7eb2e8f9f7 951 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 952 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 953 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 954 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 144:ef7eb2e8f9f7 955 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 956 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 957 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 144:ef7eb2e8f9f7 960 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 144:ef7eb2e8f9f7 961 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 962 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 963 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 964 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 144:ef7eb2e8f9f7 965 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 966 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 967 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 968 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 144:ef7eb2e8f9f7 969 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 970 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 971 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 972 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 144:ef7eb2e8f9f7 973 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 974 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 975 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 976 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 144:ef7eb2e8f9f7 977 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 978 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 979 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 980 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 144:ef7eb2e8f9f7 981 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 982 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 983 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 984 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 144:ef7eb2e8f9f7 985 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 986 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 987 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 988 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 144:ef7eb2e8f9f7 989 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 990 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 991 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 992 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 144:ef7eb2e8f9f7 993 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 994 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 995 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 996 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 144:ef7eb2e8f9f7 997 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 998 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 999 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 144:ef7eb2e8f9f7 1002 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 144:ef7eb2e8f9f7 1005 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 144:ef7eb2e8f9f7 1008 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 144:ef7eb2e8f9f7 1011 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /******************* Bit definition for ADC_HTR register ********************/
<> 144:ef7eb2e8f9f7 1014 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /******************* Bit definition for ADC_LTR register ********************/
<> 144:ef7eb2e8f9f7 1017 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /******************* Bit definition for ADC_SQR1 register *******************/
<> 144:ef7eb2e8f9f7 1020 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1021 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1022 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1023 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1024 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1025 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1026 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1027 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1028 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1029 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1030 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1031 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1032 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1033 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1034 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1035 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1036 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1037 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1038 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1039 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1040 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1041 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1042 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1043 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1044 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
<> 144:ef7eb2e8f9f7 1045 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1046 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1047 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1048 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /******************* Bit definition for ADC_SQR2 register *******************/
<> 144:ef7eb2e8f9f7 1051 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1052 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1053 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1054 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1055 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1056 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1057 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1058 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1059 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1060 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1061 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1062 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1063 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1064 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1065 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1066 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1067 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1068 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1069 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1070 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1071 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1072 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1073 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1074 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1075 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1076 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1077 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1078 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1079 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1080 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1081 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1082 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1083 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1084 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1085 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1086 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /******************* Bit definition for ADC_SQR3 register *******************/
<> 144:ef7eb2e8f9f7 1089 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1090 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1091 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1092 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1093 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1094 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1095 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1096 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1097 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1098 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1099 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1100 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1101 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1102 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1103 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1104 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1105 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1106 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1107 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1108 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1109 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1110 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1111 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1112 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1113 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1114 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1115 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1116 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1117 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1118 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1119 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1120 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1121 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1122 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1123 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1124 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /******************* Bit definition for ADC_JSQR register *******************/
<> 144:ef7eb2e8f9f7 1127 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1128 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1129 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1130 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1131 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1132 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1133 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1134 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1135 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1136 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1137 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1138 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1139 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1140 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1141 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1142 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1143 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1144 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1145 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1146 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1147 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1148 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1149 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1150 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1151 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
<> 144:ef7eb2e8f9f7 1152 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1153 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /******************* Bit definition for ADC_JDR1 register *******************/
<> 144:ef7eb2e8f9f7 1156 #define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /******************* Bit definition for ADC_JDR2 register *******************/
<> 144:ef7eb2e8f9f7 1159 #define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /******************* Bit definition for ADC_JDR3 register *******************/
<> 144:ef7eb2e8f9f7 1162 #define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /******************* Bit definition for ADC_JDR4 register *******************/
<> 144:ef7eb2e8f9f7 1165 #define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /******************** Bit definition for ADC_DR register ********************/
<> 144:ef7eb2e8f9f7 1168 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
<> 144:ef7eb2e8f9f7 1169 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /******************* Bit definition for ADC_CSR register ********************/
<> 144:ef7eb2e8f9f7 1172 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1173 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
<> 144:ef7eb2e8f9f7 1174 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1175 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1176 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1177 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1178 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1179 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
<> 144:ef7eb2e8f9f7 1180 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1181 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1182 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1183 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1184 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1185 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
<> 144:ef7eb2e8f9f7 1186 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1187 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1188 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1189 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1192 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 144:ef7eb2e8f9f7 1193 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 144:ef7eb2e8f9f7 1194 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /******************* Bit definition for ADC_CCR register ********************/
<> 144:ef7eb2e8f9f7 1197 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 144:ef7eb2e8f9f7 1198 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1199 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1200 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1201 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1202 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1203 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 144:ef7eb2e8f9f7 1204 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1205 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1206 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1207 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1208 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
<> 144:ef7eb2e8f9f7 1209 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 144:ef7eb2e8f9f7 1210 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1211 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1212 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 144:ef7eb2e8f9f7 1213 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1214 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1215 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
<> 144:ef7eb2e8f9f7 1216 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /******************* Bit definition for ADC_CDR register ********************/
<> 144:ef7eb2e8f9f7 1219 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
<> 144:ef7eb2e8f9f7 1220 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1223 /* */
<> 144:ef7eb2e8f9f7 1224 /* CRC calculation unit */
<> 144:ef7eb2e8f9f7 1225 /* */
<> 144:ef7eb2e8f9f7 1226 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1227 /******************* Bit definition for CRC_DR register *********************/
<> 144:ef7eb2e8f9f7 1228 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 /******************* Bit definition for CRC_IDR register ********************/
<> 144:ef7eb2e8f9f7 1232 #define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /******************** Bit definition for CRC_CR register ********************/
<> 144:ef7eb2e8f9f7 1236 #define CRC_CR_RESET 0x01U /*!< RESET bit */
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1239 /* */
<> 144:ef7eb2e8f9f7 1240 /* Debug MCU */
<> 144:ef7eb2e8f9f7 1241 /* */
<> 144:ef7eb2e8f9f7 1242 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1245 /* */
<> 144:ef7eb2e8f9f7 1246 /* DMA Controller */
<> 144:ef7eb2e8f9f7 1247 /* */
<> 144:ef7eb2e8f9f7 1248 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1249 /******************** Bits definition for DMA_SxCR register *****************/
<> 144:ef7eb2e8f9f7 1250 #define DMA_SxCR_CHSEL 0x0E000000U
<> 144:ef7eb2e8f9f7 1251 #define DMA_SxCR_CHSEL_0 0x02000000U
<> 144:ef7eb2e8f9f7 1252 #define DMA_SxCR_CHSEL_1 0x04000000U
<> 144:ef7eb2e8f9f7 1253 #define DMA_SxCR_CHSEL_2 0x08000000U
<> 144:ef7eb2e8f9f7 1254 #define DMA_SxCR_MBURST 0x01800000U
<> 144:ef7eb2e8f9f7 1255 #define DMA_SxCR_MBURST_0 0x00800000U
<> 144:ef7eb2e8f9f7 1256 #define DMA_SxCR_MBURST_1 0x01000000U
<> 144:ef7eb2e8f9f7 1257 #define DMA_SxCR_PBURST 0x00600000U
<> 144:ef7eb2e8f9f7 1258 #define DMA_SxCR_PBURST_0 0x00200000U
<> 144:ef7eb2e8f9f7 1259 #define DMA_SxCR_PBURST_1 0x00400000U
<> 144:ef7eb2e8f9f7 1260 #define DMA_SxCR_CT 0x00080000U
<> 144:ef7eb2e8f9f7 1261 #define DMA_SxCR_DBM 0x00040000U
<> 144:ef7eb2e8f9f7 1262 #define DMA_SxCR_PL 0x00030000U
<> 144:ef7eb2e8f9f7 1263 #define DMA_SxCR_PL_0 0x00010000U
<> 144:ef7eb2e8f9f7 1264 #define DMA_SxCR_PL_1 0x00020000U
<> 144:ef7eb2e8f9f7 1265 #define DMA_SxCR_PINCOS 0x00008000U
<> 144:ef7eb2e8f9f7 1266 #define DMA_SxCR_MSIZE 0x00006000U
<> 144:ef7eb2e8f9f7 1267 #define DMA_SxCR_MSIZE_0 0x00002000U
<> 144:ef7eb2e8f9f7 1268 #define DMA_SxCR_MSIZE_1 0x00004000U
<> 144:ef7eb2e8f9f7 1269 #define DMA_SxCR_PSIZE 0x00001800U
<> 144:ef7eb2e8f9f7 1270 #define DMA_SxCR_PSIZE_0 0x00000800U
<> 144:ef7eb2e8f9f7 1271 #define DMA_SxCR_PSIZE_1 0x00001000U
<> 144:ef7eb2e8f9f7 1272 #define DMA_SxCR_MINC 0x00000400U
<> 144:ef7eb2e8f9f7 1273 #define DMA_SxCR_PINC 0x00000200U
<> 144:ef7eb2e8f9f7 1274 #define DMA_SxCR_CIRC 0x00000100U
<> 144:ef7eb2e8f9f7 1275 #define DMA_SxCR_DIR 0x000000C0U
<> 144:ef7eb2e8f9f7 1276 #define DMA_SxCR_DIR_0 0x00000040U
<> 144:ef7eb2e8f9f7 1277 #define DMA_SxCR_DIR_1 0x00000080U
<> 144:ef7eb2e8f9f7 1278 #define DMA_SxCR_PFCTRL 0x00000020U
<> 144:ef7eb2e8f9f7 1279 #define DMA_SxCR_TCIE 0x00000010U
<> 144:ef7eb2e8f9f7 1280 #define DMA_SxCR_HTIE 0x00000008U
<> 144:ef7eb2e8f9f7 1281 #define DMA_SxCR_TEIE 0x00000004U
<> 144:ef7eb2e8f9f7 1282 #define DMA_SxCR_DMEIE 0x00000002U
<> 144:ef7eb2e8f9f7 1283 #define DMA_SxCR_EN 0x00000001U
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1286 #define DMA_SxCR_ACK 0x00100000U
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 144:ef7eb2e8f9f7 1289 #define DMA_SxNDT 0x0000FFFFU
<> 144:ef7eb2e8f9f7 1290 #define DMA_SxNDT_0 0x00000001U
<> 144:ef7eb2e8f9f7 1291 #define DMA_SxNDT_1 0x00000002U
<> 144:ef7eb2e8f9f7 1292 #define DMA_SxNDT_2 0x00000004U
<> 144:ef7eb2e8f9f7 1293 #define DMA_SxNDT_3 0x00000008U
<> 144:ef7eb2e8f9f7 1294 #define DMA_SxNDT_4 0x00000010U
<> 144:ef7eb2e8f9f7 1295 #define DMA_SxNDT_5 0x00000020U
<> 144:ef7eb2e8f9f7 1296 #define DMA_SxNDT_6 0x00000040U
<> 144:ef7eb2e8f9f7 1297 #define DMA_SxNDT_7 0x00000080U
<> 144:ef7eb2e8f9f7 1298 #define DMA_SxNDT_8 0x00000100U
<> 144:ef7eb2e8f9f7 1299 #define DMA_SxNDT_9 0x00000200U
<> 144:ef7eb2e8f9f7 1300 #define DMA_SxNDT_10 0x00000400U
<> 144:ef7eb2e8f9f7 1301 #define DMA_SxNDT_11 0x00000800U
<> 144:ef7eb2e8f9f7 1302 #define DMA_SxNDT_12 0x00001000U
<> 144:ef7eb2e8f9f7 1303 #define DMA_SxNDT_13 0x00002000U
<> 144:ef7eb2e8f9f7 1304 #define DMA_SxNDT_14 0x00004000U
<> 144:ef7eb2e8f9f7 1305 #define DMA_SxNDT_15 0x00008000U
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /******************** Bits definition for DMA_SxFCR register ****************/
<> 144:ef7eb2e8f9f7 1308 #define DMA_SxFCR_FEIE 0x00000080U
<> 144:ef7eb2e8f9f7 1309 #define DMA_SxFCR_FS 0x00000038U
<> 144:ef7eb2e8f9f7 1310 #define DMA_SxFCR_FS_0 0x00000008U
<> 144:ef7eb2e8f9f7 1311 #define DMA_SxFCR_FS_1 0x00000010U
<> 144:ef7eb2e8f9f7 1312 #define DMA_SxFCR_FS_2 0x00000020U
<> 144:ef7eb2e8f9f7 1313 #define DMA_SxFCR_DMDIS 0x00000004U
<> 144:ef7eb2e8f9f7 1314 #define DMA_SxFCR_FTH 0x00000003U
<> 144:ef7eb2e8f9f7 1315 #define DMA_SxFCR_FTH_0 0x00000001U
<> 144:ef7eb2e8f9f7 1316 #define DMA_SxFCR_FTH_1 0x00000002U
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /******************** Bits definition for DMA_LISR register *****************/
<> 144:ef7eb2e8f9f7 1319 #define DMA_LISR_TCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 1320 #define DMA_LISR_HTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 1321 #define DMA_LISR_TEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 1322 #define DMA_LISR_DMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 1323 #define DMA_LISR_FEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 1324 #define DMA_LISR_TCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 1325 #define DMA_LISR_HTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 1326 #define DMA_LISR_TEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 1327 #define DMA_LISR_DMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 1328 #define DMA_LISR_FEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 1329 #define DMA_LISR_TCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 1330 #define DMA_LISR_HTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 1331 #define DMA_LISR_TEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 1332 #define DMA_LISR_DMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 1333 #define DMA_LISR_FEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 1334 #define DMA_LISR_TCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 1335 #define DMA_LISR_HTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 1336 #define DMA_LISR_TEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 1337 #define DMA_LISR_DMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 1338 #define DMA_LISR_FEIF0 0x00000001U
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /******************** Bits definition for DMA_HISR register *****************/
<> 144:ef7eb2e8f9f7 1341 #define DMA_HISR_TCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 1342 #define DMA_HISR_HTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 1343 #define DMA_HISR_TEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 1344 #define DMA_HISR_DMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 1345 #define DMA_HISR_FEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 1346 #define DMA_HISR_TCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 1347 #define DMA_HISR_HTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 1348 #define DMA_HISR_TEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 1349 #define DMA_HISR_DMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 1350 #define DMA_HISR_FEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 1351 #define DMA_HISR_TCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 1352 #define DMA_HISR_HTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 1353 #define DMA_HISR_TEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 1354 #define DMA_HISR_DMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 1355 #define DMA_HISR_FEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 1356 #define DMA_HISR_TCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 1357 #define DMA_HISR_HTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 1358 #define DMA_HISR_TEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 1359 #define DMA_HISR_DMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 1360 #define DMA_HISR_FEIF4 0x00000001U
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /******************** Bits definition for DMA_LIFCR register ****************/
<> 144:ef7eb2e8f9f7 1363 #define DMA_LIFCR_CTCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 1364 #define DMA_LIFCR_CHTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 1365 #define DMA_LIFCR_CTEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 1366 #define DMA_LIFCR_CDMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 1367 #define DMA_LIFCR_CFEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 1368 #define DMA_LIFCR_CTCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 1369 #define DMA_LIFCR_CHTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 1370 #define DMA_LIFCR_CTEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 1371 #define DMA_LIFCR_CDMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 1372 #define DMA_LIFCR_CFEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 1373 #define DMA_LIFCR_CTCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 1374 #define DMA_LIFCR_CHTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 1375 #define DMA_LIFCR_CTEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 1376 #define DMA_LIFCR_CDMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 1377 #define DMA_LIFCR_CFEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 1378 #define DMA_LIFCR_CTCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 1379 #define DMA_LIFCR_CHTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 1380 #define DMA_LIFCR_CTEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 1381 #define DMA_LIFCR_CDMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 1382 #define DMA_LIFCR_CFEIF0 0x00000001U
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /******************** Bits definition for DMA_HIFCR register ****************/
<> 144:ef7eb2e8f9f7 1385 #define DMA_HIFCR_CTCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 1386 #define DMA_HIFCR_CHTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 1387 #define DMA_HIFCR_CTEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 1388 #define DMA_HIFCR_CDMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 1389 #define DMA_HIFCR_CFEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 1390 #define DMA_HIFCR_CTCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 1391 #define DMA_HIFCR_CHTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 1392 #define DMA_HIFCR_CTEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 1393 #define DMA_HIFCR_CDMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 1394 #define DMA_HIFCR_CFEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 1395 #define DMA_HIFCR_CTCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 1396 #define DMA_HIFCR_CHTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 1397 #define DMA_HIFCR_CTEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 1398 #define DMA_HIFCR_CDMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 1399 #define DMA_HIFCR_CFEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 1400 #define DMA_HIFCR_CTCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 1401 #define DMA_HIFCR_CHTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 1402 #define DMA_HIFCR_CTEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 1403 #define DMA_HIFCR_CDMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 1404 #define DMA_HIFCR_CFEIF4 0x00000001U
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1408 /* */
<> 144:ef7eb2e8f9f7 1409 /* External Interrupt/Event Controller */
<> 144:ef7eb2e8f9f7 1410 /* */
<> 144:ef7eb2e8f9f7 1411 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1412 /******************* Bit definition for EXTI_IMR register *******************/
<> 144:ef7eb2e8f9f7 1413 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
<> 144:ef7eb2e8f9f7 1414 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
<> 144:ef7eb2e8f9f7 1415 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
<> 144:ef7eb2e8f9f7 1416 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
<> 144:ef7eb2e8f9f7 1417 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
<> 144:ef7eb2e8f9f7 1418 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
<> 144:ef7eb2e8f9f7 1419 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
<> 144:ef7eb2e8f9f7 1420 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
<> 144:ef7eb2e8f9f7 1421 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
<> 144:ef7eb2e8f9f7 1422 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
<> 144:ef7eb2e8f9f7 1423 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
<> 144:ef7eb2e8f9f7 1424 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
<> 144:ef7eb2e8f9f7 1425 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
<> 144:ef7eb2e8f9f7 1426 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
<> 144:ef7eb2e8f9f7 1427 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
<> 144:ef7eb2e8f9f7 1428 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
<> 144:ef7eb2e8f9f7 1429 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
<> 144:ef7eb2e8f9f7 1430 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
<> 144:ef7eb2e8f9f7 1431 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
<> 144:ef7eb2e8f9f7 1432 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
<> 144:ef7eb2e8f9f7 1433 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
<> 144:ef7eb2e8f9f7 1434 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
<> 144:ef7eb2e8f9f7 1435 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /******************* Bit definition for EXTI_EMR register *******************/
<> 144:ef7eb2e8f9f7 1438 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
<> 144:ef7eb2e8f9f7 1439 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
<> 144:ef7eb2e8f9f7 1440 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
<> 144:ef7eb2e8f9f7 1441 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
<> 144:ef7eb2e8f9f7 1442 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
<> 144:ef7eb2e8f9f7 1443 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
<> 144:ef7eb2e8f9f7 1444 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
<> 144:ef7eb2e8f9f7 1445 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
<> 144:ef7eb2e8f9f7 1446 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
<> 144:ef7eb2e8f9f7 1447 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
<> 144:ef7eb2e8f9f7 1448 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
<> 144:ef7eb2e8f9f7 1449 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
<> 144:ef7eb2e8f9f7 1450 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
<> 144:ef7eb2e8f9f7 1451 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
<> 144:ef7eb2e8f9f7 1452 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
<> 144:ef7eb2e8f9f7 1453 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
<> 144:ef7eb2e8f9f7 1454 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
<> 144:ef7eb2e8f9f7 1455 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
<> 144:ef7eb2e8f9f7 1456 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
<> 144:ef7eb2e8f9f7 1457 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
<> 144:ef7eb2e8f9f7 1458 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
<> 144:ef7eb2e8f9f7 1459 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
<> 144:ef7eb2e8f9f7 1460 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /****************** Bit definition for EXTI_RTSR register *******************/
<> 144:ef7eb2e8f9f7 1463 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 1464 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 1465 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 1466 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 1467 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 1468 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 1469 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 1470 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 1471 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 1472 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 1473 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 1474 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 1475 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 1476 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 1477 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 1478 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 1479 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 1480 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 1481 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 1482 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 1483 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 1484 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 1485 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /****************** Bit definition for EXTI_FTSR register *******************/
<> 144:ef7eb2e8f9f7 1488 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 1489 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 1490 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 1491 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 1492 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 1493 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 1494 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 1495 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 1496 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 1497 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 1498 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 1499 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 1500 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 1501 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 1502 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 1503 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 1504 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 1505 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 1506 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 1507 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 1508 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 1509 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 1510 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 /****************** Bit definition for EXTI_SWIER register ******************/
<> 144:ef7eb2e8f9f7 1513 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
<> 144:ef7eb2e8f9f7 1514 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
<> 144:ef7eb2e8f9f7 1515 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
<> 144:ef7eb2e8f9f7 1516 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
<> 144:ef7eb2e8f9f7 1517 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
<> 144:ef7eb2e8f9f7 1518 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
<> 144:ef7eb2e8f9f7 1519 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
<> 144:ef7eb2e8f9f7 1520 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
<> 144:ef7eb2e8f9f7 1521 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
<> 144:ef7eb2e8f9f7 1522 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
<> 144:ef7eb2e8f9f7 1523 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
<> 144:ef7eb2e8f9f7 1524 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
<> 144:ef7eb2e8f9f7 1525 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
<> 144:ef7eb2e8f9f7 1526 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
<> 144:ef7eb2e8f9f7 1527 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
<> 144:ef7eb2e8f9f7 1528 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
<> 144:ef7eb2e8f9f7 1529 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
<> 144:ef7eb2e8f9f7 1530 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
<> 144:ef7eb2e8f9f7 1531 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
<> 144:ef7eb2e8f9f7 1532 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
<> 144:ef7eb2e8f9f7 1533 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
<> 144:ef7eb2e8f9f7 1534 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
<> 144:ef7eb2e8f9f7 1535 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 /******************* Bit definition for EXTI_PR register ********************/
<> 144:ef7eb2e8f9f7 1538 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
<> 144:ef7eb2e8f9f7 1539 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
<> 144:ef7eb2e8f9f7 1540 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
<> 144:ef7eb2e8f9f7 1541 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
<> 144:ef7eb2e8f9f7 1542 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
<> 144:ef7eb2e8f9f7 1543 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
<> 144:ef7eb2e8f9f7 1544 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
<> 144:ef7eb2e8f9f7 1545 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
<> 144:ef7eb2e8f9f7 1546 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
<> 144:ef7eb2e8f9f7 1547 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
<> 144:ef7eb2e8f9f7 1548 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
<> 144:ef7eb2e8f9f7 1549 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
<> 144:ef7eb2e8f9f7 1550 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
<> 144:ef7eb2e8f9f7 1551 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
<> 144:ef7eb2e8f9f7 1552 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
<> 144:ef7eb2e8f9f7 1553 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
<> 144:ef7eb2e8f9f7 1554 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
<> 144:ef7eb2e8f9f7 1555 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
<> 144:ef7eb2e8f9f7 1556 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
<> 144:ef7eb2e8f9f7 1557 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
<> 144:ef7eb2e8f9f7 1558 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
<> 144:ef7eb2e8f9f7 1559 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
<> 144:ef7eb2e8f9f7 1560 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
<> 144:ef7eb2e8f9f7 1561
<> 144:ef7eb2e8f9f7 1562 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1563 /* */
<> 144:ef7eb2e8f9f7 1564 /* FLASH */
<> 144:ef7eb2e8f9f7 1565 /* */
<> 144:ef7eb2e8f9f7 1566 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1567 /******************* Bits definition for FLASH_ACR register *****************/
<> 144:ef7eb2e8f9f7 1568 #define FLASH_ACR_LATENCY 0x0000000FU
<> 144:ef7eb2e8f9f7 1569 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 144:ef7eb2e8f9f7 1570 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 144:ef7eb2e8f9f7 1571 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 144:ef7eb2e8f9f7 1572 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 144:ef7eb2e8f9f7 1573 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 144:ef7eb2e8f9f7 1574 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 144:ef7eb2e8f9f7 1575 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 144:ef7eb2e8f9f7 1576 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 #define FLASH_ACR_PRFTEN 0x00000100U
<> 144:ef7eb2e8f9f7 1579 #define FLASH_ACR_ICEN 0x00000200U
<> 144:ef7eb2e8f9f7 1580 #define FLASH_ACR_DCEN 0x00000400U
<> 144:ef7eb2e8f9f7 1581 #define FLASH_ACR_ICRST 0x00000800U
<> 144:ef7eb2e8f9f7 1582 #define FLASH_ACR_DCRST 0x00001000U
<> 144:ef7eb2e8f9f7 1583 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
<> 144:ef7eb2e8f9f7 1584 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 /******************* Bits definition for FLASH_SR register ******************/
<> 144:ef7eb2e8f9f7 1587 #define FLASH_SR_EOP 0x00000001U
<> 144:ef7eb2e8f9f7 1588 #define FLASH_SR_SOP 0x00000002U
<> 144:ef7eb2e8f9f7 1589 #define FLASH_SR_WRPERR 0x00000010U
<> 144:ef7eb2e8f9f7 1590 #define FLASH_SR_PGAERR 0x00000020U
<> 144:ef7eb2e8f9f7 1591 #define FLASH_SR_PGPERR 0x00000040U
<> 144:ef7eb2e8f9f7 1592 #define FLASH_SR_PGSERR 0x00000080U
<> 144:ef7eb2e8f9f7 1593 #define FLASH_SR_BSY 0x00010000U
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /******************* Bits definition for FLASH_CR register ******************/
<> 144:ef7eb2e8f9f7 1596 #define FLASH_CR_PG 0x00000001U
<> 144:ef7eb2e8f9f7 1597 #define FLASH_CR_SER 0x00000002U
<> 144:ef7eb2e8f9f7 1598 #define FLASH_CR_MER 0x00000004U
<> 144:ef7eb2e8f9f7 1599 #define FLASH_CR_SNB 0x000000F8U
<> 144:ef7eb2e8f9f7 1600 #define FLASH_CR_SNB_0 0x00000008U
<> 144:ef7eb2e8f9f7 1601 #define FLASH_CR_SNB_1 0x00000010U
<> 144:ef7eb2e8f9f7 1602 #define FLASH_CR_SNB_2 0x00000020U
<> 144:ef7eb2e8f9f7 1603 #define FLASH_CR_SNB_3 0x00000040U
<> 144:ef7eb2e8f9f7 1604 #define FLASH_CR_SNB_4 0x00000080U
<> 144:ef7eb2e8f9f7 1605 #define FLASH_CR_PSIZE 0x00000300U
<> 144:ef7eb2e8f9f7 1606 #define FLASH_CR_PSIZE_0 0x00000100U
<> 144:ef7eb2e8f9f7 1607 #define FLASH_CR_PSIZE_1 0x00000200U
<> 144:ef7eb2e8f9f7 1608 #define FLASH_CR_STRT 0x00010000U
<> 144:ef7eb2e8f9f7 1609 #define FLASH_CR_EOPIE 0x01000000U
<> 144:ef7eb2e8f9f7 1610 #define FLASH_CR_LOCK 0x80000000U
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 144:ef7eb2e8f9f7 1613 #define FLASH_OPTCR_OPTLOCK 0x00000001U
<> 144:ef7eb2e8f9f7 1614 #define FLASH_OPTCR_OPTSTRT 0x00000002U
<> 144:ef7eb2e8f9f7 1615 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
<> 144:ef7eb2e8f9f7 1616 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
<> 144:ef7eb2e8f9f7 1617 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
<> 144:ef7eb2e8f9f7 1618
<> 144:ef7eb2e8f9f7 1619 #define FLASH_OPTCR_WDG_SW 0x00000020U
<> 144:ef7eb2e8f9f7 1620 #define FLASH_OPTCR_nRST_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 1621 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
<> 144:ef7eb2e8f9f7 1622 #define FLASH_OPTCR_RDP 0x0000FF00U
<> 144:ef7eb2e8f9f7 1623 #define FLASH_OPTCR_RDP_0 0x00000100U
<> 144:ef7eb2e8f9f7 1624 #define FLASH_OPTCR_RDP_1 0x00000200U
<> 144:ef7eb2e8f9f7 1625 #define FLASH_OPTCR_RDP_2 0x00000400U
<> 144:ef7eb2e8f9f7 1626 #define FLASH_OPTCR_RDP_3 0x00000800U
<> 144:ef7eb2e8f9f7 1627 #define FLASH_OPTCR_RDP_4 0x00001000U
<> 144:ef7eb2e8f9f7 1628 #define FLASH_OPTCR_RDP_5 0x00002000U
<> 144:ef7eb2e8f9f7 1629 #define FLASH_OPTCR_RDP_6 0x00004000U
<> 144:ef7eb2e8f9f7 1630 #define FLASH_OPTCR_RDP_7 0x00008000U
<> 144:ef7eb2e8f9f7 1631 #define FLASH_OPTCR_nWRP 0x0FFF0000U
<> 144:ef7eb2e8f9f7 1632 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 144:ef7eb2e8f9f7 1633 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 144:ef7eb2e8f9f7 1634 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 144:ef7eb2e8f9f7 1635 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 144:ef7eb2e8f9f7 1636 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 144:ef7eb2e8f9f7 1637 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 144:ef7eb2e8f9f7 1638 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 144:ef7eb2e8f9f7 1639 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 144:ef7eb2e8f9f7 1640 #define FLASH_OPTCR_nWRP_8 0x01000000U
<> 144:ef7eb2e8f9f7 1641 #define FLASH_OPTCR_nWRP_9 0x02000000U
<> 144:ef7eb2e8f9f7 1642 #define FLASH_OPTCR_nWRP_10 0x04000000U
<> 144:ef7eb2e8f9f7 1643 #define FLASH_OPTCR_nWRP_11 0x08000000U
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 /****************** Bits definition for FLASH_OPTCR1 register ***************/
<> 144:ef7eb2e8f9f7 1646 #define FLASH_OPTCR1_nWRP 0x0FFF0000U
<> 144:ef7eb2e8f9f7 1647 #define FLASH_OPTCR1_nWRP_0 0x00010000U
<> 144:ef7eb2e8f9f7 1648 #define FLASH_OPTCR1_nWRP_1 0x00020000U
<> 144:ef7eb2e8f9f7 1649 #define FLASH_OPTCR1_nWRP_2 0x00040000U
<> 144:ef7eb2e8f9f7 1650 #define FLASH_OPTCR1_nWRP_3 0x00080000U
<> 144:ef7eb2e8f9f7 1651 #define FLASH_OPTCR1_nWRP_4 0x00100000U
<> 144:ef7eb2e8f9f7 1652 #define FLASH_OPTCR1_nWRP_5 0x00200000U
<> 144:ef7eb2e8f9f7 1653 #define FLASH_OPTCR1_nWRP_6 0x00400000U
<> 144:ef7eb2e8f9f7 1654 #define FLASH_OPTCR1_nWRP_7 0x00800000U
<> 144:ef7eb2e8f9f7 1655 #define FLASH_OPTCR1_nWRP_8 0x01000000U
<> 144:ef7eb2e8f9f7 1656 #define FLASH_OPTCR1_nWRP_9 0x02000000U
<> 144:ef7eb2e8f9f7 1657 #define FLASH_OPTCR1_nWRP_10 0x04000000U
<> 144:ef7eb2e8f9f7 1658 #define FLASH_OPTCR1_nWRP_11 0x08000000U
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1661 /* */
<> 144:ef7eb2e8f9f7 1662 /* General Purpose I/O */
<> 144:ef7eb2e8f9f7 1663 /* */
<> 144:ef7eb2e8f9f7 1664 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1665 /****************** Bits definition for GPIO_MODER register *****************/
<> 144:ef7eb2e8f9f7 1666 #define GPIO_MODER_MODER0 0x00000003U
<> 144:ef7eb2e8f9f7 1667 #define GPIO_MODER_MODER0_0 0x00000001U
<> 144:ef7eb2e8f9f7 1668 #define GPIO_MODER_MODER0_1 0x00000002U
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 #define GPIO_MODER_MODER1 0x0000000CU
<> 144:ef7eb2e8f9f7 1671 #define GPIO_MODER_MODER1_0 0x00000004U
<> 144:ef7eb2e8f9f7 1672 #define GPIO_MODER_MODER1_1 0x00000008U
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 #define GPIO_MODER_MODER2 0x00000030U
<> 144:ef7eb2e8f9f7 1675 #define GPIO_MODER_MODER2_0 0x00000010U
<> 144:ef7eb2e8f9f7 1676 #define GPIO_MODER_MODER2_1 0x00000020U
<> 144:ef7eb2e8f9f7 1677
<> 144:ef7eb2e8f9f7 1678 #define GPIO_MODER_MODER3 0x000000C0U
<> 144:ef7eb2e8f9f7 1679 #define GPIO_MODER_MODER3_0 0x00000040U
<> 144:ef7eb2e8f9f7 1680 #define GPIO_MODER_MODER3_1 0x00000080U
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 #define GPIO_MODER_MODER4 0x00000300U
<> 144:ef7eb2e8f9f7 1683 #define GPIO_MODER_MODER4_0 0x00000100U
<> 144:ef7eb2e8f9f7 1684 #define GPIO_MODER_MODER4_1 0x00000200U
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 #define GPIO_MODER_MODER5 0x00000C00U
<> 144:ef7eb2e8f9f7 1687 #define GPIO_MODER_MODER5_0 0x00000400U
<> 144:ef7eb2e8f9f7 1688 #define GPIO_MODER_MODER5_1 0x00000800U
<> 144:ef7eb2e8f9f7 1689
<> 144:ef7eb2e8f9f7 1690 #define GPIO_MODER_MODER6 0x00003000U
<> 144:ef7eb2e8f9f7 1691 #define GPIO_MODER_MODER6_0 0x00001000U
<> 144:ef7eb2e8f9f7 1692 #define GPIO_MODER_MODER6_1 0x00002000U
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 #define GPIO_MODER_MODER7 0x0000C000U
<> 144:ef7eb2e8f9f7 1695 #define GPIO_MODER_MODER7_0 0x00004000U
<> 144:ef7eb2e8f9f7 1696 #define GPIO_MODER_MODER7_1 0x00008000U
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 #define GPIO_MODER_MODER8 0x00030000U
<> 144:ef7eb2e8f9f7 1699 #define GPIO_MODER_MODER8_0 0x00010000U
<> 144:ef7eb2e8f9f7 1700 #define GPIO_MODER_MODER8_1 0x00020000U
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 #define GPIO_MODER_MODER9 0x000C0000U
<> 144:ef7eb2e8f9f7 1703 #define GPIO_MODER_MODER9_0 0x00040000U
<> 144:ef7eb2e8f9f7 1704 #define GPIO_MODER_MODER9_1 0x00080000U
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 #define GPIO_MODER_MODER10 0x00300000U
<> 144:ef7eb2e8f9f7 1707 #define GPIO_MODER_MODER10_0 0x00100000U
<> 144:ef7eb2e8f9f7 1708 #define GPIO_MODER_MODER10_1 0x00200000U
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 #define GPIO_MODER_MODER11 0x00C00000U
<> 144:ef7eb2e8f9f7 1711 #define GPIO_MODER_MODER11_0 0x00400000U
<> 144:ef7eb2e8f9f7 1712 #define GPIO_MODER_MODER11_1 0x00800000U
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 #define GPIO_MODER_MODER12 0x03000000U
<> 144:ef7eb2e8f9f7 1715 #define GPIO_MODER_MODER12_0 0x01000000U
<> 144:ef7eb2e8f9f7 1716 #define GPIO_MODER_MODER12_1 0x02000000U
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 #define GPIO_MODER_MODER13 0x0C000000U
<> 144:ef7eb2e8f9f7 1719 #define GPIO_MODER_MODER13_0 0x04000000U
<> 144:ef7eb2e8f9f7 1720 #define GPIO_MODER_MODER13_1 0x08000000U
<> 144:ef7eb2e8f9f7 1721
<> 144:ef7eb2e8f9f7 1722 #define GPIO_MODER_MODER14 0x30000000U
<> 144:ef7eb2e8f9f7 1723 #define GPIO_MODER_MODER14_0 0x10000000U
<> 144:ef7eb2e8f9f7 1724 #define GPIO_MODER_MODER14_1 0x20000000U
<> 144:ef7eb2e8f9f7 1725
<> 144:ef7eb2e8f9f7 1726 #define GPIO_MODER_MODER15 0xC0000000U
<> 144:ef7eb2e8f9f7 1727 #define GPIO_MODER_MODER15_0 0x40000000U
<> 144:ef7eb2e8f9f7 1728 #define GPIO_MODER_MODER15_1 0x80000000U
<> 144:ef7eb2e8f9f7 1729
<> 144:ef7eb2e8f9f7 1730 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 144:ef7eb2e8f9f7 1731 #define GPIO_OTYPER_OT_0 0x00000001U
<> 144:ef7eb2e8f9f7 1732 #define GPIO_OTYPER_OT_1 0x00000002U
<> 144:ef7eb2e8f9f7 1733 #define GPIO_OTYPER_OT_2 0x00000004U
<> 144:ef7eb2e8f9f7 1734 #define GPIO_OTYPER_OT_3 0x00000008U
<> 144:ef7eb2e8f9f7 1735 #define GPIO_OTYPER_OT_4 0x00000010U
<> 144:ef7eb2e8f9f7 1736 #define GPIO_OTYPER_OT_5 0x00000020U
<> 144:ef7eb2e8f9f7 1737 #define GPIO_OTYPER_OT_6 0x00000040U
<> 144:ef7eb2e8f9f7 1738 #define GPIO_OTYPER_OT_7 0x00000080U
<> 144:ef7eb2e8f9f7 1739 #define GPIO_OTYPER_OT_8 0x00000100U
<> 144:ef7eb2e8f9f7 1740 #define GPIO_OTYPER_OT_9 0x00000200U
<> 144:ef7eb2e8f9f7 1741 #define GPIO_OTYPER_OT_10 0x00000400U
<> 144:ef7eb2e8f9f7 1742 #define GPIO_OTYPER_OT_11 0x00000800U
<> 144:ef7eb2e8f9f7 1743 #define GPIO_OTYPER_OT_12 0x00001000U
<> 144:ef7eb2e8f9f7 1744 #define GPIO_OTYPER_OT_13 0x00002000U
<> 144:ef7eb2e8f9f7 1745 #define GPIO_OTYPER_OT_14 0x00004000U
<> 144:ef7eb2e8f9f7 1746 #define GPIO_OTYPER_OT_15 0x00008000U
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 144:ef7eb2e8f9f7 1749 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
<> 144:ef7eb2e8f9f7 1750 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
<> 144:ef7eb2e8f9f7 1751 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
<> 144:ef7eb2e8f9f7 1754 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
<> 144:ef7eb2e8f9f7 1755 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
<> 144:ef7eb2e8f9f7 1758 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
<> 144:ef7eb2e8f9f7 1759 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
<> 144:ef7eb2e8f9f7 1762 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
<> 144:ef7eb2e8f9f7 1763 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
<> 144:ef7eb2e8f9f7 1764
<> 144:ef7eb2e8f9f7 1765 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
<> 144:ef7eb2e8f9f7 1766 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
<> 144:ef7eb2e8f9f7 1767 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
<> 144:ef7eb2e8f9f7 1770 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
<> 144:ef7eb2e8f9f7 1771 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
<> 144:ef7eb2e8f9f7 1774 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
<> 144:ef7eb2e8f9f7 1775 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
<> 144:ef7eb2e8f9f7 1776
<> 144:ef7eb2e8f9f7 1777 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
<> 144:ef7eb2e8f9f7 1778 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
<> 144:ef7eb2e8f9f7 1779 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
<> 144:ef7eb2e8f9f7 1780
<> 144:ef7eb2e8f9f7 1781 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
<> 144:ef7eb2e8f9f7 1782 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
<> 144:ef7eb2e8f9f7 1783 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
<> 144:ef7eb2e8f9f7 1786 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
<> 144:ef7eb2e8f9f7 1787 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
<> 144:ef7eb2e8f9f7 1788
<> 144:ef7eb2e8f9f7 1789 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
<> 144:ef7eb2e8f9f7 1790 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
<> 144:ef7eb2e8f9f7 1791 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
<> 144:ef7eb2e8f9f7 1792
<> 144:ef7eb2e8f9f7 1793 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
<> 144:ef7eb2e8f9f7 1794 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
<> 144:ef7eb2e8f9f7 1795 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
<> 144:ef7eb2e8f9f7 1796
<> 144:ef7eb2e8f9f7 1797 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
<> 144:ef7eb2e8f9f7 1798 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
<> 144:ef7eb2e8f9f7 1799 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
<> 144:ef7eb2e8f9f7 1802 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
<> 144:ef7eb2e8f9f7 1803 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
<> 144:ef7eb2e8f9f7 1804
<> 144:ef7eb2e8f9f7 1805 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
<> 144:ef7eb2e8f9f7 1806 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
<> 144:ef7eb2e8f9f7 1807 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
<> 144:ef7eb2e8f9f7 1810 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
<> 144:ef7eb2e8f9f7 1811 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 144:ef7eb2e8f9f7 1814 #define GPIO_PUPDR_PUPDR0 0x00000003U
<> 144:ef7eb2e8f9f7 1815 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
<> 144:ef7eb2e8f9f7 1816 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 #define GPIO_PUPDR_PUPDR1 0x0000000CU
<> 144:ef7eb2e8f9f7 1819 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
<> 144:ef7eb2e8f9f7 1820 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 #define GPIO_PUPDR_PUPDR2 0x00000030U
<> 144:ef7eb2e8f9f7 1823 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
<> 144:ef7eb2e8f9f7 1824 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 #define GPIO_PUPDR_PUPDR3 0x000000C0U
<> 144:ef7eb2e8f9f7 1827 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
<> 144:ef7eb2e8f9f7 1828 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 #define GPIO_PUPDR_PUPDR4 0x00000300U
<> 144:ef7eb2e8f9f7 1831 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
<> 144:ef7eb2e8f9f7 1832 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 #define GPIO_PUPDR_PUPDR5 0x00000C00U
<> 144:ef7eb2e8f9f7 1835 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
<> 144:ef7eb2e8f9f7 1836 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838 #define GPIO_PUPDR_PUPDR6 0x00003000U
<> 144:ef7eb2e8f9f7 1839 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
<> 144:ef7eb2e8f9f7 1840 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 #define GPIO_PUPDR_PUPDR7 0x0000C000U
<> 144:ef7eb2e8f9f7 1843 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
<> 144:ef7eb2e8f9f7 1844 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 #define GPIO_PUPDR_PUPDR8 0x00030000U
<> 144:ef7eb2e8f9f7 1847 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
<> 144:ef7eb2e8f9f7 1848 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850 #define GPIO_PUPDR_PUPDR9 0x000C0000U
<> 144:ef7eb2e8f9f7 1851 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
<> 144:ef7eb2e8f9f7 1852 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 #define GPIO_PUPDR_PUPDR10 0x00300000U
<> 144:ef7eb2e8f9f7 1855 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
<> 144:ef7eb2e8f9f7 1856 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
<> 144:ef7eb2e8f9f7 1857
<> 144:ef7eb2e8f9f7 1858 #define GPIO_PUPDR_PUPDR11 0x00C00000U
<> 144:ef7eb2e8f9f7 1859 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
<> 144:ef7eb2e8f9f7 1860 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 #define GPIO_PUPDR_PUPDR12 0x03000000U
<> 144:ef7eb2e8f9f7 1863 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
<> 144:ef7eb2e8f9f7 1864 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 #define GPIO_PUPDR_PUPDR13 0x0C000000U
<> 144:ef7eb2e8f9f7 1867 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
<> 144:ef7eb2e8f9f7 1868 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 #define GPIO_PUPDR_PUPDR14 0x30000000U
<> 144:ef7eb2e8f9f7 1871 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
<> 144:ef7eb2e8f9f7 1872 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 #define GPIO_PUPDR_PUPDR15 0xC0000000U
<> 144:ef7eb2e8f9f7 1875 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
<> 144:ef7eb2e8f9f7 1876 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /****************** Bits definition for GPIO_IDR register *******************/
<> 144:ef7eb2e8f9f7 1879 #define GPIO_IDR_IDR_0 0x00000001U
<> 144:ef7eb2e8f9f7 1880 #define GPIO_IDR_IDR_1 0x00000002U
<> 144:ef7eb2e8f9f7 1881 #define GPIO_IDR_IDR_2 0x00000004U
<> 144:ef7eb2e8f9f7 1882 #define GPIO_IDR_IDR_3 0x00000008U
<> 144:ef7eb2e8f9f7 1883 #define GPIO_IDR_IDR_4 0x00000010U
<> 144:ef7eb2e8f9f7 1884 #define GPIO_IDR_IDR_5 0x00000020U
<> 144:ef7eb2e8f9f7 1885 #define GPIO_IDR_IDR_6 0x00000040U
<> 144:ef7eb2e8f9f7 1886 #define GPIO_IDR_IDR_7 0x00000080U
<> 144:ef7eb2e8f9f7 1887 #define GPIO_IDR_IDR_8 0x00000100U
<> 144:ef7eb2e8f9f7 1888 #define GPIO_IDR_IDR_9 0x00000200U
<> 144:ef7eb2e8f9f7 1889 #define GPIO_IDR_IDR_10 0x00000400U
<> 144:ef7eb2e8f9f7 1890 #define GPIO_IDR_IDR_11 0x00000800U
<> 144:ef7eb2e8f9f7 1891 #define GPIO_IDR_IDR_12 0x00001000U
<> 144:ef7eb2e8f9f7 1892 #define GPIO_IDR_IDR_13 0x00002000U
<> 144:ef7eb2e8f9f7 1893 #define GPIO_IDR_IDR_14 0x00004000U
<> 144:ef7eb2e8f9f7 1894 #define GPIO_IDR_IDR_15 0x00008000U
<> 144:ef7eb2e8f9f7 1895 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 1896 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
<> 144:ef7eb2e8f9f7 1897 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
<> 144:ef7eb2e8f9f7 1898 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
<> 144:ef7eb2e8f9f7 1899 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
<> 144:ef7eb2e8f9f7 1900 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
<> 144:ef7eb2e8f9f7 1901 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
<> 144:ef7eb2e8f9f7 1902 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
<> 144:ef7eb2e8f9f7 1903 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
<> 144:ef7eb2e8f9f7 1904 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
<> 144:ef7eb2e8f9f7 1905 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
<> 144:ef7eb2e8f9f7 1906 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
<> 144:ef7eb2e8f9f7 1907 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
<> 144:ef7eb2e8f9f7 1908 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
<> 144:ef7eb2e8f9f7 1909 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
<> 144:ef7eb2e8f9f7 1910 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
<> 144:ef7eb2e8f9f7 1911 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
<> 144:ef7eb2e8f9f7 1912
<> 144:ef7eb2e8f9f7 1913 /****************** Bits definition for GPIO_ODR register *******************/
<> 144:ef7eb2e8f9f7 1914 #define GPIO_ODR_ODR_0 0x00000001U
<> 144:ef7eb2e8f9f7 1915 #define GPIO_ODR_ODR_1 0x00000002U
<> 144:ef7eb2e8f9f7 1916 #define GPIO_ODR_ODR_2 0x00000004U
<> 144:ef7eb2e8f9f7 1917 #define GPIO_ODR_ODR_3 0x00000008U
<> 144:ef7eb2e8f9f7 1918 #define GPIO_ODR_ODR_4 0x00000010U
<> 144:ef7eb2e8f9f7 1919 #define GPIO_ODR_ODR_5 0x00000020U
<> 144:ef7eb2e8f9f7 1920 #define GPIO_ODR_ODR_6 0x00000040U
<> 144:ef7eb2e8f9f7 1921 #define GPIO_ODR_ODR_7 0x00000080U
<> 144:ef7eb2e8f9f7 1922 #define GPIO_ODR_ODR_8 0x00000100U
<> 144:ef7eb2e8f9f7 1923 #define GPIO_ODR_ODR_9 0x00000200U
<> 144:ef7eb2e8f9f7 1924 #define GPIO_ODR_ODR_10 0x00000400U
<> 144:ef7eb2e8f9f7 1925 #define GPIO_ODR_ODR_11 0x00000800U
<> 144:ef7eb2e8f9f7 1926 #define GPIO_ODR_ODR_12 0x00001000U
<> 144:ef7eb2e8f9f7 1927 #define GPIO_ODR_ODR_13 0x00002000U
<> 144:ef7eb2e8f9f7 1928 #define GPIO_ODR_ODR_14 0x00004000U
<> 144:ef7eb2e8f9f7 1929 #define GPIO_ODR_ODR_15 0x00008000U
<> 144:ef7eb2e8f9f7 1930 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 1931 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
<> 144:ef7eb2e8f9f7 1932 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
<> 144:ef7eb2e8f9f7 1933 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
<> 144:ef7eb2e8f9f7 1934 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
<> 144:ef7eb2e8f9f7 1935 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
<> 144:ef7eb2e8f9f7 1936 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
<> 144:ef7eb2e8f9f7 1937 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
<> 144:ef7eb2e8f9f7 1938 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
<> 144:ef7eb2e8f9f7 1939 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
<> 144:ef7eb2e8f9f7 1940 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
<> 144:ef7eb2e8f9f7 1941 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
<> 144:ef7eb2e8f9f7 1942 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
<> 144:ef7eb2e8f9f7 1943 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
<> 144:ef7eb2e8f9f7 1944 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
<> 144:ef7eb2e8f9f7 1945 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
<> 144:ef7eb2e8f9f7 1946 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /****************** Bits definition for GPIO_BSRR register ******************/
<> 144:ef7eb2e8f9f7 1949 #define GPIO_BSRR_BS_0 0x00000001U
<> 144:ef7eb2e8f9f7 1950 #define GPIO_BSRR_BS_1 0x00000002U
<> 144:ef7eb2e8f9f7 1951 #define GPIO_BSRR_BS_2 0x00000004U
<> 144:ef7eb2e8f9f7 1952 #define GPIO_BSRR_BS_3 0x00000008U
<> 144:ef7eb2e8f9f7 1953 #define GPIO_BSRR_BS_4 0x00000010U
<> 144:ef7eb2e8f9f7 1954 #define GPIO_BSRR_BS_5 0x00000020U
<> 144:ef7eb2e8f9f7 1955 #define GPIO_BSRR_BS_6 0x00000040U
<> 144:ef7eb2e8f9f7 1956 #define GPIO_BSRR_BS_7 0x00000080U
<> 144:ef7eb2e8f9f7 1957 #define GPIO_BSRR_BS_8 0x00000100U
<> 144:ef7eb2e8f9f7 1958 #define GPIO_BSRR_BS_9 0x00000200U
<> 144:ef7eb2e8f9f7 1959 #define GPIO_BSRR_BS_10 0x00000400U
<> 144:ef7eb2e8f9f7 1960 #define GPIO_BSRR_BS_11 0x00000800U
<> 144:ef7eb2e8f9f7 1961 #define GPIO_BSRR_BS_12 0x00001000U
<> 144:ef7eb2e8f9f7 1962 #define GPIO_BSRR_BS_13 0x00002000U
<> 144:ef7eb2e8f9f7 1963 #define GPIO_BSRR_BS_14 0x00004000U
<> 144:ef7eb2e8f9f7 1964 #define GPIO_BSRR_BS_15 0x00008000U
<> 144:ef7eb2e8f9f7 1965 #define GPIO_BSRR_BR_0 0x00010000U
<> 144:ef7eb2e8f9f7 1966 #define GPIO_BSRR_BR_1 0x00020000U
<> 144:ef7eb2e8f9f7 1967 #define GPIO_BSRR_BR_2 0x00040000U
<> 144:ef7eb2e8f9f7 1968 #define GPIO_BSRR_BR_3 0x00080000U
<> 144:ef7eb2e8f9f7 1969 #define GPIO_BSRR_BR_4 0x00100000U
<> 144:ef7eb2e8f9f7 1970 #define GPIO_BSRR_BR_5 0x00200000U
<> 144:ef7eb2e8f9f7 1971 #define GPIO_BSRR_BR_6 0x00400000U
<> 144:ef7eb2e8f9f7 1972 #define GPIO_BSRR_BR_7 0x00800000U
<> 144:ef7eb2e8f9f7 1973 #define GPIO_BSRR_BR_8 0x01000000U
<> 144:ef7eb2e8f9f7 1974 #define GPIO_BSRR_BR_9 0x02000000U
<> 144:ef7eb2e8f9f7 1975 #define GPIO_BSRR_BR_10 0x04000000U
<> 144:ef7eb2e8f9f7 1976 #define GPIO_BSRR_BR_11 0x08000000U
<> 144:ef7eb2e8f9f7 1977 #define GPIO_BSRR_BR_12 0x10000000U
<> 144:ef7eb2e8f9f7 1978 #define GPIO_BSRR_BR_13 0x20000000U
<> 144:ef7eb2e8f9f7 1979 #define GPIO_BSRR_BR_14 0x40000000U
<> 144:ef7eb2e8f9f7 1980 #define GPIO_BSRR_BR_15 0x80000000U
<> 144:ef7eb2e8f9f7 1981
<> 144:ef7eb2e8f9f7 1982 /****************** Bit definition for GPIO_LCKR register *********************/
<> 144:ef7eb2e8f9f7 1983 #define GPIO_LCKR_LCK0 0x00000001U
<> 144:ef7eb2e8f9f7 1984 #define GPIO_LCKR_LCK1 0x00000002U
<> 144:ef7eb2e8f9f7 1985 #define GPIO_LCKR_LCK2 0x00000004U
<> 144:ef7eb2e8f9f7 1986 #define GPIO_LCKR_LCK3 0x00000008U
<> 144:ef7eb2e8f9f7 1987 #define GPIO_LCKR_LCK4 0x00000010U
<> 144:ef7eb2e8f9f7 1988 #define GPIO_LCKR_LCK5 0x00000020U
<> 144:ef7eb2e8f9f7 1989 #define GPIO_LCKR_LCK6 0x00000040U
<> 144:ef7eb2e8f9f7 1990 #define GPIO_LCKR_LCK7 0x00000080U
<> 144:ef7eb2e8f9f7 1991 #define GPIO_LCKR_LCK8 0x00000100U
<> 144:ef7eb2e8f9f7 1992 #define GPIO_LCKR_LCK9 0x00000200U
<> 144:ef7eb2e8f9f7 1993 #define GPIO_LCKR_LCK10 0x00000400U
<> 144:ef7eb2e8f9f7 1994 #define GPIO_LCKR_LCK11 0x00000800U
<> 144:ef7eb2e8f9f7 1995 #define GPIO_LCKR_LCK12 0x00001000U
<> 144:ef7eb2e8f9f7 1996 #define GPIO_LCKR_LCK13 0x00002000U
<> 144:ef7eb2e8f9f7 1997 #define GPIO_LCKR_LCK14 0x00004000U
<> 144:ef7eb2e8f9f7 1998 #define GPIO_LCKR_LCK15 0x00008000U
<> 144:ef7eb2e8f9f7 1999 #define GPIO_LCKR_LCKK 0x00010000U
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2002 /* */
<> 144:ef7eb2e8f9f7 2003 /* Inter-integrated Circuit Interface */
<> 144:ef7eb2e8f9f7 2004 /* */
<> 144:ef7eb2e8f9f7 2005 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2006 /******************* Bit definition for I2C_CR1 register ********************/
<> 144:ef7eb2e8f9f7 2007 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
<> 144:ef7eb2e8f9f7 2008 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
<> 144:ef7eb2e8f9f7 2009 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
<> 144:ef7eb2e8f9f7 2010 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
<> 144:ef7eb2e8f9f7 2011 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
<> 144:ef7eb2e8f9f7 2012 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
<> 144:ef7eb2e8f9f7 2013 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
<> 144:ef7eb2e8f9f7 2014 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
<> 144:ef7eb2e8f9f7 2015 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
<> 144:ef7eb2e8f9f7 2016 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
<> 144:ef7eb2e8f9f7 2017 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
<> 144:ef7eb2e8f9f7 2018 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
<> 144:ef7eb2e8f9f7 2019 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
<> 144:ef7eb2e8f9f7 2020 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
<> 144:ef7eb2e8f9f7 2021
<> 144:ef7eb2e8f9f7 2022 /******************* Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 2023 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 144:ef7eb2e8f9f7 2024 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2025 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2026 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2027 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2028 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 2029 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 2030
<> 144:ef7eb2e8f9f7 2031 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 2032 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
<> 144:ef7eb2e8f9f7 2033 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
<> 144:ef7eb2e8f9f7 2034 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
<> 144:ef7eb2e8f9f7 2035 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 /******************* Bit definition for I2C_OAR1 register *******************/
<> 144:ef7eb2e8f9f7 2038 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
<> 144:ef7eb2e8f9f7 2039 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
<> 144:ef7eb2e8f9f7 2040
<> 144:ef7eb2e8f9f7 2041 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2042 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2043 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2044 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2045 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 2046 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 2047 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 2048 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 2049 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 2050 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
<> 144:ef7eb2e8f9f7 2053
<> 144:ef7eb2e8f9f7 2054 /******************* Bit definition for I2C_OAR2 register *******************/
<> 144:ef7eb2e8f9f7 2055 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
<> 144:ef7eb2e8f9f7 2056 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
<> 144:ef7eb2e8f9f7 2057
<> 144:ef7eb2e8f9f7 2058 /******************** Bit definition for I2C_DR register ********************/
<> 144:ef7eb2e8f9f7 2059 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
<> 144:ef7eb2e8f9f7 2060
<> 144:ef7eb2e8f9f7 2061 /******************* Bit definition for I2C_SR1 register ********************/
<> 144:ef7eb2e8f9f7 2062 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
<> 144:ef7eb2e8f9f7 2063 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
<> 144:ef7eb2e8f9f7 2064 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
<> 144:ef7eb2e8f9f7 2065 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
<> 144:ef7eb2e8f9f7 2066 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
<> 144:ef7eb2e8f9f7 2067 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
<> 144:ef7eb2e8f9f7 2068 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
<> 144:ef7eb2e8f9f7 2069 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
<> 144:ef7eb2e8f9f7 2070 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
<> 144:ef7eb2e8f9f7 2071 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
<> 144:ef7eb2e8f9f7 2072 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
<> 144:ef7eb2e8f9f7 2073 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
<> 144:ef7eb2e8f9f7 2074 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
<> 144:ef7eb2e8f9f7 2075 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
<> 144:ef7eb2e8f9f7 2076
<> 144:ef7eb2e8f9f7 2077 /******************* Bit definition for I2C_SR2 register ********************/
<> 144:ef7eb2e8f9f7 2078 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
<> 144:ef7eb2e8f9f7 2079 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
<> 144:ef7eb2e8f9f7 2080 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
<> 144:ef7eb2e8f9f7 2081 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
<> 144:ef7eb2e8f9f7 2082 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
<> 144:ef7eb2e8f9f7 2083 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
<> 144:ef7eb2e8f9f7 2084 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
<> 144:ef7eb2e8f9f7 2085 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 /******************* Bit definition for I2C_CCR register ********************/
<> 144:ef7eb2e8f9f7 2088 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 2089 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
<> 144:ef7eb2e8f9f7 2090 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
<> 144:ef7eb2e8f9f7 2091
<> 144:ef7eb2e8f9f7 2092 /****************** Bit definition for I2C_TRISE register *******************/
<> 144:ef7eb2e8f9f7 2093 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 2094
<> 144:ef7eb2e8f9f7 2095 /****************** Bit definition for I2C_FLTR register *******************/
<> 144:ef7eb2e8f9f7 2096 #define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
<> 144:ef7eb2e8f9f7 2097 #define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2100 /* */
<> 144:ef7eb2e8f9f7 2101 /* Independent WATCHDOG */
<> 144:ef7eb2e8f9f7 2102 /* */
<> 144:ef7eb2e8f9f7 2103 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2104 /******************* Bit definition for IWDG_KR register ********************/
<> 144:ef7eb2e8f9f7 2105 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
<> 144:ef7eb2e8f9f7 2106
<> 144:ef7eb2e8f9f7 2107 /******************* Bit definition for IWDG_PR register ********************/
<> 144:ef7eb2e8f9f7 2108 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
<> 144:ef7eb2e8f9f7 2109 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2110 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2111 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2112
<> 144:ef7eb2e8f9f7 2113 /******************* Bit definition for IWDG_RLR register *******************/
<> 144:ef7eb2e8f9f7 2114 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
<> 144:ef7eb2e8f9f7 2115
<> 144:ef7eb2e8f9f7 2116 /******************* Bit definition for IWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 2117 #define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 2118 #define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
<> 144:ef7eb2e8f9f7 2119
<> 144:ef7eb2e8f9f7 2120
<> 144:ef7eb2e8f9f7 2121 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2122 /* */
<> 144:ef7eb2e8f9f7 2123 /* Power Control */
<> 144:ef7eb2e8f9f7 2124 /* */
<> 144:ef7eb2e8f9f7 2125 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2126 /******************** Bit definition for PWR_CR register ********************/
<> 144:ef7eb2e8f9f7 2127 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
<> 144:ef7eb2e8f9f7 2128 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
<> 144:ef7eb2e8f9f7 2129 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
<> 144:ef7eb2e8f9f7 2130 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
<> 144:ef7eb2e8f9f7 2131 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
<> 144:ef7eb2e8f9f7 2132
<> 144:ef7eb2e8f9f7 2133 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
<> 144:ef7eb2e8f9f7 2134 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2135 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2136 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2137
<> 144:ef7eb2e8f9f7 2138 /*!< PVD level configuration */
<> 144:ef7eb2e8f9f7 2139 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 144:ef7eb2e8f9f7 2140 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
<> 144:ef7eb2e8f9f7 2141 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
<> 144:ef7eb2e8f9f7 2142 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
<> 144:ef7eb2e8f9f7 2143 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
<> 144:ef7eb2e8f9f7 2144 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
<> 144:ef7eb2e8f9f7 2145 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
<> 144:ef7eb2e8f9f7 2146 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
<> 144:ef7eb2e8f9f7 2147
<> 144:ef7eb2e8f9f7 2148 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
<> 144:ef7eb2e8f9f7 2149 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
<> 144:ef7eb2e8f9f7 2150 #define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
<> 144:ef7eb2e8f9f7 2151 #define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
<> 144:ef7eb2e8f9f7 2152 #define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 2153
<> 144:ef7eb2e8f9f7 2154 #define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 144:ef7eb2e8f9f7 2155 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2156 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2157
<> 144:ef7eb2e8f9f7 2158 #define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
<> 144:ef7eb2e8f9f7 2159 #define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
<> 144:ef7eb2e8f9f7 2160 /* Legacy define */
<> 144:ef7eb2e8f9f7 2161 #define PWR_CR_PMODE PWR_CR_VOS
<> 144:ef7eb2e8f9f7 2162
<> 144:ef7eb2e8f9f7 2163 /******************* Bit definition for PWR_CSR register ********************/
<> 144:ef7eb2e8f9f7 2164 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
<> 144:ef7eb2e8f9f7 2165 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
<> 144:ef7eb2e8f9f7 2166 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
<> 144:ef7eb2e8f9f7 2167 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
<> 144:ef7eb2e8f9f7 2168 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
<> 144:ef7eb2e8f9f7 2169 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
<> 144:ef7eb2e8f9f7 2170 #define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 /* Legacy define */
<> 144:ef7eb2e8f9f7 2173 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
<> 144:ef7eb2e8f9f7 2174
<> 144:ef7eb2e8f9f7 2175 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2176 /* */
<> 144:ef7eb2e8f9f7 2177 /* Reset and Clock Control */
<> 144:ef7eb2e8f9f7 2178 /* */
<> 144:ef7eb2e8f9f7 2179 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2180 /******************** Bit definition for RCC_CR register ********************/
<> 144:ef7eb2e8f9f7 2181 #define RCC_CR_HSION 0x00000001U
<> 144:ef7eb2e8f9f7 2182 #define RCC_CR_HSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 2183
<> 144:ef7eb2e8f9f7 2184 #define RCC_CR_HSITRIM 0x000000F8U
<> 144:ef7eb2e8f9f7 2185 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2186 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2187 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2188 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2189 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
<> 144:ef7eb2e8f9f7 2190
<> 144:ef7eb2e8f9f7 2191 #define RCC_CR_HSICAL 0x0000FF00U
<> 144:ef7eb2e8f9f7 2192 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2193 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2194 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2195 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2196 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
<> 144:ef7eb2e8f9f7 2197 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
<> 144:ef7eb2e8f9f7 2198 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
<> 144:ef7eb2e8f9f7 2199 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
<> 144:ef7eb2e8f9f7 2200
<> 144:ef7eb2e8f9f7 2201 #define RCC_CR_HSEON 0x00010000U
<> 144:ef7eb2e8f9f7 2202 #define RCC_CR_HSERDY 0x00020000U
<> 144:ef7eb2e8f9f7 2203 #define RCC_CR_HSEBYP 0x00040000U
<> 144:ef7eb2e8f9f7 2204 #define RCC_CR_CSSON 0x00080000U
<> 144:ef7eb2e8f9f7 2205 #define RCC_CR_PLLON 0x01000000U
<> 144:ef7eb2e8f9f7 2206 #define RCC_CR_PLLRDY 0x02000000U
<> 144:ef7eb2e8f9f7 2207 #define RCC_CR_PLLI2SON 0x04000000U
<> 144:ef7eb2e8f9f7 2208 #define RCC_CR_PLLI2SRDY 0x08000000U
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 144:ef7eb2e8f9f7 2211 #define RCC_PLLCFGR_PLLM 0x0000003FU
<> 144:ef7eb2e8f9f7 2212 #define RCC_PLLCFGR_PLLM_0 0x00000001U
<> 144:ef7eb2e8f9f7 2213 #define RCC_PLLCFGR_PLLM_1 0x00000002U
<> 144:ef7eb2e8f9f7 2214 #define RCC_PLLCFGR_PLLM_2 0x00000004U
<> 144:ef7eb2e8f9f7 2215 #define RCC_PLLCFGR_PLLM_3 0x00000008U
<> 144:ef7eb2e8f9f7 2216 #define RCC_PLLCFGR_PLLM_4 0x00000010U
<> 144:ef7eb2e8f9f7 2217 #define RCC_PLLCFGR_PLLM_5 0x00000020U
<> 144:ef7eb2e8f9f7 2218
<> 144:ef7eb2e8f9f7 2219 #define RCC_PLLCFGR_PLLN 0x00007FC0U
<> 144:ef7eb2e8f9f7 2220 #define RCC_PLLCFGR_PLLN_0 0x00000040U
<> 144:ef7eb2e8f9f7 2221 #define RCC_PLLCFGR_PLLN_1 0x00000080U
<> 144:ef7eb2e8f9f7 2222 #define RCC_PLLCFGR_PLLN_2 0x00000100U
<> 144:ef7eb2e8f9f7 2223 #define RCC_PLLCFGR_PLLN_3 0x00000200U
<> 144:ef7eb2e8f9f7 2224 #define RCC_PLLCFGR_PLLN_4 0x00000400U
<> 144:ef7eb2e8f9f7 2225 #define RCC_PLLCFGR_PLLN_5 0x00000800U
<> 144:ef7eb2e8f9f7 2226 #define RCC_PLLCFGR_PLLN_6 0x00001000U
<> 144:ef7eb2e8f9f7 2227 #define RCC_PLLCFGR_PLLN_7 0x00002000U
<> 144:ef7eb2e8f9f7 2228 #define RCC_PLLCFGR_PLLN_8 0x00004000U
<> 144:ef7eb2e8f9f7 2229
<> 144:ef7eb2e8f9f7 2230 #define RCC_PLLCFGR_PLLP 0x00030000U
<> 144:ef7eb2e8f9f7 2231 #define RCC_PLLCFGR_PLLP_0 0x00010000U
<> 144:ef7eb2e8f9f7 2232 #define RCC_PLLCFGR_PLLP_1 0x00020000U
<> 144:ef7eb2e8f9f7 2233
<> 144:ef7eb2e8f9f7 2234 #define RCC_PLLCFGR_PLLSRC 0x00400000U
<> 144:ef7eb2e8f9f7 2235 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
<> 144:ef7eb2e8f9f7 2236 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 144:ef7eb2e8f9f7 2237
<> 144:ef7eb2e8f9f7 2238 #define RCC_PLLCFGR_PLLQ 0x0F000000U
<> 144:ef7eb2e8f9f7 2239 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
<> 144:ef7eb2e8f9f7 2240 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
<> 144:ef7eb2e8f9f7 2241 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
<> 144:ef7eb2e8f9f7 2242 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
<> 144:ef7eb2e8f9f7 2243
<> 144:ef7eb2e8f9f7 2244 /******************** Bit definition for RCC_CFGR register ******************/
<> 144:ef7eb2e8f9f7 2245 /*!< SW configuration */
<> 144:ef7eb2e8f9f7 2246 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
<> 144:ef7eb2e8f9f7 2247 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2248 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2249
<> 144:ef7eb2e8f9f7 2250 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 2251 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 2252 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 2253
<> 144:ef7eb2e8f9f7 2254 /*!< SWS configuration */
<> 144:ef7eb2e8f9f7 2255 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 144:ef7eb2e8f9f7 2256 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2257 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2258
<> 144:ef7eb2e8f9f7 2259 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2260 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 144:ef7eb2e8f9f7 2261 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 2262
<> 144:ef7eb2e8f9f7 2263 /*!< HPRE configuration */
<> 144:ef7eb2e8f9f7 2264 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
<> 144:ef7eb2e8f9f7 2265 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2266 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2267 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2268 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 2269
<> 144:ef7eb2e8f9f7 2270 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 2271 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2272 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2273 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2274 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 2275 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 2276 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 2277 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 2278 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 2279
<> 144:ef7eb2e8f9f7 2280 /*!< PPRE1 configuration */
<> 144:ef7eb2e8f9f7 2281 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 144:ef7eb2e8f9f7 2282 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2283 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2284 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2285
<> 144:ef7eb2e8f9f7 2286 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 2287 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2288 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2289 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2290 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /*!< PPRE2 configuration */
<> 144:ef7eb2e8f9f7 2293 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 144:ef7eb2e8f9f7 2294 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2295 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2296 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 2297
<> 144:ef7eb2e8f9f7 2298 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 2299 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 2300 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 2301 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 2302 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 2303
<> 144:ef7eb2e8f9f7 2304 /*!< RTCPRE configuration */
<> 144:ef7eb2e8f9f7 2305 #define RCC_CFGR_RTCPRE 0x001F0000U
<> 144:ef7eb2e8f9f7 2306 #define RCC_CFGR_RTCPRE_0 0x00010000U
<> 144:ef7eb2e8f9f7 2307 #define RCC_CFGR_RTCPRE_1 0x00020000U
<> 144:ef7eb2e8f9f7 2308 #define RCC_CFGR_RTCPRE_2 0x00040000U
<> 144:ef7eb2e8f9f7 2309 #define RCC_CFGR_RTCPRE_3 0x00080000U
<> 144:ef7eb2e8f9f7 2310 #define RCC_CFGR_RTCPRE_4 0x00100000U
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 /*!< MCO1 configuration */
<> 144:ef7eb2e8f9f7 2313 #define RCC_CFGR_MCO1 0x00600000U
<> 144:ef7eb2e8f9f7 2314 #define RCC_CFGR_MCO1_0 0x00200000U
<> 144:ef7eb2e8f9f7 2315 #define RCC_CFGR_MCO1_1 0x00400000U
<> 144:ef7eb2e8f9f7 2316
<> 144:ef7eb2e8f9f7 2317 #define RCC_CFGR_I2SSRC 0x00800000U
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 #define RCC_CFGR_MCO1PRE 0x07000000U
<> 144:ef7eb2e8f9f7 2320 #define RCC_CFGR_MCO1PRE_0 0x01000000U
<> 144:ef7eb2e8f9f7 2321 #define RCC_CFGR_MCO1PRE_1 0x02000000U
<> 144:ef7eb2e8f9f7 2322 #define RCC_CFGR_MCO1PRE_2 0x04000000U
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 #define RCC_CFGR_MCO2PRE 0x38000000U
<> 144:ef7eb2e8f9f7 2325 #define RCC_CFGR_MCO2PRE_0 0x08000000U
<> 144:ef7eb2e8f9f7 2326 #define RCC_CFGR_MCO2PRE_1 0x10000000U
<> 144:ef7eb2e8f9f7 2327 #define RCC_CFGR_MCO2PRE_2 0x20000000U
<> 144:ef7eb2e8f9f7 2328
<> 144:ef7eb2e8f9f7 2329 #define RCC_CFGR_MCO2 0xC0000000U
<> 144:ef7eb2e8f9f7 2330 #define RCC_CFGR_MCO2_0 0x40000000U
<> 144:ef7eb2e8f9f7 2331 #define RCC_CFGR_MCO2_1 0x80000000U
<> 144:ef7eb2e8f9f7 2332
<> 144:ef7eb2e8f9f7 2333 /******************** Bit definition for RCC_CIR register *******************/
<> 144:ef7eb2e8f9f7 2334 #define RCC_CIR_LSIRDYF 0x00000001U
<> 144:ef7eb2e8f9f7 2335 #define RCC_CIR_LSERDYF 0x00000002U
<> 144:ef7eb2e8f9f7 2336 #define RCC_CIR_HSIRDYF 0x00000004U
<> 144:ef7eb2e8f9f7 2337 #define RCC_CIR_HSERDYF 0x00000008U
<> 144:ef7eb2e8f9f7 2338 #define RCC_CIR_PLLRDYF 0x00000010U
<> 144:ef7eb2e8f9f7 2339 #define RCC_CIR_PLLI2SRDYF 0x00000020U
<> 144:ef7eb2e8f9f7 2340
<> 144:ef7eb2e8f9f7 2341 #define RCC_CIR_CSSF 0x00000080U
<> 144:ef7eb2e8f9f7 2342 #define RCC_CIR_LSIRDYIE 0x00000100U
<> 144:ef7eb2e8f9f7 2343 #define RCC_CIR_LSERDYIE 0x00000200U
<> 144:ef7eb2e8f9f7 2344 #define RCC_CIR_HSIRDYIE 0x00000400U
<> 144:ef7eb2e8f9f7 2345 #define RCC_CIR_HSERDYIE 0x00000800U
<> 144:ef7eb2e8f9f7 2346 #define RCC_CIR_PLLRDYIE 0x00001000U
<> 144:ef7eb2e8f9f7 2347 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
<> 144:ef7eb2e8f9f7 2348
<> 144:ef7eb2e8f9f7 2349 #define RCC_CIR_LSIRDYC 0x00010000U
<> 144:ef7eb2e8f9f7 2350 #define RCC_CIR_LSERDYC 0x00020000U
<> 144:ef7eb2e8f9f7 2351 #define RCC_CIR_HSIRDYC 0x00040000U
<> 144:ef7eb2e8f9f7 2352 #define RCC_CIR_HSERDYC 0x00080000U
<> 144:ef7eb2e8f9f7 2353 #define RCC_CIR_PLLRDYC 0x00100000U
<> 144:ef7eb2e8f9f7 2354 #define RCC_CIR_PLLI2SRDYC 0x00200000U
<> 144:ef7eb2e8f9f7 2355
<> 144:ef7eb2e8f9f7 2356 #define RCC_CIR_CSSC 0x00800000U
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 144:ef7eb2e8f9f7 2359 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
<> 144:ef7eb2e8f9f7 2360 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
<> 144:ef7eb2e8f9f7 2361 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
<> 144:ef7eb2e8f9f7 2362 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
<> 144:ef7eb2e8f9f7 2363 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
<> 144:ef7eb2e8f9f7 2364 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
<> 144:ef7eb2e8f9f7 2365 #define RCC_AHB1RSTR_CRCRST 0x00001000U
<> 144:ef7eb2e8f9f7 2366 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
<> 144:ef7eb2e8f9f7 2367 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
<> 144:ef7eb2e8f9f7 2368
<> 144:ef7eb2e8f9f7 2369 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 144:ef7eb2e8f9f7 2370 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 144:ef7eb2e8f9f7 2375 #define RCC_APB1RSTR_TIM2RST 0x00000001U
<> 144:ef7eb2e8f9f7 2376 #define RCC_APB1RSTR_TIM3RST 0x00000002U
<> 144:ef7eb2e8f9f7 2377 #define RCC_APB1RSTR_TIM4RST 0x00000004U
<> 144:ef7eb2e8f9f7 2378 #define RCC_APB1RSTR_TIM5RST 0x00000008U
<> 144:ef7eb2e8f9f7 2379 #define RCC_APB1RSTR_WWDGRST 0x00000800U
<> 144:ef7eb2e8f9f7 2380 #define RCC_APB1RSTR_SPI2RST 0x00004000U
<> 144:ef7eb2e8f9f7 2381 #define RCC_APB1RSTR_SPI3RST 0x00008000U
<> 144:ef7eb2e8f9f7 2382 #define RCC_APB1RSTR_USART2RST 0x00020000U
<> 144:ef7eb2e8f9f7 2383 #define RCC_APB1RSTR_I2C1RST 0x00200000U
<> 144:ef7eb2e8f9f7 2384 #define RCC_APB1RSTR_I2C2RST 0x00400000U
<> 144:ef7eb2e8f9f7 2385 #define RCC_APB1RSTR_I2C3RST 0x00800000U
<> 144:ef7eb2e8f9f7 2386 #define RCC_APB1RSTR_PWRRST 0x10000000U
<> 144:ef7eb2e8f9f7 2387
<> 144:ef7eb2e8f9f7 2388 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 144:ef7eb2e8f9f7 2389 #define RCC_APB2RSTR_TIM1RST 0x00000001U
<> 144:ef7eb2e8f9f7 2390 #define RCC_APB2RSTR_USART1RST 0x00000010U
<> 144:ef7eb2e8f9f7 2391 #define RCC_APB2RSTR_USART6RST 0x00000020U
<> 144:ef7eb2e8f9f7 2392 #define RCC_APB2RSTR_ADCRST 0x00000100U
<> 144:ef7eb2e8f9f7 2393 #define RCC_APB2RSTR_SDIORST 0x00000800U
<> 144:ef7eb2e8f9f7 2394 #define RCC_APB2RSTR_SPI1RST 0x00001000U
<> 144:ef7eb2e8f9f7 2395 #define RCC_APB2RSTR_SPI4RST 0x00002000U
<> 144:ef7eb2e8f9f7 2396 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
<> 144:ef7eb2e8f9f7 2397 #define RCC_APB2RSTR_TIM9RST 0x00010000U
<> 144:ef7eb2e8f9f7 2398 #define RCC_APB2RSTR_TIM10RST 0x00020000U
<> 144:ef7eb2e8f9f7 2399 #define RCC_APB2RSTR_TIM11RST 0x00040000U
<> 144:ef7eb2e8f9f7 2400 #define RCC_APB2RSTR_SPI5RST 0x00100000U
<> 144:ef7eb2e8f9f7 2401
<> 144:ef7eb2e8f9f7 2402 /* Old SPI1RST bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 2403 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
<> 144:ef7eb2e8f9f7 2404
<> 144:ef7eb2e8f9f7 2405 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 144:ef7eb2e8f9f7 2406 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
<> 144:ef7eb2e8f9f7 2407 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
<> 144:ef7eb2e8f9f7 2408 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
<> 144:ef7eb2e8f9f7 2409 #define RCC_AHB1ENR_GPIODEN 0x00000008U
<> 144:ef7eb2e8f9f7 2410 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
<> 144:ef7eb2e8f9f7 2411 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
<> 144:ef7eb2e8f9f7 2412 #define RCC_AHB1ENR_CRCEN 0x00001000U
<> 144:ef7eb2e8f9f7 2413 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
<> 144:ef7eb2e8f9f7 2414 #define RCC_AHB1ENR_DMA1EN 0x00200000U
<> 144:ef7eb2e8f9f7 2415 #define RCC_AHB1ENR_DMA2EN 0x00400000U
<> 144:ef7eb2e8f9f7 2416
<> 144:ef7eb2e8f9f7 2417 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 144:ef7eb2e8f9f7 2418 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
<> 144:ef7eb2e8f9f7 2419
<> 144:ef7eb2e8f9f7 2420 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 144:ef7eb2e8f9f7 2421
<> 144:ef7eb2e8f9f7 2422 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 144:ef7eb2e8f9f7 2423 #define RCC_APB1ENR_TIM2EN 0x00000001U
<> 144:ef7eb2e8f9f7 2424 #define RCC_APB1ENR_TIM3EN 0x00000002U
<> 144:ef7eb2e8f9f7 2425 #define RCC_APB1ENR_TIM4EN 0x00000004U
<> 144:ef7eb2e8f9f7 2426 #define RCC_APB1ENR_TIM5EN 0x00000008U
<> 144:ef7eb2e8f9f7 2427 #define RCC_APB1ENR_WWDGEN 0x00000800U
<> 144:ef7eb2e8f9f7 2428 #define RCC_APB1ENR_SPI2EN 0x00004000U
<> 144:ef7eb2e8f9f7 2429 #define RCC_APB1ENR_SPI3EN 0x00008000U
<> 144:ef7eb2e8f9f7 2430 #define RCC_APB1ENR_USART2EN 0x00020000U
<> 144:ef7eb2e8f9f7 2431 #define RCC_APB1ENR_I2C1EN 0x00200000U
<> 144:ef7eb2e8f9f7 2432 #define RCC_APB1ENR_I2C2EN 0x00400000U
<> 144:ef7eb2e8f9f7 2433 #define RCC_APB1ENR_I2C3EN 0x00800000U
<> 144:ef7eb2e8f9f7 2434 #define RCC_APB1ENR_PWREN 0x10000000U
<> 144:ef7eb2e8f9f7 2435
<> 144:ef7eb2e8f9f7 2436 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 144:ef7eb2e8f9f7 2437 #define RCC_APB2ENR_TIM1EN 0x00000001U
<> 144:ef7eb2e8f9f7 2438 #define RCC_APB2ENR_USART1EN 0x00000010U
<> 144:ef7eb2e8f9f7 2439 #define RCC_APB2ENR_USART6EN 0x00000020U
<> 144:ef7eb2e8f9f7 2440 #define RCC_APB2ENR_ADC1EN 0x00000100U
<> 144:ef7eb2e8f9f7 2441 #define RCC_APB2ENR_SDIOEN 0x00000800U
<> 144:ef7eb2e8f9f7 2442 #define RCC_APB2ENR_SPI1EN 0x00001000U
<> 144:ef7eb2e8f9f7 2443 #define RCC_APB2ENR_SPI4EN 0x00002000U
<> 144:ef7eb2e8f9f7 2444 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
<> 144:ef7eb2e8f9f7 2445 #define RCC_APB2ENR_TIM9EN 0x00010000U
<> 144:ef7eb2e8f9f7 2446 #define RCC_APB2ENR_TIM10EN 0x00020000U
<> 144:ef7eb2e8f9f7 2447 #define RCC_APB2ENR_TIM11EN 0x00040000U
<> 144:ef7eb2e8f9f7 2448 #define RCC_APB2ENR_SPI5EN 0x00100000U
<> 144:ef7eb2e8f9f7 2449
<> 144:ef7eb2e8f9f7 2450 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 144:ef7eb2e8f9f7 2451 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
<> 144:ef7eb2e8f9f7 2452 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
<> 144:ef7eb2e8f9f7 2453 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
<> 144:ef7eb2e8f9f7 2454 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
<> 144:ef7eb2e8f9f7 2455 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
<> 144:ef7eb2e8f9f7 2456 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
<> 144:ef7eb2e8f9f7 2457 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
<> 144:ef7eb2e8f9f7 2458 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
<> 144:ef7eb2e8f9f7 2459 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 2460 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 2461 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
<> 144:ef7eb2e8f9f7 2462 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 2463 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 2464
<> 144:ef7eb2e8f9f7 2465 /******************** Bit definition for RCC_AHB2LPENR register *************/
<> 144:ef7eb2e8f9f7 2466 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
<> 144:ef7eb2e8f9f7 2467
<> 144:ef7eb2e8f9f7 2468 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 144:ef7eb2e8f9f7 2469
<> 144:ef7eb2e8f9f7 2470 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 144:ef7eb2e8f9f7 2471 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 2472 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
<> 144:ef7eb2e8f9f7 2473 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
<> 144:ef7eb2e8f9f7 2474 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
<> 144:ef7eb2e8f9f7 2475 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
<> 144:ef7eb2e8f9f7 2476 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
<> 144:ef7eb2e8f9f7 2477 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
<> 144:ef7eb2e8f9f7 2478 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 2479 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 2480 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 2481 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
<> 144:ef7eb2e8f9f7 2482 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
<> 144:ef7eb2e8f9f7 2483 #define RCC_APB1LPENR_DACLPEN 0x20000000U
<> 144:ef7eb2e8f9f7 2484
<> 144:ef7eb2e8f9f7 2485 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 144:ef7eb2e8f9f7 2486 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 2487 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 2488 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
<> 144:ef7eb2e8f9f7 2489 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
<> 144:ef7eb2e8f9f7 2490 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
<> 144:ef7eb2e8f9f7 2491 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
<> 144:ef7eb2e8f9f7 2492 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
<> 144:ef7eb2e8f9f7 2493 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
<> 144:ef7eb2e8f9f7 2494 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 2495 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 2496 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
<> 144:ef7eb2e8f9f7 2497 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
<> 144:ef7eb2e8f9f7 2498
<> 144:ef7eb2e8f9f7 2499 /******************** Bit definition for RCC_BDCR register ******************/
<> 144:ef7eb2e8f9f7 2500 #define RCC_BDCR_LSEON 0x00000001U
<> 144:ef7eb2e8f9f7 2501 #define RCC_BDCR_LSERDY 0x00000002U
<> 144:ef7eb2e8f9f7 2502 #define RCC_BDCR_LSEBYP 0x00000004U
<> 144:ef7eb2e8f9f7 2503 #define RCC_BDCR_LSEMOD 0x00000008U
<> 144:ef7eb2e8f9f7 2504
<> 144:ef7eb2e8f9f7 2505 #define RCC_BDCR_RTCSEL 0x00000300U
<> 144:ef7eb2e8f9f7 2506 #define RCC_BDCR_RTCSEL_0 0x00000100U
<> 144:ef7eb2e8f9f7 2507 #define RCC_BDCR_RTCSEL_1 0x00000200U
<> 144:ef7eb2e8f9f7 2508
<> 144:ef7eb2e8f9f7 2509 #define RCC_BDCR_RTCEN 0x00008000U
<> 144:ef7eb2e8f9f7 2510 #define RCC_BDCR_BDRST 0x00010000U
<> 144:ef7eb2e8f9f7 2511
<> 144:ef7eb2e8f9f7 2512 /******************** Bit definition for RCC_CSR register *******************/
<> 144:ef7eb2e8f9f7 2513 #define RCC_CSR_LSION 0x00000001U
<> 144:ef7eb2e8f9f7 2514 #define RCC_CSR_LSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 2515 #define RCC_CSR_RMVF 0x01000000U
<> 144:ef7eb2e8f9f7 2516 #define RCC_CSR_BORRSTF 0x02000000U
<> 144:ef7eb2e8f9f7 2517 #define RCC_CSR_PADRSTF 0x04000000U
<> 144:ef7eb2e8f9f7 2518 #define RCC_CSR_PORRSTF 0x08000000U
<> 144:ef7eb2e8f9f7 2519 #define RCC_CSR_SFTRSTF 0x10000000U
<> 144:ef7eb2e8f9f7 2520 #define RCC_CSR_WDGRSTF 0x20000000U
<> 144:ef7eb2e8f9f7 2521 #define RCC_CSR_WWDGRSTF 0x40000000U
<> 144:ef7eb2e8f9f7 2522 #define RCC_CSR_LPWRRSTF 0x80000000U
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /******************** Bit definition for RCC_SSCGR register *****************/
<> 144:ef7eb2e8f9f7 2525 #define RCC_SSCGR_MODPER 0x00001FFFU
<> 144:ef7eb2e8f9f7 2526 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
<> 144:ef7eb2e8f9f7 2527 #define RCC_SSCGR_SPREADSEL 0x40000000U
<> 144:ef7eb2e8f9f7 2528 #define RCC_SSCGR_SSCGEN 0x80000000U
<> 144:ef7eb2e8f9f7 2529
<> 144:ef7eb2e8f9f7 2530 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
<> 144:ef7eb2e8f9f7 2531 #define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
<> 144:ef7eb2e8f9f7 2532 #define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
<> 144:ef7eb2e8f9f7 2533 #define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
<> 144:ef7eb2e8f9f7 2534 #define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
<> 144:ef7eb2e8f9f7 2535 #define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
<> 144:ef7eb2e8f9f7 2536 #define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
<> 144:ef7eb2e8f9f7 2537 #define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
<> 144:ef7eb2e8f9f7 2538
<> 144:ef7eb2e8f9f7 2539 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
<> 144:ef7eb2e8f9f7 2540 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
<> 144:ef7eb2e8f9f7 2541 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
<> 144:ef7eb2e8f9f7 2542 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
<> 144:ef7eb2e8f9f7 2543 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
<> 144:ef7eb2e8f9f7 2544 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
<> 144:ef7eb2e8f9f7 2545 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
<> 144:ef7eb2e8f9f7 2546 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
<> 144:ef7eb2e8f9f7 2547 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
<> 144:ef7eb2e8f9f7 2548 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
<> 144:ef7eb2e8f9f7 2549
<> 144:ef7eb2e8f9f7 2550 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
<> 144:ef7eb2e8f9f7 2551 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
<> 144:ef7eb2e8f9f7 2552 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
<> 144:ef7eb2e8f9f7 2553 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
<> 144:ef7eb2e8f9f7 2554
<> 144:ef7eb2e8f9f7 2555 /******************** Bit definition for RCC_DCKCFGR register ***************/
<> 144:ef7eb2e8f9f7 2556 #define RCC_DCKCFGR_TIMPRE 0x01000000U
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2559 /* */
<> 144:ef7eb2e8f9f7 2560 /* Real-Time Clock (RTC) */
<> 144:ef7eb2e8f9f7 2561 /* */
<> 144:ef7eb2e8f9f7 2562 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2563 /******************** Bits definition for RTC_TR register *******************/
<> 144:ef7eb2e8f9f7 2564 #define RTC_TR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2565 #define RTC_TR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2566 #define RTC_TR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2567 #define RTC_TR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2568 #define RTC_TR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2569 #define RTC_TR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2570 #define RTC_TR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2571 #define RTC_TR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2572 #define RTC_TR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2573 #define RTC_TR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2574 #define RTC_TR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2575 #define RTC_TR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2576 #define RTC_TR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2577 #define RTC_TR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2578 #define RTC_TR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2579 #define RTC_TR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2580 #define RTC_TR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2581 #define RTC_TR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2582 #define RTC_TR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2583 #define RTC_TR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2584 #define RTC_TR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2585 #define RTC_TR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2586 #define RTC_TR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2587 #define RTC_TR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2588 #define RTC_TR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2589 #define RTC_TR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2590 #define RTC_TR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 2591
<> 144:ef7eb2e8f9f7 2592 /******************** Bits definition for RTC_DR register *******************/
<> 144:ef7eb2e8f9f7 2593 #define RTC_DR_YT 0x00F00000U
<> 144:ef7eb2e8f9f7 2594 #define RTC_DR_YT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2595 #define RTC_DR_YT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2596 #define RTC_DR_YT_2 0x00400000U
<> 144:ef7eb2e8f9f7 2597 #define RTC_DR_YT_3 0x00800000U
<> 144:ef7eb2e8f9f7 2598 #define RTC_DR_YU 0x000F0000U
<> 144:ef7eb2e8f9f7 2599 #define RTC_DR_YU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2600 #define RTC_DR_YU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2601 #define RTC_DR_YU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2602 #define RTC_DR_YU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2603 #define RTC_DR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 2604 #define RTC_DR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 2605 #define RTC_DR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 2606 #define RTC_DR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 2607 #define RTC_DR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 2608 #define RTC_DR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 2609 #define RTC_DR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2610 #define RTC_DR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2611 #define RTC_DR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2612 #define RTC_DR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2613 #define RTC_DR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 2614 #define RTC_DR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 2615 #define RTC_DR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 2616 #define RTC_DR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 2617 #define RTC_DR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2618 #define RTC_DR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2619 #define RTC_DR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2620 #define RTC_DR_DU_3 0x00000008U
<> 144:ef7eb2e8f9f7 2621
<> 144:ef7eb2e8f9f7 2622 /******************** Bits definition for RTC_CR register *******************/
<> 144:ef7eb2e8f9f7 2623 #define RTC_CR_COE 0x00800000U
<> 144:ef7eb2e8f9f7 2624 #define RTC_CR_OSEL 0x00600000U
<> 144:ef7eb2e8f9f7 2625 #define RTC_CR_OSEL_0 0x00200000U
<> 144:ef7eb2e8f9f7 2626 #define RTC_CR_OSEL_1 0x00400000U
<> 144:ef7eb2e8f9f7 2627 #define RTC_CR_POL 0x00100000U
<> 144:ef7eb2e8f9f7 2628 #define RTC_CR_COSEL 0x00080000U
<> 144:ef7eb2e8f9f7 2629 #define RTC_CR_BCK 0x00040000U
<> 144:ef7eb2e8f9f7 2630 #define RTC_CR_SUB1H 0x00020000U
<> 144:ef7eb2e8f9f7 2631 #define RTC_CR_ADD1H 0x00010000U
<> 144:ef7eb2e8f9f7 2632 #define RTC_CR_TSIE 0x00008000U
<> 144:ef7eb2e8f9f7 2633 #define RTC_CR_WUTIE 0x00004000U
<> 144:ef7eb2e8f9f7 2634 #define RTC_CR_ALRBIE 0x00002000U
<> 144:ef7eb2e8f9f7 2635 #define RTC_CR_ALRAIE 0x00001000U
<> 144:ef7eb2e8f9f7 2636 #define RTC_CR_TSE 0x00000800U
<> 144:ef7eb2e8f9f7 2637 #define RTC_CR_WUTE 0x00000400U
<> 144:ef7eb2e8f9f7 2638 #define RTC_CR_ALRBE 0x00000200U
<> 144:ef7eb2e8f9f7 2639 #define RTC_CR_ALRAE 0x00000100U
<> 144:ef7eb2e8f9f7 2640 #define RTC_CR_DCE 0x00000080U
<> 144:ef7eb2e8f9f7 2641 #define RTC_CR_FMT 0x00000040U
<> 144:ef7eb2e8f9f7 2642 #define RTC_CR_BYPSHAD 0x00000020U
<> 144:ef7eb2e8f9f7 2643 #define RTC_CR_REFCKON 0x00000010U
<> 144:ef7eb2e8f9f7 2644 #define RTC_CR_TSEDGE 0x00000008U
<> 144:ef7eb2e8f9f7 2645 #define RTC_CR_WUCKSEL 0x00000007U
<> 144:ef7eb2e8f9f7 2646 #define RTC_CR_WUCKSEL_0 0x00000001U
<> 144:ef7eb2e8f9f7 2647 #define RTC_CR_WUCKSEL_1 0x00000002U
<> 144:ef7eb2e8f9f7 2648 #define RTC_CR_WUCKSEL_2 0x00000004U
<> 144:ef7eb2e8f9f7 2649
<> 144:ef7eb2e8f9f7 2650 /******************** Bits definition for RTC_ISR register ******************/
<> 144:ef7eb2e8f9f7 2651 #define RTC_ISR_RECALPF 0x00010000U
<> 144:ef7eb2e8f9f7 2652 #define RTC_ISR_TAMP1F 0x00002000U
<> 144:ef7eb2e8f9f7 2653 #define RTC_ISR_TAMP2F 0x00004000U
<> 144:ef7eb2e8f9f7 2654 #define RTC_ISR_TSOVF 0x00001000U
<> 144:ef7eb2e8f9f7 2655 #define RTC_ISR_TSF 0x00000800U
<> 144:ef7eb2e8f9f7 2656 #define RTC_ISR_WUTF 0x00000400U
<> 144:ef7eb2e8f9f7 2657 #define RTC_ISR_ALRBF 0x00000200U
<> 144:ef7eb2e8f9f7 2658 #define RTC_ISR_ALRAF 0x00000100U
<> 144:ef7eb2e8f9f7 2659 #define RTC_ISR_INIT 0x00000080U
<> 144:ef7eb2e8f9f7 2660 #define RTC_ISR_INITF 0x00000040U
<> 144:ef7eb2e8f9f7 2661 #define RTC_ISR_RSF 0x00000020U
<> 144:ef7eb2e8f9f7 2662 #define RTC_ISR_INITS 0x00000010U
<> 144:ef7eb2e8f9f7 2663 #define RTC_ISR_SHPF 0x00000008U
<> 144:ef7eb2e8f9f7 2664 #define RTC_ISR_WUTWF 0x00000004U
<> 144:ef7eb2e8f9f7 2665 #define RTC_ISR_ALRBWF 0x00000002U
<> 144:ef7eb2e8f9f7 2666 #define RTC_ISR_ALRAWF 0x00000001U
<> 144:ef7eb2e8f9f7 2667
<> 144:ef7eb2e8f9f7 2668 /******************** Bits definition for RTC_PRER register *****************/
<> 144:ef7eb2e8f9f7 2669 #define RTC_PRER_PREDIV_A 0x007F0000U
<> 144:ef7eb2e8f9f7 2670 #define RTC_PRER_PREDIV_S 0x00007FFFU
<> 144:ef7eb2e8f9f7 2671
<> 144:ef7eb2e8f9f7 2672 /******************** Bits definition for RTC_WUTR register *****************/
<> 144:ef7eb2e8f9f7 2673 #define RTC_WUTR_WUT 0x0000FFFFU
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /******************** Bits definition for RTC_CALIBR register ***************/
<> 144:ef7eb2e8f9f7 2676 #define RTC_CALIBR_DCS 0x00000080U
<> 144:ef7eb2e8f9f7 2677 #define RTC_CALIBR_DC 0x0000001FU
<> 144:ef7eb2e8f9f7 2678
<> 144:ef7eb2e8f9f7 2679 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 144:ef7eb2e8f9f7 2680 #define RTC_ALRMAR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 2681 #define RTC_ALRMAR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 2682 #define RTC_ALRMAR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 2683 #define RTC_ALRMAR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 2684 #define RTC_ALRMAR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 2685 #define RTC_ALRMAR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 2686 #define RTC_ALRMAR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 2687 #define RTC_ALRMAR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 2688 #define RTC_ALRMAR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 2689 #define RTC_ALRMAR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 2690 #define RTC_ALRMAR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 2691 #define RTC_ALRMAR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2692 #define RTC_ALRMAR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2693 #define RTC_ALRMAR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2694 #define RTC_ALRMAR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2695 #define RTC_ALRMAR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2696 #define RTC_ALRMAR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2697 #define RTC_ALRMAR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2698 #define RTC_ALRMAR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2699 #define RTC_ALRMAR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2700 #define RTC_ALRMAR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 2701 #define RTC_ALRMAR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2702 #define RTC_ALRMAR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2703 #define RTC_ALRMAR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2704 #define RTC_ALRMAR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2705 #define RTC_ALRMAR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2706 #define RTC_ALRMAR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2707 #define RTC_ALRMAR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2708 #define RTC_ALRMAR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2709 #define RTC_ALRMAR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2710 #define RTC_ALRMAR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 2711 #define RTC_ALRMAR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2712 #define RTC_ALRMAR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2713 #define RTC_ALRMAR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2714 #define RTC_ALRMAR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2715 #define RTC_ALRMAR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2716 #define RTC_ALRMAR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2717 #define RTC_ALRMAR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2718 #define RTC_ALRMAR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2719 #define RTC_ALRMAR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 2720
<> 144:ef7eb2e8f9f7 2721 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 144:ef7eb2e8f9f7 2722 #define RTC_ALRMBR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 2723 #define RTC_ALRMBR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 2724 #define RTC_ALRMBR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 2725 #define RTC_ALRMBR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 2726 #define RTC_ALRMBR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 2727 #define RTC_ALRMBR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 2728 #define RTC_ALRMBR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 2729 #define RTC_ALRMBR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 2730 #define RTC_ALRMBR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 2731 #define RTC_ALRMBR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 2732 #define RTC_ALRMBR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 2733 #define RTC_ALRMBR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2734 #define RTC_ALRMBR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2735 #define RTC_ALRMBR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2736 #define RTC_ALRMBR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2737 #define RTC_ALRMBR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2738 #define RTC_ALRMBR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2739 #define RTC_ALRMBR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2740 #define RTC_ALRMBR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2741 #define RTC_ALRMBR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2742 #define RTC_ALRMBR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 2743 #define RTC_ALRMBR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2744 #define RTC_ALRMBR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2745 #define RTC_ALRMBR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2746 #define RTC_ALRMBR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2747 #define RTC_ALRMBR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2748 #define RTC_ALRMBR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2749 #define RTC_ALRMBR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2750 #define RTC_ALRMBR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2751 #define RTC_ALRMBR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2752 #define RTC_ALRMBR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 2753 #define RTC_ALRMBR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2754 #define RTC_ALRMBR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2755 #define RTC_ALRMBR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2756 #define RTC_ALRMBR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2757 #define RTC_ALRMBR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2758 #define RTC_ALRMBR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2759 #define RTC_ALRMBR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2760 #define RTC_ALRMBR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2761 #define RTC_ALRMBR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 2762
<> 144:ef7eb2e8f9f7 2763 /******************** Bits definition for RTC_WPR register ******************/
<> 144:ef7eb2e8f9f7 2764 #define RTC_WPR_KEY 0x000000FFU
<> 144:ef7eb2e8f9f7 2765
<> 144:ef7eb2e8f9f7 2766 /******************** Bits definition for RTC_SSR register ******************/
<> 144:ef7eb2e8f9f7 2767 #define RTC_SSR_SS 0x0000FFFFU
<> 144:ef7eb2e8f9f7 2768
<> 144:ef7eb2e8f9f7 2769 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 144:ef7eb2e8f9f7 2770 #define RTC_SHIFTR_SUBFS 0x00007FFFU
<> 144:ef7eb2e8f9f7 2771 #define RTC_SHIFTR_ADD1S 0x80000000U
<> 144:ef7eb2e8f9f7 2772
<> 144:ef7eb2e8f9f7 2773 /******************** Bits definition for RTC_TSTR register *****************/
<> 144:ef7eb2e8f9f7 2774 #define RTC_TSTR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 2775 #define RTC_TSTR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 2776 #define RTC_TSTR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 2777 #define RTC_TSTR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 2778 #define RTC_TSTR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 2779 #define RTC_TSTR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 2780 #define RTC_TSTR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 2781 #define RTC_TSTR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 2782 #define RTC_TSTR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 2783 #define RTC_TSTR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 2784 #define RTC_TSTR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 2785 #define RTC_TSTR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 2786 #define RTC_TSTR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 2787 #define RTC_TSTR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 2788 #define RTC_TSTR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2789 #define RTC_TSTR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2790 #define RTC_TSTR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2791 #define RTC_TSTR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2792 #define RTC_TSTR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 2793 #define RTC_TSTR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 2794 #define RTC_TSTR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 2795 #define RTC_TSTR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 2796 #define RTC_TSTR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 2797 #define RTC_TSTR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2798 #define RTC_TSTR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2799 #define RTC_TSTR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2800 #define RTC_TSTR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 2801
<> 144:ef7eb2e8f9f7 2802 /******************** Bits definition for RTC_TSDR register *****************/
<> 144:ef7eb2e8f9f7 2803 #define RTC_TSDR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 2804 #define RTC_TSDR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 2805 #define RTC_TSDR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 2806 #define RTC_TSDR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 2807 #define RTC_TSDR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 2808 #define RTC_TSDR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 2809 #define RTC_TSDR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 2810 #define RTC_TSDR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 2811 #define RTC_TSDR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 2812 #define RTC_TSDR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 2813 #define RTC_TSDR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 2814 #define RTC_TSDR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 2815 #define RTC_TSDR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 2816 #define RTC_TSDR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 2817 #define RTC_TSDR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 2818 #define RTC_TSDR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 2819 #define RTC_TSDR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 2820 #define RTC_TSDR_DU_3 0x00000008U
<> 144:ef7eb2e8f9f7 2821
<> 144:ef7eb2e8f9f7 2822 /******************** Bits definition for RTC_TSSSR register ****************/
<> 144:ef7eb2e8f9f7 2823 #define RTC_TSSSR_SS 0x0000FFFFU
<> 144:ef7eb2e8f9f7 2824
<> 144:ef7eb2e8f9f7 2825 /******************** Bits definition for RTC_CAL register *****************/
<> 144:ef7eb2e8f9f7 2826 #define RTC_CALR_CALP 0x00008000U
<> 144:ef7eb2e8f9f7 2827 #define RTC_CALR_CALW8 0x00004000U
<> 144:ef7eb2e8f9f7 2828 #define RTC_CALR_CALW16 0x00002000U
<> 144:ef7eb2e8f9f7 2829 #define RTC_CALR_CALM 0x000001FFU
<> 144:ef7eb2e8f9f7 2830 #define RTC_CALR_CALM_0 0x00000001U
<> 144:ef7eb2e8f9f7 2831 #define RTC_CALR_CALM_1 0x00000002U
<> 144:ef7eb2e8f9f7 2832 #define RTC_CALR_CALM_2 0x00000004U
<> 144:ef7eb2e8f9f7 2833 #define RTC_CALR_CALM_3 0x00000008U
<> 144:ef7eb2e8f9f7 2834 #define RTC_CALR_CALM_4 0x00000010U
<> 144:ef7eb2e8f9f7 2835 #define RTC_CALR_CALM_5 0x00000020U
<> 144:ef7eb2e8f9f7 2836 #define RTC_CALR_CALM_6 0x00000040U
<> 144:ef7eb2e8f9f7 2837 #define RTC_CALR_CALM_7 0x00000080U
<> 144:ef7eb2e8f9f7 2838 #define RTC_CALR_CALM_8 0x00000100U
<> 144:ef7eb2e8f9f7 2839
<> 144:ef7eb2e8f9f7 2840 /******************** Bits definition for RTC_TAFCR register ****************/
<> 144:ef7eb2e8f9f7 2841 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
<> 144:ef7eb2e8f9f7 2842 #define RTC_TAFCR_TSINSEL 0x00020000U
<> 144:ef7eb2e8f9f7 2843 #define RTC_TAFCR_TAMPINSEL 0x00010000U
<> 144:ef7eb2e8f9f7 2844 #define RTC_TAFCR_TAMPPUDIS 0x00008000U
<> 144:ef7eb2e8f9f7 2845 #define RTC_TAFCR_TAMPPRCH 0x00006000U
<> 144:ef7eb2e8f9f7 2846 #define RTC_TAFCR_TAMPPRCH_0 0x00002000U
<> 144:ef7eb2e8f9f7 2847 #define RTC_TAFCR_TAMPPRCH_1 0x00004000U
<> 144:ef7eb2e8f9f7 2848 #define RTC_TAFCR_TAMPFLT 0x00001800U
<> 144:ef7eb2e8f9f7 2849 #define RTC_TAFCR_TAMPFLT_0 0x00000800U
<> 144:ef7eb2e8f9f7 2850 #define RTC_TAFCR_TAMPFLT_1 0x00001000U
<> 144:ef7eb2e8f9f7 2851 #define RTC_TAFCR_TAMPFREQ 0x00000700U
<> 144:ef7eb2e8f9f7 2852 #define RTC_TAFCR_TAMPFREQ_0 0x00000100U
<> 144:ef7eb2e8f9f7 2853 #define RTC_TAFCR_TAMPFREQ_1 0x00000200U
<> 144:ef7eb2e8f9f7 2854 #define RTC_TAFCR_TAMPFREQ_2 0x00000400U
<> 144:ef7eb2e8f9f7 2855 #define RTC_TAFCR_TAMPTS 0x00000080U
<> 144:ef7eb2e8f9f7 2856 #define RTC_TAFCR_TAMP2TRG 0x00000010U
<> 144:ef7eb2e8f9f7 2857 #define RTC_TAFCR_TAMP2E 0x00000008U
<> 144:ef7eb2e8f9f7 2858 #define RTC_TAFCR_TAMPIE 0x00000004U
<> 144:ef7eb2e8f9f7 2859 #define RTC_TAFCR_TAMP1TRG 0x00000002U
<> 144:ef7eb2e8f9f7 2860 #define RTC_TAFCR_TAMP1E 0x00000001U
<> 144:ef7eb2e8f9f7 2861
<> 144:ef7eb2e8f9f7 2862 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 144:ef7eb2e8f9f7 2863 #define RTC_ALRMASSR_MASKSS 0x0F000000U
<> 144:ef7eb2e8f9f7 2864 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
<> 144:ef7eb2e8f9f7 2865 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
<> 144:ef7eb2e8f9f7 2866 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
<> 144:ef7eb2e8f9f7 2867 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
<> 144:ef7eb2e8f9f7 2868 #define RTC_ALRMASSR_SS 0x00007FFFU
<> 144:ef7eb2e8f9f7 2869
<> 144:ef7eb2e8f9f7 2870 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 144:ef7eb2e8f9f7 2871 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
<> 144:ef7eb2e8f9f7 2872 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
<> 144:ef7eb2e8f9f7 2873 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
<> 144:ef7eb2e8f9f7 2874 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
<> 144:ef7eb2e8f9f7 2875 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
<> 144:ef7eb2e8f9f7 2876 #define RTC_ALRMBSSR_SS 0x00007FFFU
<> 144:ef7eb2e8f9f7 2877
<> 144:ef7eb2e8f9f7 2878 /******************** Bits definition for RTC_BKP0R register ****************/
<> 144:ef7eb2e8f9f7 2879 #define RTC_BKP0R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2880
<> 144:ef7eb2e8f9f7 2881 /******************** Bits definition for RTC_BKP1R register ****************/
<> 144:ef7eb2e8f9f7 2882 #define RTC_BKP1R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2883
<> 144:ef7eb2e8f9f7 2884 /******************** Bits definition for RTC_BKP2R register ****************/
<> 144:ef7eb2e8f9f7 2885 #define RTC_BKP2R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2886
<> 144:ef7eb2e8f9f7 2887 /******************** Bits definition for RTC_BKP3R register ****************/
<> 144:ef7eb2e8f9f7 2888 #define RTC_BKP3R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2889
<> 144:ef7eb2e8f9f7 2890 /******************** Bits definition for RTC_BKP4R register ****************/
<> 144:ef7eb2e8f9f7 2891 #define RTC_BKP4R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2892
<> 144:ef7eb2e8f9f7 2893 /******************** Bits definition for RTC_BKP5R register ****************/
<> 144:ef7eb2e8f9f7 2894 #define RTC_BKP5R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2895
<> 144:ef7eb2e8f9f7 2896 /******************** Bits definition for RTC_BKP6R register ****************/
<> 144:ef7eb2e8f9f7 2897 #define RTC_BKP6R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2898
<> 144:ef7eb2e8f9f7 2899 /******************** Bits definition for RTC_BKP7R register ****************/
<> 144:ef7eb2e8f9f7 2900 #define RTC_BKP7R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2901
<> 144:ef7eb2e8f9f7 2902 /******************** Bits definition for RTC_BKP8R register ****************/
<> 144:ef7eb2e8f9f7 2903 #define RTC_BKP8R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2904
<> 144:ef7eb2e8f9f7 2905 /******************** Bits definition for RTC_BKP9R register ****************/
<> 144:ef7eb2e8f9f7 2906 #define RTC_BKP9R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2907
<> 144:ef7eb2e8f9f7 2908 /******************** Bits definition for RTC_BKP10R register ***************/
<> 144:ef7eb2e8f9f7 2909 #define RTC_BKP10R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2910
<> 144:ef7eb2e8f9f7 2911 /******************** Bits definition for RTC_BKP11R register ***************/
<> 144:ef7eb2e8f9f7 2912 #define RTC_BKP11R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2913
<> 144:ef7eb2e8f9f7 2914 /******************** Bits definition for RTC_BKP12R register ***************/
<> 144:ef7eb2e8f9f7 2915 #define RTC_BKP12R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2916
<> 144:ef7eb2e8f9f7 2917 /******************** Bits definition for RTC_BKP13R register ***************/
<> 144:ef7eb2e8f9f7 2918 #define RTC_BKP13R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2919
<> 144:ef7eb2e8f9f7 2920 /******************** Bits definition for RTC_BKP14R register ***************/
<> 144:ef7eb2e8f9f7 2921 #define RTC_BKP14R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2922
<> 144:ef7eb2e8f9f7 2923 /******************** Bits definition for RTC_BKP15R register ***************/
<> 144:ef7eb2e8f9f7 2924 #define RTC_BKP15R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2925
<> 144:ef7eb2e8f9f7 2926 /******************** Bits definition for RTC_BKP16R register ***************/
<> 144:ef7eb2e8f9f7 2927 #define RTC_BKP16R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2928
<> 144:ef7eb2e8f9f7 2929 /******************** Bits definition for RTC_BKP17R register ***************/
<> 144:ef7eb2e8f9f7 2930 #define RTC_BKP17R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2931
<> 144:ef7eb2e8f9f7 2932 /******************** Bits definition for RTC_BKP18R register ***************/
<> 144:ef7eb2e8f9f7 2933 #define RTC_BKP18R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2934
<> 144:ef7eb2e8f9f7 2935 /******************** Bits definition for RTC_BKP19R register ***************/
<> 144:ef7eb2e8f9f7 2936 #define RTC_BKP19R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 2937
<> 144:ef7eb2e8f9f7 2938
<> 144:ef7eb2e8f9f7 2939
<> 144:ef7eb2e8f9f7 2940 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2941 /* */
<> 144:ef7eb2e8f9f7 2942 /* SD host Interface */
<> 144:ef7eb2e8f9f7 2943 /* */
<> 144:ef7eb2e8f9f7 2944 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2945 /****************** Bit definition for SDIO_POWER register ******************/
<> 144:ef7eb2e8f9f7 2946 #define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 144:ef7eb2e8f9f7 2947 #define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2948 #define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2949
<> 144:ef7eb2e8f9f7 2950 /****************** Bit definition for SDIO_CLKCR register ******************/
<> 144:ef7eb2e8f9f7 2951 #define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
<> 144:ef7eb2e8f9f7 2952 #define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
<> 144:ef7eb2e8f9f7 2953 #define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
<> 144:ef7eb2e8f9f7 2954 #define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
<> 144:ef7eb2e8f9f7 2955
<> 144:ef7eb2e8f9f7 2956 #define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 144:ef7eb2e8f9f7 2957 #define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2958 #define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2959
<> 144:ef7eb2e8f9f7 2960 #define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
<> 144:ef7eb2e8f9f7 2961 #define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
<> 144:ef7eb2e8f9f7 2962
<> 144:ef7eb2e8f9f7 2963 /******************* Bit definition for SDIO_ARG register *******************/
<> 144:ef7eb2e8f9f7 2964 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
<> 144:ef7eb2e8f9f7 2965
<> 144:ef7eb2e8f9f7 2966 /******************* Bit definition for SDIO_CMD register *******************/
<> 144:ef7eb2e8f9f7 2967 #define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
<> 144:ef7eb2e8f9f7 2968
<> 144:ef7eb2e8f9f7 2969 #define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 144:ef7eb2e8f9f7 2970 #define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 2971 #define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 2972
<> 144:ef7eb2e8f9f7 2973 #define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
<> 144:ef7eb2e8f9f7 2974 #define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 144:ef7eb2e8f9f7 2975 #define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
<> 144:ef7eb2e8f9f7 2976 #define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
<> 144:ef7eb2e8f9f7 2977 #define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
<> 144:ef7eb2e8f9f7 2978 #define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
<> 144:ef7eb2e8f9f7 2979 #define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
<> 144:ef7eb2e8f9f7 2980
<> 144:ef7eb2e8f9f7 2981 /***************** Bit definition for SDIO_RESPCMD register *****************/
<> 144:ef7eb2e8f9f7 2982 #define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
<> 144:ef7eb2e8f9f7 2983
<> 144:ef7eb2e8f9f7 2984 /****************** Bit definition for SDIO_RESP0 register ******************/
<> 144:ef7eb2e8f9f7 2985 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 2986
<> 144:ef7eb2e8f9f7 2987 /****************** Bit definition for SDIO_RESP1 register ******************/
<> 144:ef7eb2e8f9f7 2988 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 2989
<> 144:ef7eb2e8f9f7 2990 /****************** Bit definition for SDIO_RESP2 register ******************/
<> 144:ef7eb2e8f9f7 2991 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 2992
<> 144:ef7eb2e8f9f7 2993 /****************** Bit definition for SDIO_RESP3 register ******************/
<> 144:ef7eb2e8f9f7 2994 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 2995
<> 144:ef7eb2e8f9f7 2996 /****************** Bit definition for SDIO_RESP4 register ******************/
<> 144:ef7eb2e8f9f7 2997 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 2998
<> 144:ef7eb2e8f9f7 2999 /****************** Bit definition for SDIO_DTIMER register *****************/
<> 144:ef7eb2e8f9f7 3000 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
<> 144:ef7eb2e8f9f7 3001
<> 144:ef7eb2e8f9f7 3002 /****************** Bit definition for SDIO_DLEN register *******************/
<> 144:ef7eb2e8f9f7 3003 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
<> 144:ef7eb2e8f9f7 3004
<> 144:ef7eb2e8f9f7 3005 /****************** Bit definition for SDIO_DCTRL register ******************/
<> 144:ef7eb2e8f9f7 3006 #define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
<> 144:ef7eb2e8f9f7 3007 #define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
<> 144:ef7eb2e8f9f7 3008 #define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
<> 144:ef7eb2e8f9f7 3009 #define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
<> 144:ef7eb2e8f9f7 3010
<> 144:ef7eb2e8f9f7 3011 #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 144:ef7eb2e8f9f7 3012 #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3013 #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3014 #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3015 #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3016
<> 144:ef7eb2e8f9f7 3017 #define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
<> 144:ef7eb2e8f9f7 3018 #define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
<> 144:ef7eb2e8f9f7 3019 #define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
<> 144:ef7eb2e8f9f7 3020 #define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
<> 144:ef7eb2e8f9f7 3021
<> 144:ef7eb2e8f9f7 3022 /****************** Bit definition for SDIO_DCOUNT register *****************/
<> 144:ef7eb2e8f9f7 3023 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
<> 144:ef7eb2e8f9f7 3024
<> 144:ef7eb2e8f9f7 3025 /****************** Bit definition for SDIO_STA register ********************/
<> 144:ef7eb2e8f9f7 3026 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
<> 144:ef7eb2e8f9f7 3027 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
<> 144:ef7eb2e8f9f7 3028 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
<> 144:ef7eb2e8f9f7 3029 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
<> 144:ef7eb2e8f9f7 3030 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
<> 144:ef7eb2e8f9f7 3031 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
<> 144:ef7eb2e8f9f7 3032 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
<> 144:ef7eb2e8f9f7 3033 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
<> 144:ef7eb2e8f9f7 3034 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 144:ef7eb2e8f9f7 3035 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
<> 144:ef7eb2e8f9f7 3036 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
<> 144:ef7eb2e8f9f7 3037 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
<> 144:ef7eb2e8f9f7 3038 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
<> 144:ef7eb2e8f9f7 3039 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
<> 144:ef7eb2e8f9f7 3040 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 144:ef7eb2e8f9f7 3041 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 144:ef7eb2e8f9f7 3042 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
<> 144:ef7eb2e8f9f7 3043 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
<> 144:ef7eb2e8f9f7 3044 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
<> 144:ef7eb2e8f9f7 3045 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
<> 144:ef7eb2e8f9f7 3046 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
<> 144:ef7eb2e8f9f7 3047 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
<> 144:ef7eb2e8f9f7 3048 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
<> 144:ef7eb2e8f9f7 3049 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
<> 144:ef7eb2e8f9f7 3050
<> 144:ef7eb2e8f9f7 3051 /******************* Bit definition for SDIO_ICR register *******************/
<> 144:ef7eb2e8f9f7 3052 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
<> 144:ef7eb2e8f9f7 3053 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
<> 144:ef7eb2e8f9f7 3054 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
<> 144:ef7eb2e8f9f7 3055 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
<> 144:ef7eb2e8f9f7 3056 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
<> 144:ef7eb2e8f9f7 3057 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
<> 144:ef7eb2e8f9f7 3058 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
<> 144:ef7eb2e8f9f7 3059 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
<> 144:ef7eb2e8f9f7 3060 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
<> 144:ef7eb2e8f9f7 3061 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
<> 144:ef7eb2e8f9f7 3062 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
<> 144:ef7eb2e8f9f7 3063 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
<> 144:ef7eb2e8f9f7 3064 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
<> 144:ef7eb2e8f9f7 3065
<> 144:ef7eb2e8f9f7 3066 /****************** Bit definition for SDIO_MASK register *******************/
<> 144:ef7eb2e8f9f7 3067 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 3068 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 3069 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 3070 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 3071 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3072 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3073 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
<> 144:ef7eb2e8f9f7 3074 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
<> 144:ef7eb2e8f9f7 3075 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
<> 144:ef7eb2e8f9f7 3076 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3077 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
<> 144:ef7eb2e8f9f7 3078 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
<> 144:ef7eb2e8f9f7 3079 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
<> 144:ef7eb2e8f9f7 3080 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
<> 144:ef7eb2e8f9f7 3081 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 3082 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
<> 144:ef7eb2e8f9f7 3083 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
<> 144:ef7eb2e8f9f7 3084 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
<> 144:ef7eb2e8f9f7 3085 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 3086 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 3087 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
<> 144:ef7eb2e8f9f7 3088 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
<> 144:ef7eb2e8f9f7 3089 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
<> 144:ef7eb2e8f9f7 3090 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
<> 144:ef7eb2e8f9f7 3091
<> 144:ef7eb2e8f9f7 3092 /***************** Bit definition for SDIO_FIFOCNT register *****************/
<> 144:ef7eb2e8f9f7 3093 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
<> 144:ef7eb2e8f9f7 3094
<> 144:ef7eb2e8f9f7 3095 /****************** Bit definition for SDIO_FIFO register *******************/
<> 144:ef7eb2e8f9f7 3096 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
<> 144:ef7eb2e8f9f7 3097
<> 144:ef7eb2e8f9f7 3098 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3099 /* */
<> 144:ef7eb2e8f9f7 3100 /* Serial Peripheral Interface */
<> 144:ef7eb2e8f9f7 3101 /* */
<> 144:ef7eb2e8f9f7 3102 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3103 /******************* Bit definition for SPI_CR1 register ********************/
<> 144:ef7eb2e8f9f7 3104 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
<> 144:ef7eb2e8f9f7 3105 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
<> 144:ef7eb2e8f9f7 3106 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
<> 144:ef7eb2e8f9f7 3107
<> 144:ef7eb2e8f9f7 3108 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
<> 144:ef7eb2e8f9f7 3109 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3110 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3111 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3112
<> 144:ef7eb2e8f9f7 3113 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
<> 144:ef7eb2e8f9f7 3114 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
<> 144:ef7eb2e8f9f7 3115 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
<> 144:ef7eb2e8f9f7 3116 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
<> 144:ef7eb2e8f9f7 3117 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
<> 144:ef7eb2e8f9f7 3118 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
<> 144:ef7eb2e8f9f7 3119 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
<> 144:ef7eb2e8f9f7 3120 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
<> 144:ef7eb2e8f9f7 3121 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
<> 144:ef7eb2e8f9f7 3122 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
<> 144:ef7eb2e8f9f7 3123
<> 144:ef7eb2e8f9f7 3124 /******************* Bit definition for SPI_CR2 register ********************/
<> 144:ef7eb2e8f9f7 3125 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 3126 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 3127 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
<> 144:ef7eb2e8f9f7 3128 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
<> 144:ef7eb2e8f9f7 3129 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3130 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 3131 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 3132
<> 144:ef7eb2e8f9f7 3133 /******************** Bit definition for SPI_SR register ********************/
<> 144:ef7eb2e8f9f7 3134 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
<> 144:ef7eb2e8f9f7 3135 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
<> 144:ef7eb2e8f9f7 3136 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
<> 144:ef7eb2e8f9f7 3137 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
<> 144:ef7eb2e8f9f7 3138 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
<> 144:ef7eb2e8f9f7 3139 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
<> 144:ef7eb2e8f9f7 3140 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 3141 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
<> 144:ef7eb2e8f9f7 3142 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
<> 144:ef7eb2e8f9f7 3143
<> 144:ef7eb2e8f9f7 3144 /******************** Bit definition for SPI_DR register ********************/
<> 144:ef7eb2e8f9f7 3145 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
<> 144:ef7eb2e8f9f7 3146
<> 144:ef7eb2e8f9f7 3147 /******************* Bit definition for SPI_CRCPR register ******************/
<> 144:ef7eb2e8f9f7 3148 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
<> 144:ef7eb2e8f9f7 3149
<> 144:ef7eb2e8f9f7 3150 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 144:ef7eb2e8f9f7 3151 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
<> 144:ef7eb2e8f9f7 3152
<> 144:ef7eb2e8f9f7 3153 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 144:ef7eb2e8f9f7 3154 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
<> 144:ef7eb2e8f9f7 3155
<> 144:ef7eb2e8f9f7 3156 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 144:ef7eb2e8f9f7 3157 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
<> 144:ef7eb2e8f9f7 3158
<> 144:ef7eb2e8f9f7 3159 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 144:ef7eb2e8f9f7 3160 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3161 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3162
<> 144:ef7eb2e8f9f7 3163 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
<> 144:ef7eb2e8f9f7 3164
<> 144:ef7eb2e8f9f7 3165 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 144:ef7eb2e8f9f7 3166 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3167 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3168
<> 144:ef7eb2e8f9f7 3169 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
<> 144:ef7eb2e8f9f7 3170
<> 144:ef7eb2e8f9f7 3171 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 144:ef7eb2e8f9f7 3172 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3173 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3174
<> 144:ef7eb2e8f9f7 3175 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
<> 144:ef7eb2e8f9f7 3176 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
<> 144:ef7eb2e8f9f7 3177
<> 144:ef7eb2e8f9f7 3178 /****************** Bit definition for SPI_I2SPR register *******************/
<> 144:ef7eb2e8f9f7 3179 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
<> 144:ef7eb2e8f9f7 3180 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
<> 144:ef7eb2e8f9f7 3181 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
<> 144:ef7eb2e8f9f7 3182
<> 144:ef7eb2e8f9f7 3183 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3184 /* */
<> 144:ef7eb2e8f9f7 3185 /* SYSCFG */
<> 144:ef7eb2e8f9f7 3186 /* */
<> 144:ef7eb2e8f9f7 3187 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3188 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 144:ef7eb2e8f9f7 3189 #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
<> 144:ef7eb2e8f9f7 3190 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
<> 144:ef7eb2e8f9f7 3191 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
<> 144:ef7eb2e8f9f7 3192 #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
<> 144:ef7eb2e8f9f7 3193
<> 144:ef7eb2e8f9f7 3194 /****************** Bit definition for SYSCFG_PMC register ******************/
<> 144:ef7eb2e8f9f7 3195 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 3196
<> 144:ef7eb2e8f9f7 3197 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 144:ef7eb2e8f9f7 3198 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
<> 144:ef7eb2e8f9f7 3199 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
<> 144:ef7eb2e8f9f7 3200 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
<> 144:ef7eb2e8f9f7 3201 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
<> 144:ef7eb2e8f9f7 3202 /**
<> 144:ef7eb2e8f9f7 3203 * @brief EXTI0 configuration
<> 144:ef7eb2e8f9f7 3204 */
<> 144:ef7eb2e8f9f7 3205 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
<> 144:ef7eb2e8f9f7 3206 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
<> 144:ef7eb2e8f9f7 3207 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
<> 144:ef7eb2e8f9f7 3208 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
<> 144:ef7eb2e8f9f7 3209 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
<> 144:ef7eb2e8f9f7 3210 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
<> 144:ef7eb2e8f9f7 3211
<> 144:ef7eb2e8f9f7 3212 /**
<> 144:ef7eb2e8f9f7 3213 * @brief EXTI1 configuration
<> 144:ef7eb2e8f9f7 3214 */
<> 144:ef7eb2e8f9f7 3215 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
<> 144:ef7eb2e8f9f7 3216 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
<> 144:ef7eb2e8f9f7 3217 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
<> 144:ef7eb2e8f9f7 3218 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
<> 144:ef7eb2e8f9f7 3219 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
<> 144:ef7eb2e8f9f7 3220 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
<> 144:ef7eb2e8f9f7 3221
<> 144:ef7eb2e8f9f7 3222 /**
<> 144:ef7eb2e8f9f7 3223 * @brief EXTI2 configuration
<> 144:ef7eb2e8f9f7 3224 */
<> 144:ef7eb2e8f9f7 3225 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
<> 144:ef7eb2e8f9f7 3226 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
<> 144:ef7eb2e8f9f7 3227 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
<> 144:ef7eb2e8f9f7 3228 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
<> 144:ef7eb2e8f9f7 3229 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
<> 144:ef7eb2e8f9f7 3230 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
<> 144:ef7eb2e8f9f7 3231
<> 144:ef7eb2e8f9f7 3232 /**
<> 144:ef7eb2e8f9f7 3233 * @brief EXTI3 configuration
<> 144:ef7eb2e8f9f7 3234 */
<> 144:ef7eb2e8f9f7 3235 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
<> 144:ef7eb2e8f9f7 3236 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
<> 144:ef7eb2e8f9f7 3237 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
<> 144:ef7eb2e8f9f7 3238 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
<> 144:ef7eb2e8f9f7 3239 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
<> 144:ef7eb2e8f9f7 3240 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
<> 144:ef7eb2e8f9f7 3241
<> 144:ef7eb2e8f9f7 3242 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 144:ef7eb2e8f9f7 3243 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
<> 144:ef7eb2e8f9f7 3244 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
<> 144:ef7eb2e8f9f7 3245 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
<> 144:ef7eb2e8f9f7 3246 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
<> 144:ef7eb2e8f9f7 3247 /**
<> 144:ef7eb2e8f9f7 3248 * @brief EXTI4 configuration
<> 144:ef7eb2e8f9f7 3249 */
<> 144:ef7eb2e8f9f7 3250 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
<> 144:ef7eb2e8f9f7 3251 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
<> 144:ef7eb2e8f9f7 3252 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
<> 144:ef7eb2e8f9f7 3253 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
<> 144:ef7eb2e8f9f7 3254 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
<> 144:ef7eb2e8f9f7 3255 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
<> 144:ef7eb2e8f9f7 3256
<> 144:ef7eb2e8f9f7 3257 /**
<> 144:ef7eb2e8f9f7 3258 * @brief EXTI5 configuration
<> 144:ef7eb2e8f9f7 3259 */
<> 144:ef7eb2e8f9f7 3260 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
<> 144:ef7eb2e8f9f7 3261 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
<> 144:ef7eb2e8f9f7 3262 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
<> 144:ef7eb2e8f9f7 3263 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
<> 144:ef7eb2e8f9f7 3264 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
<> 144:ef7eb2e8f9f7 3265 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
<> 144:ef7eb2e8f9f7 3266
<> 144:ef7eb2e8f9f7 3267 /**
<> 144:ef7eb2e8f9f7 3268 * @brief EXTI6 configuration
<> 144:ef7eb2e8f9f7 3269 */
<> 144:ef7eb2e8f9f7 3270 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
<> 144:ef7eb2e8f9f7 3271 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
<> 144:ef7eb2e8f9f7 3272 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
<> 144:ef7eb2e8f9f7 3273 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
<> 144:ef7eb2e8f9f7 3274 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
<> 144:ef7eb2e8f9f7 3275 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
<> 144:ef7eb2e8f9f7 3276
<> 144:ef7eb2e8f9f7 3277 /**
<> 144:ef7eb2e8f9f7 3278 * @brief EXTI7 configuration
<> 144:ef7eb2e8f9f7 3279 */
<> 144:ef7eb2e8f9f7 3280 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
<> 144:ef7eb2e8f9f7 3281 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
<> 144:ef7eb2e8f9f7 3282 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
<> 144:ef7eb2e8f9f7 3283 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
<> 144:ef7eb2e8f9f7 3284 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
<> 144:ef7eb2e8f9f7 3285 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
<> 144:ef7eb2e8f9f7 3286
<> 144:ef7eb2e8f9f7 3287
<> 144:ef7eb2e8f9f7 3288 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 144:ef7eb2e8f9f7 3289 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
<> 144:ef7eb2e8f9f7 3290 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
<> 144:ef7eb2e8f9f7 3291 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
<> 144:ef7eb2e8f9f7 3292 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
<> 144:ef7eb2e8f9f7 3293
<> 144:ef7eb2e8f9f7 3294 /**
<> 144:ef7eb2e8f9f7 3295 * @brief EXTI8 configuration
<> 144:ef7eb2e8f9f7 3296 */
<> 144:ef7eb2e8f9f7 3297 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
<> 144:ef7eb2e8f9f7 3298 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
<> 144:ef7eb2e8f9f7 3299 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
<> 144:ef7eb2e8f9f7 3300 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
<> 144:ef7eb2e8f9f7 3301 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
<> 144:ef7eb2e8f9f7 3302 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
<> 144:ef7eb2e8f9f7 3303
<> 144:ef7eb2e8f9f7 3304 /**
<> 144:ef7eb2e8f9f7 3305 * @brief EXTI9 configuration
<> 144:ef7eb2e8f9f7 3306 */
<> 144:ef7eb2e8f9f7 3307 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
<> 144:ef7eb2e8f9f7 3308 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
<> 144:ef7eb2e8f9f7 3309 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
<> 144:ef7eb2e8f9f7 3310 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
<> 144:ef7eb2e8f9f7 3311 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
<> 144:ef7eb2e8f9f7 3312 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
<> 144:ef7eb2e8f9f7 3313
<> 144:ef7eb2e8f9f7 3314 /**
<> 144:ef7eb2e8f9f7 3315 * @brief EXTI10 configuration
<> 144:ef7eb2e8f9f7 3316 */
<> 144:ef7eb2e8f9f7 3317 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
<> 144:ef7eb2e8f9f7 3318 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
<> 144:ef7eb2e8f9f7 3319 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
<> 144:ef7eb2e8f9f7 3320 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
<> 144:ef7eb2e8f9f7 3321 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
<> 144:ef7eb2e8f9f7 3322 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
<> 144:ef7eb2e8f9f7 3323
<> 144:ef7eb2e8f9f7 3324 /**
<> 144:ef7eb2e8f9f7 3325 * @brief EXTI11 configuration
<> 144:ef7eb2e8f9f7 3326 */
<> 144:ef7eb2e8f9f7 3327 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
<> 144:ef7eb2e8f9f7 3328 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
<> 144:ef7eb2e8f9f7 3329 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
<> 144:ef7eb2e8f9f7 3330 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
<> 144:ef7eb2e8f9f7 3331 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
<> 144:ef7eb2e8f9f7 3332 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
<> 144:ef7eb2e8f9f7 3333
<> 144:ef7eb2e8f9f7 3334 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 144:ef7eb2e8f9f7 3335 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
<> 144:ef7eb2e8f9f7 3336 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
<> 144:ef7eb2e8f9f7 3337 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
<> 144:ef7eb2e8f9f7 3338 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
<> 144:ef7eb2e8f9f7 3339 /**
<> 144:ef7eb2e8f9f7 3340 * @brief EXTI12 configuration
<> 144:ef7eb2e8f9f7 3341 */
<> 144:ef7eb2e8f9f7 3342 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
<> 144:ef7eb2e8f9f7 3343 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
<> 144:ef7eb2e8f9f7 3344 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
<> 144:ef7eb2e8f9f7 3345 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
<> 144:ef7eb2e8f9f7 3346 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
<> 144:ef7eb2e8f9f7 3347 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
<> 144:ef7eb2e8f9f7 3348
<> 144:ef7eb2e8f9f7 3349 /**
<> 144:ef7eb2e8f9f7 3350 * @brief EXTI13 configuration
<> 144:ef7eb2e8f9f7 3351 */
<> 144:ef7eb2e8f9f7 3352 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
<> 144:ef7eb2e8f9f7 3353 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
<> 144:ef7eb2e8f9f7 3354 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
<> 144:ef7eb2e8f9f7 3355 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
<> 144:ef7eb2e8f9f7 3356 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
<> 144:ef7eb2e8f9f7 3357 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
<> 144:ef7eb2e8f9f7 3358
<> 144:ef7eb2e8f9f7 3359 /**
<> 144:ef7eb2e8f9f7 3360 * @brief EXTI14 configuration
<> 144:ef7eb2e8f9f7 3361 */
<> 144:ef7eb2e8f9f7 3362 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
<> 144:ef7eb2e8f9f7 3363 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
<> 144:ef7eb2e8f9f7 3364 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
<> 144:ef7eb2e8f9f7 3365 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
<> 144:ef7eb2e8f9f7 3366 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
<> 144:ef7eb2e8f9f7 3367 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
<> 144:ef7eb2e8f9f7 3368
<> 144:ef7eb2e8f9f7 3369 /**
<> 144:ef7eb2e8f9f7 3370 * @brief EXTI15 configuration
<> 144:ef7eb2e8f9f7 3371 */
<> 144:ef7eb2e8f9f7 3372 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
<> 144:ef7eb2e8f9f7 3373 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
<> 144:ef7eb2e8f9f7 3374 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
<> 144:ef7eb2e8f9f7 3375 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
<> 144:ef7eb2e8f9f7 3376 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
<> 144:ef7eb2e8f9f7 3377 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
<> 144:ef7eb2e8f9f7 3378
<> 144:ef7eb2e8f9f7 3379 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 144:ef7eb2e8f9f7 3380 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
<> 144:ef7eb2e8f9f7 3381 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
<> 144:ef7eb2e8f9f7 3382
<> 144:ef7eb2e8f9f7 3383 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3384 /* */
<> 144:ef7eb2e8f9f7 3385 /* TIM */
<> 144:ef7eb2e8f9f7 3386 /* */
<> 144:ef7eb2e8f9f7 3387 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3388 /******************* Bit definition for TIM_CR1 register ********************/
<> 144:ef7eb2e8f9f7 3389 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
<> 144:ef7eb2e8f9f7 3390 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
<> 144:ef7eb2e8f9f7 3391 #define TIM_CR1_URS 0x0004U /*!<Update request source */
<> 144:ef7eb2e8f9f7 3392 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
<> 144:ef7eb2e8f9f7 3393 #define TIM_CR1_DIR 0x0010U /*!<Direction */
<> 144:ef7eb2e8f9f7 3394
<> 144:ef7eb2e8f9f7 3395 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 144:ef7eb2e8f9f7 3396 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3397 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3398
<> 144:ef7eb2e8f9f7 3399 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
<> 144:ef7eb2e8f9f7 3400
<> 144:ef7eb2e8f9f7 3401 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
<> 144:ef7eb2e8f9f7 3402 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3403 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3404
<> 144:ef7eb2e8f9f7 3405 /******************* Bit definition for TIM_CR2 register ********************/
<> 144:ef7eb2e8f9f7 3406 #define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
<> 144:ef7eb2e8f9f7 3407 #define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
<> 144:ef7eb2e8f9f7 3408 #define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
<> 144:ef7eb2e8f9f7 3409
<> 144:ef7eb2e8f9f7 3410 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 3411 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3412 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3413 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3414
<> 144:ef7eb2e8f9f7 3415 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
<> 144:ef7eb2e8f9f7 3416 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
<> 144:ef7eb2e8f9f7 3417 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
<> 144:ef7eb2e8f9f7 3418 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
<> 144:ef7eb2e8f9f7 3419 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
<> 144:ef7eb2e8f9f7 3420 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
<> 144:ef7eb2e8f9f7 3421 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
<> 144:ef7eb2e8f9f7 3422 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 3423
<> 144:ef7eb2e8f9f7 3424 /******************* Bit definition for TIM_SMCR register *******************/
<> 144:ef7eb2e8f9f7 3425 #define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
<> 144:ef7eb2e8f9f7 3426 #define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3427 #define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3428 #define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3429
<> 144:ef7eb2e8f9f7 3430 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
<> 144:ef7eb2e8f9f7 3431 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3432 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3433 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3434
<> 144:ef7eb2e8f9f7 3435 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
<> 144:ef7eb2e8f9f7 3436
<> 144:ef7eb2e8f9f7 3437 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
<> 144:ef7eb2e8f9f7 3438 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3439 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3440 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3441 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3442
<> 144:ef7eb2e8f9f7 3443 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 144:ef7eb2e8f9f7 3444 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3445 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3446
<> 144:ef7eb2e8f9f7 3447 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
<> 144:ef7eb2e8f9f7 3448 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
<> 144:ef7eb2e8f9f7 3449
<> 144:ef7eb2e8f9f7 3450 /******************* Bit definition for TIM_DIER register *******************/
<> 144:ef7eb2e8f9f7 3451 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
<> 144:ef7eb2e8f9f7 3452 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
<> 144:ef7eb2e8f9f7 3453 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
<> 144:ef7eb2e8f9f7 3454 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
<> 144:ef7eb2e8f9f7 3455 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
<> 144:ef7eb2e8f9f7 3456 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
<> 144:ef7eb2e8f9f7 3457 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
<> 144:ef7eb2e8f9f7 3458 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
<> 144:ef7eb2e8f9f7 3459 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
<> 144:ef7eb2e8f9f7 3460 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
<> 144:ef7eb2e8f9f7 3461 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
<> 144:ef7eb2e8f9f7 3462 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
<> 144:ef7eb2e8f9f7 3463 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
<> 144:ef7eb2e8f9f7 3464 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
<> 144:ef7eb2e8f9f7 3465 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
<> 144:ef7eb2e8f9f7 3466
<> 144:ef7eb2e8f9f7 3467 /******************** Bit definition for TIM_SR register ********************/
<> 144:ef7eb2e8f9f7 3468 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
<> 144:ef7eb2e8f9f7 3469 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
<> 144:ef7eb2e8f9f7 3470 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
<> 144:ef7eb2e8f9f7 3471 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
<> 144:ef7eb2e8f9f7 3472 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
<> 144:ef7eb2e8f9f7 3473 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
<> 144:ef7eb2e8f9f7 3474 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
<> 144:ef7eb2e8f9f7 3475 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
<> 144:ef7eb2e8f9f7 3476 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3477 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3478 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3479 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
<> 144:ef7eb2e8f9f7 3480
<> 144:ef7eb2e8f9f7 3481 /******************* Bit definition for TIM_EGR register ********************/
<> 144:ef7eb2e8f9f7 3482 #define TIM_EGR_UG 0x01U /*!<Update Generation */
<> 144:ef7eb2e8f9f7 3483 #define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
<> 144:ef7eb2e8f9f7 3484 #define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
<> 144:ef7eb2e8f9f7 3485 #define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
<> 144:ef7eb2e8f9f7 3486 #define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
<> 144:ef7eb2e8f9f7 3487 #define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
<> 144:ef7eb2e8f9f7 3488 #define TIM_EGR_TG 0x40U /*!<Trigger Generation */
<> 144:ef7eb2e8f9f7 3489 #define TIM_EGR_BG 0x80U /*!<Break Generation */
<> 144:ef7eb2e8f9f7 3490
<> 144:ef7eb2e8f9f7 3491 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 144:ef7eb2e8f9f7 3492 #define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 144:ef7eb2e8f9f7 3493 #define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3494 #define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3495
<> 144:ef7eb2e8f9f7 3496 #define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
<> 144:ef7eb2e8f9f7 3497 #define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
<> 144:ef7eb2e8f9f7 3498
<> 144:ef7eb2e8f9f7 3499 #define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 144:ef7eb2e8f9f7 3500 #define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3501 #define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3502 #define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3503
<> 144:ef7eb2e8f9f7 3504 #define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
<> 144:ef7eb2e8f9f7 3505
<> 144:ef7eb2e8f9f7 3506 #define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 144:ef7eb2e8f9f7 3507 #define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3508 #define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3509
<> 144:ef7eb2e8f9f7 3510 #define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
<> 144:ef7eb2e8f9f7 3511 #define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
<> 144:ef7eb2e8f9f7 3512
<> 144:ef7eb2e8f9f7 3513 #define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 144:ef7eb2e8f9f7 3514 #define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3515 #define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3516 #define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3517
<> 144:ef7eb2e8f9f7 3518 #define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
<> 144:ef7eb2e8f9f7 3519
<> 144:ef7eb2e8f9f7 3520 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 3521
<> 144:ef7eb2e8f9f7 3522 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 144:ef7eb2e8f9f7 3523 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3524 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3525
<> 144:ef7eb2e8f9f7 3526 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 144:ef7eb2e8f9f7 3527 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3528 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3529 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3530 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3531
<> 144:ef7eb2e8f9f7 3532 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 144:ef7eb2e8f9f7 3533 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3534 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3535
<> 144:ef7eb2e8f9f7 3536 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 144:ef7eb2e8f9f7 3537 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3538 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3539 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3540 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3541
<> 144:ef7eb2e8f9f7 3542 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 144:ef7eb2e8f9f7 3543 #define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 144:ef7eb2e8f9f7 3544 #define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3545 #define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3546
<> 144:ef7eb2e8f9f7 3547 #define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
<> 144:ef7eb2e8f9f7 3548 #define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
<> 144:ef7eb2e8f9f7 3549
<> 144:ef7eb2e8f9f7 3550 #define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 144:ef7eb2e8f9f7 3551 #define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3552 #define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3553 #define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3554
<> 144:ef7eb2e8f9f7 3555 #define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
<> 144:ef7eb2e8f9f7 3556
<> 144:ef7eb2e8f9f7 3557 #define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 144:ef7eb2e8f9f7 3558 #define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3559 #define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3560
<> 144:ef7eb2e8f9f7 3561 #define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 3562 #define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 3563
<> 144:ef7eb2e8f9f7 3564 #define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 3565 #define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3566 #define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3567 #define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3568
<> 144:ef7eb2e8f9f7 3569 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
<> 144:ef7eb2e8f9f7 3570
<> 144:ef7eb2e8f9f7 3571 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 3572
<> 144:ef7eb2e8f9f7 3573 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 144:ef7eb2e8f9f7 3574 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3575 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3576
<> 144:ef7eb2e8f9f7 3577 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 144:ef7eb2e8f9f7 3578 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3579 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3580 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3581 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3582
<> 144:ef7eb2e8f9f7 3583 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 144:ef7eb2e8f9f7 3584 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3585 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3586
<> 144:ef7eb2e8f9f7 3587 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 144:ef7eb2e8f9f7 3588 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3589 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3590 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3591 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3592
<> 144:ef7eb2e8f9f7 3593 /******************* Bit definition for TIM_CCER register *******************/
<> 144:ef7eb2e8f9f7 3594 #define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
<> 144:ef7eb2e8f9f7 3595 #define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
<> 144:ef7eb2e8f9f7 3596 #define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
<> 144:ef7eb2e8f9f7 3597 #define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3598 #define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
<> 144:ef7eb2e8f9f7 3599 #define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
<> 144:ef7eb2e8f9f7 3600 #define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
<> 144:ef7eb2e8f9f7 3601 #define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3602 #define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
<> 144:ef7eb2e8f9f7 3603 #define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
<> 144:ef7eb2e8f9f7 3604 #define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
<> 144:ef7eb2e8f9f7 3605 #define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3606 #define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
<> 144:ef7eb2e8f9f7 3607 #define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
<> 144:ef7eb2e8f9f7 3608 #define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 3609
<> 144:ef7eb2e8f9f7 3610 /******************* Bit definition for TIM_CNT register ********************/
<> 144:ef7eb2e8f9f7 3611 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
<> 144:ef7eb2e8f9f7 3612
<> 144:ef7eb2e8f9f7 3613 /******************* Bit definition for TIM_PSC register ********************/
<> 144:ef7eb2e8f9f7 3614 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
<> 144:ef7eb2e8f9f7 3615
<> 144:ef7eb2e8f9f7 3616 /******************* Bit definition for TIM_ARR register ********************/
<> 144:ef7eb2e8f9f7 3617 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
<> 144:ef7eb2e8f9f7 3618
<> 144:ef7eb2e8f9f7 3619 /******************* Bit definition for TIM_RCR register ********************/
<> 144:ef7eb2e8f9f7 3620 #define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
<> 144:ef7eb2e8f9f7 3621
<> 144:ef7eb2e8f9f7 3622 /******************* Bit definition for TIM_CCR1 register *******************/
<> 144:ef7eb2e8f9f7 3623 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
<> 144:ef7eb2e8f9f7 3624
<> 144:ef7eb2e8f9f7 3625 /******************* Bit definition for TIM_CCR2 register *******************/
<> 144:ef7eb2e8f9f7 3626 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
<> 144:ef7eb2e8f9f7 3627
<> 144:ef7eb2e8f9f7 3628 /******************* Bit definition for TIM_CCR3 register *******************/
<> 144:ef7eb2e8f9f7 3629 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
<> 144:ef7eb2e8f9f7 3630
<> 144:ef7eb2e8f9f7 3631 /******************* Bit definition for TIM_CCR4 register *******************/
<> 144:ef7eb2e8f9f7 3632 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
<> 144:ef7eb2e8f9f7 3633
<> 144:ef7eb2e8f9f7 3634 /******************* Bit definition for TIM_BDTR register *******************/
<> 144:ef7eb2e8f9f7 3635 #define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 144:ef7eb2e8f9f7 3636 #define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3637 #define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3638 #define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3639 #define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3640 #define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3641 #define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3642 #define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3643 #define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3644
<> 144:ef7eb2e8f9f7 3645 #define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
<> 144:ef7eb2e8f9f7 3646 #define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3647 #define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3648
<> 144:ef7eb2e8f9f7 3649 #define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
<> 144:ef7eb2e8f9f7 3650 #define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
<> 144:ef7eb2e8f9f7 3651 #define TIM_BDTR_BKE 0x1000U /*!<Break enable */
<> 144:ef7eb2e8f9f7 3652 #define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
<> 144:ef7eb2e8f9f7 3653 #define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
<> 144:ef7eb2e8f9f7 3654 #define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
<> 144:ef7eb2e8f9f7 3655
<> 144:ef7eb2e8f9f7 3656 /******************* Bit definition for TIM_DCR register ********************/
<> 144:ef7eb2e8f9f7 3657 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
<> 144:ef7eb2e8f9f7 3658 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3659 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3660 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3661 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3662 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3663
<> 144:ef7eb2e8f9f7 3664 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
<> 144:ef7eb2e8f9f7 3665 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3666 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3667 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3668 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3669 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3670
<> 144:ef7eb2e8f9f7 3671 /******************* Bit definition for TIM_DMAR register *******************/
<> 144:ef7eb2e8f9f7 3672 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
<> 144:ef7eb2e8f9f7 3673
<> 144:ef7eb2e8f9f7 3674 /******************* Bit definition for TIM_OR register *********************/
<> 144:ef7eb2e8f9f7 3675 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 144:ef7eb2e8f9f7 3676 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3677 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3678 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
<> 144:ef7eb2e8f9f7 3679 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3680 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3681
<> 144:ef7eb2e8f9f7 3682
<> 144:ef7eb2e8f9f7 3683 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3684 /* */
<> 144:ef7eb2e8f9f7 3685 /* Universal Synchronous Asynchronous Receiver Transmitter */
<> 144:ef7eb2e8f9f7 3686 /* */
<> 144:ef7eb2e8f9f7 3687 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3688 /******************* Bit definition for USART_SR register *******************/
<> 144:ef7eb2e8f9f7 3689 #define USART_SR_PE 0x0001U /*!<Parity Error */
<> 144:ef7eb2e8f9f7 3690 #define USART_SR_FE 0x0002U /*!<Framing Error */
<> 144:ef7eb2e8f9f7 3691 #define USART_SR_NE 0x0004U /*!<Noise Error Flag */
<> 144:ef7eb2e8f9f7 3692 #define USART_SR_ORE 0x0008U /*!<OverRun Error */
<> 144:ef7eb2e8f9f7 3693 #define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
<> 144:ef7eb2e8f9f7 3694 #define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
<> 144:ef7eb2e8f9f7 3695 #define USART_SR_TC 0x0040U /*!<Transmission Complete */
<> 144:ef7eb2e8f9f7 3696 #define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
<> 144:ef7eb2e8f9f7 3697 #define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
<> 144:ef7eb2e8f9f7 3698 #define USART_SR_CTS 0x0200U /*!<CTS Flag */
<> 144:ef7eb2e8f9f7 3699
<> 144:ef7eb2e8f9f7 3700 /******************* Bit definition for USART_DR register *******************/
<> 144:ef7eb2e8f9f7 3701 #define USART_DR_DR 0x01FFU /*!<Data value */
<> 144:ef7eb2e8f9f7 3702
<> 144:ef7eb2e8f9f7 3703 /****************** Bit definition for USART_BRR register *******************/
<> 144:ef7eb2e8f9f7 3704 #define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
<> 144:ef7eb2e8f9f7 3705 #define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
<> 144:ef7eb2e8f9f7 3706
<> 144:ef7eb2e8f9f7 3707 /****************** Bit definition for USART_CR1 register *******************/
<> 144:ef7eb2e8f9f7 3708 #define USART_CR1_SBK 0x0001U /*!<Send Break */
<> 144:ef7eb2e8f9f7 3709 #define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
<> 144:ef7eb2e8f9f7 3710 #define USART_CR1_RE 0x0004U /*!<Receiver Enable */
<> 144:ef7eb2e8f9f7 3711 #define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
<> 144:ef7eb2e8f9f7 3712 #define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3713 #define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3714 #define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 3715 #define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3716 #define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 3717 #define USART_CR1_PS 0x0200U /*!<Parity Selection */
<> 144:ef7eb2e8f9f7 3718 #define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
<> 144:ef7eb2e8f9f7 3719 #define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
<> 144:ef7eb2e8f9f7 3720 #define USART_CR1_M 0x1000U /*!<Word length */
<> 144:ef7eb2e8f9f7 3721 #define USART_CR1_UE 0x2000U /*!<USART Enable */
<> 144:ef7eb2e8f9f7 3722 #define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
<> 144:ef7eb2e8f9f7 3723
<> 144:ef7eb2e8f9f7 3724 /****************** Bit definition for USART_CR2 register *******************/
<> 144:ef7eb2e8f9f7 3725 #define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
<> 144:ef7eb2e8f9f7 3726 #define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
<> 144:ef7eb2e8f9f7 3727 #define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
<> 144:ef7eb2e8f9f7 3728 #define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
<> 144:ef7eb2e8f9f7 3729 #define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
<> 144:ef7eb2e8f9f7 3730 #define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
<> 144:ef7eb2e8f9f7 3731 #define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
<> 144:ef7eb2e8f9f7 3732
<> 144:ef7eb2e8f9f7 3733 #define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
<> 144:ef7eb2e8f9f7 3734 #define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3735 #define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3736
<> 144:ef7eb2e8f9f7 3737 #define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
<> 144:ef7eb2e8f9f7 3738
<> 144:ef7eb2e8f9f7 3739 /****************** Bit definition for USART_CR3 register *******************/
<> 144:ef7eb2e8f9f7 3740 #define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3741 #define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
<> 144:ef7eb2e8f9f7 3742 #define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
<> 144:ef7eb2e8f9f7 3743 #define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
<> 144:ef7eb2e8f9f7 3744 #define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
<> 144:ef7eb2e8f9f7 3745 #define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
<> 144:ef7eb2e8f9f7 3746 #define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
<> 144:ef7eb2e8f9f7 3747 #define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
<> 144:ef7eb2e8f9f7 3748 #define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
<> 144:ef7eb2e8f9f7 3749 #define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
<> 144:ef7eb2e8f9f7 3750 #define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
<> 144:ef7eb2e8f9f7 3751 #define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
<> 144:ef7eb2e8f9f7 3752
<> 144:ef7eb2e8f9f7 3753 /****************** Bit definition for USART_GTPR register ******************/
<> 144:ef7eb2e8f9f7 3754 #define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
<> 144:ef7eb2e8f9f7 3755 #define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3756 #define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3757 #define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3758 #define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3759 #define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3760 #define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3761 #define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3762 #define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3763
<> 144:ef7eb2e8f9f7 3764 #define USART_GTPR_GT 0xFF00U /*!<Guard time value */
<> 144:ef7eb2e8f9f7 3765
<> 144:ef7eb2e8f9f7 3766 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3767 /* */
<> 144:ef7eb2e8f9f7 3768 /* Window WATCHDOG */
<> 144:ef7eb2e8f9f7 3769 /* */
<> 144:ef7eb2e8f9f7 3770 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3771 /******************* Bit definition for WWDG_CR register ********************/
<> 144:ef7eb2e8f9f7 3772 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 144:ef7eb2e8f9f7 3773 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3774 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3775 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3776 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3777 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3778 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3779 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3780 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3781 #define WWDG_CR_T0 WWDG_CR_T_0
<> 144:ef7eb2e8f9f7 3782 #define WWDG_CR_T1 WWDG_CR_T_1
<> 144:ef7eb2e8f9f7 3783 #define WWDG_CR_T2 WWDG_CR_T_2
<> 144:ef7eb2e8f9f7 3784 #define WWDG_CR_T3 WWDG_CR_T_3
<> 144:ef7eb2e8f9f7 3785 #define WWDG_CR_T4 WWDG_CR_T_4
<> 144:ef7eb2e8f9f7 3786 #define WWDG_CR_T5 WWDG_CR_T_5
<> 144:ef7eb2e8f9f7 3787 #define WWDG_CR_T6 WWDG_CR_T_6
<> 144:ef7eb2e8f9f7 3788
<> 144:ef7eb2e8f9f7 3789 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
<> 144:ef7eb2e8f9f7 3790
<> 144:ef7eb2e8f9f7 3791 /******************* Bit definition for WWDG_CFR register *******************/
<> 144:ef7eb2e8f9f7 3792 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
<> 144:ef7eb2e8f9f7 3793 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3794 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3795 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3796 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3797 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3798 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3799 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3800 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3801 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 144:ef7eb2e8f9f7 3802 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 144:ef7eb2e8f9f7 3803 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 144:ef7eb2e8f9f7 3804 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 144:ef7eb2e8f9f7 3805 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 144:ef7eb2e8f9f7 3806 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 144:ef7eb2e8f9f7 3807 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 144:ef7eb2e8f9f7 3808
<> 144:ef7eb2e8f9f7 3809 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
<> 144:ef7eb2e8f9f7 3810 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3811 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3812 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3813 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 144:ef7eb2e8f9f7 3814 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 144:ef7eb2e8f9f7 3815
<> 144:ef7eb2e8f9f7 3816 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 3817
<> 144:ef7eb2e8f9f7 3818 /******************* Bit definition for WWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 3819 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
<> 144:ef7eb2e8f9f7 3820
<> 144:ef7eb2e8f9f7 3821
<> 144:ef7eb2e8f9f7 3822 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3823 /* */
<> 144:ef7eb2e8f9f7 3824 /* DBG */
<> 144:ef7eb2e8f9f7 3825 /* */
<> 144:ef7eb2e8f9f7 3826 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3827 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 144:ef7eb2e8f9f7 3828 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
<> 144:ef7eb2e8f9f7 3829 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
<> 144:ef7eb2e8f9f7 3830
<> 144:ef7eb2e8f9f7 3831 /******************** Bit definition for DBGMCU_CR register *****************/
<> 144:ef7eb2e8f9f7 3832 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
<> 144:ef7eb2e8f9f7 3833 #define DBGMCU_CR_DBG_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 3834 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
<> 144:ef7eb2e8f9f7 3835 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
<> 144:ef7eb2e8f9f7 3836
<> 144:ef7eb2e8f9f7 3837 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
<> 144:ef7eb2e8f9f7 3838 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3839 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3840
<> 144:ef7eb2e8f9f7 3841 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 144:ef7eb2e8f9f7 3842 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 3843 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 3844 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
<> 144:ef7eb2e8f9f7 3845 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
<> 144:ef7eb2e8f9f7 3846 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
<> 144:ef7eb2e8f9f7 3847 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
<> 144:ef7eb2e8f9f7 3848 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 3849 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
<> 144:ef7eb2e8f9f7 3850 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
<> 144:ef7eb2e8f9f7 3851 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
<> 144:ef7eb2e8f9f7 3852 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
<> 144:ef7eb2e8f9f7 3853 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
<> 144:ef7eb2e8f9f7 3854 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
<> 144:ef7eb2e8f9f7 3855 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
<> 144:ef7eb2e8f9f7 3856 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
<> 144:ef7eb2e8f9f7 3857 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
<> 144:ef7eb2e8f9f7 3858 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
<> 144:ef7eb2e8f9f7 3859 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 3860 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
<> 144:ef7eb2e8f9f7 3861
<> 144:ef7eb2e8f9f7 3862 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 144:ef7eb2e8f9f7 3863 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 3864 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 3865 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
<> 144:ef7eb2e8f9f7 3866 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
<> 144:ef7eb2e8f9f7 3867 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
<> 144:ef7eb2e8f9f7 3868
<> 144:ef7eb2e8f9f7 3869 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3870 /* */
<> 144:ef7eb2e8f9f7 3871 /* USB_OTG */
<> 144:ef7eb2e8f9f7 3872 /* */
<> 144:ef7eb2e8f9f7 3873 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3874 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
<> 144:ef7eb2e8f9f7 3875 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
<> 144:ef7eb2e8f9f7 3876 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
<> 144:ef7eb2e8f9f7 3877 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
<> 144:ef7eb2e8f9f7 3878 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
<> 144:ef7eb2e8f9f7 3879 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
<> 144:ef7eb2e8f9f7 3880 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
<> 144:ef7eb2e8f9f7 3881 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
<> 144:ef7eb2e8f9f7 3882 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
<> 144:ef7eb2e8f9f7 3883 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
<> 144:ef7eb2e8f9f7 3884 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
<> 144:ef7eb2e8f9f7 3885
<> 144:ef7eb2e8f9f7 3886 /******************** Bit definition forUSB_OTG_HCFG register ********************/
<> 144:ef7eb2e8f9f7 3887
<> 144:ef7eb2e8f9f7 3888 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
<> 144:ef7eb2e8f9f7 3889 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3890 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3891 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
<> 144:ef7eb2e8f9f7 3892
<> 144:ef7eb2e8f9f7 3893 /******************** Bit definition forUSB_OTG_DCFG register ********************/
<> 144:ef7eb2e8f9f7 3894
<> 144:ef7eb2e8f9f7 3895 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
<> 144:ef7eb2e8f9f7 3896 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3897 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3898 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
<> 144:ef7eb2e8f9f7 3899
<> 144:ef7eb2e8f9f7 3900 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
<> 144:ef7eb2e8f9f7 3901 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3902 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3903 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3904 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3905 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3906 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3907 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3908
<> 144:ef7eb2e8f9f7 3909 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
<> 144:ef7eb2e8f9f7 3910 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3911 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3912
<> 144:ef7eb2e8f9f7 3913 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
<> 144:ef7eb2e8f9f7 3914 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3915 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3916
<> 144:ef7eb2e8f9f7 3917 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
<> 144:ef7eb2e8f9f7 3918 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
<> 144:ef7eb2e8f9f7 3919 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
<> 144:ef7eb2e8f9f7 3920 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
<> 144:ef7eb2e8f9f7 3921
<> 144:ef7eb2e8f9f7 3922 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
<> 144:ef7eb2e8f9f7 3923 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
<> 144:ef7eb2e8f9f7 3924 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
<> 144:ef7eb2e8f9f7 3925 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
<> 144:ef7eb2e8f9f7 3926 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
<> 144:ef7eb2e8f9f7 3927 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
<> 144:ef7eb2e8f9f7 3928 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
<> 144:ef7eb2e8f9f7 3929
<> 144:ef7eb2e8f9f7 3930 /******************** Bit definition forUSB_OTG_DCTL register ********************/
<> 144:ef7eb2e8f9f7 3931 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
<> 144:ef7eb2e8f9f7 3932 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
<> 144:ef7eb2e8f9f7 3933 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
<> 144:ef7eb2e8f9f7 3934 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
<> 144:ef7eb2e8f9f7 3935
<> 144:ef7eb2e8f9f7 3936 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
<> 144:ef7eb2e8f9f7 3937 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3938 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3939 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3940 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
<> 144:ef7eb2e8f9f7 3941 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
<> 144:ef7eb2e8f9f7 3942 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
<> 144:ef7eb2e8f9f7 3943 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
<> 144:ef7eb2e8f9f7 3944 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
<> 144:ef7eb2e8f9f7 3945
<> 144:ef7eb2e8f9f7 3946 /******************** Bit definition forUSB_OTG_HFIR register ********************/
<> 144:ef7eb2e8f9f7 3947 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
<> 144:ef7eb2e8f9f7 3948
<> 144:ef7eb2e8f9f7 3949 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
<> 144:ef7eb2e8f9f7 3950 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
<> 144:ef7eb2e8f9f7 3951 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
<> 144:ef7eb2e8f9f7 3952
<> 144:ef7eb2e8f9f7 3953 /******************** Bit definition forUSB_OTG_DSTS register ********************/
<> 144:ef7eb2e8f9f7 3954 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
<> 144:ef7eb2e8f9f7 3955
<> 144:ef7eb2e8f9f7 3956 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
<> 144:ef7eb2e8f9f7 3957 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3958 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3959 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
<> 144:ef7eb2e8f9f7 3960 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
<> 144:ef7eb2e8f9f7 3961
<> 144:ef7eb2e8f9f7 3962 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
<> 144:ef7eb2e8f9f7 3963 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
<> 144:ef7eb2e8f9f7 3964
<> 144:ef7eb2e8f9f7 3965 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
<> 144:ef7eb2e8f9f7 3966 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3967 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3968 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3969 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3970 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
<> 144:ef7eb2e8f9f7 3971 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
<> 144:ef7eb2e8f9f7 3972 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
<> 144:ef7eb2e8f9f7 3973
<> 144:ef7eb2e8f9f7 3974 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
<> 144:ef7eb2e8f9f7 3975
<> 144:ef7eb2e8f9f7 3976 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
<> 144:ef7eb2e8f9f7 3977 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3978 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3979 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3980 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 144:ef7eb2e8f9f7 3981 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
<> 144:ef7eb2e8f9f7 3982 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
<> 144:ef7eb2e8f9f7 3983
<> 144:ef7eb2e8f9f7 3984 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
<> 144:ef7eb2e8f9f7 3985 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3986 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3987 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3988 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3989 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
<> 144:ef7eb2e8f9f7 3990 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
<> 144:ef7eb2e8f9f7 3991 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
<> 144:ef7eb2e8f9f7 3992 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
<> 144:ef7eb2e8f9f7 3993 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
<> 144:ef7eb2e8f9f7 3994 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
<> 144:ef7eb2e8f9f7 3995 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
<> 144:ef7eb2e8f9f7 3996 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
<> 144:ef7eb2e8f9f7 3997 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
<> 144:ef7eb2e8f9f7 3998 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
<> 144:ef7eb2e8f9f7 3999 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
<> 144:ef7eb2e8f9f7 4000 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
<> 144:ef7eb2e8f9f7 4001 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
<> 144:ef7eb2e8f9f7 4002
<> 144:ef7eb2e8f9f7 4003 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
<> 144:ef7eb2e8f9f7 4004 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
<> 144:ef7eb2e8f9f7 4005 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
<> 144:ef7eb2e8f9f7 4006 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
<> 144:ef7eb2e8f9f7 4007 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
<> 144:ef7eb2e8f9f7 4008 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
<> 144:ef7eb2e8f9f7 4009
<> 144:ef7eb2e8f9f7 4010 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
<> 144:ef7eb2e8f9f7 4011 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4012 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4013 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4014 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4015 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4016 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
<> 144:ef7eb2e8f9f7 4017 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
<> 144:ef7eb2e8f9f7 4018
<> 144:ef7eb2e8f9f7 4019 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
<> 144:ef7eb2e8f9f7 4020 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 4021 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 4022 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 144:ef7eb2e8f9f7 4023 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 4024 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 4025 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 4026 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 144:ef7eb2e8f9f7 4027 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 4028
<> 144:ef7eb2e8f9f7 4029 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
<> 144:ef7eb2e8f9f7 4030 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
<> 144:ef7eb2e8f9f7 4031
<> 144:ef7eb2e8f9f7 4032 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
<> 144:ef7eb2e8f9f7 4033 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4034 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4035 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4036 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4037 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4038 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4039 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4040 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4041
<> 144:ef7eb2e8f9f7 4042 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
<> 144:ef7eb2e8f9f7 4043 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4044 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4045 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4046 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4047 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4048 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4049 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4050 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4051
<> 144:ef7eb2e8f9f7 4052 /******************** Bit definition forUSB_OTG_HAINT register ********************/
<> 144:ef7eb2e8f9f7 4053 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
<> 144:ef7eb2e8f9f7 4054
<> 144:ef7eb2e8f9f7 4055 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
<> 144:ef7eb2e8f9f7 4056 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 4057 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 4058 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
<> 144:ef7eb2e8f9f7 4059 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
<> 144:ef7eb2e8f9f7 4060 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
<> 144:ef7eb2e8f9f7 4061 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
<> 144:ef7eb2e8f9f7 4062 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 4063
<> 144:ef7eb2e8f9f7 4064 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
<> 144:ef7eb2e8f9f7 4065 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
<> 144:ef7eb2e8f9f7 4066 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
<> 144:ef7eb2e8f9f7 4067 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
<> 144:ef7eb2e8f9f7 4068 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
<> 144:ef7eb2e8f9f7 4069 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
<> 144:ef7eb2e8f9f7 4070 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
<> 144:ef7eb2e8f9f7 4071 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
<> 144:ef7eb2e8f9f7 4072 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
<> 144:ef7eb2e8f9f7 4073 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
<> 144:ef7eb2e8f9f7 4074 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
<> 144:ef7eb2e8f9f7 4075 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
<> 144:ef7eb2e8f9f7 4076 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
<> 144:ef7eb2e8f9f7 4077 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
<> 144:ef7eb2e8f9f7 4078 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
<> 144:ef7eb2e8f9f7 4079 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
<> 144:ef7eb2e8f9f7 4080 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
<> 144:ef7eb2e8f9f7 4081 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
<> 144:ef7eb2e8f9f7 4082 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
<> 144:ef7eb2e8f9f7 4083 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
<> 144:ef7eb2e8f9f7 4084 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
<> 144:ef7eb2e8f9f7 4085 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
<> 144:ef7eb2e8f9f7 4086 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
<> 144:ef7eb2e8f9f7 4087 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
<> 144:ef7eb2e8f9f7 4088 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
<> 144:ef7eb2e8f9f7 4089 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
<> 144:ef7eb2e8f9f7 4090 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
<> 144:ef7eb2e8f9f7 4091
<> 144:ef7eb2e8f9f7 4092 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
<> 144:ef7eb2e8f9f7 4093 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
<> 144:ef7eb2e8f9f7 4094 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
<> 144:ef7eb2e8f9f7 4095 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
<> 144:ef7eb2e8f9f7 4096 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
<> 144:ef7eb2e8f9f7 4097 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 4098 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
<> 144:ef7eb2e8f9f7 4099 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
<> 144:ef7eb2e8f9f7 4100 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
<> 144:ef7eb2e8f9f7 4101 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
<> 144:ef7eb2e8f9f7 4102 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
<> 144:ef7eb2e8f9f7 4103 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
<> 144:ef7eb2e8f9f7 4104 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
<> 144:ef7eb2e8f9f7 4105 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
<> 144:ef7eb2e8f9f7 4106 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
<> 144:ef7eb2e8f9f7 4107 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
<> 144:ef7eb2e8f9f7 4108 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
<> 144:ef7eb2e8f9f7 4109 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
<> 144:ef7eb2e8f9f7 4110 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
<> 144:ef7eb2e8f9f7 4111 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
<> 144:ef7eb2e8f9f7 4112 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
<> 144:ef7eb2e8f9f7 4113 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
<> 144:ef7eb2e8f9f7 4114 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 4115 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
<> 144:ef7eb2e8f9f7 4116 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
<> 144:ef7eb2e8f9f7 4117 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
<> 144:ef7eb2e8f9f7 4118 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
<> 144:ef7eb2e8f9f7 4119
<> 144:ef7eb2e8f9f7 4120 /******************** Bit definition forUSB_OTG_DAINT register ********************/
<> 144:ef7eb2e8f9f7 4121 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
<> 144:ef7eb2e8f9f7 4122 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
<> 144:ef7eb2e8f9f7 4123
<> 144:ef7eb2e8f9f7 4124 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
<> 144:ef7eb2e8f9f7 4125 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
<> 144:ef7eb2e8f9f7 4126
<> 144:ef7eb2e8f9f7 4127 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 144:ef7eb2e8f9f7 4128 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 4129 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 4130 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 4131 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 4132
<> 144:ef7eb2e8f9f7 4133 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
<> 144:ef7eb2e8f9f7 4134 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 4135 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 4136
<> 144:ef7eb2e8f9f7 4137 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 4138
<> 144:ef7eb2e8f9f7 4139 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 144:ef7eb2e8f9f7 4140 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4141 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4142 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4143 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4144 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 144:ef7eb2e8f9f7 4145
<> 144:ef7eb2e8f9f7 4146 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 4147 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4148 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4149
<> 144:ef7eb2e8f9f7 4150 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 144:ef7eb2e8f9f7 4151 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4152 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4153 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4154 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4155
<> 144:ef7eb2e8f9f7 4156 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 4157 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4158 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4159 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4160 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4161
<> 144:ef7eb2e8f9f7 4162 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 144:ef7eb2e8f9f7 4163 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4164 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4165 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4166 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4167
<> 144:ef7eb2e8f9f7 4168 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 4169
<> 144:ef7eb2e8f9f7 4170 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 144:ef7eb2e8f9f7 4171 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4172 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4173 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4174 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4175 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 144:ef7eb2e8f9f7 4176
<> 144:ef7eb2e8f9f7 4177 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 4178 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4179 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4180
<> 144:ef7eb2e8f9f7 4181 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 144:ef7eb2e8f9f7 4182 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4183 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4184 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4185 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4186
<> 144:ef7eb2e8f9f7 4187 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 4188 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4189 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4190 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4191 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4192
<> 144:ef7eb2e8f9f7 4193 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 144:ef7eb2e8f9f7 4194 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4195 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4196 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4197 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4198
<> 144:ef7eb2e8f9f7 4199 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
<> 144:ef7eb2e8f9f7 4200 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
<> 144:ef7eb2e8f9f7 4201
<> 144:ef7eb2e8f9f7 4202 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
<> 144:ef7eb2e8f9f7 4203 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
<> 144:ef7eb2e8f9f7 4204
<> 144:ef7eb2e8f9f7 4205 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 4206 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
<> 144:ef7eb2e8f9f7 4207 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
<> 144:ef7eb2e8f9f7 4208 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
<> 144:ef7eb2e8f9f7 4209 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
<> 144:ef7eb2e8f9f7 4210
<> 144:ef7eb2e8f9f7 4211 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
<> 144:ef7eb2e8f9f7 4212 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
<> 144:ef7eb2e8f9f7 4213
<> 144:ef7eb2e8f9f7 4214 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
<> 144:ef7eb2e8f9f7 4215 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
<> 144:ef7eb2e8f9f7 4216
<> 144:ef7eb2e8f9f7 4217 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
<> 144:ef7eb2e8f9f7 4218 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4219 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4220 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4221 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4222 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4223 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4224 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4225 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4226
<> 144:ef7eb2e8f9f7 4227 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
<> 144:ef7eb2e8f9f7 4228 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4229 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4230 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4231 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4232 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4233 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4234 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4235
<> 144:ef7eb2e8f9f7 4236 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
<> 144:ef7eb2e8f9f7 4237 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
<> 144:ef7eb2e8f9f7 4238 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
<> 144:ef7eb2e8f9f7 4239
<> 144:ef7eb2e8f9f7 4240 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
<> 144:ef7eb2e8f9f7 4241 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4242 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4243 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4244 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4245 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4246 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4247 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4248 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4249 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 4250 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
<> 144:ef7eb2e8f9f7 4251
<> 144:ef7eb2e8f9f7 4252 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
<> 144:ef7eb2e8f9f7 4253 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4254 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4255 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4256 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4257 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4258 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4259 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4260 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4261 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 4262 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
<> 144:ef7eb2e8f9f7 4263
<> 144:ef7eb2e8f9f7 4264 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
<> 144:ef7eb2e8f9f7 4265 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
<> 144:ef7eb2e8f9f7 4266
<> 144:ef7eb2e8f9f7 4267 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
<> 144:ef7eb2e8f9f7 4268 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
<> 144:ef7eb2e8f9f7 4269 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
<> 144:ef7eb2e8f9f7 4270
<> 144:ef7eb2e8f9f7 4271 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
<> 144:ef7eb2e8f9f7 4272 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
<> 144:ef7eb2e8f9f7 4273 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
<> 144:ef7eb2e8f9f7 4274 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
<> 144:ef7eb2e8f9f7 4275 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
<> 144:ef7eb2e8f9f7 4276 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
<> 144:ef7eb2e8f9f7 4277 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
<> 144:ef7eb2e8f9f7 4278
<> 144:ef7eb2e8f9f7 4279 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
<> 144:ef7eb2e8f9f7 4280 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
<> 144:ef7eb2e8f9f7 4281 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
<> 144:ef7eb2e8f9f7 4282
<> 144:ef7eb2e8f9f7 4283 /******************** Bit definition forUSB_OTG_CID register ********************/
<> 144:ef7eb2e8f9f7 4284 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
<> 144:ef7eb2e8f9f7 4285
<> 144:ef7eb2e8f9f7 4286 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
<> 144:ef7eb2e8f9f7 4287 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 4288 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 4289 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 144:ef7eb2e8f9f7 4290 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 4291 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 4292 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 4293 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 144:ef7eb2e8f9f7 4294 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 4295 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 144:ef7eb2e8f9f7 4296
<> 144:ef7eb2e8f9f7 4297 /******************** Bit definition forUSB_OTG_HPRT register ********************/
<> 144:ef7eb2e8f9f7 4298 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
<> 144:ef7eb2e8f9f7 4299 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
<> 144:ef7eb2e8f9f7 4300 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
<> 144:ef7eb2e8f9f7 4301 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
<> 144:ef7eb2e8f9f7 4302 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
<> 144:ef7eb2e8f9f7 4303 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
<> 144:ef7eb2e8f9f7 4304 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
<> 144:ef7eb2e8f9f7 4305 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
<> 144:ef7eb2e8f9f7 4306 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
<> 144:ef7eb2e8f9f7 4307
<> 144:ef7eb2e8f9f7 4308 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
<> 144:ef7eb2e8f9f7 4309 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4310 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4311 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
<> 144:ef7eb2e8f9f7 4314 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4315 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4316 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4317 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4318
<> 144:ef7eb2e8f9f7 4319 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
<> 144:ef7eb2e8f9f7 4320 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4321 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4322
<> 144:ef7eb2e8f9f7 4323 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
<> 144:ef7eb2e8f9f7 4324 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 4325 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 4326 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
<> 144:ef7eb2e8f9f7 4327 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 4328 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 4329 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 4330 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
<> 144:ef7eb2e8f9f7 4331 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 4332 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
<> 144:ef7eb2e8f9f7 4333 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 144:ef7eb2e8f9f7 4334 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
<> 144:ef7eb2e8f9f7 4335
<> 144:ef7eb2e8f9f7 4336 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
<> 144:ef7eb2e8f9f7 4337 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
<> 144:ef7eb2e8f9f7 4338 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
<> 144:ef7eb2e8f9f7 4339
<> 144:ef7eb2e8f9f7 4340 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
<> 144:ef7eb2e8f9f7 4341 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 144:ef7eb2e8f9f7 4342 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 144:ef7eb2e8f9f7 4343 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
<> 144:ef7eb2e8f9f7 4344 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 144:ef7eb2e8f9f7 4345
<> 144:ef7eb2e8f9f7 4346 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 4347 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4348 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4349 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 144:ef7eb2e8f9f7 4350
<> 144:ef7eb2e8f9f7 4351 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
<> 144:ef7eb2e8f9f7 4352 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4353 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4354 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4355 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4356 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 144:ef7eb2e8f9f7 4357 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 144:ef7eb2e8f9f7 4358 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 144:ef7eb2e8f9f7 4359 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 144:ef7eb2e8f9f7 4360 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 144:ef7eb2e8f9f7 4361 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 144:ef7eb2e8f9f7 4362
<> 144:ef7eb2e8f9f7 4363 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
<> 144:ef7eb2e8f9f7 4364 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 144:ef7eb2e8f9f7 4365
<> 144:ef7eb2e8f9f7 4366 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 4367 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4368 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4369 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4370 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4371 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
<> 144:ef7eb2e8f9f7 4372 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
<> 144:ef7eb2e8f9f7 4373
<> 144:ef7eb2e8f9f7 4374 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 4375 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4376 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4377
<> 144:ef7eb2e8f9f7 4378 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
<> 144:ef7eb2e8f9f7 4379 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4380 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4381
<> 144:ef7eb2e8f9f7 4382 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
<> 144:ef7eb2e8f9f7 4383 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4384 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4385 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4386 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4387 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4388 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4389 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4390 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
<> 144:ef7eb2e8f9f7 4391 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
<> 144:ef7eb2e8f9f7 4392 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
<> 144:ef7eb2e8f9f7 4393
<> 144:ef7eb2e8f9f7 4394 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
<> 144:ef7eb2e8f9f7 4395
<> 144:ef7eb2e8f9f7 4396 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
<> 144:ef7eb2e8f9f7 4397 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4398 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4399 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4400 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4401 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4402 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4403 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4404
<> 144:ef7eb2e8f9f7 4405 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
<> 144:ef7eb2e8f9f7 4406 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4407 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4408 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4409 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4410 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4411 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4412 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4413
<> 144:ef7eb2e8f9f7 4414 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
<> 144:ef7eb2e8f9f7 4415 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4416 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4417 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
<> 144:ef7eb2e8f9f7 4418 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
<> 144:ef7eb2e8f9f7 4419
<> 144:ef7eb2e8f9f7 4420 /******************** Bit definition forUSB_OTG_HCINT register ********************/
<> 144:ef7eb2e8f9f7 4421 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
<> 144:ef7eb2e8f9f7 4422 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
<> 144:ef7eb2e8f9f7 4423 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
<> 144:ef7eb2e8f9f7 4424 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
<> 144:ef7eb2e8f9f7 4425 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
<> 144:ef7eb2e8f9f7 4426 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
<> 144:ef7eb2e8f9f7 4427 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
<> 144:ef7eb2e8f9f7 4428 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
<> 144:ef7eb2e8f9f7 4429 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
<> 144:ef7eb2e8f9f7 4430 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
<> 144:ef7eb2e8f9f7 4431 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
<> 144:ef7eb2e8f9f7 4432
<> 144:ef7eb2e8f9f7 4433 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
<> 144:ef7eb2e8f9f7 4434 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 144:ef7eb2e8f9f7 4435 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 144:ef7eb2e8f9f7 4436 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
<> 144:ef7eb2e8f9f7 4437 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
<> 144:ef7eb2e8f9f7 4438 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
<> 144:ef7eb2e8f9f7 4439 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
<> 144:ef7eb2e8f9f7 4440 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
<> 144:ef7eb2e8f9f7 4441 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
<> 144:ef7eb2e8f9f7 4442 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
<> 144:ef7eb2e8f9f7 4443 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
<> 144:ef7eb2e8f9f7 4444 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
<> 144:ef7eb2e8f9f7 4445
<> 144:ef7eb2e8f9f7 4446 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
<> 144:ef7eb2e8f9f7 4447 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
<> 144:ef7eb2e8f9f7 4448 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
<> 144:ef7eb2e8f9f7 4449 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
<> 144:ef7eb2e8f9f7 4450 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
<> 144:ef7eb2e8f9f7 4451 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
<> 144:ef7eb2e8f9f7 4452 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
<> 144:ef7eb2e8f9f7 4453 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
<> 144:ef7eb2e8f9f7 4454 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
<> 144:ef7eb2e8f9f7 4455 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
<> 144:ef7eb2e8f9f7 4456 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
<> 144:ef7eb2e8f9f7 4457 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
<> 144:ef7eb2e8f9f7 4458
<> 144:ef7eb2e8f9f7 4459 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 4460
<> 144:ef7eb2e8f9f7 4461 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 4462 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 4463 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 4464 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
<> 144:ef7eb2e8f9f7 4465 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 4466 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 4467 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
<> 144:ef7eb2e8f9f7 4468 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 4469 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4470 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4471
<> 144:ef7eb2e8f9f7 4472 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
<> 144:ef7eb2e8f9f7 4473 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 144:ef7eb2e8f9f7 4474
<> 144:ef7eb2e8f9f7 4475 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
<> 144:ef7eb2e8f9f7 4476 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 144:ef7eb2e8f9f7 4477
<> 144:ef7eb2e8f9f7 4478 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
<> 144:ef7eb2e8f9f7 4479 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
<> 144:ef7eb2e8f9f7 4480
<> 144:ef7eb2e8f9f7 4481 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
<> 144:ef7eb2e8f9f7 4482 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
<> 144:ef7eb2e8f9f7 4483 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
<> 144:ef7eb2e8f9f7 4484
<> 144:ef7eb2e8f9f7 4485 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
<> 144:ef7eb2e8f9f7 4486
<> 144:ef7eb2e8f9f7 4487 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4488 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 144:ef7eb2e8f9f7 4489 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 144:ef7eb2e8f9f7 4490 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 144:ef7eb2e8f9f7 4491 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 144:ef7eb2e8f9f7 4492 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 4493 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4494 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4495 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
<> 144:ef7eb2e8f9f7 4496 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 144:ef7eb2e8f9f7 4497 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 144:ef7eb2e8f9f7 4498 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 144:ef7eb2e8f9f7 4499 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 144:ef7eb2e8f9f7 4500 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 144:ef7eb2e8f9f7 4501
<> 144:ef7eb2e8f9f7 4502 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
<> 144:ef7eb2e8f9f7 4503 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 144:ef7eb2e8f9f7 4504 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 144:ef7eb2e8f9f7 4505 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
<> 144:ef7eb2e8f9f7 4506 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
<> 144:ef7eb2e8f9f7 4507 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
<> 144:ef7eb2e8f9f7 4508 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 4511
<> 144:ef7eb2e8f9f7 4512 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 4513 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 4514
<> 144:ef7eb2e8f9f7 4515 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
<> 144:ef7eb2e8f9f7 4516 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4517 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4518
<> 144:ef7eb2e8f9f7 4519 /******************** Bit definition for PCGCCTL register ********************/
<> 144:ef7eb2e8f9f7 4520 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
<> 144:ef7eb2e8f9f7 4521 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4522 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4523
<> 144:ef7eb2e8f9f7 4524 /**
<> 144:ef7eb2e8f9f7 4525 * @}
<> 144:ef7eb2e8f9f7 4526 */
<> 144:ef7eb2e8f9f7 4527
<> 144:ef7eb2e8f9f7 4528 /**
<> 144:ef7eb2e8f9f7 4529 * @}
<> 144:ef7eb2e8f9f7 4530 */
<> 144:ef7eb2e8f9f7 4531
<> 144:ef7eb2e8f9f7 4532 /** @addtogroup Exported_macros
<> 144:ef7eb2e8f9f7 4533 * @{
<> 144:ef7eb2e8f9f7 4534 */
<> 144:ef7eb2e8f9f7 4535
<> 144:ef7eb2e8f9f7 4536 /******************************* ADC Instances ********************************/
<> 144:ef7eb2e8f9f7 4537 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 144:ef7eb2e8f9f7 4538
<> 144:ef7eb2e8f9f7 4539 /******************************* CRC Instances ********************************/
<> 144:ef7eb2e8f9f7 4540 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 144:ef7eb2e8f9f7 4541
<> 144:ef7eb2e8f9f7 4542 /******************************** DMA Instances *******************************/
<> 144:ef7eb2e8f9f7 4543 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
<> 144:ef7eb2e8f9f7 4544 ((INSTANCE) == DMA1_Stream1) || \
<> 144:ef7eb2e8f9f7 4545 ((INSTANCE) == DMA1_Stream2) || \
<> 144:ef7eb2e8f9f7 4546 ((INSTANCE) == DMA1_Stream3) || \
<> 144:ef7eb2e8f9f7 4547 ((INSTANCE) == DMA1_Stream4) || \
<> 144:ef7eb2e8f9f7 4548 ((INSTANCE) == DMA1_Stream5) || \
<> 144:ef7eb2e8f9f7 4549 ((INSTANCE) == DMA1_Stream6) || \
<> 144:ef7eb2e8f9f7 4550 ((INSTANCE) == DMA1_Stream7) || \
<> 144:ef7eb2e8f9f7 4551 ((INSTANCE) == DMA2_Stream0) || \
<> 144:ef7eb2e8f9f7 4552 ((INSTANCE) == DMA2_Stream1) || \
<> 144:ef7eb2e8f9f7 4553 ((INSTANCE) == DMA2_Stream2) || \
<> 144:ef7eb2e8f9f7 4554 ((INSTANCE) == DMA2_Stream3) || \
<> 144:ef7eb2e8f9f7 4555 ((INSTANCE) == DMA2_Stream4) || \
<> 144:ef7eb2e8f9f7 4556 ((INSTANCE) == DMA2_Stream5) || \
<> 144:ef7eb2e8f9f7 4557 ((INSTANCE) == DMA2_Stream6) || \
<> 144:ef7eb2e8f9f7 4558 ((INSTANCE) == DMA2_Stream7))
<> 144:ef7eb2e8f9f7 4559
<> 144:ef7eb2e8f9f7 4560 /******************************* GPIO Instances *******************************/
<> 144:ef7eb2e8f9f7 4561 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 144:ef7eb2e8f9f7 4562 ((INSTANCE) == GPIOB) || \
<> 144:ef7eb2e8f9f7 4563 ((INSTANCE) == GPIOC) || \
<> 144:ef7eb2e8f9f7 4564 ((INSTANCE) == GPIOD) || \
<> 144:ef7eb2e8f9f7 4565 ((INSTANCE) == GPIOE) || \
<> 144:ef7eb2e8f9f7 4566 ((INSTANCE) == GPIOH))
<> 144:ef7eb2e8f9f7 4567
<> 144:ef7eb2e8f9f7 4568 /******************************** I2C Instances *******************************/
<> 144:ef7eb2e8f9f7 4569 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 144:ef7eb2e8f9f7 4570 ((INSTANCE) == I2C2) || \
<> 144:ef7eb2e8f9f7 4571 ((INSTANCE) == I2C3))
<> 144:ef7eb2e8f9f7 4572
<> 144:ef7eb2e8f9f7 4573 /******************************** I2S Instances *******************************/
<> 144:ef7eb2e8f9f7 4574 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 144:ef7eb2e8f9f7 4575 ((INSTANCE) == SPI2) || \
<> 144:ef7eb2e8f9f7 4576 ((INSTANCE) == SPI3) || \
<> 144:ef7eb2e8f9f7 4577 ((INSTANCE) == SPI4) || \
<> 144:ef7eb2e8f9f7 4578 ((INSTANCE) == SPI5))
<> 144:ef7eb2e8f9f7 4579
<> 144:ef7eb2e8f9f7 4580 /*************************** I2S Extended Instances ***************************/
<> 144:ef7eb2e8f9f7 4581 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
<> 144:ef7eb2e8f9f7 4582 ((INSTANCE) == SPI3) || \
<> 144:ef7eb2e8f9f7 4583 ((INSTANCE) == I2S2ext) || \
<> 144:ef7eb2e8f9f7 4584 ((INSTANCE) == I2S3ext))
<> 144:ef7eb2e8f9f7 4585
<> 144:ef7eb2e8f9f7 4586
<> 144:ef7eb2e8f9f7 4587 /****************************** RTC Instances *********************************/
<> 144:ef7eb2e8f9f7 4588 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 144:ef7eb2e8f9f7 4589
<> 144:ef7eb2e8f9f7 4590 /******************************** SPI Instances *******************************/
<> 144:ef7eb2e8f9f7 4591 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 144:ef7eb2e8f9f7 4592 ((INSTANCE) == SPI2) || \
<> 144:ef7eb2e8f9f7 4593 ((INSTANCE) == SPI3) || \
<> 144:ef7eb2e8f9f7 4594 ((INSTANCE) == SPI4) || \
<> 144:ef7eb2e8f9f7 4595 ((INSTANCE) == SPI5))
<> 144:ef7eb2e8f9f7 4596 /*************************** SPI Extended Instances ***************************/
<> 144:ef7eb2e8f9f7 4597 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
<> 144:ef7eb2e8f9f7 4598 ((INSTANCE) == SPI2) || \
<> 144:ef7eb2e8f9f7 4599 ((INSTANCE) == SPI3) || \
<> 144:ef7eb2e8f9f7 4600 ((INSTANCE) == SPI4) || \
<> 144:ef7eb2e8f9f7 4601 ((INSTANCE) == SPI5) || \
<> 144:ef7eb2e8f9f7 4602 ((INSTANCE) == I2S2ext) || \
<> 144:ef7eb2e8f9f7 4603 ((INSTANCE) == I2S3ext))
<> 144:ef7eb2e8f9f7 4604
<> 144:ef7eb2e8f9f7 4605 /****************** TIM Instances : All supported instances *******************/
<> 144:ef7eb2e8f9f7 4606 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4607 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4608 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4609 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4610 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 4611 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 4612 ((INSTANCE) == TIM10) || \
<> 144:ef7eb2e8f9f7 4613 ((INSTANCE) == TIM11))
<> 144:ef7eb2e8f9f7 4614
<> 144:ef7eb2e8f9f7 4615 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 144:ef7eb2e8f9f7 4616 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4617 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4618 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4619 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4620 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 4621 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 4622 ((INSTANCE) == TIM10) || \
<> 144:ef7eb2e8f9f7 4623 ((INSTANCE) == TIM11))
<> 144:ef7eb2e8f9f7 4624
<> 144:ef7eb2e8f9f7 4625 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 4626 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4627 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4628 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4629 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4630 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 4631 ((INSTANCE) == TIM9))
<> 144:ef7eb2e8f9f7 4632
<> 144:ef7eb2e8f9f7 4633 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 4634 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4635 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4636 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4637 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4638 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4639
<> 144:ef7eb2e8f9f7 4640 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 4641 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4642 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4643 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4644 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4645 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4646
<> 144:ef7eb2e8f9f7 4647 /******************** TIM Instances : Advanced-control timers *****************/
<> 144:ef7eb2e8f9f7 4648 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
<> 144:ef7eb2e8f9f7 4649
<> 144:ef7eb2e8f9f7 4650 /******************* TIM Instances : Timer input XOR function *****************/
<> 144:ef7eb2e8f9f7 4651 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4652 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4653 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4654 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4655 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4656
<> 144:ef7eb2e8f9f7 4657 /****************** TIM Instances : DMA requests generation (UDE) *************/
<> 144:ef7eb2e8f9f7 4658 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4659 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4660 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4661 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4662 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4663
<> 144:ef7eb2e8f9f7 4664 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 144:ef7eb2e8f9f7 4665 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4666 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4667 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4668 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4669 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4670
<> 144:ef7eb2e8f9f7 4671 /************ TIM Instances : DMA requests generation (COMDE) *****************/
<> 144:ef7eb2e8f9f7 4672 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4673 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4674 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4675 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4676 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4677
<> 144:ef7eb2e8f9f7 4678 /******************** TIM Instances : DMA burst feature ***********************/
<> 144:ef7eb2e8f9f7 4679 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4680 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4681 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4682 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4683 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4684
<> 144:ef7eb2e8f9f7 4685 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
<> 144:ef7eb2e8f9f7 4686 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4687 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4688 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4689 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4690 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 4691 ((INSTANCE) == TIM9))
<> 144:ef7eb2e8f9f7 4692
<> 144:ef7eb2e8f9f7 4693 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 144:ef7eb2e8f9f7 4694 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4695 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4696 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4697 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4698 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 4699 ((INSTANCE) == TIM9))
<> 144:ef7eb2e8f9f7 4700
<> 144:ef7eb2e8f9f7 4701 /********************** TIM Instances : 32 bit Counter ************************/
<> 144:ef7eb2e8f9f7 4702 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4703 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4704
<> 144:ef7eb2e8f9f7 4705 /***************** TIM Instances : external trigger input availabe ************/
<> 144:ef7eb2e8f9f7 4706 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 4707 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4708 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 4709 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 4710 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 4711
<> 144:ef7eb2e8f9f7 4712 /****************** TIM Instances : remapping capability **********************/
<> 144:ef7eb2e8f9f7 4713 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 4714 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 4715 ((INSTANCE) == TIM11))
<> 144:ef7eb2e8f9f7 4716
<> 144:ef7eb2e8f9f7 4717 /******************* TIM Instances : output(s) available **********************/
<> 144:ef7eb2e8f9f7 4718 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 4719 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 4720 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4721 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 4722 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 4723 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 4724 || \
<> 144:ef7eb2e8f9f7 4725 (((INSTANCE) == TIM2) && \
<> 144:ef7eb2e8f9f7 4726 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4727 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 4728 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 4729 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 4730 || \
<> 144:ef7eb2e8f9f7 4731 (((INSTANCE) == TIM3) && \
<> 144:ef7eb2e8f9f7 4732 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4733 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 4734 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 4735 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 4736 || \
<> 144:ef7eb2e8f9f7 4737 (((INSTANCE) == TIM4) && \
<> 144:ef7eb2e8f9f7 4738 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4739 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 4740 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 4741 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 4742 || \
<> 144:ef7eb2e8f9f7 4743 (((INSTANCE) == TIM5) && \
<> 144:ef7eb2e8f9f7 4744 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4745 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 4746 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 4747 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 4748 || \
<> 144:ef7eb2e8f9f7 4749 (((INSTANCE) == TIM9) && \
<> 144:ef7eb2e8f9f7 4750 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4751 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 4752 || \
<> 144:ef7eb2e8f9f7 4753 (((INSTANCE) == TIM10) && \
<> 144:ef7eb2e8f9f7 4754 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 4755 || \
<> 144:ef7eb2e8f9f7 4756 (((INSTANCE) == TIM11) && \
<> 144:ef7eb2e8f9f7 4757 (((CHANNEL) == TIM_CHANNEL_1))))
<> 144:ef7eb2e8f9f7 4758
<> 144:ef7eb2e8f9f7 4759 /************ TIM Instances : complementary output(s) available ***************/
<> 144:ef7eb2e8f9f7 4760 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 4761 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 4762 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 4763 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 4764 ((CHANNEL) == TIM_CHANNEL_3))))
<> 144:ef7eb2e8f9f7 4765
<> 144:ef7eb2e8f9f7 4766 /******************** USART Instances : Synchronous mode **********************/
<> 144:ef7eb2e8f9f7 4767 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 4768 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 4769 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 4770
<> 144:ef7eb2e8f9f7 4771 /******************** UART Instances : Asynchronous mode **********************/
<> 144:ef7eb2e8f9f7 4772 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 4773 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 4774 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 4775
<> 144:ef7eb2e8f9f7 4776 /****************** UART Instances : Hardware Flow control ********************/
<> 144:ef7eb2e8f9f7 4777 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 4778 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 4779 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 4780
<> 144:ef7eb2e8f9f7 4781 /********************* UART Instances : Smard card mode ***********************/
<> 144:ef7eb2e8f9f7 4782 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 4783 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 4784 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 4785
<> 144:ef7eb2e8f9f7 4786 /*********************** UART Instances : IRDA mode ***************************/
<> 144:ef7eb2e8f9f7 4787 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 4788 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 4789 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 4790
<> 144:ef7eb2e8f9f7 4791 /*********************** PCD Instances ****************************************/
<> 144:ef7eb2e8f9f7 4792 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
<> 144:ef7eb2e8f9f7 4793
<> 144:ef7eb2e8f9f7 4794 /*********************** HCD Instances ****************************************/
<> 144:ef7eb2e8f9f7 4795 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
<> 144:ef7eb2e8f9f7 4796
<> 144:ef7eb2e8f9f7 4797 /****************************** IWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 4798 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 144:ef7eb2e8f9f7 4799
<> 144:ef7eb2e8f9f7 4800 /****************************** WWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 4801 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 144:ef7eb2e8f9f7 4802
<> 144:ef7eb2e8f9f7 4803 /****************************** SDIO Instances ********************************/
<> 144:ef7eb2e8f9f7 4804 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
<> 144:ef7eb2e8f9f7 4805
<> 144:ef7eb2e8f9f7 4806 /****************************** USB Exported Constants ************************/
<> 144:ef7eb2e8f9f7 4807 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
<> 144:ef7eb2e8f9f7 4808 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
<> 144:ef7eb2e8f9f7 4809 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
<> 144:ef7eb2e8f9f7 4810 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
<> 144:ef7eb2e8f9f7 4811
<> 144:ef7eb2e8f9f7 4812 /**
<> 144:ef7eb2e8f9f7 4813 * @}
<> 144:ef7eb2e8f9f7 4814 */
<> 144:ef7eb2e8f9f7 4815
<> 144:ef7eb2e8f9f7 4816 /**
<> 144:ef7eb2e8f9f7 4817 * @}
<> 144:ef7eb2e8f9f7 4818 */
<> 144:ef7eb2e8f9f7 4819
<> 144:ef7eb2e8f9f7 4820 /**
<> 144:ef7eb2e8f9f7 4821 * @}
<> 144:ef7eb2e8f9f7 4822 */
<> 144:ef7eb2e8f9f7 4823
<> 144:ef7eb2e8f9f7 4824 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 4825 }
<> 144:ef7eb2e8f9f7 4826 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 4827
<> 144:ef7eb2e8f9f7 4828 #endif /* __STM32F411xE_H */
<> 144:ef7eb2e8f9f7 4829
<> 144:ef7eb2e8f9f7 4830
<> 144:ef7eb2e8f9f7 4831
<> 144:ef7eb2e8f9f7 4832 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/