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targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 150:02e0a0aed4ec
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file Serial.c |
<> | 149:156823d33999 | 4 | * @brief Implementation of a 16C550 UART driver |
<> | 149:156823d33999 | 5 | * @internal |
<> | 149:156823d33999 | 6 | * @author ON Semiconductor |
<> | 149:156823d33999 | 7 | * $Rev: 0.1 $ |
<> | 149:156823d33999 | 8 | * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $ |
<> | 149:156823d33999 | 9 | ****************************************************************************** |
<> | 149:156823d33999 | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
<> | 149:156823d33999 | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
<> | 149:156823d33999 | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
<> | 149:156823d33999 | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
<> | 149:156823d33999 | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
<> | 149:156823d33999 | 15 | * if applicable the software license agreement. Do not use this software and/or |
<> | 149:156823d33999 | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
<> | 149:156823d33999 | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
<> | 149:156823d33999 | 18 | * terms and conditions. |
<> | 149:156823d33999 | 19 | * |
<> | 149:156823d33999 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 149:156823d33999 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 149:156823d33999 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 149:156823d33999 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
<> | 149:156823d33999 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 149:156823d33999 | 25 | * @endinternal |
<> | 149:156823d33999 | 26 | * |
<> | 149:156823d33999 | 27 | * @ingroup uart_16c550 |
<> | 149:156823d33999 | 28 | * |
<> | 149:156823d33999 | 29 | */ |
<> | 149:156823d33999 | 30 | #if DEVICE_SERIAL |
<> | 149:156823d33999 | 31 | |
<> | 149:156823d33999 | 32 | #include "serial_api.h" |
<> | 149:156823d33999 | 33 | |
<> | 149:156823d33999 | 34 | #include "cmsis.h" |
<> | 149:156823d33999 | 35 | #include "pinmap.h" |
<> | 149:156823d33999 | 36 | #include "PeripheralPins.h" |
<> | 149:156823d33999 | 37 | |
<> | 149:156823d33999 | 38 | #include "mbed_assert.h" |
<> | 149:156823d33999 | 39 | #include <string.h> |
<> | 149:156823d33999 | 40 | #include "uart_16c550.h" |
<> | 149:156823d33999 | 41 | #include "cmsis_nvic.h" |
<> | 149:156823d33999 | 42 | |
<> | 149:156823d33999 | 43 | static IRQn_Type Irq; |
<> | 149:156823d33999 | 44 | |
<> | 149:156823d33999 | 45 | uint32_t stdio_uart_inited = 0; |
<> | 149:156823d33999 | 46 | serial_t stdio_uart; |
<> | 149:156823d33999 | 47 | |
<> | 149:156823d33999 | 48 | static uint32_t serial_irq_ids[UART_NUM] = {0}; |
<> | 149:156823d33999 | 49 | static uart_irq_handler irq_handler; |
<> | 149:156823d33999 | 50 | static inline void uart_irq(uint8_t status, uint32_t index); |
<> | 149:156823d33999 | 51 | |
<> | 149:156823d33999 | 52 | |
<> | 149:156823d33999 | 53 | /** Opens UART device. |
<> | 149:156823d33999 | 54 | * @details |
<> | 149:156823d33999 | 55 | * Sets the necessary registers. Set to default Baud rate 115200, 8 bit, parity None and stop bit 1. |
<> | 149:156823d33999 | 56 | * The UART interrupt is enabled. |
<> | 149:156823d33999 | 57 | * |
<> | 149:156823d33999 | 58 | * @note The UART transmit interrupt is not enabled, because sending is controlled |
<> | 149:156823d33999 | 59 | * by the task. |
<> | 149:156823d33999 | 60 | * |
<> | 149:156823d33999 | 61 | * @param UartNum A UART device instance. |
<> | 149:156823d33999 | 62 | * @param options The options parameter containing the baud rate. |
<> | 149:156823d33999 | 63 | * @return True if opening was successful. |
<> | 149:156823d33999 | 64 | */ |
<> | 149:156823d33999 | 65 | |
<> | 149:156823d33999 | 66 | void serial_init(serial_t *obj, PinName tx, PinName rx) |
<> | 149:156823d33999 | 67 | { |
<> | 149:156823d33999 | 68 | uint16_t clockDivisor; |
<> | 149:156823d33999 | 69 | |
<> | 149:156823d33999 | 70 | CrossbReg_t *CbRegOffSet; |
<> | 149:156823d33999 | 71 | PadReg_t *PadRegOffset; |
<> | 149:156823d33999 | 72 | |
<> | 149:156823d33999 | 73 | //find which peripheral is associated with the rx and tx pins |
<> | 149:156823d33999 | 74 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); |
<> | 149:156823d33999 | 75 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); |
<> | 149:156823d33999 | 76 | //check if the peripherals for each pin are the same or not |
<> | 149:156823d33999 | 77 | //returns the enum associated with the peripheral |
<> | 149:156823d33999 | 78 | //in the case of this target, the enum is the base address of the peripheral |
<> | 149:156823d33999 | 79 | obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx); |
<> | 149:156823d33999 | 80 | MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC); |
<> | 149:156823d33999 | 81 | |
<> | 149:156823d33999 | 82 | pinmap_pinout(tx, PinMap_UART_TX); |
<> | 149:156823d33999 | 83 | pinmap_pinout(rx, PinMap_UART_RX); |
<> | 149:156823d33999 | 84 | |
<> | 149:156823d33999 | 85 | /*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */ |
<> | 149:156823d33999 | 86 | |
<> | 149:156823d33999 | 87 | if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) { |
<> | 149:156823d33999 | 88 | stdio_uart_inited = 1; |
<> | 149:156823d33999 | 89 | memcpy(&stdio_uart, obj, sizeof(serial_t)); |
<> | 149:156823d33999 | 90 | } |
<> | 149:156823d33999 | 91 | /*TODO: determine if pullups are needed/recommended */ |
<> | 149:156823d33999 | 92 | /* if (tx != NC) { |
<> | 149:156823d33999 | 93 | pin_mode(tx, PullUp); |
<> | 149:156823d33999 | 94 | } |
<> | 149:156823d33999 | 95 | if (rx != NC) { |
<> | 149:156823d33999 | 96 | pin_mode(rx, PullUp); |
<> | 149:156823d33999 | 97 | } |
<> | 149:156823d33999 | 98 | */ |
<> | 149:156823d33999 | 99 | /* Configure IOs to UART using cross bar, pad and GPIO settings */ |
<> | 149:156823d33999 | 100 | |
<> | 149:156823d33999 | 101 | if(obj->UARTREG == UART2REG) { |
<> | 149:156823d33999 | 102 | /* UART 2 */ |
<> | 149:156823d33999 | 103 | CLOCK_ENABLE(CLOCK_UART2); |
<> | 149:156823d33999 | 104 | Irq = Uart2_IRQn; |
<> | 149:156823d33999 | 105 | } else if(obj->UARTREG == UART1REG) { |
<> | 149:156823d33999 | 106 | /* UART 1 */ |
<> | 149:156823d33999 | 107 | CLOCK_ENABLE(CLOCK_UART1); |
<> | 149:156823d33999 | 108 | |
<> | 149:156823d33999 | 109 | Irq = Uart1_IRQn; |
<> | 149:156823d33999 | 110 | } else { |
<> | 149:156823d33999 | 111 | MBED_ASSERT(False); |
<> | 149:156823d33999 | 112 | } |
<> | 149:156823d33999 | 113 | |
<> | 149:156823d33999 | 114 | CLOCK_ENABLE(CLOCK_GPIO); |
<> | 149:156823d33999 | 115 | CLOCK_ENABLE(CLOCK_CROSSB); |
<> | 149:156823d33999 | 116 | CLOCK_ENABLE(CLOCK_PAD); |
<> | 149:156823d33999 | 117 | |
<> | 149:156823d33999 | 118 | /*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/ |
<> | 149:156823d33999 | 119 | |
<> | 149:156823d33999 | 120 | /* Configure tx pin as UART */ |
<> | 149:156823d33999 | 121 | CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE)); |
<> | 149:156823d33999 | 122 | CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */ |
<> | 149:156823d33999 | 123 | |
<> | 149:156823d33999 | 124 | /* Configure rx pin as UART */ |
<> | 149:156823d33999 | 125 | CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE)); |
<> | 149:156823d33999 | 126 | CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */ |
<> | 149:156823d33999 | 127 | |
<> | 149:156823d33999 | 128 | /** - Set pad parameters, output drive strength, pull piece control, output drive type */ |
<> | 149:156823d33999 | 129 | PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE)); |
<> | 149:156823d33999 | 130 | PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */ |
<> | 149:156823d33999 | 131 | |
<> | 149:156823d33999 | 132 | PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE)); |
<> | 149:156823d33999 | 133 | PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */ |
<> | 149:156823d33999 | 134 | |
<> | 150:02e0a0aed4ec | 135 | GPIOREG->W_OUT = (0x1 << tx); /* tx as OUT direction */ |
<> | 150:02e0a0aed4ec | 136 | GPIOREG->W_IN = (0x1 << rx); /* rx as IN directon */ |
<> | 149:156823d33999 | 137 | |
<> | 149:156823d33999 | 138 | CLOCK_DISABLE(CLOCK_PAD); |
<> | 149:156823d33999 | 139 | CLOCK_DISABLE(CLOCK_CROSSB); |
<> | 149:156823d33999 | 140 | CLOCK_DISABLE(CLOCK_GPIO); |
<> | 149:156823d33999 | 141 | |
<> | 149:156823d33999 | 142 | /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers. |
<> | 149:156823d33999 | 143 | * The right-shift of 4 is a division of 16, representing the oversampling rate. */ |
<> | 149:156823d33999 | 144 | clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4; |
<> | 149:156823d33999 | 145 | obj->UARTREG->LCR.WORD = 0x80; |
<> | 149:156823d33999 | 146 | obj->UARTREG->DLL = clockDivisor & 0xFF; |
<> | 149:156823d33999 | 147 | obj->UARTREG->DLM = clockDivisor >> 8; |
<> | 149:156823d33999 | 148 | |
<> | 149:156823d33999 | 149 | /* Set the character width to 8 data bits, no parity, 1 stop bit. Write the entire line control register, |
<> | 149:156823d33999 | 150 | * effectively disabling the divisor latch. */ |
<> | 149:156823d33999 | 151 | obj->UARTREG->LCR.WORD = 0x03; |
<> | 149:156823d33999 | 152 | |
<> | 149:156823d33999 | 153 | /* Enable the FIFOs, reset the Tx and Rx FIFOs, set the Rx FIFO trigger level to 8 bytes, and set DMA Mode |
<> | 149:156823d33999 | 154 | to 1. */ |
<> | 149:156823d33999 | 155 | obj->UARTREG->FCR.WORD = (FCR_RXFIFOTRIGGERLEVEL_8 | FCR_DMA_MODE_1 | |
<> | 149:156823d33999 | 156 | FCR_TXFIFO_RESET | FCR_RXFIFO_RESET | FCR_FIFO_ENABLE); |
<> | 149:156823d33999 | 157 | |
<> | 149:156823d33999 | 158 | /* Make a copy of the current MSR to the SCR register. This is used from task space to determine the |
<> | 149:156823d33999 | 159 | * flow control state. */ |
<> | 149:156823d33999 | 160 | obj->UARTREG->SCR = obj->UARTREG->MSR.WORD; |
<> | 149:156823d33999 | 161 | |
<> | 149:156823d33999 | 162 | if((int)obj->UARTREG == STDIO_UART) { |
<> | 149:156823d33999 | 163 | stdio_uart_inited = 1; |
<> | 149:156823d33999 | 164 | memcpy(&stdio_uart, obj, sizeof(serial_t)); |
<> | 149:156823d33999 | 165 | } |
<> | 149:156823d33999 | 166 | |
<> | 149:156823d33999 | 167 | NVIC_ClearPendingIRQ(Irq); |
<> | 149:156823d33999 | 168 | |
<> | 149:156823d33999 | 169 | return; |
<> | 149:156823d33999 | 170 | } |
<> | 149:156823d33999 | 171 | |
<> | 149:156823d33999 | 172 | /** Closes a UART device. |
<> | 149:156823d33999 | 173 | * @details |
<> | 149:156823d33999 | 174 | * Disables the UART interrupt. |
<> | 149:156823d33999 | 175 | * |
<> | 149:156823d33999 | 176 | * @param device The UART device to close. |
<> | 149:156823d33999 | 177 | */ |
<> | 149:156823d33999 | 178 | void serial_free(serial_t *obj) |
<> | 149:156823d33999 | 179 | { |
<> | 149:156823d33999 | 180 | NVIC_DisableIRQ(obj->IRQType); |
<> | 149:156823d33999 | 181 | } |
<> | 149:156823d33999 | 182 | |
<> | 149:156823d33999 | 183 | void serial_baud(serial_t *obj, int baudrate) |
<> | 149:156823d33999 | 184 | { |
<> | 149:156823d33999 | 185 | /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers. |
<> | 149:156823d33999 | 186 | * The right-shift of 4 is a division of 16, representing the oversampling rate. */ |
<> | 149:156823d33999 | 187 | uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4; |
<> | 149:156823d33999 | 188 | |
<> | 149:156823d33999 | 189 | obj->UARTREG->LCR.BITS.DLAB = True; |
<> | 149:156823d33999 | 190 | obj->UARTREG->DLL = clockDivisor & 0xFF; |
<> | 149:156823d33999 | 191 | obj->UARTREG->DLM = clockDivisor >> 8; |
<> | 149:156823d33999 | 192 | obj->UARTREG->LCR.BITS.DLAB = False; |
<> | 149:156823d33999 | 193 | } |
<> | 149:156823d33999 | 194 | |
<> | 149:156823d33999 | 195 | /* |
<> | 149:156823d33999 | 196 | Parity XX0 â Parity disabled; 001 â Odd Parity; 011 â Even Parity; 101 â Stick Parity, checked as 1; 111 â Stick Parity, checked as 0. |
<> | 149:156823d33999 | 197 | StopBit 0 â 1 stop bit; 1 â 2 stop bits. |
<> | 149:156823d33999 | 198 | DataLen 00 â 5 bits; 01 â 6 bits; 10 â 7 bits; 11 â 8 bits |
<> | 149:156823d33999 | 199 | */ |
<> | 149:156823d33999 | 200 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) |
<> | 149:156823d33999 | 201 | { |
<> | 149:156823d33999 | 202 | if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) { |
<> | 149:156823d33999 | 203 | if(parity == (SerialParity)0) { |
<> | 149:156823d33999 | 204 | parity = (SerialParity)0; |
<> | 149:156823d33999 | 205 | } else { |
<> | 149:156823d33999 | 206 | parity = (SerialParity)(parity + parity - 1) ; |
<> | 149:156823d33999 | 207 | } |
<> | 149:156823d33999 | 208 | |
<> | 149:156823d33999 | 209 | obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) | |
<> | 149:156823d33999 | 210 | (parity << UART_LCR_PARITY_BIT_POS) | |
<> | 149:156823d33999 | 211 | ((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F); |
<> | 149:156823d33999 | 212 | } else { |
<> | 149:156823d33999 | 213 | MBED_ASSERT(False); |
<> | 149:156823d33999 | 214 | } |
<> | 149:156823d33999 | 215 | } |
<> | 149:156823d33999 | 216 | |
<> | 149:156823d33999 | 217 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) |
<> | 149:156823d33999 | 218 | { |
<> | 149:156823d33999 | 219 | irq_handler = handler; |
<> | 149:156823d33999 | 220 | serial_irq_ids[obj->index] = id; |
<> | 149:156823d33999 | 221 | } |
<> | 149:156823d33999 | 222 | |
<> | 149:156823d33999 | 223 | /****************************************************** |
<> | 149:156823d33999 | 224 | ************* Internal IRQ functions ****************** |
<> | 149:156823d33999 | 225 | *******************************************************/ |
<> | 149:156823d33999 | 226 | void Uart1_Irq() |
<> | 149:156823d33999 | 227 | { |
<> | 149:156823d33999 | 228 | uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF; |
<> | 149:156823d33999 | 229 | uint8_t irq_mask = 0; |
<> | 149:156823d33999 | 230 | |
<> | 149:156823d33999 | 231 | if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/ |
<> | 149:156823d33999 | 232 | irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK; |
<> | 149:156823d33999 | 233 | } |
<> | 149:156823d33999 | 234 | |
<> | 149:156823d33999 | 235 | if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/ |
<> | 149:156823d33999 | 236 | irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK; |
<> | 149:156823d33999 | 237 | } |
<> | 149:156823d33999 | 238 | |
<> | 149:156823d33999 | 239 | //uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0); |
<> | 149:156823d33999 | 240 | uart_irq(active_irq & irq_mask, 0); |
<> | 149:156823d33999 | 241 | } |
<> | 149:156823d33999 | 242 | |
<> | 149:156823d33999 | 243 | void Uart2_Irq() |
<> | 149:156823d33999 | 244 | { |
<> | 149:156823d33999 | 245 | uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF; |
<> | 149:156823d33999 | 246 | uint8_t irq_mask = 0; |
<> | 149:156823d33999 | 247 | |
<> | 149:156823d33999 | 248 | if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/ |
<> | 149:156823d33999 | 249 | irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK; |
<> | 149:156823d33999 | 250 | } |
<> | 149:156823d33999 | 251 | |
<> | 149:156823d33999 | 252 | if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/ |
<> | 149:156823d33999 | 253 | irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK; |
<> | 149:156823d33999 | 254 | } |
<> | 149:156823d33999 | 255 | |
<> | 149:156823d33999 | 256 | //uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1); |
<> | 149:156823d33999 | 257 | uart_irq(active_irq & irq_mask, 1); |
<> | 149:156823d33999 | 258 | |
<> | 149:156823d33999 | 259 | } |
<> | 149:156823d33999 | 260 | |
<> | 149:156823d33999 | 261 | static inline void uart_irq(uint8_t status, uint32_t index) |
<> | 149:156823d33999 | 262 | { |
<> | 149:156823d33999 | 263 | if (serial_irq_ids[index] != 0) { |
<> | 149:156823d33999 | 264 | if (status & UART_LSR_TX_EMPTY_MASK) { |
<> | 149:156823d33999 | 265 | irq_handler(serial_irq_ids[index], TxIrq); |
<> | 149:156823d33999 | 266 | } |
<> | 149:156823d33999 | 267 | if (status & UART_LSR_RX_DATA_READY_MASK) { |
<> | 149:156823d33999 | 268 | irq_handler(serial_irq_ids[index], RxIrq); |
<> | 149:156823d33999 | 269 | } |
<> | 149:156823d33999 | 270 | } |
<> | 149:156823d33999 | 271 | } |
<> | 149:156823d33999 | 272 | /******************************************************/ |
<> | 149:156823d33999 | 273 | |
<> | 149:156823d33999 | 274 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) |
<> | 149:156823d33999 | 275 | { |
<> | 149:156823d33999 | 276 | IRQn_Type irq_n = (IRQn_Type)0; |
<> | 149:156823d33999 | 277 | uint32_t Vector = 0; |
<> | 149:156823d33999 | 278 | |
<> | 149:156823d33999 | 279 | /* Check UART number & assign irq handler */ |
<> | 149:156823d33999 | 280 | if(obj->UARTREG == UART1REG) { |
<> | 149:156823d33999 | 281 | /* UART 2 */ |
<> | 149:156823d33999 | 282 | Vector = (uint32_t)&Uart1_Irq; |
<> | 149:156823d33999 | 283 | irq_n = Uart1_IRQn; |
<> | 149:156823d33999 | 284 | } else if(obj->UARTREG == UART2REG) { |
<> | 149:156823d33999 | 285 | /* UART 1 */ |
<> | 149:156823d33999 | 286 | Vector = (uint32_t)&Uart2_Irq; |
<> | 149:156823d33999 | 287 | irq_n = Uart2_IRQn; |
<> | 149:156823d33999 | 288 | } else { |
<> | 149:156823d33999 | 289 | MBED_ASSERT(False); |
<> | 149:156823d33999 | 290 | } |
<> | 149:156823d33999 | 291 | |
<> | 149:156823d33999 | 292 | /* Check IRQ type & enable/disable accordingly */ |
<> | 149:156823d33999 | 293 | if(enable) { |
<> | 149:156823d33999 | 294 | /* Enable */ |
<> | 149:156823d33999 | 295 | if(irq == RxIrq) { |
<> | 149:156823d33999 | 296 | /* Rx IRQ */ |
<> | 149:156823d33999 | 297 | obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0; |
<> | 149:156823d33999 | 298 | obj->UARTREG->IER.BITS.RX_DATA_INT = True; |
<> | 149:156823d33999 | 299 | } else if(irq == TxIrq) { |
<> | 149:156823d33999 | 300 | /* Tx IRQ */ |
<> | 149:156823d33999 | 301 | obj->UARTREG->IER.BITS.TX_HOLD_INT = True; |
<> | 149:156823d33999 | 302 | } else { |
<> | 149:156823d33999 | 303 | MBED_ASSERT(False); |
<> | 149:156823d33999 | 304 | } |
<> | 149:156823d33999 | 305 | NVIC_SetVector(irq_n, Vector); |
<> | 149:156823d33999 | 306 | NVIC_EnableIRQ(irq_n); |
<> | 149:156823d33999 | 307 | } else { |
<> | 149:156823d33999 | 308 | /* Disable */ |
<> | 149:156823d33999 | 309 | NVIC_DisableIRQ(irq_n); |
<> | 149:156823d33999 | 310 | if(irq == RxIrq) { |
<> | 149:156823d33999 | 311 | /* Rx IRQ */ |
<> | 149:156823d33999 | 312 | obj->UARTREG->IER.BITS.RX_DATA_INT = False; |
<> | 149:156823d33999 | 313 | } else if(irq == TxIrq) { |
<> | 149:156823d33999 | 314 | /* Tx IRQ */ |
<> | 149:156823d33999 | 315 | |
<> | 149:156823d33999 | 316 | obj->UARTREG->IER.BITS.TX_HOLD_INT = False; |
<> | 149:156823d33999 | 317 | } else { |
<> | 149:156823d33999 | 318 | MBED_ASSERT(False); |
<> | 149:156823d33999 | 319 | } |
<> | 149:156823d33999 | 320 | } |
<> | 149:156823d33999 | 321 | } |
<> | 149:156823d33999 | 322 | |
<> | 149:156823d33999 | 323 | int serial_getc(serial_t *obj) |
<> | 149:156823d33999 | 324 | { |
<> | 149:156823d33999 | 325 | uint8_t c; |
<> | 149:156823d33999 | 326 | |
<> | 149:156823d33999 | 327 | while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */ |
<> | 149:156823d33999 | 328 | c = obj->UARTREG->RBR & 0xFF; /* Get received character */ |
<> | 149:156823d33999 | 329 | return c; |
<> | 149:156823d33999 | 330 | } |
<> | 149:156823d33999 | 331 | |
<> | 149:156823d33999 | 332 | void serial_putc(serial_t *obj, int c) |
<> | 149:156823d33999 | 333 | { |
<> | 149:156823d33999 | 334 | |
<> | 149:156823d33999 | 335 | while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */ |
<> | 149:156823d33999 | 336 | obj->UARTREG->THR = c; /* Transmit byte */ |
<> | 149:156823d33999 | 337 | |
<> | 149:156823d33999 | 338 | } |
<> | 149:156823d33999 | 339 | |
<> | 149:156823d33999 | 340 | int serial_readable(serial_t *obj) |
<> | 149:156823d33999 | 341 | { |
<> | 149:156823d33999 | 342 | return obj->UARTREG->LSR.BITS.READY; |
<> | 149:156823d33999 | 343 | } |
<> | 149:156823d33999 | 344 | |
<> | 149:156823d33999 | 345 | int serial_writable(serial_t *obj) |
<> | 149:156823d33999 | 346 | { |
<> | 149:156823d33999 | 347 | return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY; |
<> | 149:156823d33999 | 348 | } |
<> | 149:156823d33999 | 349 | |
<> | 149:156823d33999 | 350 | void serial_clear(serial_t *obj) |
<> | 149:156823d33999 | 351 | { |
<> | 149:156823d33999 | 352 | /* Reset TX & RX FIFO */ |
<> | 149:156823d33999 | 353 | obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) | |
<> | 149:156823d33999 | 354 | (True << UART_FCS_RX_FIFO_RST_BIT_POS)); |
<> | 149:156823d33999 | 355 | } |
<> | 149:156823d33999 | 356 | |
<> | 149:156823d33999 | 357 | void serial_break_set(serial_t *obj) |
<> | 149:156823d33999 | 358 | { |
<> | 149:156823d33999 | 359 | obj->UARTREG->LCR.BITS.BREAK = True; |
<> | 149:156823d33999 | 360 | } |
<> | 149:156823d33999 | 361 | |
<> | 149:156823d33999 | 362 | void serial_break_clear(serial_t *obj) |
<> | 149:156823d33999 | 363 | { |
<> | 149:156823d33999 | 364 | obj->UARTREG->LCR.BITS.BREAK = False; |
<> | 149:156823d33999 | 365 | } |
<> | 149:156823d33999 | 366 | |
<> | 149:156823d33999 | 367 | void serial_pinout_tx(PinName tx) |
<> | 149:156823d33999 | 368 | { |
<> | 149:156823d33999 | 369 | /* COnfigure PinNo to drive strength of 1, Push pull and pull none */ |
<> | 149:156823d33999 | 370 | fPadIOCtrl(tx, 1, 0, 1); |
<> | 149:156823d33999 | 371 | } |
<> | 149:156823d33999 | 372 | |
<> | 149:156823d33999 | 373 | /** Configure the serial for the flow control. It sets flow control in the hardware |
<> | 149:156823d33999 | 374 | * if a serial peripheral supports it, otherwise software emulation is used. |
<> | 149:156823d33999 | 375 | * |
<> | 149:156823d33999 | 376 | * @param obj The serial object |
<> | 149:156823d33999 | 377 | * @param type The type of the flow control. Look at the available FlowControl types. |
<> | 149:156823d33999 | 378 | * @param rxflow The TX pin name |
<> | 149:156823d33999 | 379 | * @param txflow The RX pin name |
<> | 149:156823d33999 | 380 | */ |
<> | 149:156823d33999 | 381 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) |
<> | 149:156823d33999 | 382 | { |
<> | 149:156823d33999 | 383 | /* TODO: This is an empty implementation for now.*/ |
<> | 149:156823d33999 | 384 | } |
<> | 149:156823d33999 | 385 | |
<> | 149:156823d33999 | 386 | #endif /* DEVICE_SERIAL */ |