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targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 153:fa9ff456f731
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | *************************************************************************** |
<> | 149:156823d33999 | 3 | * @file ncs36510_init.c |
<> | 149:156823d33999 | 4 | * @brief Initialization of Orion SoC |
<> | 149:156823d33999 | 5 | * @internal |
<> | 149:156823d33999 | 6 | * @author ON Semiconductor |
<> | 149:156823d33999 | 7 | * $Rev: |
<> | 149:156823d33999 | 8 | * $Date: $ |
<> | 149:156823d33999 | 9 | ****************************************************************************** |
<> | 149:156823d33999 | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
<> | 149:156823d33999 | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
<> | 149:156823d33999 | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
<> | 149:156823d33999 | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
<> | 149:156823d33999 | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
<> | 149:156823d33999 | 15 | * if applicable the software license agreement. Do not use this software and/or |
<> | 149:156823d33999 | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
<> | 149:156823d33999 | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
<> | 149:156823d33999 | 18 | * terms and conditions. |
<> | 149:156823d33999 | 19 | * |
<> | 149:156823d33999 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 149:156823d33999 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 149:156823d33999 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 149:156823d33999 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
<> | 149:156823d33999 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 149:156823d33999 | 25 | * @endinternal |
<> | 149:156823d33999 | 26 | * |
<> | 149:156823d33999 | 27 | * @ingroup main |
<> | 149:156823d33999 | 28 | * |
<> | 149:156823d33999 | 29 | * @details |
<> | 149:156823d33999 | 30 | */ |
<> | 149:156823d33999 | 31 | |
<> | 149:156823d33999 | 32 | /************************************************************************************************* |
<> | 149:156823d33999 | 33 | * * |
<> | 149:156823d33999 | 34 | * Header files * |
<> | 149:156823d33999 | 35 | * * |
<> | 149:156823d33999 | 36 | *************************************************************************************************/ |
<> | 149:156823d33999 | 37 | #include "ncs36510Init.h" |
<> | 149:156823d33999 | 38 | |
<> | 149:156823d33999 | 39 | void fPmuInit(void); |
<> | 153:fa9ff456f731 | 40 | |
<> | 149:156823d33999 | 41 | /** |
<> | 149:156823d33999 | 42 | * @brief |
<> | 149:156823d33999 | 43 | * Hardware trimming function |
<> | 149:156823d33999 | 44 | * This function copies trim codes from specific flash location |
<> | 149:156823d33999 | 45 | * where they are stored to proper hw registers. |
<> | 149:156823d33999 | 46 | */ |
<> | 149:156823d33999 | 47 | boolean fTrim() |
<> | 149:156823d33999 | 48 | { |
<> | 151:5eaa88a5bcc7 | 49 | boolean status = False; |
<> | 149:156823d33999 | 50 | |
<> | 149:156823d33999 | 51 | /**- Check if trim values are present */ |
<> | 149:156823d33999 | 52 | /**- If Trim data is present. Only trim if valid trim values are present. */ |
<> | 149:156823d33999 | 53 | /**- Copy trims in registers */ |
<> | 149:156823d33999 | 54 | if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) { |
<> | 149:156823d33999 | 55 | |
<> | 151:5eaa88a5bcc7 | 56 | if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) { |
<> | 151:5eaa88a5bcc7 | 57 | MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW; |
<> | 151:5eaa88a5bcc7 | 58 | } |
<> | 151:5eaa88a5bcc7 | 59 | |
<> | 151:5eaa88a5bcc7 | 60 | if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) { |
<> | 151:5eaa88a5bcc7 | 61 | MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH; |
<> | 151:5eaa88a5bcc7 | 62 | } |
<> | 151:5eaa88a5bcc7 | 63 | |
<> | 149:156823d33999 | 64 | /**- board specific clock trims may only be done when present, writing all 1's is not good */ |
<> | 149:156823d33999 | 65 | if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) { |
<> | 151:5eaa88a5bcc7 | 66 | CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT; |
<> | 149:156823d33999 | 67 | } |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) { |
<> | 151:5eaa88a5bcc7 | 70 | CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT; |
<> | 149:156823d33999 | 71 | } |
<> | 149:156823d33999 | 72 | |
<> | 149:156823d33999 | 73 | MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS; |
<> | 149:156823d33999 | 74 | |
<> | 151:5eaa88a5bcc7 | 75 | if ((TRIMREG->TX_TRIM & 0xFFFF0000) != 0xFFFF0000) { |
<> | 151:5eaa88a5bcc7 | 76 | RFANATRIMREG->TX_TRIM.WORD = TRIMREG->TX_TRIM; |
<> | 151:5eaa88a5bcc7 | 77 | } |
<> | 149:156823d33999 | 78 | RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION; |
<> | 149:156823d33999 | 79 | RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM; |
<> | 149:156823d33999 | 80 | |
<> | 149:156823d33999 | 81 | /**- board specific RSSI trims may only be done when present, writing all 1's is not good */ |
<> | 149:156823d33999 | 82 | if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) { |
<> | 149:156823d33999 | 83 | DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET; |
<> | 149:156823d33999 | 84 | } |
<> | 149:156823d33999 | 85 | |
<> | 149:156823d33999 | 86 | RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM; |
<> | 149:156823d33999 | 87 | RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM; |
<> | 149:156823d33999 | 88 | RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND; |
<> | 149:156823d33999 | 89 | |
<> | 151:5eaa88a5bcc7 | 90 | /* High side injection settings */ |
<> | 149:156823d33999 | 91 | RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;; |
<> | 149:156823d33999 | 92 | RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;; |
<> | 149:156823d33999 | 93 | |
<> | 149:156823d33999 | 94 | RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;; |
<> | 149:156823d33999 | 95 | RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;; |
<> | 149:156823d33999 | 96 | |
<> | 151:5eaa88a5bcc7 | 97 | status = True; |
<> | 151:5eaa88a5bcc7 | 98 | |
<> | 151:5eaa88a5bcc7 | 99 | } else { |
<> | 151:5eaa88a5bcc7 | 100 | |
<> | 151:5eaa88a5bcc7 | 101 | return(False); |
<> | 151:5eaa88a5bcc7 | 102 | } |
<> | 151:5eaa88a5bcc7 | 103 | |
<> | 151:5eaa88a5bcc7 | 104 | /** Read in user trim values programmed in the flash memory |
<> | 151:5eaa88a5bcc7 | 105 | The user trim values take precedence over factory trim for MAC address |
<> | 151:5eaa88a5bcc7 | 106 | */ |
<> | 151:5eaa88a5bcc7 | 107 | if (( USERTRIMREG->MAC_ADDRESS_LOW != 0xFFFFFFFF ) && |
<> | 151:5eaa88a5bcc7 | 108 | (USERTRIMREG->MAC_ADDRESS_HIGH != 0xFFFFFFFF)) { |
<> | 150:02e0a0aed4ec | 109 | |
<> | 151:5eaa88a5bcc7 | 110 | MACHWREG->LONG_ADDRESS_LOW = USERTRIMREG->MAC_ADDRESS_LOW; |
<> | 151:5eaa88a5bcc7 | 111 | MACHWREG->LONG_ADDRESS_HIGH = USERTRIMREG->MAC_ADDRESS_HIGH; |
<> | 151:5eaa88a5bcc7 | 112 | } |
<> | 151:5eaa88a5bcc7 | 113 | |
<> | 151:5eaa88a5bcc7 | 114 | if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) { |
<> | 151:5eaa88a5bcc7 | 115 | CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF); |
<> | 151:5eaa88a5bcc7 | 116 | } |
<> | 149:156823d33999 | 117 | |
<> | 151:5eaa88a5bcc7 | 118 | if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) { |
<> | 151:5eaa88a5bcc7 | 119 | CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF); |
<> | 149:156823d33999 | 120 | } |
<> | 151:5eaa88a5bcc7 | 121 | |
<> | 151:5eaa88a5bcc7 | 122 | if (USERTRIMREG->RSSI_OFFSET != 0xFFFFFFFF) { |
<> | 151:5eaa88a5bcc7 | 123 | DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = (USERTRIMREG->RSSI_OFFSET & 0x0000003F); |
<> | 151:5eaa88a5bcc7 | 124 | } |
<> | 151:5eaa88a5bcc7 | 125 | |
<> | 151:5eaa88a5bcc7 | 126 | if (USERTRIMREG->TX_TRIM != 0xFFFFFFFF) { |
<> | 151:5eaa88a5bcc7 | 127 | RFANATRIMREG->TX_TRIM.BITS.TX_TUNE = (USERTRIMREG->TX_TRIM & 0x0000000F); |
<> | 151:5eaa88a5bcc7 | 128 | } |
<> | 151:5eaa88a5bcc7 | 129 | return(status); |
<> | 149:156823d33999 | 130 | } |
<> | 149:156823d33999 | 131 | |
<> | 149:156823d33999 | 132 | /* See clock.h for documentation. */ |
<> | 149:156823d33999 | 133 | void fClockInit() |
<> | 149:156823d33999 | 134 | { |
<> | 149:156823d33999 | 135 | |
<> | 149:156823d33999 | 136 | /** Enable external 32MHz oscillator */ |
<> | 149:156823d33999 | 137 | CLOCKREG->CCR.BITS.OSC_SEL = 1; |
<> | 149:156823d33999 | 138 | |
<> | 149:156823d33999 | 139 | /** - Wait external 32MHz oscillator to be ready */ |
<> | 149:156823d33999 | 140 | while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */ |
<> | 149:156823d33999 | 141 | |
<> | 149:156823d33999 | 142 | /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */ |
<> | 149:156823d33999 | 143 | PMUREG->CONTROL.BITS.INT32M = 0; |
<> | 149:156823d33999 | 144 | |
<> | 149:156823d33999 | 145 | /** - Wait 5 uSec for clock to stabilize */ |
<> | 149:156823d33999 | 146 | volatile uint8_t Timer; |
<> | 149:156823d33999 | 147 | for(Timer = 0; Timer < 10; Timer++); |
<> | 149:156823d33999 | 148 | |
<> | 149:156823d33999 | 149 | /** - Enable calibration */ |
<> | 149:156823d33999 | 150 | CLOCKREG->CCR.BITS.CAL32M = True; |
<> | 149:156823d33999 | 151 | |
<> | 149:156823d33999 | 152 | /** - Wait calibration to be completed */ |
<> | 149:156823d33999 | 153 | while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */ |
<> | 149:156823d33999 | 154 | |
<> | 149:156823d33999 | 155 | /** - Check calibration status */ |
<> | 149:156823d33999 | 156 | while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */ |
<> | 149:156823d33999 | 157 | |
<> | 149:156823d33999 | 158 | /** - Power down internal 32MHz osc */ |
<> | 149:156823d33999 | 159 | PMUREG->CONTROL.BITS.INT32M = 1; |
<> | 149:156823d33999 | 160 | |
<> | 149:156823d33999 | 161 | /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */ |
<> | 149:156823d33999 | 162 | PMUREG->CONTROL.BITS.INT32K = 0; |
<> | 149:156823d33999 | 163 | |
<> | 149:156823d33999 | 164 | /** - Wait 5 uSec for clock to stabilize */ |
<> | 149:156823d33999 | 165 | for(Timer = 0; Timer < 10; Timer++); |
<> | 149:156823d33999 | 166 | |
<> | 149:156823d33999 | 167 | /** - Enable calibration */ |
<> | 149:156823d33999 | 168 | CLOCKREG->CCR.BITS.CAL32K = True; |
<> | 149:156823d33999 | 169 | |
<> | 149:156823d33999 | 170 | /** - Wait calibration to be completed */ |
<> | 149:156823d33999 | 171 | while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */ |
<> | 149:156823d33999 | 172 | |
<> | 149:156823d33999 | 173 | /** - Check calibration status */ |
<> | 149:156823d33999 | 174 | while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */ |
<> | 149:156823d33999 | 175 | |
<> | 149:156823d33999 | 176 | /** - Power down external 32KHz osc */ |
<> | 149:156823d33999 | 177 | PMUREG->CONTROL.BITS.EXT32K = 1; |
<> | 149:156823d33999 | 178 | |
<> | 149:156823d33999 | 179 | /** Disable all peripheral clocks by default */ |
<> | 149:156823d33999 | 180 | CLOCKREG->PDIS.WORD = 0xFFFFFFFF; |
<> | 149:156823d33999 | 181 | |
<> | 149:156823d33999 | 182 | /** Set core frequency */ |
<> | 149:156823d33999 | 183 | CLOCKREG->FDIV = CPU_CLOCK_DIV - 1; |
<> | 149:156823d33999 | 184 | } |
<> | 149:156823d33999 | 185 | |
<> | 149:156823d33999 | 186 | /* Initializes PMU module */ |
<> | 149:156823d33999 | 187 | void fPmuInit() |
<> | 149:156823d33999 | 188 | { |
<> | 149:156823d33999 | 189 | /** Enable the clock for PMU peripheral device */ |
<> | 149:156823d33999 | 190 | CLOCK_ENABLE(CLOCK_PMU); |
<> | 149:156823d33999 | 191 | |
<> | 149:156823d33999 | 192 | /** Unset wakeup on pending (only enabled irq can wakeup) */ |
<> | 149:156823d33999 | 193 | SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk; |
<> | 149:156823d33999 | 194 | |
<> | 149:156823d33999 | 195 | /** Unset auto sleep when returning from wakeup irq */ |
<> | 149:156823d33999 | 196 | SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; |
<> | 149:156823d33999 | 197 | |
<> | 149:156823d33999 | 198 | /** Set regulator timings */ |
<> | 150:02e0a0aed4ec | 199 | PMUREG->FVDD_TSETTLE = 160; |
<> | 150:02e0a0aed4ec | 200 | PMUREG->FVDD_TSTARTUP = 400; |
<> | 150:02e0a0aed4ec | 201 | |
<> | 149:156823d33999 | 202 | |
<> | 149:156823d33999 | 203 | /** Keep SRAMA & SRAMB powered in coma mode */ |
<> | 149:156823d33999 | 204 | PMUREG->CONTROL.BITS.SRAMA = False; |
<> | 149:156823d33999 | 205 | PMUREG->CONTROL.BITS.SRAMB = False; |
<> | 149:156823d33999 | 206 | |
<> | 150:02e0a0aed4ec | 207 | PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */ |
<> | 150:02e0a0aed4ec | 208 | PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */ |
<> | 149:156823d33999 | 209 | |
<> | 149:156823d33999 | 210 | /** Disable the clock for PMU peripheral device, all settings are done */ |
<> | 149:156823d33999 | 211 | CLOCK_DISABLE(CLOCK_PMU); |
<> | 149:156823d33999 | 212 | } |
<> | 149:156823d33999 | 213 | |
<> | 149:156823d33999 | 214 | /* See clock.h for documentation. */ |
<> | 149:156823d33999 | 215 | uint32_t fClockGetPeriphClockfrequency() |
<> | 149:156823d33999 | 216 | { |
<> | 149:156823d33999 | 217 | return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV); |
<> | 149:156823d33999 | 218 | } |
<> | 149:156823d33999 | 219 | |
<> | 149:156823d33999 | 220 | |
<> | 149:156823d33999 | 221 | /** |
<> | 149:156823d33999 | 222 | * @brief |
<> | 149:156823d33999 | 223 | * Hardware initialization function |
<> | 149:156823d33999 | 224 | * This function initializes hardware at application start up prior |
<> | 149:156823d33999 | 225 | * to other initializations or OS operations. |
<> | 149:156823d33999 | 226 | */ |
<> | 149:156823d33999 | 227 | static void fHwInit(void) |
<> | 149:156823d33999 | 228 | { |
<> | 149:156823d33999 | 229 | |
<> | 149:156823d33999 | 230 | /* Trim register settings */ |
<> | 149:156823d33999 | 231 | fTrim(); |
<> | 149:156823d33999 | 232 | |
<> | 149:156823d33999 | 233 | /* Clock setting */ |
<> | 149:156823d33999 | 234 | /** - Initialize clock */ |
<> | 149:156823d33999 | 235 | fClockInit(); |
<> | 149:156823d33999 | 236 | |
<> | 149:156823d33999 | 237 | /** - Initialize pmu */ |
<> | 149:156823d33999 | 238 | fPmuInit(); |
<> | 149:156823d33999 | 239 | |
<> | 149:156823d33999 | 240 | /** Orion has 4 interrupt bits in interrupt priority register |
<> | 149:156823d33999 | 241 | * The lowest 4 bits are not used. |
<> | 149:156823d33999 | 242 | * |
<> | 149:156823d33999 | 243 | @verbatim |
<> | 149:156823d33999 | 244 | +-----+-----+-----+-----+-----+-----+-----+-----+ |
<> | 149:156823d33999 | 245 | |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0| |
<> | 149:156823d33999 | 246 | | | | | | 0 | 0 | 0 | 0 | |
<> | 149:156823d33999 | 247 | +-----+-----+-----+-----+-----+-----+-----+-----+ |
<> | 149:156823d33999 | 248 | | |
<> | 149:156823d33999 | 249 | INTERRUPT PRIORITY | NOT IMPLEMENTED, |
<> | 149:156823d33999 | 250 | | read as 0 |
<> | 149:156823d33999 | 251 | Valid priorities are 0x00, 0x10, 0x20, 0x30 |
<> | 149:156823d33999 | 252 | 0x40, 0x50, 0x60, 0x70 |
<> | 149:156823d33999 | 253 | 0x80, 0x90, 0xA0, 0xB0 |
<> | 149:156823d33999 | 254 | 0xC0, 0xD0, 0xE0, 0xF0 |
<> | 149:156823d33999 | 255 | @endverbatim |
<> | 149:156823d33999 | 256 | * Lowest number is highest priority |
<> | 149:156823d33999 | 257 | * |
<> | 149:156823d33999 | 258 | * |
<> | 149:156823d33999 | 259 | * This range is defined by |
<> | 149:156823d33999 | 260 | * configKERNEL_INTERRUPT_PRIORITY (lowest) |
<> | 149:156823d33999 | 261 | * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt |
<> | 149:156823d33999 | 262 | * priorities need to fall in that range. |
<> | 149:156823d33999 | 263 | * |
<> | 149:156823d33999 | 264 | * To be future safe, the LSbits of the priority are set to 0xF. |
<> | 149:156823d33999 | 265 | * This wil lmake sure that if more interrupt bits are used, the |
<> | 149:156823d33999 | 266 | * priority is maintained. |
<> | 149:156823d33999 | 267 | */ |
<> | 149:156823d33999 | 268 | |
<> | 149:156823d33999 | 269 | /** - Set IRQs priorities */ |
<> | 149:156823d33999 | 270 | NVIC_SetPriority(Tim0_IRQn, 14); |
<> | 149:156823d33999 | 271 | NVIC_SetPriority(Tim1_IRQn, 14); |
<> | 149:156823d33999 | 272 | NVIC_SetPriority(Tim2_IRQn, 14); |
<> | 149:156823d33999 | 273 | NVIC_SetPriority(Uart1_IRQn,14); |
<> | 149:156823d33999 | 274 | NVIC_SetPriority(Spi_IRQn, 14); |
<> | 149:156823d33999 | 275 | NVIC_SetPriority(I2C_IRQn, 14); |
<> | 149:156823d33999 | 276 | NVIC_SetPriority(Gpio_IRQn, 14); |
<> | 149:156823d33999 | 277 | NVIC_SetPriority(Rtc_IRQn, 14); |
<> | 149:156823d33999 | 278 | NVIC_SetPriority(MacHw_IRQn, 13); |
<> | 149:156823d33999 | 279 | NVIC_SetPriority(Aes_IRQn, 13); |
<> | 149:156823d33999 | 280 | NVIC_SetPriority(Adc_IRQn, 14); |
<> | 149:156823d33999 | 281 | NVIC_SetPriority(ClockCal_IRQn, 14); |
<> | 149:156823d33999 | 282 | NVIC_SetPriority(Uart2_IRQn, 14); |
<> | 149:156823d33999 | 283 | NVIC_SetPriority(Dma_IRQn, 14); |
<> | 149:156823d33999 | 284 | NVIC_SetPriority(Uvi_IRQn, 14); |
<> | 149:156823d33999 | 285 | NVIC_SetPriority(DbgPwrUp_IRQn, 14); |
<> | 149:156823d33999 | 286 | NVIC_SetPriority(Spi2_IRQn, 14); |
<> | 149:156823d33999 | 287 | NVIC_SetPriority(I2C2_IRQn, 14); |
<> | 149:156823d33999 | 288 | } |
<> | 149:156823d33999 | 289 | |
<> | 149:156823d33999 | 290 | extern void __Vectors; |
<> | 149:156823d33999 | 291 | |
<> | 149:156823d33999 | 292 | void fNcs36510Init(void) |
<> | 149:156823d33999 | 293 | { |
<> | 149:156823d33999 | 294 | /** Setting this register is helping to debug imprecise bus access faults |
<> | 149:156823d33999 | 295 | * making them precise bus access faults. It has an impact on application |
<> | 149:156823d33999 | 296 | * performance. */ |
<> | 149:156823d33999 | 297 | // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk; |
<> | 149:156823d33999 | 298 | |
<> | 149:156823d33999 | 299 | /** This main function implements: */ |
<> | 149:156823d33999 | 300 | /**- Disable all interrupts */ |
<> | 149:156823d33999 | 301 | NVIC->ICER[0] = 0x1F; |
<> | 149:156823d33999 | 302 | |
<> | 149:156823d33999 | 303 | /**- Clear all Pending interrupts */ |
<> | 149:156823d33999 | 304 | NVIC->ICPR[0] = 0x1F; |
<> | 149:156823d33999 | 305 | |
<> | 149:156823d33999 | 306 | /**- Clear all pending SV and systick */ |
<> | 149:156823d33999 | 307 | SCB->ICSR = (uint32_t)0x0A000000; |
<> | 149:156823d33999 | 308 | SCB->VTOR = (uint32_t) (&__Vectors); |
<> | 149:156823d33999 | 309 | |
<> | 149:156823d33999 | 310 | /**- Initialize hardware */ |
<> | 149:156823d33999 | 311 | fHwInit(); |
<> | 149:156823d33999 | 312 | } |