Amit Gandhi / sensen_copy_2

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targets/TARGET_Maxim/TARGET_MAX32625/mxc/lp.c@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 * $Date: 2016-05-06 14:27:28 -0500 (Fri, 06 May 2016) $
<> 150:02e0a0aed4ec 33 * $Revision: 22742 $
<> 150:02e0a0aed4ec 34 * ******************************************************************************/
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 /***** Includes *****/
<> 150:02e0a0aed4ec 37 #include "mxc_config.h"
<> 150:02e0a0aed4ec 38 #include "mxc_assert.h"
<> 150:02e0a0aed4ec 39 #include "lp.h"
<> 150:02e0a0aed4ec 40 #include "ioman_regs.h"
<> 150:02e0a0aed4ec 41
<> 150:02e0a0aed4ec 42 /***** Definitions *****/
<> 150:02e0a0aed4ec 43
<> 150:02e0a0aed4ec 44 #ifndef LP0_PRE_HOOK
<> 150:02e0a0aed4ec 45 #define LP0_PRE_HOOK
<> 150:02e0a0aed4ec 46 #endif
<> 150:02e0a0aed4ec 47 #ifndef LP1_PRE_HOOK
<> 150:02e0a0aed4ec 48 #define LP1_PRE_HOOK
<> 150:02e0a0aed4ec 49 #endif
<> 150:02e0a0aed4ec 50 #ifndef LP1_POST_HOOK
<> 150:02e0a0aed4ec 51 #define LP1_POST_HOOK
<> 150:02e0a0aed4ec 52 #endif
<> 150:02e0a0aed4ec 53
<> 150:02e0a0aed4ec 54 /***** Globals *****/
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56 /***** Functions *****/
<> 150:02e0a0aed4ec 57
<> 150:02e0a0aed4ec 58 /* Clear all wake-up configuration */
<> 150:02e0a0aed4ec 59 void LP_ClearWakeUpConfig(void)
<> 150:02e0a0aed4ec 60 {
<> 150:02e0a0aed4ec 61 /* Clear GPIO WUD event and configuration registers, globally */
<> 150:02e0a0aed4ec 62 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
<> 150:02e0a0aed4ec 63 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 150:02e0a0aed4ec 64 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
<> 150:02e0a0aed4ec 65 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 /* Mask off all wake-up sources */
<> 150:02e0a0aed4ec 68 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP |
<> 150:02e0a0aed4ec 69 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
<> 150:02e0a0aed4ec 70 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP |
<> 150:02e0a0aed4ec 71 MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 |
<> 150:02e0a0aed4ec 72 MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
<> 150:02e0a0aed4ec 73 MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP |
<> 150:02e0a0aed4ec 74 MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER);
<> 150:02e0a0aed4ec 75 }
<> 150:02e0a0aed4ec 76
<> 150:02e0a0aed4ec 77 /* Clear wake-up flags */
<> 150:02e0a0aed4ec 78 unsigned int LP_ClearWakeUpFlags(void)
<> 150:02e0a0aed4ec 79 {
<> 150:02e0a0aed4ec 80 unsigned int flags_tmp;
<> 150:02e0a0aed4ec 81
<> 150:02e0a0aed4ec 82 /* Get flags */
<> 150:02e0a0aed4ec 83 flags_tmp = MXC_PWRSEQ->flags;
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 /* Clear GPIO WUD event registers, globally */
<> 150:02e0a0aed4ec 86 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
<> 150:02e0a0aed4ec 87 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
<> 150:02e0a0aed4ec 88
<> 150:02e0a0aed4ec 89 /* Clear power sequencer event flags (write-1-to-clear) */
<> 150:02e0a0aed4ec 90 MXC_PWRSEQ->flags = flags_tmp;
<> 150:02e0a0aed4ec 91
<> 150:02e0a0aed4ec 92 return flags_tmp;
<> 150:02e0a0aed4ec 93 }
<> 150:02e0a0aed4ec 94
<> 150:02e0a0aed4ec 95 /* Configure the selected pin for wake-up detect */
<> 150:02e0a0aed4ec 96 int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd)
<> 150:02e0a0aed4ec 97 {
<> 150:02e0a0aed4ec 98 int result = E_NO_ERROR;
<> 150:02e0a0aed4ec 99 unsigned int pin;
<> 150:02e0a0aed4ec 100
<> 150:02e0a0aed4ec 101 /* Check that port and pin are within range */
<> 150:02e0a0aed4ec 102 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
<> 150:02e0a0aed4ec 103 MXC_ASSERT(gpio->mask > 0);
<> 150:02e0a0aed4ec 104
<> 150:02e0a0aed4ec 105 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */
<> 150:02e0a0aed4ec 106 if (gpio->port < 4) {
<> 150:02e0a0aed4ec 107 MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
<> 150:02e0a0aed4ec 108 if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
<> 150:02e0a0aed4ec 109 result = E_BUSY;
<> 150:02e0a0aed4ec 110 }
<> 150:02e0a0aed4ec 111 } else if (gpio->port < 8) {
<> 150:02e0a0aed4ec 112 MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
<> 150:02e0a0aed4ec 113 if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
<> 150:02e0a0aed4ec 114 result = E_BUSY;
<> 150:02e0a0aed4ec 115 }
<> 150:02e0a0aed4ec 116 } else {
<> 150:02e0a0aed4ec 117 return E_NOT_SUPPORTED;
<> 150:02e0a0aed4ec 118 }
<> 150:02e0a0aed4ec 119
<> 150:02e0a0aed4ec 120 if (result == E_NO_ERROR) {
<> 150:02e0a0aed4ec 121
<> 150:02e0a0aed4ec 122 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 150:02e0a0aed4ec 123
<> 150:02e0a0aed4ec 124 if (gpio->mask & (1 << pin)) {
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 /* Enable modifications to WUD configuration */
<> 150:02e0a0aed4ec 127 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 /* Select pad in WUD control */
<> 150:02e0a0aed4ec 130 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 150:02e0a0aed4ec 131 MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133 /* Configure sense level on this pad */
<> 150:02e0a0aed4ec 134 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 if (act_high) {
<> 150:02e0a0aed4ec 137 /* Select active high with PULSE0 (backwards from what you'd expect) */
<> 150:02e0a0aed4ec 138 MXC_PWRMAN->wud_pulse0 = 1;
<> 150:02e0a0aed4ec 139 } else {
<> 150:02e0a0aed4ec 140 /* Select active low with PULSE1 (backwards from what you'd expect) */
<> 150:02e0a0aed4ec 141 MXC_PWRMAN->wud_pulse1 = 1;
<> 150:02e0a0aed4ec 142 }
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 /* Clear out the pad mode */
<> 150:02e0a0aed4ec 145 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 150:02e0a0aed4ec 146
<> 150:02e0a0aed4ec 147 /* Select this pad to have the wake-up function enabled */
<> 150:02e0a0aed4ec 148 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 150:02e0a0aed4ec 149
<> 150:02e0a0aed4ec 150 /* Activate with PULSE1 */
<> 150:02e0a0aed4ec 151 MXC_PWRMAN->wud_pulse1 = 1;
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 if (wk_pu_pd != LP_NO_PULL) {
<> 150:02e0a0aed4ec 154 /* Select weak pull-up/pull-down on this pad while in LP1 */
<> 150:02e0a0aed4ec 155 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 150:02e0a0aed4ec 156
<> 150:02e0a0aed4ec 157 /* Again, logic is opposite of what you'd expect */
<> 150:02e0a0aed4ec 158 if (wk_pu_pd == LP_WEAK_PULL_UP) {
<> 150:02e0a0aed4ec 159 MXC_PWRMAN->wud_pulse0 = 1;
<> 150:02e0a0aed4ec 160 } else {
<> 150:02e0a0aed4ec 161 MXC_PWRMAN->wud_pulse1 = 1;
<> 150:02e0a0aed4ec 162 }
<> 150:02e0a0aed4ec 163 }
<> 150:02e0a0aed4ec 164
<> 150:02e0a0aed4ec 165 /* Disable configuration each time, required by hardware */
<> 150:02e0a0aed4ec 166 MXC_PWRMAN->wud_ctrl = 0;
<> 150:02e0a0aed4ec 167 }
<> 150:02e0a0aed4ec 168 }
<> 150:02e0a0aed4ec 169 }
<> 150:02e0a0aed4ec 170
<> 150:02e0a0aed4ec 171 /* Disable configuration */
<> 150:02e0a0aed4ec 172 MXC_IOMAN->wud_req0 = 0;
<> 150:02e0a0aed4ec 173 MXC_IOMAN->wud_req1 = 0;
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
<> 150:02e0a0aed4ec 176 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
<> 150:02e0a0aed4ec 177
<> 150:02e0a0aed4ec 178 return result;
<> 150:02e0a0aed4ec 179 }
<> 150:02e0a0aed4ec 180
<> 150:02e0a0aed4ec 181 uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
<> 150:02e0a0aed4ec 182 {
<> 150:02e0a0aed4ec 183 uint8_t gpioWokeUp = 0;
<> 150:02e0a0aed4ec 184
<> 150:02e0a0aed4ec 185 /* Check that port and pin are within range */
<> 150:02e0a0aed4ec 186 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
<> 150:02e0a0aed4ec 187 MXC_ASSERT(gpio->mask > 0);
<> 150:02e0a0aed4ec 188
<> 150:02e0a0aed4ec 189 /* Ports 0-3 are wud_seen0, while 4-7 are wud_seen1*/
<> 150:02e0a0aed4ec 190 if (gpio->port < 4) {
<> 150:02e0a0aed4ec 191 gpioWokeUp = (MXC_PWRMAN->wud_seen0 >> (gpio->port << 3)) & gpio->mask;
<> 150:02e0a0aed4ec 192 } else if (gpio->port < 8) {
<> 150:02e0a0aed4ec 193 gpioWokeUp = (MXC_PWRMAN->wud_seen1 >> ((gpio->port - 4) << 3)) & gpio->mask;
<> 150:02e0a0aed4ec 194 } else {
<> 150:02e0a0aed4ec 195 return E_NOT_SUPPORTED;
<> 150:02e0a0aed4ec 196 }
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 return gpioWokeUp;
<> 150:02e0a0aed4ec 199 }
<> 150:02e0a0aed4ec 200
<> 150:02e0a0aed4ec 201 int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio)
<> 150:02e0a0aed4ec 202 {
<> 150:02e0a0aed4ec 203 int result = E_NO_ERROR;
<> 150:02e0a0aed4ec 204 unsigned int pin;
<> 150:02e0a0aed4ec 205
<> 150:02e0a0aed4ec 206 /* Check that port and pin are within range */
<> 150:02e0a0aed4ec 207 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
<> 150:02e0a0aed4ec 208 MXC_ASSERT(gpio->mask > 0);
<> 150:02e0a0aed4ec 209
<> 150:02e0a0aed4ec 210 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1*/
<> 150:02e0a0aed4ec 211 if (gpio->port < 4) {
<> 150:02e0a0aed4ec 212 MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
<> 150:02e0a0aed4ec 213 if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
<> 150:02e0a0aed4ec 214 result = E_BUSY;
<> 150:02e0a0aed4ec 215 }
<> 150:02e0a0aed4ec 216 } else if (gpio->port < 8) {
<> 150:02e0a0aed4ec 217 MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
<> 150:02e0a0aed4ec 218 if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
<> 150:02e0a0aed4ec 219 result = E_BUSY;
<> 150:02e0a0aed4ec 220 }
<> 150:02e0a0aed4ec 221 } else {
<> 150:02e0a0aed4ec 222 return E_NOT_SUPPORTED;
<> 150:02e0a0aed4ec 223 }
<> 150:02e0a0aed4ec 224
<> 150:02e0a0aed4ec 225 if (result == E_NO_ERROR) {
<> 150:02e0a0aed4ec 226 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 150:02e0a0aed4ec 227 if (gpio->mask & (1 << pin)) {
<> 150:02e0a0aed4ec 228
<> 150:02e0a0aed4ec 229 /* Enable modifications to WUD configuration */
<> 150:02e0a0aed4ec 230 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 150:02e0a0aed4ec 231
<> 150:02e0a0aed4ec 232 /* Select pad in WUD control */
<> 150:02e0a0aed4ec 233 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 150:02e0a0aed4ec 234 MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
<> 150:02e0a0aed4ec 235
<> 150:02e0a0aed4ec 236 /* Clear out the pad mode */
<> 150:02e0a0aed4ec 237 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 150:02e0a0aed4ec 238
<> 150:02e0a0aed4ec 239 /* Select the wake up function on this pad */
<> 150:02e0a0aed4ec 240 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 150:02e0a0aed4ec 241
<> 150:02e0a0aed4ec 242 /* disable wake up with PULSE0 */
<> 150:02e0a0aed4ec 243 MXC_PWRMAN->wud_pulse0 = 1;
<> 150:02e0a0aed4ec 244
<> 150:02e0a0aed4ec 245 /* Disable configuration each time, required by hardware */
<> 150:02e0a0aed4ec 246 MXC_PWRMAN->wud_ctrl = 0;
<> 150:02e0a0aed4ec 247 }
<> 150:02e0a0aed4ec 248 }
<> 150:02e0a0aed4ec 249 }
<> 150:02e0a0aed4ec 250
<> 150:02e0a0aed4ec 251 /* Disable configuration */
<> 150:02e0a0aed4ec 252 MXC_IOMAN->wud_req0 = 0;
<> 150:02e0a0aed4ec 253 MXC_IOMAN->wud_req1 = 0;
<> 150:02e0a0aed4ec 254
<> 150:02e0a0aed4ec 255 return result;
<> 150:02e0a0aed4ec 256 }
<> 150:02e0a0aed4ec 257
<> 150:02e0a0aed4ec 258 int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en)
<> 150:02e0a0aed4ec 259 {
<> 150:02e0a0aed4ec 260 /* Enable or disable wake on USB plug-in */
<> 150:02e0a0aed4ec 261 if (plug_en) {
<> 150:02e0a0aed4ec 262 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP;
<> 150:02e0a0aed4ec 263 } else {
<> 150:02e0a0aed4ec 264 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP);
<> 150:02e0a0aed4ec 265 }
<> 150:02e0a0aed4ec 266
<> 150:02e0a0aed4ec 267 /* Enable or disable wake on USB unplug */
<> 150:02e0a0aed4ec 268 if (unplug_en) {
<> 150:02e0a0aed4ec 269 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP;
<> 150:02e0a0aed4ec 270 } else {
<> 150:02e0a0aed4ec 271 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
<> 150:02e0a0aed4ec 272 }
<> 150:02e0a0aed4ec 273
<> 150:02e0a0aed4ec 274 return E_NO_ERROR;
<> 150:02e0a0aed4ec 275 }
<> 150:02e0a0aed4ec 276
<> 150:02e0a0aed4ec 277 int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en,
<> 150:02e0a0aed4ec 278 unsigned int prescale_cmp_en, unsigned int rollover_en)
<> 150:02e0a0aed4ec 279 {
<> 150:02e0a0aed4ec 280 /* Note: MXC_PWRSEQ.pwr_misc[0] should be set to have the mask be active low */
<> 150:02e0a0aed4ec 281
<> 150:02e0a0aed4ec 282 /* Enable or disable wake on RTC Compare 0 */
<> 150:02e0a0aed4ec 283 if (comp0_en) {
<> 150:02e0a0aed4ec 284 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR0;
<> 150:02e0a0aed4ec 285
<> 150:02e0a0aed4ec 286 } else {
<> 150:02e0a0aed4ec 287 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR0);
<> 150:02e0a0aed4ec 288 }
<> 150:02e0a0aed4ec 289
<> 150:02e0a0aed4ec 290 /* Enable or disable wake on RTC Compare 1 */
<> 150:02e0a0aed4ec 291 if (comp1_en) {
<> 150:02e0a0aed4ec 292 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR1;
<> 150:02e0a0aed4ec 293
<> 150:02e0a0aed4ec 294 } else {
<> 150:02e0a0aed4ec 295 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR1);
<> 150:02e0a0aed4ec 296 }
<> 150:02e0a0aed4ec 297
<> 150:02e0a0aed4ec 298 /* Enable or disable wake on RTC Prescaler */
<> 150:02e0a0aed4ec 299 if (prescale_cmp_en) {
<> 150:02e0a0aed4ec 300 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP;
<> 150:02e0a0aed4ec 301
<> 150:02e0a0aed4ec 302 } else {
<> 150:02e0a0aed4ec 303 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP);
<> 150:02e0a0aed4ec 304 }
<> 150:02e0a0aed4ec 305
<> 150:02e0a0aed4ec 306 /* Enable or disable wake on RTC Rollover */
<> 150:02e0a0aed4ec 307 if (rollover_en) {
<> 150:02e0a0aed4ec 308 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER;
<> 150:02e0a0aed4ec 309
<> 150:02e0a0aed4ec 310 } else {
<> 150:02e0a0aed4ec 311 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER);
<> 150:02e0a0aed4ec 312 }
<> 150:02e0a0aed4ec 313
<> 150:02e0a0aed4ec 314 return E_NO_ERROR;
<> 150:02e0a0aed4ec 315 }
<> 150:02e0a0aed4ec 316
<> 150:02e0a0aed4ec 317
<> 150:02e0a0aed4ec 318 int LP_EnterLP2(void)
<> 150:02e0a0aed4ec 319 {
<> 150:02e0a0aed4ec 320 /* Clear SLEEPDEEP bit to avoid LP1/LP0 entry*/
<> 150:02e0a0aed4ec 321 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 150:02e0a0aed4ec 322
<> 150:02e0a0aed4ec 323 /* Go into LP2 mode and wait for an interrupt to wake the processor */
<> 150:02e0a0aed4ec 324 __WFI();
<> 150:02e0a0aed4ec 325
<> 150:02e0a0aed4ec 326 return E_NO_ERROR;
<> 150:02e0a0aed4ec 327 }
<> 150:02e0a0aed4ec 328
<> 150:02e0a0aed4ec 329 int LP_EnterLP1(void)
<> 150:02e0a0aed4ec 330 {
<> 150:02e0a0aed4ec 331 /* Turn on retention controller */
<> 150:02e0a0aed4ec 332 MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
<> 150:02e0a0aed4ec 333
<> 150:02e0a0aed4ec 334 /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
<> 150:02e0a0aed4ec 335 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
<> 150:02e0a0aed4ec 336
<> 150:02e0a0aed4ec 337 /* Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP */
<> 150:02e0a0aed4ec 338 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
<> 150:02e0a0aed4ec 339
<> 150:02e0a0aed4ec 340 /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
<> 150:02e0a0aed4ec 341 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 150:02e0a0aed4ec 342
<> 150:02e0a0aed4ec 343 /* Performance-measurement hook, may be defined as nothing */
<> 150:02e0a0aed4ec 344 LP1_PRE_HOOK;
<> 150:02e0a0aed4ec 345
<> 150:02e0a0aed4ec 346 /* Dummy read to make sure SSB writes are complete */
<> 150:02e0a0aed4ec 347 MXC_PWRSEQ->reg0;
<> 150:02e0a0aed4ec 348
<> 150:02e0a0aed4ec 349 /* Enter LP1 -- sequence is per instructions from ARM, Ltd. */
<> 150:02e0a0aed4ec 350 __SEV();
<> 150:02e0a0aed4ec 351 __WFE();
<> 150:02e0a0aed4ec 352 __WFE();
<> 150:02e0a0aed4ec 353
<> 150:02e0a0aed4ec 354 /* Performance-measurement hook, may be defined as nothing */
<> 150:02e0a0aed4ec 355 LP1_POST_HOOK;
<> 150:02e0a0aed4ec 356
<> 150:02e0a0aed4ec 357 /* Clear SLEEPDEEP bit */
<> 150:02e0a0aed4ec 358 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 150:02e0a0aed4ec 359
<> 150:02e0a0aed4ec 360 /* No error */
<> 150:02e0a0aed4ec 361 return E_NO_ERROR;
<> 150:02e0a0aed4ec 362 }
<> 150:02e0a0aed4ec 363
<> 150:02e0a0aed4ec 364 void LP_EnterLP0(void)
<> 150:02e0a0aed4ec 365 {
<> 150:02e0a0aed4ec 366 /* Turn off Auto GPIO Freeze/UnFreeze in sleep modes */
<> 150:02e0a0aed4ec 367 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE;
<> 150:02e0a0aed4ec 368
<> 150:02e0a0aed4ec 369 /* Disable interrupts, ok not to save state as exit LP0 is a reset */
<> 150:02e0a0aed4ec 370 __disable_irq();
<> 150:02e0a0aed4ec 371
<> 150:02e0a0aed4ec 372 /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
<> 150:02e0a0aed4ec 373 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
<> 150:02e0a0aed4ec 374
<> 150:02e0a0aed4ec 375 /* Turn off retention controller */
<> 150:02e0a0aed4ec 376 MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN);
<> 150:02e0a0aed4ec 377
<> 150:02e0a0aed4ec 378 /* Turn off retention regulator */
<> 150:02e0a0aed4ec 379 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
<> 150:02e0a0aed4ec 380
<> 150:02e0a0aed4ec 381 /* LP0 ONLY to eliminate ~50nA of leakage on VDD12 */
<> 150:02e0a0aed4ec 382 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
<> 150:02e0a0aed4ec 383
<> 150:02e0a0aed4ec 384 /* Clear the LP1 select bit so CPU goes to LP0 during SLEEPDEEP */
<> 150:02e0a0aed4ec 385 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_LP1);
<> 150:02e0a0aed4ec 386
<> 150:02e0a0aed4ec 387 /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
<> 150:02e0a0aed4ec 388 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 150:02e0a0aed4ec 389
<> 150:02e0a0aed4ec 390 /* Performance-measurement hook, may be defined as nothing */
<> 150:02e0a0aed4ec 391 LP0_PRE_HOOK;
<> 150:02e0a0aed4ec 392
<> 150:02e0a0aed4ec 393 /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
<> 150:02e0a0aed4ec 394 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
<> 150:02e0a0aed4ec 395
<> 150:02e0a0aed4ec 396 /* Dummy read to make sure SSB writes are complete */
<> 150:02e0a0aed4ec 397 MXC_PWRSEQ->reg0;
<> 150:02e0a0aed4ec 398
<> 150:02e0a0aed4ec 399 /* Go into LP0 -- sequence is per instructions from ARM, Ltd. */
<> 150:02e0a0aed4ec 400 __SEV();
<> 150:02e0a0aed4ec 401 __WFE();
<> 150:02e0a0aed4ec 402 __WFE();
<> 150:02e0a0aed4ec 403
<> 150:02e0a0aed4ec 404 /* Catch the case where this code does not properly sleep */
<> 150:02e0a0aed4ec 405 /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
<> 150:02e0a0aed4ec 406 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
<> 150:02e0a0aed4ec 407 MXC_ASSERT_FAIL();
<> 150:02e0a0aed4ec 408 while (1) {
<> 150:02e0a0aed4ec 409 __NOP();
<> 150:02e0a0aed4ec 410 }
<> 150:02e0a0aed4ec 411
<> 150:02e0a0aed4ec 412 /* Does not actually return */
<> 150:02e0a0aed4ec 413 }