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targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma_crc.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Nov 04 16:30:11 2015 +0000
- Revision:
- 15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514
Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/
Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 15:a81a8d6c1dfe | 1 | /** |
mbed_official | 15:a81a8d6c1dfe | 2 | * \file |
mbed_official | 15:a81a8d6c1dfe | 3 | * |
mbed_official | 15:a81a8d6c1dfe | 4 | * \brief SAM DMA cyclic redundancy check (CRC) Driver |
mbed_official | 15:a81a8d6c1dfe | 5 | * |
mbed_official | 15:a81a8d6c1dfe | 6 | * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. |
mbed_official | 15:a81a8d6c1dfe | 7 | * |
mbed_official | 15:a81a8d6c1dfe | 8 | * \asf_license_start |
mbed_official | 15:a81a8d6c1dfe | 9 | * |
mbed_official | 15:a81a8d6c1dfe | 10 | * \page License |
mbed_official | 15:a81a8d6c1dfe | 11 | * |
mbed_official | 15:a81a8d6c1dfe | 12 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 15:a81a8d6c1dfe | 13 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 15:a81a8d6c1dfe | 14 | * |
mbed_official | 15:a81a8d6c1dfe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 15:a81a8d6c1dfe | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 15:a81a8d6c1dfe | 17 | * |
mbed_official | 15:a81a8d6c1dfe | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 15:a81a8d6c1dfe | 19 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 15:a81a8d6c1dfe | 20 | * and/or other materials provided with the distribution. |
mbed_official | 15:a81a8d6c1dfe | 21 | * |
mbed_official | 15:a81a8d6c1dfe | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
mbed_official | 15:a81a8d6c1dfe | 23 | * from this software without specific prior written permission. |
mbed_official | 15:a81a8d6c1dfe | 24 | * |
mbed_official | 15:a81a8d6c1dfe | 25 | * 4. This software may only be redistributed and used in connection with an |
mbed_official | 15:a81a8d6c1dfe | 26 | * Atmel microcontroller product. |
mbed_official | 15:a81a8d6c1dfe | 27 | * |
mbed_official | 15:a81a8d6c1dfe | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 15:a81a8d6c1dfe | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 15:a81a8d6c1dfe | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
mbed_official | 15:a81a8d6c1dfe | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
mbed_official | 15:a81a8d6c1dfe | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 15:a81a8d6c1dfe | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
mbed_official | 15:a81a8d6c1dfe | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
mbed_official | 15:a81a8d6c1dfe | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
mbed_official | 15:a81a8d6c1dfe | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
mbed_official | 15:a81a8d6c1dfe | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
mbed_official | 15:a81a8d6c1dfe | 38 | * POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 15:a81a8d6c1dfe | 39 | * |
mbed_official | 15:a81a8d6c1dfe | 40 | * \asf_license_stop |
mbed_official | 15:a81a8d6c1dfe | 41 | * |
mbed_official | 15:a81a8d6c1dfe | 42 | */ |
mbed_official | 15:a81a8d6c1dfe | 43 | /* |
mbed_official | 15:a81a8d6c1dfe | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
mbed_official | 15:a81a8d6c1dfe | 45 | */ |
mbed_official | 15:a81a8d6c1dfe | 46 | #ifndef DMA_CRC_H_INCLUDED |
mbed_official | 15:a81a8d6c1dfe | 47 | #define DMA_CRC_H_INCLUDED |
mbed_official | 15:a81a8d6c1dfe | 48 | |
mbed_official | 15:a81a8d6c1dfe | 49 | #include <compiler.h> |
mbed_official | 15:a81a8d6c1dfe | 50 | |
mbed_official | 15:a81a8d6c1dfe | 51 | #ifdef __cplusplus |
mbed_official | 15:a81a8d6c1dfe | 52 | extern "C" { |
mbed_official | 15:a81a8d6c1dfe | 53 | #endif |
mbed_official | 15:a81a8d6c1dfe | 54 | |
mbed_official | 15:a81a8d6c1dfe | 55 | /** DMA channel n offset. */ |
mbed_official | 15:a81a8d6c1dfe | 56 | #define DMA_CRC_CHANNEL_N_OFFSET 0x20 |
mbed_official | 15:a81a8d6c1dfe | 57 | |
mbed_official | 15:a81a8d6c1dfe | 58 | /** CRC Polynomial Type. */ |
mbed_official | 15:a81a8d6c1dfe | 59 | enum crc_polynomial_type { |
mbed_official | 15:a81a8d6c1dfe | 60 | /** CRC16 (CRC-CCITT). */ |
mbed_official | 15:a81a8d6c1dfe | 61 | CRC_TYPE_16, |
mbed_official | 15:a81a8d6c1dfe | 62 | /** CRC32 (IEEE 802.3). */ |
mbed_official | 15:a81a8d6c1dfe | 63 | CRC_TYPE_32, |
mbed_official | 15:a81a8d6c1dfe | 64 | }; |
mbed_official | 15:a81a8d6c1dfe | 65 | |
mbed_official | 15:a81a8d6c1dfe | 66 | /** CRC Beat Type. */ |
mbed_official | 15:a81a8d6c1dfe | 67 | enum crc_beat_size { |
mbed_official | 15:a81a8d6c1dfe | 68 | /** Byte bus access. */ |
mbed_official | 15:a81a8d6c1dfe | 69 | CRC_BEAT_SIZE_BYTE, |
mbed_official | 15:a81a8d6c1dfe | 70 | /** Half-word bus access. */ |
mbed_official | 15:a81a8d6c1dfe | 71 | CRC_BEAT_SIZE_HWORD, |
mbed_official | 15:a81a8d6c1dfe | 72 | /** Word bus access. */ |
mbed_official | 15:a81a8d6c1dfe | 73 | CRC_BEAT_SIZE_WORD, |
mbed_official | 15:a81a8d6c1dfe | 74 | }; |
mbed_official | 15:a81a8d6c1dfe | 75 | |
mbed_official | 15:a81a8d6c1dfe | 76 | /** Configurations for CRC calculation. */ |
mbed_official | 15:a81a8d6c1dfe | 77 | struct dma_crc_config { |
mbed_official | 15:a81a8d6c1dfe | 78 | /** CRC polynomial type. */ |
mbed_official | 15:a81a8d6c1dfe | 79 | enum crc_polynomial_type type; |
mbed_official | 15:a81a8d6c1dfe | 80 | /** CRC beat size. */ |
mbed_official | 15:a81a8d6c1dfe | 81 | enum crc_beat_size size; |
mbed_official | 15:a81a8d6c1dfe | 82 | }; |
mbed_official | 15:a81a8d6c1dfe | 83 | |
mbed_official | 15:a81a8d6c1dfe | 84 | /** |
mbed_official | 15:a81a8d6c1dfe | 85 | * \brief Get DMA CRC default configurations. |
mbed_official | 15:a81a8d6c1dfe | 86 | * |
mbed_official | 15:a81a8d6c1dfe | 87 | * The default configuration is as follows: |
mbed_official | 15:a81a8d6c1dfe | 88 | * \li Polynomial type is set to CRC-16(CRC-CCITT) |
mbed_official | 15:a81a8d6c1dfe | 89 | * \li CRC Beat size: BYTE |
mbed_official | 15:a81a8d6c1dfe | 90 | * |
mbed_official | 15:a81a8d6c1dfe | 91 | * \param[in] config default configurations |
mbed_official | 15:a81a8d6c1dfe | 92 | */ |
mbed_official | 15:a81a8d6c1dfe | 93 | static inline void dma_crc_get_config_defaults(struct dma_crc_config *config) |
mbed_official | 15:a81a8d6c1dfe | 94 | { |
mbed_official | 15:a81a8d6c1dfe | 95 | Assert(config); |
mbed_official | 15:a81a8d6c1dfe | 96 | |
mbed_official | 15:a81a8d6c1dfe | 97 | config->type = CRC_TYPE_16; |
mbed_official | 15:a81a8d6c1dfe | 98 | config->size = CRC_BEAT_SIZE_BYTE; |
mbed_official | 15:a81a8d6c1dfe | 99 | } |
mbed_official | 15:a81a8d6c1dfe | 100 | |
mbed_official | 15:a81a8d6c1dfe | 101 | /** |
mbed_official | 15:a81a8d6c1dfe | 102 | * \brief Enable DMA CRC module with an DMA channel. |
mbed_official | 15:a81a8d6c1dfe | 103 | * |
mbed_official | 15:a81a8d6c1dfe | 104 | * This function enables a CRC calculation with an allocated DMA channel. This channel ID |
mbed_official | 15:a81a8d6c1dfe | 105 | * can be gotten from a successful \ref dma_allocate. |
mbed_official | 15:a81a8d6c1dfe | 106 | * |
mbed_official | 15:a81a8d6c1dfe | 107 | * \param[in] channel_id DMA channel expected with CRC calculation |
mbed_official | 15:a81a8d6c1dfe | 108 | * \param[in] config CRC calculation configurations |
mbed_official | 15:a81a8d6c1dfe | 109 | * |
mbed_official | 15:a81a8d6c1dfe | 110 | * \return Status of the DMC CRC. |
mbed_official | 15:a81a8d6c1dfe | 111 | * \retval STATUS_OK Get the DMA CRC module |
mbed_official | 15:a81a8d6c1dfe | 112 | * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet |
mbed_official | 15:a81a8d6c1dfe | 113 | */ |
mbed_official | 15:a81a8d6c1dfe | 114 | static inline enum status_code dma_crc_channel_enable(uint32_t channel_id, |
mbed_official | 15:a81a8d6c1dfe | 115 | struct dma_crc_config *config) |
mbed_official | 15:a81a8d6c1dfe | 116 | { |
mbed_official | 15:a81a8d6c1dfe | 117 | if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { |
mbed_official | 15:a81a8d6c1dfe | 118 | return STATUS_BUSY; |
mbed_official | 15:a81a8d6c1dfe | 119 | } |
mbed_official | 15:a81a8d6c1dfe | 120 | |
mbed_official | 15:a81a8d6c1dfe | 121 | DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | |
mbed_official | 15:a81a8d6c1dfe | 122 | DMAC_CRCCTRL_CRCPOLY(config->type) | |
mbed_official | 15:a81a8d6c1dfe | 123 | DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET); |
mbed_official | 15:a81a8d6c1dfe | 124 | |
mbed_official | 15:a81a8d6c1dfe | 125 | DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; |
mbed_official | 15:a81a8d6c1dfe | 126 | |
mbed_official | 15:a81a8d6c1dfe | 127 | return STATUS_OK; |
mbed_official | 15:a81a8d6c1dfe | 128 | } |
mbed_official | 15:a81a8d6c1dfe | 129 | |
mbed_official | 15:a81a8d6c1dfe | 130 | /** |
mbed_official | 15:a81a8d6c1dfe | 131 | * \brief Disable DMA CRC module. |
mbed_official | 15:a81a8d6c1dfe | 132 | * |
mbed_official | 15:a81a8d6c1dfe | 133 | */ |
mbed_official | 15:a81a8d6c1dfe | 134 | static inline void dma_crc_disable(void) |
mbed_official | 15:a81a8d6c1dfe | 135 | { |
mbed_official | 15:a81a8d6c1dfe | 136 | DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; |
mbed_official | 15:a81a8d6c1dfe | 137 | DMAC->CRCCTRL.reg = 0; |
mbed_official | 15:a81a8d6c1dfe | 138 | } |
mbed_official | 15:a81a8d6c1dfe | 139 | |
mbed_official | 15:a81a8d6c1dfe | 140 | /** |
mbed_official | 15:a81a8d6c1dfe | 141 | * \brief Get DMA CRC checksum value. |
mbed_official | 15:a81a8d6c1dfe | 142 | * |
mbed_official | 15:a81a8d6c1dfe | 143 | * \return Calculated CRC checksum. |
mbed_official | 15:a81a8d6c1dfe | 144 | */ |
mbed_official | 15:a81a8d6c1dfe | 145 | static inline uint32_t dma_crc_get_checksum(void) |
mbed_official | 15:a81a8d6c1dfe | 146 | { |
mbed_official | 15:a81a8d6c1dfe | 147 | if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) { |
mbed_official | 15:a81a8d6c1dfe | 148 | DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; |
mbed_official | 15:a81a8d6c1dfe | 149 | } |
mbed_official | 15:a81a8d6c1dfe | 150 | |
mbed_official | 15:a81a8d6c1dfe | 151 | return DMAC->CRCCHKSUM.reg; |
mbed_official | 15:a81a8d6c1dfe | 152 | } |
mbed_official | 15:a81a8d6c1dfe | 153 | |
mbed_official | 15:a81a8d6c1dfe | 154 | /** |
mbed_official | 15:a81a8d6c1dfe | 155 | * \brief Enable DMA CRC module with I/O. |
mbed_official | 15:a81a8d6c1dfe | 156 | * |
mbed_official | 15:a81a8d6c1dfe | 157 | * This function enables a CRC calculation with I/O mode. |
mbed_official | 15:a81a8d6c1dfe | 158 | * |
mbed_official | 15:a81a8d6c1dfe | 159 | * \param[in] config CRC calculation configurations. |
mbed_official | 15:a81a8d6c1dfe | 160 | * |
mbed_official | 15:a81a8d6c1dfe | 161 | * \return Status of the DMC CRC. |
mbed_official | 15:a81a8d6c1dfe | 162 | * \retval STATUS_OK Get the DMA CRC module |
mbed_official | 15:a81a8d6c1dfe | 163 | * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet |
mbed_official | 15:a81a8d6c1dfe | 164 | */ |
mbed_official | 15:a81a8d6c1dfe | 165 | static inline enum status_code dma_crc_io_enable( |
mbed_official | 15:a81a8d6c1dfe | 166 | struct dma_crc_config *config) |
mbed_official | 15:a81a8d6c1dfe | 167 | { |
mbed_official | 15:a81a8d6c1dfe | 168 | if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { |
mbed_official | 15:a81a8d6c1dfe | 169 | return STATUS_BUSY; |
mbed_official | 15:a81a8d6c1dfe | 170 | } |
mbed_official | 15:a81a8d6c1dfe | 171 | |
mbed_official | 15:a81a8d6c1dfe | 172 | if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) { |
mbed_official | 15:a81a8d6c1dfe | 173 | return STATUS_BUSY; |
mbed_official | 15:a81a8d6c1dfe | 174 | } |
mbed_official | 15:a81a8d6c1dfe | 175 | |
mbed_official | 15:a81a8d6c1dfe | 176 | DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | |
mbed_official | 15:a81a8d6c1dfe | 177 | DMAC_CRCCTRL_CRCPOLY(config->type) | |
mbed_official | 15:a81a8d6c1dfe | 178 | DMAC_CRCCTRL_CRCSRC_IO; |
mbed_official | 15:a81a8d6c1dfe | 179 | |
mbed_official | 15:a81a8d6c1dfe | 180 | if (config->type == CRC_TYPE_32) { |
mbed_official | 15:a81a8d6c1dfe | 181 | DMAC->CRCCHKSUM.reg = 0xFFFFFFFF; |
mbed_official | 15:a81a8d6c1dfe | 182 | } |
mbed_official | 15:a81a8d6c1dfe | 183 | |
mbed_official | 15:a81a8d6c1dfe | 184 | DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; |
mbed_official | 15:a81a8d6c1dfe | 185 | |
mbed_official | 15:a81a8d6c1dfe | 186 | return STATUS_OK; |
mbed_official | 15:a81a8d6c1dfe | 187 | } |
mbed_official | 15:a81a8d6c1dfe | 188 | |
mbed_official | 15:a81a8d6c1dfe | 189 | /** |
mbed_official | 15:a81a8d6c1dfe | 190 | * \brief Calculate CRC with I/O. |
mbed_official | 15:a81a8d6c1dfe | 191 | * |
mbed_official | 15:a81a8d6c1dfe | 192 | * This function calculate the CRC of the input data buffer. |
mbed_official | 15:a81a8d6c1dfe | 193 | * |
mbed_official | 15:a81a8d6c1dfe | 194 | * \param[in] buffer CRC Pointer to calculation buffer |
mbed_official | 15:a81a8d6c1dfe | 195 | * \param[in] total_beat_size Total beat size to be calculated |
mbed_official | 15:a81a8d6c1dfe | 196 | * |
mbed_official | 15:a81a8d6c1dfe | 197 | * \return Calculated CRC checksum value. |
mbed_official | 15:a81a8d6c1dfe | 198 | */ |
mbed_official | 15:a81a8d6c1dfe | 199 | static inline void dma_crc_io_calculation(void *buffer, |
mbed_official | 15:a81a8d6c1dfe | 200 | uint32_t total_beat_size) |
mbed_official | 15:a81a8d6c1dfe | 201 | { |
mbed_official | 15:a81a8d6c1dfe | 202 | uint32_t counter = total_beat_size; |
mbed_official | 15:a81a8d6c1dfe | 203 | uint8_t *buffer_8; |
mbed_official | 15:a81a8d6c1dfe | 204 | uint16_t *buffer_16; |
mbed_official | 15:a81a8d6c1dfe | 205 | uint32_t *buffer_32; |
mbed_official | 15:a81a8d6c1dfe | 206 | |
mbed_official | 15:a81a8d6c1dfe | 207 | for (counter=0; counter<total_beat_size; counter++) { |
mbed_official | 15:a81a8d6c1dfe | 208 | if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) { |
mbed_official | 15:a81a8d6c1dfe | 209 | buffer_8 = buffer; |
mbed_official | 15:a81a8d6c1dfe | 210 | DMAC->CRCDATAIN.reg = buffer_8[counter]; |
mbed_official | 15:a81a8d6c1dfe | 211 | } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) { |
mbed_official | 15:a81a8d6c1dfe | 212 | buffer_16 = buffer; |
mbed_official | 15:a81a8d6c1dfe | 213 | DMAC->CRCDATAIN.reg = buffer_16[counter]; |
mbed_official | 15:a81a8d6c1dfe | 214 | } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) { |
mbed_official | 15:a81a8d6c1dfe | 215 | buffer_32 = buffer; |
mbed_official | 15:a81a8d6c1dfe | 216 | DMAC->CRCDATAIN.reg = buffer_32[counter]; |
mbed_official | 15:a81a8d6c1dfe | 217 | } |
mbed_official | 15:a81a8d6c1dfe | 218 | /* Wait several cycle to make sure CRC complete */ |
mbed_official | 15:a81a8d6c1dfe | 219 | nop(); |
mbed_official | 15:a81a8d6c1dfe | 220 | nop(); |
mbed_official | 15:a81a8d6c1dfe | 221 | nop(); |
mbed_official | 15:a81a8d6c1dfe | 222 | nop(); |
mbed_official | 15:a81a8d6c1dfe | 223 | } |
mbed_official | 15:a81a8d6c1dfe | 224 | } |
mbed_official | 15:a81a8d6c1dfe | 225 | |
mbed_official | 15:a81a8d6c1dfe | 226 | #ifdef __cplusplus |
mbed_official | 15:a81a8d6c1dfe | 227 | } |
mbed_official | 15:a81a8d6c1dfe | 228 | #endif |
mbed_official | 15:a81a8d6c1dfe | 229 | |
mbed_official | 15:a81a8d6c1dfe | 230 | #endif /* DMA_CRC_H_INCLUDED */ |