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targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 66:fdb3f9f9a72f
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /* mbed Microcontroller Library |
bogdanm | 0:9b334a45a8ff | 2 | * Copyright (c) 2006-2015 ARM Limited |
bogdanm | 0:9b334a45a8ff | 3 | * |
bogdanm | 0:9b334a45a8ff | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 0:9b334a45a8ff | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 0:9b334a45a8ff | 6 | * You may obtain a copy of the License at |
bogdanm | 0:9b334a45a8ff | 7 | * |
bogdanm | 0:9b334a45a8ff | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 0:9b334a45a8ff | 9 | * |
bogdanm | 0:9b334a45a8ff | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 0:9b334a45a8ff | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 0:9b334a45a8ff | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 0:9b334a45a8ff | 13 | * See the License for the specific language governing permissions and |
bogdanm | 0:9b334a45a8ff | 14 | * limitations under the License. |
bogdanm | 0:9b334a45a8ff | 15 | */ |
bogdanm | 0:9b334a45a8ff | 16 | // math.h required for floating point operations for baud rate calculation |
bogdanm | 0:9b334a45a8ff | 17 | #include "mbed_assert.h" |
bogdanm | 0:9b334a45a8ff | 18 | #include <math.h> |
bogdanm | 0:9b334a45a8ff | 19 | #include <string.h> |
bogdanm | 0:9b334a45a8ff | 20 | #include <stdlib.h> |
bogdanm | 0:9b334a45a8ff | 21 | |
bogdanm | 0:9b334a45a8ff | 22 | #include "serial_api.h" |
bogdanm | 0:9b334a45a8ff | 23 | #include "cmsis.h" |
bogdanm | 0:9b334a45a8ff | 24 | #include "pinmap.h" |
bogdanm | 0:9b334a45a8ff | 25 | #include "gpio_api.h" |
bogdanm | 0:9b334a45a8ff | 26 | |
bogdanm | 0:9b334a45a8ff | 27 | #include "scif_iodefine.h" |
bogdanm | 0:9b334a45a8ff | 28 | #include "cpg_iodefine.h" |
bogdanm | 0:9b334a45a8ff | 29 | |
bogdanm | 0:9b334a45a8ff | 30 | /****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 31 | * INITIALIZATION |
bogdanm | 0:9b334a45a8ff | 32 | ******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 33 | #define PCLK (66666666) // Define the peripheral clock P1 frequency. |
bogdanm | 0:9b334a45a8ff | 34 | |
bogdanm | 0:9b334a45a8ff | 35 | #define UART_NUM 8 |
bogdanm | 0:9b334a45a8ff | 36 | #define IRQ_NUM 2 |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | static void uart0_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 39 | static void uart1_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 40 | static void uart2_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 41 | static void uart3_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 42 | static void uart4_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 43 | static void uart5_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 44 | static void uart6_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 45 | static void uart7_tx_irq(void); |
bogdanm | 0:9b334a45a8ff | 46 | static void uart0_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 47 | static void uart1_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 48 | static void uart2_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 49 | static void uart3_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 50 | static void uart4_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 51 | static void uart5_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 52 | static void uart6_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 53 | static void uart7_rx_irq(void); |
bogdanm | 0:9b334a45a8ff | 54 | |
bogdanm | 0:9b334a45a8ff | 55 | |
bogdanm | 0:9b334a45a8ff | 56 | static const PinMap PinMap_UART_TX[] = { |
bogdanm | 0:9b334a45a8ff | 57 | {P2_14 , UART0, 6}, |
bogdanm | 0:9b334a45a8ff | 58 | {P2_5 , UART1, 6}, |
bogdanm | 0:9b334a45a8ff | 59 | {P4_12 , UART1, 7}, |
bogdanm | 0:9b334a45a8ff | 60 | {P6_3 , UART2, 7}, |
bogdanm | 0:9b334a45a8ff | 61 | {P4_14 , UART2, 7}, |
bogdanm | 0:9b334a45a8ff | 62 | {P5_3 , UART3, 5}, |
bogdanm | 0:9b334a45a8ff | 63 | {P8_8 , UART3, 7}, |
bogdanm | 0:9b334a45a8ff | 64 | {P5_0 , UART4, 5}, |
bogdanm | 0:9b334a45a8ff | 65 | {P8_14 , UART4, 7}, |
bogdanm | 0:9b334a45a8ff | 66 | {P8_13 , UART5, 5}, |
bogdanm | 0:9b334a45a8ff | 67 | {P11_10, UART5, 3}, |
bogdanm | 0:9b334a45a8ff | 68 | {P6_6 , UART5, 5}, |
bogdanm | 0:9b334a45a8ff | 69 | {P5_6 , UART6, 5}, |
bogdanm | 0:9b334a45a8ff | 70 | {P11_1 , UART6, 4}, |
bogdanm | 0:9b334a45a8ff | 71 | {P7_4 , UART7, 4}, |
bogdanm | 0:9b334a45a8ff | 72 | {NC , NC , 0} |
bogdanm | 0:9b334a45a8ff | 73 | }; |
bogdanm | 0:9b334a45a8ff | 74 | |
bogdanm | 0:9b334a45a8ff | 75 | static const PinMap PinMap_UART_RX[] = { |
bogdanm | 0:9b334a45a8ff | 76 | {P2_15 , UART0, 6}, |
bogdanm | 0:9b334a45a8ff | 77 | {P2_6 , UART1, 6}, |
bogdanm | 0:9b334a45a8ff | 78 | {P4_13 , UART1, 7}, |
bogdanm | 0:9b334a45a8ff | 79 | {P6_2 , UART2, 7}, |
bogdanm | 0:9b334a45a8ff | 80 | {P4_15 , UART2, 7}, |
bogdanm | 0:9b334a45a8ff | 81 | {P5_4 , UART3, 5}, |
bogdanm | 0:9b334a45a8ff | 82 | {P8_9 , UART3, 7}, |
bogdanm | 0:9b334a45a8ff | 83 | {P5_1 , UART4, 5}, |
bogdanm | 0:9b334a45a8ff | 84 | {P8_15 , UART4, 7}, |
bogdanm | 0:9b334a45a8ff | 85 | {P8_11 , UART5, 5}, |
bogdanm | 0:9b334a45a8ff | 86 | {P11_11, UART5, 3}, |
bogdanm | 0:9b334a45a8ff | 87 | {P6_7 , UART5, 5}, |
bogdanm | 0:9b334a45a8ff | 88 | {P5_7 , UART6, 5}, |
bogdanm | 0:9b334a45a8ff | 89 | {P11_2 , UART6, 4}, |
bogdanm | 0:9b334a45a8ff | 90 | {P7_5 , UART7, 4}, |
bogdanm | 0:9b334a45a8ff | 91 | {NC , NC , 0} |
bogdanm | 0:9b334a45a8ff | 92 | }; |
bogdanm | 0:9b334a45a8ff | 93 | |
bogdanm | 0:9b334a45a8ff | 94 | static const PinMap PinMap_UART_CTS[] = { |
bogdanm | 0:9b334a45a8ff | 95 | {P2_3 , UART1, 6}, |
bogdanm | 0:9b334a45a8ff | 96 | {P11_7 , UART5, 3}, |
bogdanm | 0:9b334a45a8ff | 97 | {P7_6 , UART7, 4}, |
bogdanm | 0:9b334a45a8ff | 98 | {NC , NC , 0} |
bogdanm | 0:9b334a45a8ff | 99 | }; |
bogdanm | 0:9b334a45a8ff | 100 | static const PinMap PinMap_UART_RTS[] = { |
bogdanm | 0:9b334a45a8ff | 101 | {P2_7 , UART1, 6}, |
bogdanm | 0:9b334a45a8ff | 102 | {P11_8 , UART5, 3}, |
bogdanm | 0:9b334a45a8ff | 103 | {P7_7 , UART7, 4}, |
bogdanm | 0:9b334a45a8ff | 104 | {NC , NC , 0} |
bogdanm | 0:9b334a45a8ff | 105 | }; |
bogdanm | 0:9b334a45a8ff | 106 | |
bogdanm | 0:9b334a45a8ff | 107 | |
bogdanm | 0:9b334a45a8ff | 108 | |
bogdanm | 0:9b334a45a8ff | 109 | static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; |
bogdanm | 0:9b334a45a8ff | 110 | static uart_irq_handler irq_handler; |
bogdanm | 0:9b334a45a8ff | 111 | |
bogdanm | 0:9b334a45a8ff | 112 | int stdio_uart_inited = 0; |
bogdanm | 0:9b334a45a8ff | 113 | serial_t stdio_uart; |
bogdanm | 0:9b334a45a8ff | 114 | |
bogdanm | 0:9b334a45a8ff | 115 | struct serial_global_data_s { |
bogdanm | 0:9b334a45a8ff | 116 | uint32_t serial_irq_id; |
bogdanm | 0:9b334a45a8ff | 117 | gpio_t sw_rts, sw_cts; |
bogdanm | 0:9b334a45a8ff | 118 | uint8_t count, rx_irq_set_flow, rx_irq_set_api; |
bogdanm | 0:9b334a45a8ff | 119 | }; |
bogdanm | 0:9b334a45a8ff | 120 | |
bogdanm | 0:9b334a45a8ff | 121 | static struct serial_global_data_s uart_data[UART_NUM]; |
bogdanm | 0:9b334a45a8ff | 122 | |
bogdanm | 0:9b334a45a8ff | 123 | static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { |
bogdanm | 0:9b334a45a8ff | 124 | {SCIFRXI0_IRQn, SCIFTXI0_IRQn}, |
bogdanm | 0:9b334a45a8ff | 125 | {SCIFRXI1_IRQn, SCIFTXI1_IRQn}, |
bogdanm | 0:9b334a45a8ff | 126 | {SCIFRXI2_IRQn, SCIFTXI2_IRQn}, |
bogdanm | 0:9b334a45a8ff | 127 | {SCIFRXI3_IRQn, SCIFTXI3_IRQn}, |
bogdanm | 0:9b334a45a8ff | 128 | {SCIFRXI4_IRQn, SCIFTXI4_IRQn}, |
bogdanm | 0:9b334a45a8ff | 129 | {SCIFRXI5_IRQn, SCIFTXI5_IRQn}, |
bogdanm | 0:9b334a45a8ff | 130 | {SCIFRXI6_IRQn, SCIFTXI6_IRQn}, |
bogdanm | 0:9b334a45a8ff | 131 | {SCIFRXI7_IRQn, SCIFTXI7_IRQn} |
bogdanm | 0:9b334a45a8ff | 132 | }; |
bogdanm | 0:9b334a45a8ff | 133 | |
bogdanm | 0:9b334a45a8ff | 134 | static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { |
bogdanm | 0:9b334a45a8ff | 135 | {uart0_rx_irq, uart0_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 136 | {uart1_rx_irq, uart1_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 137 | {uart2_rx_irq, uart2_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 138 | {uart3_rx_irq, uart3_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 139 | {uart4_rx_irq, uart4_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 140 | {uart5_rx_irq, uart5_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 141 | {uart6_rx_irq, uart6_tx_irq}, |
bogdanm | 0:9b334a45a8ff | 142 | {uart7_rx_irq, uart7_tx_irq} |
bogdanm | 0:9b334a45a8ff | 143 | }; |
bogdanm | 0:9b334a45a8ff | 144 | |
bogdanm | 0:9b334a45a8ff | 145 | static __IO uint16_t *SCSCR_MATCH[] = { |
bogdanm | 0:9b334a45a8ff | 146 | &SCSCR_0, |
bogdanm | 0:9b334a45a8ff | 147 | &SCSCR_1, |
bogdanm | 0:9b334a45a8ff | 148 | &SCSCR_2, |
bogdanm | 0:9b334a45a8ff | 149 | &SCSCR_3, |
bogdanm | 0:9b334a45a8ff | 150 | &SCSCR_4, |
bogdanm | 0:9b334a45a8ff | 151 | &SCSCR_5, |
bogdanm | 0:9b334a45a8ff | 152 | &SCSCR_6, |
bogdanm | 0:9b334a45a8ff | 153 | &SCSCR_7, |
bogdanm | 0:9b334a45a8ff | 154 | }; |
bogdanm | 0:9b334a45a8ff | 155 | |
bogdanm | 0:9b334a45a8ff | 156 | static __IO uint16_t *SCFSR_MATCH[] = { |
bogdanm | 0:9b334a45a8ff | 157 | &SCFSR_0, |
bogdanm | 0:9b334a45a8ff | 158 | &SCFSR_1, |
bogdanm | 0:9b334a45a8ff | 159 | &SCFSR_2, |
bogdanm | 0:9b334a45a8ff | 160 | &SCFSR_3, |
bogdanm | 0:9b334a45a8ff | 161 | &SCFSR_4, |
bogdanm | 0:9b334a45a8ff | 162 | &SCFSR_5, |
bogdanm | 0:9b334a45a8ff | 163 | &SCFSR_6, |
bogdanm | 0:9b334a45a8ff | 164 | &SCFSR_7, |
bogdanm | 0:9b334a45a8ff | 165 | }; |
bogdanm | 0:9b334a45a8ff | 166 | |
bogdanm | 0:9b334a45a8ff | 167 | |
bogdanm | 0:9b334a45a8ff | 168 | void serial_init(serial_t *obj, PinName tx, PinName rx) { |
bogdanm | 0:9b334a45a8ff | 169 | volatile uint8_t dummy ; |
bogdanm | 0:9b334a45a8ff | 170 | int is_stdio_uart = 0; |
bogdanm | 0:9b334a45a8ff | 171 | // determine the UART to use |
bogdanm | 0:9b334a45a8ff | 172 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); |
bogdanm | 0:9b334a45a8ff | 173 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); |
bogdanm | 0:9b334a45a8ff | 174 | uint32_t uart = pinmap_merge(uart_tx, uart_rx); |
bogdanm | 0:9b334a45a8ff | 175 | |
bogdanm | 0:9b334a45a8ff | 176 | MBED_ASSERT((int)uart != NC); |
bogdanm | 0:9b334a45a8ff | 177 | |
bogdanm | 0:9b334a45a8ff | 178 | obj->uart = (struct st_scif *)SCIF[uart]; |
bogdanm | 0:9b334a45a8ff | 179 | // enable power |
bogdanm | 0:9b334a45a8ff | 180 | switch (uart) { |
bogdanm | 0:9b334a45a8ff | 181 | case UART0: |
bogdanm | 0:9b334a45a8ff | 182 | CPG.STBCR4 &= ~(1 << 7); |
bogdanm | 0:9b334a45a8ff | 183 | break; |
bogdanm | 0:9b334a45a8ff | 184 | case UART1: |
bogdanm | 0:9b334a45a8ff | 185 | CPG.STBCR4 &= ~(1 << 6); |
bogdanm | 0:9b334a45a8ff | 186 | break; |
bogdanm | 0:9b334a45a8ff | 187 | case UART2: |
bogdanm | 0:9b334a45a8ff | 188 | CPG.STBCR4 &= ~(1 << 5); |
bogdanm | 0:9b334a45a8ff | 189 | break; |
bogdanm | 0:9b334a45a8ff | 190 | case UART3: |
bogdanm | 0:9b334a45a8ff | 191 | CPG.STBCR4 &= ~(1 << 4); |
bogdanm | 0:9b334a45a8ff | 192 | break; |
bogdanm | 0:9b334a45a8ff | 193 | case UART4: |
bogdanm | 0:9b334a45a8ff | 194 | CPG.STBCR4 &= ~(1 << 3); |
bogdanm | 0:9b334a45a8ff | 195 | break; |
bogdanm | 0:9b334a45a8ff | 196 | case UART5: |
bogdanm | 0:9b334a45a8ff | 197 | CPG.STBCR4 &= ~(1 << 2); |
bogdanm | 0:9b334a45a8ff | 198 | break; |
bogdanm | 0:9b334a45a8ff | 199 | case UART6: |
bogdanm | 0:9b334a45a8ff | 200 | CPG.STBCR4 &= ~(1 << 1); |
bogdanm | 0:9b334a45a8ff | 201 | break; |
bogdanm | 0:9b334a45a8ff | 202 | case UART7: |
bogdanm | 0:9b334a45a8ff | 203 | CPG.STBCR4 &= ~(1 << 0); |
bogdanm | 0:9b334a45a8ff | 204 | break; |
bogdanm | 0:9b334a45a8ff | 205 | } |
bogdanm | 0:9b334a45a8ff | 206 | dummy = CPG.STBCR4; |
bogdanm | 0:9b334a45a8ff | 207 | |
bogdanm | 0:9b334a45a8ff | 208 | /* ==== SCIF initial setting ==== */ |
bogdanm | 0:9b334a45a8ff | 209 | /* ---- Serial control register (SCSCR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 210 | /* B'00 : Internal CLK */ |
bogdanm | 0:9b334a45a8ff | 211 | obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ |
bogdanm | 0:9b334a45a8ff | 212 | |
bogdanm | 0:9b334a45a8ff | 213 | /* ---- FIFO control register (SCFCR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 214 | /* Transmit FIFO reset & Receive FIFO data register reset */ |
bogdanm | 0:9b334a45a8ff | 215 | obj->uart->SCFCR = 0x0006; |
bogdanm | 0:9b334a45a8ff | 216 | |
bogdanm | 0:9b334a45a8ff | 217 | /* ---- Serial status register (SCFSR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 218 | dummy = obj->uart->SCFSR; |
bogdanm | 0:9b334a45a8ff | 219 | obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */ |
bogdanm | 0:9b334a45a8ff | 220 | |
bogdanm | 0:9b334a45a8ff | 221 | /* ---- Line status register (SCLSR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 222 | /* ORER bit clear */ |
bogdanm | 0:9b334a45a8ff | 223 | obj->uart->SCLSR = 0; |
bogdanm | 0:9b334a45a8ff | 224 | |
bogdanm | 0:9b334a45a8ff | 225 | /* ---- Serial extension mode register (SCEMR) setting ---- |
bogdanm | 0:9b334a45a8ff | 226 | b7 BGDM - Baud rate generator double-speed mode : Normal mode |
bogdanm | 0:9b334a45a8ff | 227 | b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ |
bogdanm | 0:9b334a45a8ff | 228 | obj->uart->SCEMR = 0x0000u; |
bogdanm | 0:9b334a45a8ff | 229 | |
bogdanm | 0:9b334a45a8ff | 230 | /* ---- Bit rate register (SCBRR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 231 | serial_baud (obj, 9600); |
bogdanm | 0:9b334a45a8ff | 232 | serial_format(obj, 8, ParityNone, 1); |
bogdanm | 0:9b334a45a8ff | 233 | |
bogdanm | 0:9b334a45a8ff | 234 | /* ---- FIFO control register (SCFCR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 235 | obj->uart->SCFCR = 0x0030u; |
bogdanm | 0:9b334a45a8ff | 236 | |
bogdanm | 0:9b334a45a8ff | 237 | /* ---- Serial port register (SCSPTR) setting ---- |
bogdanm | 0:9b334a45a8ff | 238 | b1 SPB2IO - Serial port break output : disabled |
bogdanm | 0:9b334a45a8ff | 239 | b0 SPB2DT - Serial port break data : High-level */ |
bogdanm | 0:9b334a45a8ff | 240 | obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1 |
bogdanm | 0:9b334a45a8ff | 241 | |
bogdanm | 0:9b334a45a8ff | 242 | /* ---- Line status register (SCLSR) setting ---- |
bogdanm | 0:9b334a45a8ff | 243 | b0 ORER - Overrun error detect : clear */ |
bogdanm | 0:9b334a45a8ff | 244 | |
bogdanm | 0:9b334a45a8ff | 245 | if (obj->uart->SCLSR & 0x0001) { |
bogdanm | 0:9b334a45a8ff | 246 | obj->uart->SCLSR = 0u; // ORER clear |
bogdanm | 0:9b334a45a8ff | 247 | } |
bogdanm | 0:9b334a45a8ff | 248 | |
bogdanm | 0:9b334a45a8ff | 249 | // pinout the chosen uart |
bogdanm | 0:9b334a45a8ff | 250 | pinmap_pinout(tx, PinMap_UART_TX); |
bogdanm | 0:9b334a45a8ff | 251 | pinmap_pinout(rx, PinMap_UART_RX); |
bogdanm | 0:9b334a45a8ff | 252 | |
bogdanm | 0:9b334a45a8ff | 253 | switch (uart) { |
bogdanm | 0:9b334a45a8ff | 254 | case UART0: |
bogdanm | 0:9b334a45a8ff | 255 | obj->index = 0; |
bogdanm | 0:9b334a45a8ff | 256 | break; |
bogdanm | 0:9b334a45a8ff | 257 | case UART1: |
bogdanm | 0:9b334a45a8ff | 258 | obj->index = 1; |
bogdanm | 0:9b334a45a8ff | 259 | break; |
bogdanm | 0:9b334a45a8ff | 260 | case UART2: |
bogdanm | 0:9b334a45a8ff | 261 | obj->index = 2; |
bogdanm | 0:9b334a45a8ff | 262 | break; |
bogdanm | 0:9b334a45a8ff | 263 | case UART3: |
bogdanm | 0:9b334a45a8ff | 264 | obj->index = 3; |
bogdanm | 0:9b334a45a8ff | 265 | break; |
bogdanm | 0:9b334a45a8ff | 266 | case UART4: |
bogdanm | 0:9b334a45a8ff | 267 | obj->index = 4; |
bogdanm | 0:9b334a45a8ff | 268 | break; |
bogdanm | 0:9b334a45a8ff | 269 | case UART5: |
bogdanm | 0:9b334a45a8ff | 270 | obj->index = 5; |
bogdanm | 0:9b334a45a8ff | 271 | break; |
bogdanm | 0:9b334a45a8ff | 272 | case UART6: |
bogdanm | 0:9b334a45a8ff | 273 | obj->index = 6; |
bogdanm | 0:9b334a45a8ff | 274 | break; |
bogdanm | 0:9b334a45a8ff | 275 | case UART7: |
bogdanm | 0:9b334a45a8ff | 276 | obj->index = 7; |
bogdanm | 0:9b334a45a8ff | 277 | break; |
bogdanm | 0:9b334a45a8ff | 278 | } |
bogdanm | 0:9b334a45a8ff | 279 | uart_data[obj->index].sw_rts.pin = NC; |
bogdanm | 0:9b334a45a8ff | 280 | uart_data[obj->index].sw_cts.pin = NC; |
bogdanm | 0:9b334a45a8ff | 281 | |
bogdanm | 0:9b334a45a8ff | 282 | /* ---- Serial control register (SCSCR) setting ---- */ |
bogdanm | 0:9b334a45a8ff | 283 | /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */ |
bogdanm | 0:9b334a45a8ff | 284 | obj->uart->SCSCR = 0x00F0; |
bogdanm | 0:9b334a45a8ff | 285 | |
bogdanm | 0:9b334a45a8ff | 286 | is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); |
bogdanm | 0:9b334a45a8ff | 287 | |
bogdanm | 0:9b334a45a8ff | 288 | if (is_stdio_uart) { |
bogdanm | 0:9b334a45a8ff | 289 | stdio_uart_inited = 1; |
bogdanm | 0:9b334a45a8ff | 290 | memcpy(&stdio_uart, obj, sizeof(serial_t)); |
bogdanm | 0:9b334a45a8ff | 291 | } |
bogdanm | 0:9b334a45a8ff | 292 | } |
bogdanm | 0:9b334a45a8ff | 293 | |
bogdanm | 0:9b334a45a8ff | 294 | void serial_free(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 295 | uart_data[obj->index].serial_irq_id = 0; |
bogdanm | 0:9b334a45a8ff | 296 | } |
bogdanm | 0:9b334a45a8ff | 297 | |
bogdanm | 0:9b334a45a8ff | 298 | // serial_baud |
bogdanm | 0:9b334a45a8ff | 299 | // set the baud rate, taking in to account the current SystemFrequency |
bogdanm | 0:9b334a45a8ff | 300 | void serial_baud(serial_t *obj, int baudrate) { |
bogdanm | 0:9b334a45a8ff | 301 | uint16_t DL; |
bogdanm | 0:9b334a45a8ff | 302 | |
bogdanm | 0:9b334a45a8ff | 303 | obj->uart->SCSMR &= ~0x0003; |
bogdanm | 0:9b334a45a8ff | 304 | |
bogdanm | 0:9b334a45a8ff | 305 | if (baudrate > 32552) { |
bogdanm | 0:9b334a45a8ff | 306 | obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 |
bogdanm | 0:9b334a45a8ff | 307 | DL = PCLK / (8 * baudrate); |
bogdanm | 0:9b334a45a8ff | 308 | if (DL > 0) { |
bogdanm | 0:9b334a45a8ff | 309 | DL--; |
bogdanm | 0:9b334a45a8ff | 310 | } |
bogdanm | 0:9b334a45a8ff | 311 | obj->uart->SCBRR = (uint8_t)DL; |
bogdanm | 0:9b334a45a8ff | 312 | } else if (baudrate > 16276) { |
bogdanm | 0:9b334a45a8ff | 313 | obj->uart->SCEMR = 0x0080; // BGDM = 1 |
bogdanm | 0:9b334a45a8ff | 314 | obj->uart->SCBRR = PCLK / (16 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 315 | } else if (baudrate > 8138) { |
bogdanm | 0:9b334a45a8ff | 316 | obj->uart->SCEMR = 0x0000; |
bogdanm | 0:9b334a45a8ff | 317 | obj->uart->SCBRR = PCLK / (32 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 318 | } else if (baudrate > 4169) { |
bogdanm | 0:9b334a45a8ff | 319 | obj->uart->SCSMR |= 0x0001; |
bogdanm | 0:9b334a45a8ff | 320 | obj->uart->SCEMR = 0x0080; // BGDM = 1 |
bogdanm | 0:9b334a45a8ff | 321 | obj->uart->SCBRR = PCLK / (64 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 322 | } else if (baudrate > 2034) { |
bogdanm | 0:9b334a45a8ff | 323 | obj->uart->SCSMR |= 0x0001; |
bogdanm | 0:9b334a45a8ff | 324 | obj->uart->SCEMR = 0x0000; |
bogdanm | 0:9b334a45a8ff | 325 | obj->uart->SCBRR = PCLK / (128 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 326 | } else if (baudrate > 1017) { |
bogdanm | 0:9b334a45a8ff | 327 | obj->uart->SCSMR |= 0x0002; |
bogdanm | 0:9b334a45a8ff | 328 | obj->uart->SCEMR = 0x0080; // BGDM = 1 |
bogdanm | 0:9b334a45a8ff | 329 | obj->uart->SCBRR = PCLK / (256 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 330 | } else if (baudrate > 508) { |
bogdanm | 0:9b334a45a8ff | 331 | obj->uart->SCSMR |= 0x0002; |
bogdanm | 0:9b334a45a8ff | 332 | obj->uart->SCEMR = 0x0000; |
bogdanm | 0:9b334a45a8ff | 333 | obj->uart->SCBRR = PCLK / (512 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 334 | } else if (baudrate > 254) { |
bogdanm | 0:9b334a45a8ff | 335 | obj->uart->SCSMR |= 0x0003; |
bogdanm | 0:9b334a45a8ff | 336 | obj->uart->SCEMR = 0x0080; // BGDM = 1 |
bogdanm | 0:9b334a45a8ff | 337 | obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 338 | } else if (baudrate > 127) { |
bogdanm | 0:9b334a45a8ff | 339 | obj->uart->SCSMR |= 0x0003; |
bogdanm | 0:9b334a45a8ff | 340 | obj->uart->SCEMR = 0x0000; |
bogdanm | 0:9b334a45a8ff | 341 | obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1; |
bogdanm | 0:9b334a45a8ff | 342 | } else { |
bogdanm | 0:9b334a45a8ff | 343 | obj->uart->SCSMR |= 0x0003; |
bogdanm | 0:9b334a45a8ff | 344 | obj->uart->SCEMR = 0x0000; |
bogdanm | 0:9b334a45a8ff | 345 | obj->uart->SCBRR = 0xFFu; |
bogdanm | 0:9b334a45a8ff | 346 | } |
bogdanm | 0:9b334a45a8ff | 347 | } |
bogdanm | 0:9b334a45a8ff | 348 | |
bogdanm | 0:9b334a45a8ff | 349 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { |
bogdanm | 0:9b334a45a8ff | 350 | int parity_enable; |
bogdanm | 0:9b334a45a8ff | 351 | int parity_select; |
bogdanm | 0:9b334a45a8ff | 352 | |
bogdanm | 0:9b334a45a8ff | 353 | MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits |
bogdanm | 0:9b334a45a8ff | 354 | MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits |
bogdanm | 0:9b334a45a8ff | 355 | MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || |
bogdanm | 0:9b334a45a8ff | 356 | (parity == ParityForced1) || (parity == ParityForced0)); |
bogdanm | 0:9b334a45a8ff | 357 | |
bogdanm | 0:9b334a45a8ff | 358 | stop_bits = (stop_bits == 1)? 0: |
bogdanm | 0:9b334a45a8ff | 359 | (stop_bits == 2)? 1: |
bogdanm | 0:9b334a45a8ff | 360 | 0; // must not to be |
bogdanm | 0:9b334a45a8ff | 361 | |
bogdanm | 0:9b334a45a8ff | 362 | data_bits = (data_bits == 8)? 0: |
bogdanm | 0:9b334a45a8ff | 363 | (data_bits == 7)? 1: |
bogdanm | 0:9b334a45a8ff | 364 | 0; // must not to be |
bogdanm | 0:9b334a45a8ff | 365 | |
bogdanm | 0:9b334a45a8ff | 366 | switch (parity) { |
bogdanm | 0:9b334a45a8ff | 367 | case ParityNone: |
bogdanm | 0:9b334a45a8ff | 368 | parity_enable = 0; |
bogdanm | 0:9b334a45a8ff | 369 | parity_select = 0; |
bogdanm | 0:9b334a45a8ff | 370 | break; |
bogdanm | 0:9b334a45a8ff | 371 | case ParityOdd: |
bogdanm | 0:9b334a45a8ff | 372 | parity_enable = 1; |
bogdanm | 0:9b334a45a8ff | 373 | parity_select = 1; |
bogdanm | 0:9b334a45a8ff | 374 | break; |
bogdanm | 0:9b334a45a8ff | 375 | case ParityEven: |
bogdanm | 0:9b334a45a8ff | 376 | parity_enable = 1; |
bogdanm | 0:9b334a45a8ff | 377 | parity_select = 0; |
bogdanm | 0:9b334a45a8ff | 378 | break; |
bogdanm | 0:9b334a45a8ff | 379 | case ParityForced1: |
bogdanm | 0:9b334a45a8ff | 380 | case ParityForced0: |
bogdanm | 0:9b334a45a8ff | 381 | default: |
bogdanm | 0:9b334a45a8ff | 382 | parity_enable = 0; |
bogdanm | 0:9b334a45a8ff | 383 | parity_select = 0; |
bogdanm | 0:9b334a45a8ff | 384 | break; |
bogdanm | 0:9b334a45a8ff | 385 | } |
bogdanm | 0:9b334a45a8ff | 386 | |
bogdanm | 0:9b334a45a8ff | 387 | obj->uart->SCSMR = data_bits << 6 |
bogdanm | 0:9b334a45a8ff | 388 | | parity_enable << 5 |
bogdanm | 0:9b334a45a8ff | 389 | | parity_select << 4 |
bogdanm | 0:9b334a45a8ff | 390 | | stop_bits << 3; |
bogdanm | 0:9b334a45a8ff | 391 | } |
bogdanm | 0:9b334a45a8ff | 392 | |
bogdanm | 0:9b334a45a8ff | 393 | /****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 394 | * INTERRUPTS HANDLING |
bogdanm | 0:9b334a45a8ff | 395 | ******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 396 | |
bogdanm | 0:9b334a45a8ff | 397 | static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { |
bogdanm | 0:9b334a45a8ff | 398 | __IO uint16_t *dmy_rd_scscr; |
bogdanm | 0:9b334a45a8ff | 399 | __IO uint16_t *dmy_rd_scfsr; |
bogdanm | 0:9b334a45a8ff | 400 | |
bogdanm | 0:9b334a45a8ff | 401 | dmy_rd_scscr = SCSCR_MATCH[index]; |
bogdanm | 0:9b334a45a8ff | 402 | *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0 |
bogdanm | 0:9b334a45a8ff | 403 | dmy_rd_scfsr = SCFSR_MATCH[index]; |
bogdanm | 0:9b334a45a8ff | 404 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE |
bogdanm | 0:9b334a45a8ff | 405 | |
bogdanm | 0:9b334a45a8ff | 406 | irq_handler(uart_data[index].serial_irq_id, TxIrq); |
bogdanm | 0:9b334a45a8ff | 407 | } |
bogdanm | 0:9b334a45a8ff | 408 | |
bogdanm | 0:9b334a45a8ff | 409 | static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { |
bogdanm | 0:9b334a45a8ff | 410 | __IO uint16_t *dmy_rd_scscr; |
bogdanm | 0:9b334a45a8ff | 411 | __IO uint16_t *dmy_rd_scfsr; |
bogdanm | 0:9b334a45a8ff | 412 | |
bogdanm | 0:9b334a45a8ff | 413 | dmy_rd_scscr = SCSCR_MATCH[index]; |
bogdanm | 0:9b334a45a8ff | 414 | *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0 |
bogdanm | 0:9b334a45a8ff | 415 | dmy_rd_scfsr = SCFSR_MATCH[index]; |
bogdanm | 0:9b334a45a8ff | 416 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR |
bogdanm | 0:9b334a45a8ff | 417 | |
bogdanm | 0:9b334a45a8ff | 418 | irq_handler(uart_data[index].serial_irq_id, RxIrq); |
bogdanm | 0:9b334a45a8ff | 419 | } |
bogdanm | 0:9b334a45a8ff | 420 | |
bogdanm | 0:9b334a45a8ff | 421 | /* TX handler */ |
bogdanm | 0:9b334a45a8ff | 422 | static void uart0_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 423 | uart_tx_irq(SCIFTXI0_IRQn, 0); |
bogdanm | 0:9b334a45a8ff | 424 | } |
bogdanm | 0:9b334a45a8ff | 425 | static void uart1_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 426 | uart_tx_irq(SCIFTXI1_IRQn, 1); |
bogdanm | 0:9b334a45a8ff | 427 | } |
bogdanm | 0:9b334a45a8ff | 428 | static void uart2_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 429 | uart_tx_irq(SCIFTXI2_IRQn, 2); |
bogdanm | 0:9b334a45a8ff | 430 | } |
bogdanm | 0:9b334a45a8ff | 431 | static void uart3_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 432 | uart_tx_irq(SCIFTXI3_IRQn, 3); |
bogdanm | 0:9b334a45a8ff | 433 | } |
bogdanm | 0:9b334a45a8ff | 434 | static void uart4_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 435 | uart_tx_irq(SCIFTXI4_IRQn, 4); |
bogdanm | 0:9b334a45a8ff | 436 | } |
bogdanm | 0:9b334a45a8ff | 437 | static void uart5_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 438 | uart_tx_irq(SCIFTXI5_IRQn, 5); |
bogdanm | 0:9b334a45a8ff | 439 | } |
bogdanm | 0:9b334a45a8ff | 440 | static void uart6_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 441 | uart_tx_irq(SCIFTXI6_IRQn, 6); |
bogdanm | 0:9b334a45a8ff | 442 | } |
bogdanm | 0:9b334a45a8ff | 443 | static void uart7_tx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 444 | uart_tx_irq(SCIFTXI7_IRQn, 7); |
bogdanm | 0:9b334a45a8ff | 445 | } |
bogdanm | 0:9b334a45a8ff | 446 | /* RX handler */ |
bogdanm | 0:9b334a45a8ff | 447 | static void uart0_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 448 | uart_rx_irq(SCIFRXI0_IRQn, 0); |
bogdanm | 0:9b334a45a8ff | 449 | } |
bogdanm | 0:9b334a45a8ff | 450 | static void uart1_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 451 | uart_rx_irq(SCIFRXI1_IRQn, 1); |
bogdanm | 0:9b334a45a8ff | 452 | } |
bogdanm | 0:9b334a45a8ff | 453 | static void uart2_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 454 | uart_rx_irq(SCIFRXI2_IRQn, 2); |
bogdanm | 0:9b334a45a8ff | 455 | } |
bogdanm | 0:9b334a45a8ff | 456 | static void uart3_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 457 | uart_rx_irq(SCIFRXI3_IRQn, 3); |
bogdanm | 0:9b334a45a8ff | 458 | } |
bogdanm | 0:9b334a45a8ff | 459 | static void uart4_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 460 | uart_rx_irq(SCIFRXI4_IRQn, 4); |
bogdanm | 0:9b334a45a8ff | 461 | } |
bogdanm | 0:9b334a45a8ff | 462 | static void uart5_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 463 | uart_rx_irq(SCIFRXI5_IRQn, 5); |
bogdanm | 0:9b334a45a8ff | 464 | } |
bogdanm | 0:9b334a45a8ff | 465 | static void uart6_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 466 | uart_rx_irq(SCIFRXI6_IRQn, 6); |
bogdanm | 0:9b334a45a8ff | 467 | } |
bogdanm | 0:9b334a45a8ff | 468 | static void uart7_rx_irq(void) { |
bogdanm | 0:9b334a45a8ff | 469 | uart_rx_irq(SCIFRXI7_IRQn, 7); |
bogdanm | 0:9b334a45a8ff | 470 | } |
bogdanm | 0:9b334a45a8ff | 471 | |
bogdanm | 0:9b334a45a8ff | 472 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { |
bogdanm | 0:9b334a45a8ff | 473 | irq_handler = handler; |
bogdanm | 0:9b334a45a8ff | 474 | uart_data[obj->index].serial_irq_id = id; |
bogdanm | 0:9b334a45a8ff | 475 | } |
bogdanm | 0:9b334a45a8ff | 476 | |
bogdanm | 0:9b334a45a8ff | 477 | static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { |
bogdanm | 0:9b334a45a8ff | 478 | IRQn_Type IRQn; |
bogdanm | 0:9b334a45a8ff | 479 | IRQHandler handler; |
bogdanm | 0:9b334a45a8ff | 480 | |
bogdanm | 0:9b334a45a8ff | 481 | IRQn = irq_set_tbl[obj->index][irq]; |
bogdanm | 0:9b334a45a8ff | 482 | handler = hander_set_tbl[obj->index][irq]; |
bogdanm | 0:9b334a45a8ff | 483 | |
bogdanm | 0:9b334a45a8ff | 484 | if ((obj->index >= 0) && (obj->index <= 7)) { |
bogdanm | 0:9b334a45a8ff | 485 | if (enable) { |
bogdanm | 0:9b334a45a8ff | 486 | InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); |
bogdanm | 0:9b334a45a8ff | 487 | GIC_SetPriority(IRQn, 5); |
bogdanm | 0:9b334a45a8ff | 488 | GIC_EnableIRQ(IRQn); |
bogdanm | 0:9b334a45a8ff | 489 | } else { |
bogdanm | 0:9b334a45a8ff | 490 | GIC_DisableIRQ(IRQn); |
bogdanm | 0:9b334a45a8ff | 491 | } |
bogdanm | 0:9b334a45a8ff | 492 | } |
bogdanm | 0:9b334a45a8ff | 493 | } |
bogdanm | 0:9b334a45a8ff | 494 | |
bogdanm | 0:9b334a45a8ff | 495 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { |
bogdanm | 0:9b334a45a8ff | 496 | if (RxIrq == irq) { |
bogdanm | 0:9b334a45a8ff | 497 | uart_data[obj->index].rx_irq_set_api = enable; |
bogdanm | 0:9b334a45a8ff | 498 | } |
bogdanm | 0:9b334a45a8ff | 499 | serial_irq_set_internal(obj, irq, enable); |
bogdanm | 0:9b334a45a8ff | 500 | } |
bogdanm | 0:9b334a45a8ff | 501 | |
bogdanm | 0:9b334a45a8ff | 502 | static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { |
bogdanm | 0:9b334a45a8ff | 503 | uart_data[obj->index].rx_irq_set_flow = enable; |
bogdanm | 0:9b334a45a8ff | 504 | serial_irq_set_internal(obj, RxIrq, enable); |
bogdanm | 0:9b334a45a8ff | 505 | } |
bogdanm | 0:9b334a45a8ff | 506 | |
bogdanm | 0:9b334a45a8ff | 507 | /****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 508 | * READ/WRITE |
bogdanm | 0:9b334a45a8ff | 509 | ******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 510 | int serial_getc(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 511 | uint16_t err_read; |
bogdanm | 0:9b334a45a8ff | 512 | int data; |
bogdanm | 0:9b334a45a8ff | 513 | int was_masked; |
bogdanm | 0:9b334a45a8ff | 514 | |
bogdanm | 0:9b334a45a8ff | 515 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 516 | if (obj->uart->SCFSR & 0x93) { |
bogdanm | 0:9b334a45a8ff | 517 | err_read = obj->uart->SCFSR; |
bogdanm | 0:9b334a45a8ff | 518 | obj->uart->SCFSR = (err_read & ~0x93); |
bogdanm | 0:9b334a45a8ff | 519 | } |
bogdanm | 0:9b334a45a8ff | 520 | obj->uart->SCSCR |= 0x0040; // Set RIE |
bogdanm | 0:9b334a45a8ff | 521 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 522 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 523 | } |
bogdanm | 0:9b334a45a8ff | 524 | |
bogdanm | 0:9b334a45a8ff | 525 | if (obj->uart->SCLSR & 0x0001) { |
bogdanm | 0:9b334a45a8ff | 526 | obj->uart->SCLSR = 0u; // ORER clear |
bogdanm | 0:9b334a45a8ff | 527 | } |
bogdanm | 0:9b334a45a8ff | 528 | |
bogdanm | 0:9b334a45a8ff | 529 | while (!serial_readable(obj)); |
bogdanm | 0:9b334a45a8ff | 530 | data = obj->uart->SCFRDR & 0xff; |
bogdanm | 0:9b334a45a8ff | 531 | |
bogdanm | 0:9b334a45a8ff | 532 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 533 | err_read = obj->uart->SCFSR; |
bogdanm | 0:9b334a45a8ff | 534 | obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF |
bogdanm | 0:9b334a45a8ff | 535 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 536 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 537 | } |
bogdanm | 0:9b334a45a8ff | 538 | |
bogdanm | 0:9b334a45a8ff | 539 | if (err_read & 0x80) { |
bogdanm | 0:9b334a45a8ff | 540 | data = -1; //err |
bogdanm | 0:9b334a45a8ff | 541 | } |
bogdanm | 0:9b334a45a8ff | 542 | return data; |
bogdanm | 0:9b334a45a8ff | 543 | } |
bogdanm | 0:9b334a45a8ff | 544 | |
bogdanm | 0:9b334a45a8ff | 545 | void serial_putc(serial_t *obj, int c) { |
bogdanm | 0:9b334a45a8ff | 546 | uint16_t dummy_read; |
bogdanm | 0:9b334a45a8ff | 547 | int was_masked; |
bogdanm | 0:9b334a45a8ff | 548 | |
bogdanm | 0:9b334a45a8ff | 549 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 550 | obj->uart->SCSCR |= 0x0080; // Set TIE |
bogdanm | 0:9b334a45a8ff | 551 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 552 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 553 | } |
bogdanm | 0:9b334a45a8ff | 554 | while (!serial_writable(obj)); |
bogdanm | 0:9b334a45a8ff | 555 | obj->uart->SCFTDR = c; |
bogdanm | 0:9b334a45a8ff | 556 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 557 | dummy_read = obj->uart->SCFSR; |
bogdanm | 0:9b334a45a8ff | 558 | obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE |
bogdanm | 0:9b334a45a8ff | 559 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 560 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 561 | } |
bogdanm | 0:9b334a45a8ff | 562 | uart_data[obj->index].count++; |
bogdanm | 0:9b334a45a8ff | 563 | } |
bogdanm | 0:9b334a45a8ff | 564 | |
bogdanm | 0:9b334a45a8ff | 565 | int serial_readable(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 566 | return ((obj->uart->SCFSR & 0x02) != 0); // RDF |
bogdanm | 0:9b334a45a8ff | 567 | } |
bogdanm | 0:9b334a45a8ff | 568 | |
bogdanm | 0:9b334a45a8ff | 569 | int serial_writable(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 570 | return ((obj->uart->SCFSR & 0x20) != 0); // TDFE |
bogdanm | 0:9b334a45a8ff | 571 | } |
bogdanm | 0:9b334a45a8ff | 572 | |
bogdanm | 0:9b334a45a8ff | 573 | void serial_clear(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 574 | int was_masked; |
bogdanm | 0:9b334a45a8ff | 575 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 576 | |
bogdanm | 0:9b334a45a8ff | 577 | obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 |
bogdanm | 0:9b334a45a8ff | 578 | obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 |
bogdanm | 0:9b334a45a8ff | 579 | obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 |
bogdanm | 0:9b334a45a8ff | 580 | |
bogdanm | 0:9b334a45a8ff | 581 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 582 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 583 | } |
bogdanm | 0:9b334a45a8ff | 584 | } |
bogdanm | 0:9b334a45a8ff | 585 | |
bogdanm | 0:9b334a45a8ff | 586 | void serial_pinout_tx(PinName tx) { |
bogdanm | 0:9b334a45a8ff | 587 | pinmap_pinout(tx, PinMap_UART_TX); |
bogdanm | 0:9b334a45a8ff | 588 | } |
bogdanm | 0:9b334a45a8ff | 589 | |
bogdanm | 0:9b334a45a8ff | 590 | void serial_break_set(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 591 | int was_masked; |
bogdanm | 0:9b334a45a8ff | 592 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 593 | // TxD Output(L) |
bogdanm | 0:9b334a45a8ff | 594 | obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0 |
bogdanm | 0:9b334a45a8ff | 595 | obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable) |
bogdanm | 0:9b334a45a8ff | 596 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 597 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 598 | } |
bogdanm | 0:9b334a45a8ff | 599 | } |
bogdanm | 0:9b334a45a8ff | 600 | |
bogdanm | 0:9b334a45a8ff | 601 | void serial_break_clear(serial_t *obj) { |
bogdanm | 0:9b334a45a8ff | 602 | int was_masked; |
bogdanm | 0:9b334a45a8ff | 603 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 604 | obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable) |
bogdanm | 0:9b334a45a8ff | 605 | obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1 |
bogdanm | 0:9b334a45a8ff | 606 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 607 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 608 | } |
bogdanm | 0:9b334a45a8ff | 609 | } |
bogdanm | 0:9b334a45a8ff | 610 | |
bogdanm | 0:9b334a45a8ff | 611 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { |
bogdanm | 0:9b334a45a8ff | 612 | // determine the UART to use |
bogdanm | 0:9b334a45a8ff | 613 | int was_masked; |
bogdanm | 0:9b334a45a8ff | 614 | |
bogdanm | 0:9b334a45a8ff | 615 | serial_flow_irq_set(obj, 0); |
bogdanm | 0:9b334a45a8ff | 616 | |
bogdanm | 0:9b334a45a8ff | 617 | if (type == FlowControlRTSCTS) { |
bogdanm | 0:9b334a45a8ff | 618 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 619 | obj->uart->SCFCR = 0x0008u; // CTS/RTS enable |
bogdanm | 0:9b334a45a8ff | 620 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 621 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 622 | } |
bogdanm | 0:9b334a45a8ff | 623 | pinmap_pinout(rxflow, PinMap_UART_RTS); |
bogdanm | 0:9b334a45a8ff | 624 | pinmap_pinout(txflow, PinMap_UART_CTS); |
bogdanm | 0:9b334a45a8ff | 625 | } else { |
bogdanm | 0:9b334a45a8ff | 626 | was_masked = __disable_irq(); |
bogdanm | 0:9b334a45a8ff | 627 | obj->uart->SCFCR = 0x0000u; // CTS/RTS diable |
bogdanm | 0:9b334a45a8ff | 628 | if (!was_masked) { |
bogdanm | 0:9b334a45a8ff | 629 | __enable_irq(); |
bogdanm | 0:9b334a45a8ff | 630 | } |
bogdanm | 0:9b334a45a8ff | 631 | } |
bogdanm | 0:9b334a45a8ff | 632 | } |
bogdanm | 0:9b334a45a8ff | 633 | |
bogdanm | 0:9b334a45a8ff | 634 | |
bogdanm | 0:9b334a45a8ff | 635 | |
bogdanm | 0:9b334a45a8ff | 636 |