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targets/TARGET_Maxim/TARGET_MAX32625/device/spim_regs.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

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<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_SPIM_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_SPIM_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
<> 150:02e0a0aed4ec 66 __IO uint32_t ss_sr_polarity; /* 0x0004 SPI Master Polarity Control for SS and SR Signals */
<> 150:02e0a0aed4ec 67 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
<> 150:02e0a0aed4ec 68 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
<> 150:02e0a0aed4ec 69 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
<> 150:02e0a0aed4ec 70 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
<> 150:02e0a0aed4ec 71 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
<> 150:02e0a0aed4ec 72 __IO uint32_t simple_headers; /* 0x001C SPI Master Simple Mode Transaction Headers */
<> 150:02e0a0aed4ec 73 } mxc_spim_regs_t;
<> 150:02e0a0aed4ec 74
<> 150:02e0a0aed4ec 75
<> 150:02e0a0aed4ec 76 /* Offset Register Description
<> 150:02e0a0aed4ec 77 ============= ============================================================================ */
<> 150:02e0a0aed4ec 78 typedef struct {
<> 150:02e0a0aed4ec 79 union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */
<> 150:02e0a0aed4ec 80 __IO uint8_t trans_8[2048];
<> 150:02e0a0aed4ec 81 __IO uint16_t trans_16[1024];
<> 150:02e0a0aed4ec 82 __IO uint32_t trans_32[512];
<> 150:02e0a0aed4ec 83 };
<> 150:02e0a0aed4ec 84 union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */
<> 150:02e0a0aed4ec 85 __IO uint8_t rslts_8[2048];
<> 150:02e0a0aed4ec 86 __IO uint16_t rslts_16[1024];
<> 150:02e0a0aed4ec 87 __IO uint32_t rslts_32[512];
<> 150:02e0a0aed4ec 88 };
<> 150:02e0a0aed4ec 89 } mxc_spim_fifo_regs_t;
<> 150:02e0a0aed4ec 90
<> 150:02e0a0aed4ec 91
<> 150:02e0a0aed4ec 92 /*
<> 150:02e0a0aed4ec 93 Register offsets for module SPIM.
<> 150:02e0a0aed4ec 94 */
<> 150:02e0a0aed4ec 95
<> 150:02e0a0aed4ec 96 #define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 97 #define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 98 #define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 99 #define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 100 #define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 101 #define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 102 #define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 103 #define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL)
<> 150:02e0a0aed4ec 104 #define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 105 #define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
<> 150:02e0a0aed4ec 106
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 /*
<> 150:02e0a0aed4ec 109 Field positions and masks for module SPIM.
<> 150:02e0a0aed4ec 110 */
<> 150:02e0a0aed4ec 111
<> 150:02e0a0aed4ec 112 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0
<> 150:02e0a0aed4ec 113 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS))
<> 150:02e0a0aed4ec 114 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3
<> 150:02e0a0aed4ec 115 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS))
<> 150:02e0a0aed4ec 116 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4
<> 150:02e0a0aed4ec 117 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS))
<> 150:02e0a0aed4ec 118 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6
<> 150:02e0a0aed4ec 119 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS))
<> 150:02e0a0aed4ec 120 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8
<> 150:02e0a0aed4ec 121 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS))
<> 150:02e0a0aed4ec 122 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12
<> 150:02e0a0aed4ec 123 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS))
<> 150:02e0a0aed4ec 124 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16
<> 150:02e0a0aed4ec 125 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS))
<> 150:02e0a0aed4ec 126 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18
<> 150:02e0a0aed4ec 127 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS))
<> 150:02e0a0aed4ec 128 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20
<> 150:02e0a0aed4ec 129 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS))
<> 150:02e0a0aed4ec 130
<> 150:02e0a0aed4ec 131 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 132 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
<> 150:02e0a0aed4ec 133 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
<> 150:02e0a0aed4ec 134 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 #define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
<> 150:02e0a0aed4ec 137 #define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
<> 150:02e0a0aed4ec 138 #define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
<> 150:02e0a0aed4ec 139 #define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0
<> 150:02e0a0aed4ec 142 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS))
<> 150:02e0a0aed4ec 143 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8
<> 150:02e0a0aed4ec 144 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS))
<> 150:02e0a0aed4ec 145
<> 150:02e0a0aed4ec 146 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0
<> 150:02e0a0aed4ec 147 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS))
<> 150:02e0a0aed4ec 148 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1
<> 150:02e0a0aed4ec 149 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 150 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2
<> 150:02e0a0aed4ec 151 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 152 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3
<> 150:02e0a0aed4ec 153 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS))
<> 150:02e0a0aed4ec 154 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4
<> 150:02e0a0aed4ec 155 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS))
<> 150:02e0a0aed4ec 156 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5
<> 150:02e0a0aed4ec 157 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS))
<> 150:02e0a0aed4ec 158 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6
<> 150:02e0a0aed4ec 159 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS))
<> 150:02e0a0aed4ec 160 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8
<> 150:02e0a0aed4ec 161 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS))
<> 150:02e0a0aed4ec 162 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12
<> 150:02e0a0aed4ec 163 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS))
<> 150:02e0a0aed4ec 164 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16
<> 150:02e0a0aed4ec 165 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS))
<> 150:02e0a0aed4ec 166 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20
<> 150:02e0a0aed4ec 167 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS))
<> 150:02e0a0aed4ec 168 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21
<> 150:02e0a0aed4ec 169 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS))
<> 150:02e0a0aed4ec 170 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22
<> 150:02e0a0aed4ec 171 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS))
<> 150:02e0a0aed4ec 172 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24
<> 150:02e0a0aed4ec 173 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS))
<> 150:02e0a0aed4ec 174 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25
<> 150:02e0a0aed4ec 175 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS))
<> 150:02e0a0aed4ec 176
<> 150:02e0a0aed4ec 177 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
<> 150:02e0a0aed4ec 178 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
<> 150:02e0a0aed4ec 179 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8
<> 150:02e0a0aed4ec 180 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS))
<> 150:02e0a0aed4ec 181 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
<> 150:02e0a0aed4ec 182 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
<> 150:02e0a0aed4ec 183 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24
<> 150:02e0a0aed4ec 184 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS))
<> 150:02e0a0aed4ec 185
<> 150:02e0a0aed4ec 186 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
<> 150:02e0a0aed4ec 187 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS))
<> 150:02e0a0aed4ec 188 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1
<> 150:02e0a0aed4ec 189 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS))
<> 150:02e0a0aed4ec 190 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
<> 150:02e0a0aed4ec 191 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
<> 150:02e0a0aed4ec 192 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
<> 150:02e0a0aed4ec 193 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
<> 150:02e0a0aed4ec 194
<> 150:02e0a0aed4ec 195 #if (MXC_SPIM_REV == 0)
<> 150:02e0a0aed4ec 196 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16
<> 150:02e0a0aed4ec 197 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS))
<> 150:02e0a0aed4ec 198 #else
<> 150:02e0a0aed4ec 199 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12
<> 150:02e0a0aed4ec 200 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS))
<> 150:02e0a0aed4ec 201 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16
<> 150:02e0a0aed4ec 202 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS))
<> 150:02e0a0aed4ec 203 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20
<> 150:02e0a0aed4ec 204 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS))
<> 150:02e0a0aed4ec 205 #endif
<> 150:02e0a0aed4ec 206
<> 150:02e0a0aed4ec 207 #define MXC_F_SPIM_INTFL_TX_STALLED_POS 0
<> 150:02e0a0aed4ec 208 #define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS))
<> 150:02e0a0aed4ec 209 #define MXC_F_SPIM_INTFL_RX_STALLED_POS 1
<> 150:02e0a0aed4ec 210 #define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS))
<> 150:02e0a0aed4ec 211 #define MXC_F_SPIM_INTFL_TX_READY_POS 2
<> 150:02e0a0aed4ec 212 #define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS))
<> 150:02e0a0aed4ec 213 #define MXC_F_SPIM_INTFL_RX_DONE_POS 3
<> 150:02e0a0aed4ec 214 #define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS))
<> 150:02e0a0aed4ec 215 #define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4
<> 150:02e0a0aed4ec 216 #define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS))
<> 150:02e0a0aed4ec 217 #define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5
<> 150:02e0a0aed4ec 218 #define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS))
<> 150:02e0a0aed4ec 219
<> 150:02e0a0aed4ec 220 #define MXC_F_SPIM_INTEN_TX_STALLED_POS 0
<> 150:02e0a0aed4ec 221 #define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS))
<> 150:02e0a0aed4ec 222 #define MXC_F_SPIM_INTEN_RX_STALLED_POS 1
<> 150:02e0a0aed4ec 223 #define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS))
<> 150:02e0a0aed4ec 224 #define MXC_F_SPIM_INTEN_TX_READY_POS 2
<> 150:02e0a0aed4ec 225 #define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS))
<> 150:02e0a0aed4ec 226 #define MXC_F_SPIM_INTEN_RX_DONE_POS 3
<> 150:02e0a0aed4ec 227 #define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS))
<> 150:02e0a0aed4ec 228 #define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4
<> 150:02e0a0aed4ec 229 #define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS))
<> 150:02e0a0aed4ec 230 #define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5
<> 150:02e0a0aed4ec 231 #define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS))
<> 150:02e0a0aed4ec 232
<> 150:02e0a0aed4ec 233 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0
<> 150:02e0a0aed4ec 234 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS))
<> 150:02e0a0aed4ec 235 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16
<> 150:02e0a0aed4ec 236 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS))
<> 150:02e0a0aed4ec 237
<> 150:02e0a0aed4ec 238
<> 150:02e0a0aed4ec 239
<> 150:02e0a0aed4ec 240 #ifdef __cplusplus
<> 150:02e0a0aed4ec 241 }
<> 150:02e0a0aed4ec 242 #endif
<> 150:02e0a0aed4ec 243
<> 150:02e0a0aed4ec 244 #endif /* _MXC_SPIM_REGS_H_ */
<> 150:02e0a0aed4ec 245